Commit | Line | Data |
---|---|---|
3fb1b6ad MD |
1 | /* |
2 | * SuperH Timer Support - CMT | |
3 | * | |
4 | * Copyright (C) 2008 Magnus Damm | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
3fb1b6ad MD |
14 | */ |
15 | ||
e7a9bcc2 LP |
16 | #include <linux/clk.h> |
17 | #include <linux/clockchips.h> | |
18 | #include <linux/clocksource.h> | |
19 | #include <linux/delay.h> | |
20 | #include <linux/err.h> | |
3fb1b6ad | 21 | #include <linux/init.h> |
3fb1b6ad | 22 | #include <linux/interrupt.h> |
3fb1b6ad | 23 | #include <linux/io.h> |
e7a9bcc2 | 24 | #include <linux/ioport.h> |
3fb1b6ad | 25 | #include <linux/irq.h> |
7deeab5d | 26 | #include <linux/module.h> |
1768aa2f | 27 | #include <linux/of.h> |
e7a9bcc2 | 28 | #include <linux/platform_device.h> |
615a445f | 29 | #include <linux/pm_domain.h> |
bad81383 | 30 | #include <linux/pm_runtime.h> |
e7a9bcc2 LP |
31 | #include <linux/sh_timer.h> |
32 | #include <linux/slab.h> | |
33 | #include <linux/spinlock.h> | |
3fb1b6ad | 34 | |
2653caf4 | 35 | struct sh_cmt_device; |
7269f933 | 36 | |
2cda3ac4 LP |
37 | /* |
38 | * The CMT comes in 5 different identified flavours, depending not only on the | |
39 | * SoC but also on the particular instance. The following table lists the main | |
40 | * characteristics of those flavours. | |
41 | * | |
83c79a6d | 42 | * 16B 32B 32B-F 48B R-Car Gen2 |
2cda3ac4 LP |
43 | * ----------------------------------------------------------------------------- |
44 | * Channels 2 1/4 1 6 2/8 | |
45 | * Control Width 16 16 16 16 32 | |
46 | * Counter Width 16 32 32 32/48 32/48 | |
47 | * Shared Start/Stop Y Y Y Y N | |
48 | * | |
83c79a6d MD |
49 | * The r8a73a4 / R-Car Gen2 version has a per-channel start/stop register |
50 | * located in the channel registers block. All other versions have a shared | |
51 | * start/stop register located in the global space. | |
2cda3ac4 | 52 | * |
81b3b271 LP |
53 | * Channels are indexed from 0 to N-1 in the documentation. The channel index |
54 | * infers the start/stop bit position in the control register and the channel | |
55 | * registers block address. Some CMT instances have a subset of channels | |
56 | * available, in which case the index in the documentation doesn't match the | |
57 | * "real" index as implemented in hardware. This is for instance the case with | |
58 | * CMT0 on r8a7740, which is a 32-bit variant with a single channel numbered 0 | |
59 | * in the documentation but using start/stop bit 5 and having its registers | |
60 | * block at 0x60. | |
61 | * | |
62 | * Similarly CMT0 on r8a73a4, r8a7790 and r8a7791, while implementing 32-bit | |
2cda3ac4 LP |
63 | * channels only, is a 48-bit gen2 CMT with the 48-bit channels unavailable. |
64 | */ | |
65 | ||
66 | enum sh_cmt_model { | |
67 | SH_CMT_16BIT, | |
68 | SH_CMT_32BIT, | |
69 | SH_CMT_32BIT_FAST, | |
70 | SH_CMT_48BIT, | |
83c79a6d MD |
71 | SH_CMT0_RCAR_GEN2, |
72 | SH_CMT1_RCAR_GEN2, | |
2cda3ac4 LP |
73 | }; |
74 | ||
75 | struct sh_cmt_info { | |
76 | enum sh_cmt_model model; | |
77 | ||
464eed84 MD |
78 | unsigned int channels_mask; |
79 | ||
2cda3ac4 LP |
80 | unsigned long width; /* 16 or 32 bit version of hardware block */ |
81 | unsigned long overflow_bit; | |
82 | unsigned long clear_bits; | |
83 | ||
84 | /* callbacks for CMSTR and CMCSR access */ | |
85 | unsigned long (*read_control)(void __iomem *base, unsigned long offs); | |
86 | void (*write_control)(void __iomem *base, unsigned long offs, | |
87 | unsigned long value); | |
88 | ||
89 | /* callbacks for CMCNT and CMCOR access */ | |
90 | unsigned long (*read_count)(void __iomem *base, unsigned long offs); | |
91 | void (*write_count)(void __iomem *base, unsigned long offs, | |
92 | unsigned long value); | |
93 | }; | |
94 | ||
7269f933 | 95 | struct sh_cmt_channel { |
2653caf4 | 96 | struct sh_cmt_device *cmt; |
3fb1b6ad | 97 | |
81b3b271 LP |
98 | unsigned int index; /* Index in the documentation */ |
99 | unsigned int hwidx; /* Real hardware index */ | |
100 | ||
101 | void __iomem *iostart; | |
102 | void __iomem *ioctrl; | |
c924d2d2 | 103 | |
81b3b271 | 104 | unsigned int timer_bit; |
3fb1b6ad MD |
105 | unsigned long flags; |
106 | unsigned long match_value; | |
107 | unsigned long next_match_value; | |
108 | unsigned long max_match_value; | |
7d0c399f | 109 | raw_spinlock_t lock; |
3fb1b6ad | 110 | struct clock_event_device ced; |
19bdc9d0 | 111 | struct clocksource cs; |
3fb1b6ad | 112 | unsigned long total_cycles; |
bad81383 | 113 | bool cs_enabled; |
7269f933 LP |
114 | }; |
115 | ||
2653caf4 | 116 | struct sh_cmt_device { |
7269f933 LP |
117 | struct platform_device *pdev; |
118 | ||
2cda3ac4 LP |
119 | const struct sh_cmt_info *info; |
120 | ||
7269f933 | 121 | void __iomem *mapbase; |
7269f933 | 122 | struct clk *clk; |
890f423b | 123 | unsigned long rate; |
7269f933 | 124 | |
de599c88 LP |
125 | raw_spinlock_t lock; /* Protect the shared start/stop register */ |
126 | ||
f5ec9b19 LP |
127 | struct sh_cmt_channel *channels; |
128 | unsigned int num_channels; | |
1768aa2f | 129 | unsigned int hw_channels; |
81b3b271 LP |
130 | |
131 | bool has_clockevent; | |
132 | bool has_clocksource; | |
3fb1b6ad MD |
133 | }; |
134 | ||
d14be99b LP |
135 | #define SH_CMT16_CMCSR_CMF (1 << 7) |
136 | #define SH_CMT16_CMCSR_CMIE (1 << 6) | |
137 | #define SH_CMT16_CMCSR_CKS8 (0 << 0) | |
138 | #define SH_CMT16_CMCSR_CKS32 (1 << 0) | |
139 | #define SH_CMT16_CMCSR_CKS128 (2 << 0) | |
140 | #define SH_CMT16_CMCSR_CKS512 (3 << 0) | |
141 | #define SH_CMT16_CMCSR_CKS_MASK (3 << 0) | |
142 | ||
143 | #define SH_CMT32_CMCSR_CMF (1 << 15) | |
144 | #define SH_CMT32_CMCSR_OVF (1 << 14) | |
145 | #define SH_CMT32_CMCSR_WRFLG (1 << 13) | |
146 | #define SH_CMT32_CMCSR_STTF (1 << 12) | |
147 | #define SH_CMT32_CMCSR_STPF (1 << 11) | |
148 | #define SH_CMT32_CMCSR_SSIE (1 << 10) | |
149 | #define SH_CMT32_CMCSR_CMS (1 << 9) | |
150 | #define SH_CMT32_CMCSR_CMM (1 << 8) | |
151 | #define SH_CMT32_CMCSR_CMTOUT_IE (1 << 7) | |
152 | #define SH_CMT32_CMCSR_CMR_NONE (0 << 4) | |
153 | #define SH_CMT32_CMCSR_CMR_DMA (1 << 4) | |
154 | #define SH_CMT32_CMCSR_CMR_IRQ (2 << 4) | |
155 | #define SH_CMT32_CMCSR_CMR_MASK (3 << 4) | |
156 | #define SH_CMT32_CMCSR_DBGIVD (1 << 3) | |
157 | #define SH_CMT32_CMCSR_CKS_RCLK8 (4 << 0) | |
158 | #define SH_CMT32_CMCSR_CKS_RCLK32 (5 << 0) | |
159 | #define SH_CMT32_CMCSR_CKS_RCLK128 (6 << 0) | |
160 | #define SH_CMT32_CMCSR_CKS_RCLK1 (7 << 0) | |
161 | #define SH_CMT32_CMCSR_CKS_MASK (7 << 0) | |
162 | ||
a6a912ca | 163 | static unsigned long sh_cmt_read16(void __iomem *base, unsigned long offs) |
587acb3d MD |
164 | { |
165 | return ioread16(base + (offs << 1)); | |
166 | } | |
167 | ||
a6a912ca MD |
168 | static unsigned long sh_cmt_read32(void __iomem *base, unsigned long offs) |
169 | { | |
170 | return ioread32(base + (offs << 2)); | |
171 | } | |
172 | ||
173 | static void sh_cmt_write16(void __iomem *base, unsigned long offs, | |
174 | unsigned long value) | |
587acb3d MD |
175 | { |
176 | iowrite16(value, base + (offs << 1)); | |
177 | } | |
3fb1b6ad | 178 | |
a6a912ca MD |
179 | static void sh_cmt_write32(void __iomem *base, unsigned long offs, |
180 | unsigned long value) | |
181 | { | |
182 | iowrite32(value, base + (offs << 2)); | |
183 | } | |
184 | ||
2cda3ac4 LP |
185 | static const struct sh_cmt_info sh_cmt_info[] = { |
186 | [SH_CMT_16BIT] = { | |
187 | .model = SH_CMT_16BIT, | |
188 | .width = 16, | |
d14be99b LP |
189 | .overflow_bit = SH_CMT16_CMCSR_CMF, |
190 | .clear_bits = ~SH_CMT16_CMCSR_CMF, | |
2cda3ac4 LP |
191 | .read_control = sh_cmt_read16, |
192 | .write_control = sh_cmt_write16, | |
193 | .read_count = sh_cmt_read16, | |
194 | .write_count = sh_cmt_write16, | |
195 | }, | |
196 | [SH_CMT_32BIT] = { | |
197 | .model = SH_CMT_32BIT, | |
198 | .width = 32, | |
d14be99b LP |
199 | .overflow_bit = SH_CMT32_CMCSR_CMF, |
200 | .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), | |
2cda3ac4 LP |
201 | .read_control = sh_cmt_read16, |
202 | .write_control = sh_cmt_write16, | |
203 | .read_count = sh_cmt_read32, | |
204 | .write_count = sh_cmt_write32, | |
205 | }, | |
206 | [SH_CMT_32BIT_FAST] = { | |
207 | .model = SH_CMT_32BIT_FAST, | |
208 | .width = 32, | |
d14be99b LP |
209 | .overflow_bit = SH_CMT32_CMCSR_CMF, |
210 | .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), | |
2cda3ac4 LP |
211 | .read_control = sh_cmt_read16, |
212 | .write_control = sh_cmt_write16, | |
213 | .read_count = sh_cmt_read32, | |
214 | .write_count = sh_cmt_write32, | |
215 | }, | |
216 | [SH_CMT_48BIT] = { | |
217 | .model = SH_CMT_48BIT, | |
464eed84 | 218 | .channels_mask = 0x3f, |
2cda3ac4 | 219 | .width = 32, |
d14be99b LP |
220 | .overflow_bit = SH_CMT32_CMCSR_CMF, |
221 | .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), | |
2cda3ac4 LP |
222 | .read_control = sh_cmt_read32, |
223 | .write_control = sh_cmt_write32, | |
224 | .read_count = sh_cmt_read32, | |
225 | .write_count = sh_cmt_write32, | |
226 | }, | |
83c79a6d MD |
227 | [SH_CMT0_RCAR_GEN2] = { |
228 | .model = SH_CMT0_RCAR_GEN2, | |
229 | .channels_mask = 0x60, | |
230 | .width = 32, | |
231 | .overflow_bit = SH_CMT32_CMCSR_CMF, | |
232 | .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), | |
233 | .read_control = sh_cmt_read32, | |
234 | .write_control = sh_cmt_write32, | |
235 | .read_count = sh_cmt_read32, | |
236 | .write_count = sh_cmt_write32, | |
237 | }, | |
238 | [SH_CMT1_RCAR_GEN2] = { | |
239 | .model = SH_CMT1_RCAR_GEN2, | |
240 | .channels_mask = 0xff, | |
2cda3ac4 | 241 | .width = 32, |
d14be99b LP |
242 | .overflow_bit = SH_CMT32_CMCSR_CMF, |
243 | .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), | |
2cda3ac4 LP |
244 | .read_control = sh_cmt_read32, |
245 | .write_control = sh_cmt_write32, | |
246 | .read_count = sh_cmt_read32, | |
247 | .write_count = sh_cmt_write32, | |
248 | }, | |
249 | }; | |
250 | ||
3fb1b6ad MD |
251 | #define CMCSR 0 /* channel register */ |
252 | #define CMCNT 1 /* channel register */ | |
253 | #define CMCOR 2 /* channel register */ | |
254 | ||
7269f933 | 255 | static inline unsigned long sh_cmt_read_cmstr(struct sh_cmt_channel *ch) |
1b56b96b | 256 | { |
81b3b271 LP |
257 | if (ch->iostart) |
258 | return ch->cmt->info->read_control(ch->iostart, 0); | |
259 | else | |
260 | return ch->cmt->info->read_control(ch->cmt->mapbase, 0); | |
1b56b96b MD |
261 | } |
262 | ||
81b3b271 LP |
263 | static inline void sh_cmt_write_cmstr(struct sh_cmt_channel *ch, |
264 | unsigned long value) | |
1b56b96b | 265 | { |
81b3b271 LP |
266 | if (ch->iostart) |
267 | ch->cmt->info->write_control(ch->iostart, 0, value); | |
268 | else | |
269 | ch->cmt->info->write_control(ch->cmt->mapbase, 0, value); | |
1b56b96b MD |
270 | } |
271 | ||
81b3b271 | 272 | static inline unsigned long sh_cmt_read_cmcsr(struct sh_cmt_channel *ch) |
1b56b96b | 273 | { |
81b3b271 | 274 | return ch->cmt->info->read_control(ch->ioctrl, CMCSR); |
3fb1b6ad MD |
275 | } |
276 | ||
81b3b271 | 277 | static inline void sh_cmt_write_cmcsr(struct sh_cmt_channel *ch, |
1b56b96b MD |
278 | unsigned long value) |
279 | { | |
81b3b271 | 280 | ch->cmt->info->write_control(ch->ioctrl, CMCSR, value); |
1b56b96b MD |
281 | } |
282 | ||
81b3b271 | 283 | static inline unsigned long sh_cmt_read_cmcnt(struct sh_cmt_channel *ch) |
1b56b96b | 284 | { |
81b3b271 | 285 | return ch->cmt->info->read_count(ch->ioctrl, CMCNT); |
1b56b96b MD |
286 | } |
287 | ||
7269f933 | 288 | static inline void sh_cmt_write_cmcnt(struct sh_cmt_channel *ch, |
1b56b96b MD |
289 | unsigned long value) |
290 | { | |
81b3b271 | 291 | ch->cmt->info->write_count(ch->ioctrl, CMCNT, value); |
1b56b96b MD |
292 | } |
293 | ||
7269f933 | 294 | static inline void sh_cmt_write_cmcor(struct sh_cmt_channel *ch, |
1b56b96b MD |
295 | unsigned long value) |
296 | { | |
81b3b271 | 297 | ch->cmt->info->write_count(ch->ioctrl, CMCOR, value); |
1b56b96b MD |
298 | } |
299 | ||
7269f933 | 300 | static unsigned long sh_cmt_get_counter(struct sh_cmt_channel *ch, |
3fb1b6ad MD |
301 | int *has_wrapped) |
302 | { | |
303 | unsigned long v1, v2, v3; | |
5b644c7a MD |
304 | int o1, o2; |
305 | ||
2cda3ac4 | 306 | o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit; |
3fb1b6ad MD |
307 | |
308 | /* Make sure the timer value is stable. Stolen from acpi_pm.c */ | |
309 | do { | |
5b644c7a | 310 | o2 = o1; |
7269f933 LP |
311 | v1 = sh_cmt_read_cmcnt(ch); |
312 | v2 = sh_cmt_read_cmcnt(ch); | |
313 | v3 = sh_cmt_read_cmcnt(ch); | |
2cda3ac4 | 314 | o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit; |
5b644c7a MD |
315 | } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3) |
316 | || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2))); | |
3fb1b6ad | 317 | |
5b644c7a | 318 | *has_wrapped = o1; |
3fb1b6ad MD |
319 | return v2; |
320 | } | |
321 | ||
7269f933 | 322 | static void sh_cmt_start_stop_ch(struct sh_cmt_channel *ch, int start) |
3fb1b6ad | 323 | { |
3fb1b6ad MD |
324 | unsigned long flags, value; |
325 | ||
326 | /* start stop register shared by multiple timer channels */ | |
de599c88 | 327 | raw_spin_lock_irqsave(&ch->cmt->lock, flags); |
7269f933 | 328 | value = sh_cmt_read_cmstr(ch); |
3fb1b6ad MD |
329 | |
330 | if (start) | |
81b3b271 | 331 | value |= 1 << ch->timer_bit; |
3fb1b6ad | 332 | else |
81b3b271 | 333 | value &= ~(1 << ch->timer_bit); |
3fb1b6ad | 334 | |
7269f933 | 335 | sh_cmt_write_cmstr(ch, value); |
de599c88 | 336 | raw_spin_unlock_irqrestore(&ch->cmt->lock, flags); |
3fb1b6ad MD |
337 | } |
338 | ||
890f423b | 339 | static int sh_cmt_enable(struct sh_cmt_channel *ch) |
3fb1b6ad | 340 | { |
3f7e5e24 | 341 | int k, ret; |
3fb1b6ad | 342 | |
7269f933 LP |
343 | pm_runtime_get_sync(&ch->cmt->pdev->dev); |
344 | dev_pm_syscore_device(&ch->cmt->pdev->dev, true); | |
bad81383 | 345 | |
9436b4ab | 346 | /* enable clock */ |
7269f933 | 347 | ret = clk_enable(ch->cmt->clk); |
3fb1b6ad | 348 | if (ret) { |
740a9518 LP |
349 | dev_err(&ch->cmt->pdev->dev, "ch%u: cannot enable clock\n", |
350 | ch->index); | |
3f7e5e24 | 351 | goto err0; |
3fb1b6ad | 352 | } |
3fb1b6ad MD |
353 | |
354 | /* make sure channel is disabled */ | |
7269f933 | 355 | sh_cmt_start_stop_ch(ch, 0); |
3fb1b6ad MD |
356 | |
357 | /* configure channel, periodic mode and maximum timeout */ | |
2cda3ac4 | 358 | if (ch->cmt->info->width == 16) { |
d14be99b LP |
359 | sh_cmt_write_cmcsr(ch, SH_CMT16_CMCSR_CMIE | |
360 | SH_CMT16_CMCSR_CKS512); | |
3014f474 | 361 | } else { |
d14be99b LP |
362 | sh_cmt_write_cmcsr(ch, SH_CMT32_CMCSR_CMM | |
363 | SH_CMT32_CMCSR_CMTOUT_IE | | |
364 | SH_CMT32_CMCSR_CMR_IRQ | | |
365 | SH_CMT32_CMCSR_CKS_RCLK8); | |
3014f474 | 366 | } |
3fb1b6ad | 367 | |
7269f933 LP |
368 | sh_cmt_write_cmcor(ch, 0xffffffff); |
369 | sh_cmt_write_cmcnt(ch, 0); | |
3fb1b6ad | 370 | |
3f7e5e24 MD |
371 | /* |
372 | * According to the sh73a0 user's manual, as CMCNT can be operated | |
373 | * only by the RCLK (Pseudo 32 KHz), there's one restriction on | |
374 | * modifying CMCNT register; two RCLK cycles are necessary before | |
375 | * this register is either read or any modification of the value | |
376 | * it holds is reflected in the LSI's actual operation. | |
377 | * | |
378 | * While at it, we're supposed to clear out the CMCNT as of this | |
379 | * moment, so make sure it's processed properly here. This will | |
380 | * take RCLKx2 at maximum. | |
381 | */ | |
382 | for (k = 0; k < 100; k++) { | |
7269f933 | 383 | if (!sh_cmt_read_cmcnt(ch)) |
3f7e5e24 MD |
384 | break; |
385 | udelay(1); | |
386 | } | |
387 | ||
7269f933 | 388 | if (sh_cmt_read_cmcnt(ch)) { |
740a9518 LP |
389 | dev_err(&ch->cmt->pdev->dev, "ch%u: cannot clear CMCNT\n", |
390 | ch->index); | |
3f7e5e24 MD |
391 | ret = -ETIMEDOUT; |
392 | goto err1; | |
393 | } | |
394 | ||
3fb1b6ad | 395 | /* enable channel */ |
7269f933 | 396 | sh_cmt_start_stop_ch(ch, 1); |
3fb1b6ad | 397 | return 0; |
3f7e5e24 MD |
398 | err1: |
399 | /* stop clock */ | |
7269f933 | 400 | clk_disable(ch->cmt->clk); |
3f7e5e24 MD |
401 | |
402 | err0: | |
403 | return ret; | |
3fb1b6ad MD |
404 | } |
405 | ||
7269f933 | 406 | static void sh_cmt_disable(struct sh_cmt_channel *ch) |
3fb1b6ad MD |
407 | { |
408 | /* disable channel */ | |
7269f933 | 409 | sh_cmt_start_stop_ch(ch, 0); |
3fb1b6ad | 410 | |
be890a1a | 411 | /* disable interrupts in CMT block */ |
7269f933 | 412 | sh_cmt_write_cmcsr(ch, 0); |
be890a1a | 413 | |
9436b4ab | 414 | /* stop clock */ |
7269f933 | 415 | clk_disable(ch->cmt->clk); |
bad81383 | 416 | |
7269f933 LP |
417 | dev_pm_syscore_device(&ch->cmt->pdev->dev, false); |
418 | pm_runtime_put(&ch->cmt->pdev->dev); | |
3fb1b6ad MD |
419 | } |
420 | ||
421 | /* private flags */ | |
422 | #define FLAG_CLOCKEVENT (1 << 0) | |
423 | #define FLAG_CLOCKSOURCE (1 << 1) | |
424 | #define FLAG_REPROGRAM (1 << 2) | |
425 | #define FLAG_SKIPEVENT (1 << 3) | |
426 | #define FLAG_IRQCONTEXT (1 << 4) | |
427 | ||
7269f933 | 428 | static void sh_cmt_clock_event_program_verify(struct sh_cmt_channel *ch, |
3fb1b6ad MD |
429 | int absolute) |
430 | { | |
431 | unsigned long new_match; | |
7269f933 | 432 | unsigned long value = ch->next_match_value; |
3fb1b6ad MD |
433 | unsigned long delay = 0; |
434 | unsigned long now = 0; | |
435 | int has_wrapped; | |
436 | ||
7269f933 LP |
437 | now = sh_cmt_get_counter(ch, &has_wrapped); |
438 | ch->flags |= FLAG_REPROGRAM; /* force reprogram */ | |
3fb1b6ad MD |
439 | |
440 | if (has_wrapped) { | |
441 | /* we're competing with the interrupt handler. | |
442 | * -> let the interrupt handler reprogram the timer. | |
443 | * -> interrupt number two handles the event. | |
444 | */ | |
7269f933 | 445 | ch->flags |= FLAG_SKIPEVENT; |
3fb1b6ad MD |
446 | return; |
447 | } | |
448 | ||
449 | if (absolute) | |
450 | now = 0; | |
451 | ||
452 | do { | |
453 | /* reprogram the timer hardware, | |
454 | * but don't save the new match value yet. | |
455 | */ | |
456 | new_match = now + value + delay; | |
7269f933 LP |
457 | if (new_match > ch->max_match_value) |
458 | new_match = ch->max_match_value; | |
3fb1b6ad | 459 | |
7269f933 | 460 | sh_cmt_write_cmcor(ch, new_match); |
3fb1b6ad | 461 | |
7269f933 LP |
462 | now = sh_cmt_get_counter(ch, &has_wrapped); |
463 | if (has_wrapped && (new_match > ch->match_value)) { | |
3fb1b6ad MD |
464 | /* we are changing to a greater match value, |
465 | * so this wrap must be caused by the counter | |
466 | * matching the old value. | |
467 | * -> first interrupt reprograms the timer. | |
468 | * -> interrupt number two handles the event. | |
469 | */ | |
7269f933 | 470 | ch->flags |= FLAG_SKIPEVENT; |
3fb1b6ad MD |
471 | break; |
472 | } | |
473 | ||
474 | if (has_wrapped) { | |
475 | /* we are changing to a smaller match value, | |
476 | * so the wrap must be caused by the counter | |
477 | * matching the new value. | |
478 | * -> save programmed match value. | |
479 | * -> let isr handle the event. | |
480 | */ | |
7269f933 | 481 | ch->match_value = new_match; |
3fb1b6ad MD |
482 | break; |
483 | } | |
484 | ||
485 | /* be safe: verify hardware settings */ | |
486 | if (now < new_match) { | |
487 | /* timer value is below match value, all good. | |
488 | * this makes sure we won't miss any match events. | |
489 | * -> save programmed match value. | |
490 | * -> let isr handle the event. | |
491 | */ | |
7269f933 | 492 | ch->match_value = new_match; |
3fb1b6ad MD |
493 | break; |
494 | } | |
495 | ||
496 | /* the counter has reached a value greater | |
497 | * than our new match value. and since the | |
498 | * has_wrapped flag isn't set we must have | |
499 | * programmed a too close event. | |
500 | * -> increase delay and retry. | |
501 | */ | |
502 | if (delay) | |
503 | delay <<= 1; | |
504 | else | |
505 | delay = 1; | |
506 | ||
507 | if (!delay) | |
740a9518 LP |
508 | dev_warn(&ch->cmt->pdev->dev, "ch%u: too long delay\n", |
509 | ch->index); | |
3fb1b6ad MD |
510 | |
511 | } while (delay); | |
512 | } | |
513 | ||
7269f933 | 514 | static void __sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta) |
3fb1b6ad | 515 | { |
7269f933 | 516 | if (delta > ch->max_match_value) |
740a9518 LP |
517 | dev_warn(&ch->cmt->pdev->dev, "ch%u: delta out of range\n", |
518 | ch->index); | |
3fb1b6ad | 519 | |
7269f933 LP |
520 | ch->next_match_value = delta; |
521 | sh_cmt_clock_event_program_verify(ch, 0); | |
65ada547 TY |
522 | } |
523 | ||
7269f933 | 524 | static void sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta) |
65ada547 TY |
525 | { |
526 | unsigned long flags; | |
527 | ||
7269f933 LP |
528 | raw_spin_lock_irqsave(&ch->lock, flags); |
529 | __sh_cmt_set_next(ch, delta); | |
530 | raw_spin_unlock_irqrestore(&ch->lock, flags); | |
3fb1b6ad MD |
531 | } |
532 | ||
533 | static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id) | |
534 | { | |
7269f933 | 535 | struct sh_cmt_channel *ch = dev_id; |
3fb1b6ad MD |
536 | |
537 | /* clear flags */ | |
2cda3ac4 LP |
538 | sh_cmt_write_cmcsr(ch, sh_cmt_read_cmcsr(ch) & |
539 | ch->cmt->info->clear_bits); | |
3fb1b6ad MD |
540 | |
541 | /* update clock source counter to begin with if enabled | |
542 | * the wrap flag should be cleared by the timer specific | |
543 | * isr before we end up here. | |
544 | */ | |
7269f933 LP |
545 | if (ch->flags & FLAG_CLOCKSOURCE) |
546 | ch->total_cycles += ch->match_value + 1; | |
3fb1b6ad | 547 | |
7269f933 LP |
548 | if (!(ch->flags & FLAG_REPROGRAM)) |
549 | ch->next_match_value = ch->max_match_value; | |
3fb1b6ad | 550 | |
7269f933 | 551 | ch->flags |= FLAG_IRQCONTEXT; |
3fb1b6ad | 552 | |
7269f933 LP |
553 | if (ch->flags & FLAG_CLOCKEVENT) { |
554 | if (!(ch->flags & FLAG_SKIPEVENT)) { | |
051b782e | 555 | if (clockevent_state_oneshot(&ch->ced)) { |
7269f933 LP |
556 | ch->next_match_value = ch->max_match_value; |
557 | ch->flags |= FLAG_REPROGRAM; | |
3fb1b6ad MD |
558 | } |
559 | ||
7269f933 | 560 | ch->ced.event_handler(&ch->ced); |
3fb1b6ad MD |
561 | } |
562 | } | |
563 | ||
7269f933 | 564 | ch->flags &= ~FLAG_SKIPEVENT; |
3fb1b6ad | 565 | |
7269f933 LP |
566 | if (ch->flags & FLAG_REPROGRAM) { |
567 | ch->flags &= ~FLAG_REPROGRAM; | |
568 | sh_cmt_clock_event_program_verify(ch, 1); | |
3fb1b6ad | 569 | |
7269f933 | 570 | if (ch->flags & FLAG_CLOCKEVENT) |
051b782e | 571 | if ((clockevent_state_shutdown(&ch->ced)) |
7269f933 LP |
572 | || (ch->match_value == ch->next_match_value)) |
573 | ch->flags &= ~FLAG_REPROGRAM; | |
3fb1b6ad MD |
574 | } |
575 | ||
7269f933 | 576 | ch->flags &= ~FLAG_IRQCONTEXT; |
3fb1b6ad MD |
577 | |
578 | return IRQ_HANDLED; | |
579 | } | |
580 | ||
7269f933 | 581 | static int sh_cmt_start(struct sh_cmt_channel *ch, unsigned long flag) |
3fb1b6ad MD |
582 | { |
583 | int ret = 0; | |
584 | unsigned long flags; | |
585 | ||
7269f933 | 586 | raw_spin_lock_irqsave(&ch->lock, flags); |
3fb1b6ad | 587 | |
7269f933 | 588 | if (!(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) |
890f423b | 589 | ret = sh_cmt_enable(ch); |
3fb1b6ad MD |
590 | |
591 | if (ret) | |
592 | goto out; | |
7269f933 | 593 | ch->flags |= flag; |
3fb1b6ad MD |
594 | |
595 | /* setup timeout if no clockevent */ | |
7269f933 LP |
596 | if ((flag == FLAG_CLOCKSOURCE) && (!(ch->flags & FLAG_CLOCKEVENT))) |
597 | __sh_cmt_set_next(ch, ch->max_match_value); | |
3fb1b6ad | 598 | out: |
7269f933 | 599 | raw_spin_unlock_irqrestore(&ch->lock, flags); |
3fb1b6ad MD |
600 | |
601 | return ret; | |
602 | } | |
603 | ||
7269f933 | 604 | static void sh_cmt_stop(struct sh_cmt_channel *ch, unsigned long flag) |
3fb1b6ad MD |
605 | { |
606 | unsigned long flags; | |
607 | unsigned long f; | |
608 | ||
7269f933 | 609 | raw_spin_lock_irqsave(&ch->lock, flags); |
3fb1b6ad | 610 | |
7269f933 LP |
611 | f = ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE); |
612 | ch->flags &= ~flag; | |
3fb1b6ad | 613 | |
7269f933 LP |
614 | if (f && !(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) |
615 | sh_cmt_disable(ch); | |
3fb1b6ad MD |
616 | |
617 | /* adjust the timeout to maximum if only clocksource left */ | |
7269f933 LP |
618 | if ((flag == FLAG_CLOCKEVENT) && (ch->flags & FLAG_CLOCKSOURCE)) |
619 | __sh_cmt_set_next(ch, ch->max_match_value); | |
3fb1b6ad | 620 | |
7269f933 | 621 | raw_spin_unlock_irqrestore(&ch->lock, flags); |
3fb1b6ad MD |
622 | } |
623 | ||
7269f933 | 624 | static struct sh_cmt_channel *cs_to_sh_cmt(struct clocksource *cs) |
19bdc9d0 | 625 | { |
7269f933 | 626 | return container_of(cs, struct sh_cmt_channel, cs); |
19bdc9d0 MD |
627 | } |
628 | ||
a5a1d1c2 | 629 | static u64 sh_cmt_clocksource_read(struct clocksource *cs) |
19bdc9d0 | 630 | { |
7269f933 | 631 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
19bdc9d0 MD |
632 | unsigned long flags, raw; |
633 | unsigned long value; | |
634 | int has_wrapped; | |
635 | ||
7269f933 LP |
636 | raw_spin_lock_irqsave(&ch->lock, flags); |
637 | value = ch->total_cycles; | |
638 | raw = sh_cmt_get_counter(ch, &has_wrapped); | |
19bdc9d0 MD |
639 | |
640 | if (unlikely(has_wrapped)) | |
7269f933 LP |
641 | raw += ch->match_value + 1; |
642 | raw_spin_unlock_irqrestore(&ch->lock, flags); | |
19bdc9d0 MD |
643 | |
644 | return value + raw; | |
645 | } | |
646 | ||
647 | static int sh_cmt_clocksource_enable(struct clocksource *cs) | |
648 | { | |
3593f5fe | 649 | int ret; |
7269f933 | 650 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
19bdc9d0 | 651 | |
7269f933 | 652 | WARN_ON(ch->cs_enabled); |
bad81383 | 653 | |
7269f933 | 654 | ch->total_cycles = 0; |
19bdc9d0 | 655 | |
7269f933 | 656 | ret = sh_cmt_start(ch, FLAG_CLOCKSOURCE); |
890f423b | 657 | if (!ret) |
7269f933 | 658 | ch->cs_enabled = true; |
890f423b | 659 | |
3593f5fe | 660 | return ret; |
19bdc9d0 MD |
661 | } |
662 | ||
663 | static void sh_cmt_clocksource_disable(struct clocksource *cs) | |
664 | { | |
7269f933 | 665 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
bad81383 | 666 | |
7269f933 | 667 | WARN_ON(!ch->cs_enabled); |
bad81383 | 668 | |
7269f933 LP |
669 | sh_cmt_stop(ch, FLAG_CLOCKSOURCE); |
670 | ch->cs_enabled = false; | |
19bdc9d0 MD |
671 | } |
672 | ||
9bb5ec88 RW |
673 | static void sh_cmt_clocksource_suspend(struct clocksource *cs) |
674 | { | |
7269f933 | 675 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
9bb5ec88 | 676 | |
54d46b7f GU |
677 | if (!ch->cs_enabled) |
678 | return; | |
679 | ||
7269f933 LP |
680 | sh_cmt_stop(ch, FLAG_CLOCKSOURCE); |
681 | pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev); | |
9bb5ec88 RW |
682 | } |
683 | ||
c8162884 MD |
684 | static void sh_cmt_clocksource_resume(struct clocksource *cs) |
685 | { | |
7269f933 | 686 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
9bb5ec88 | 687 | |
54d46b7f GU |
688 | if (!ch->cs_enabled) |
689 | return; | |
690 | ||
7269f933 LP |
691 | pm_genpd_syscore_poweron(&ch->cmt->pdev->dev); |
692 | sh_cmt_start(ch, FLAG_CLOCKSOURCE); | |
c8162884 MD |
693 | } |
694 | ||
7269f933 | 695 | static int sh_cmt_register_clocksource(struct sh_cmt_channel *ch, |
fb28a659 | 696 | const char *name) |
19bdc9d0 | 697 | { |
7269f933 | 698 | struct clocksource *cs = &ch->cs; |
19bdc9d0 MD |
699 | |
700 | cs->name = name; | |
fb28a659 | 701 | cs->rating = 125; |
19bdc9d0 MD |
702 | cs->read = sh_cmt_clocksource_read; |
703 | cs->enable = sh_cmt_clocksource_enable; | |
704 | cs->disable = sh_cmt_clocksource_disable; | |
9bb5ec88 | 705 | cs->suspend = sh_cmt_clocksource_suspend; |
c8162884 | 706 | cs->resume = sh_cmt_clocksource_resume; |
19bdc9d0 MD |
707 | cs->mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8); |
708 | cs->flags = CLOCK_SOURCE_IS_CONTINUOUS; | |
f4d7c356 | 709 | |
740a9518 LP |
710 | dev_info(&ch->cmt->pdev->dev, "ch%u: used as clock source\n", |
711 | ch->index); | |
f4d7c356 | 712 | |
890f423b | 713 | clocksource_register_hz(cs, ch->cmt->rate); |
19bdc9d0 MD |
714 | return 0; |
715 | } | |
716 | ||
7269f933 | 717 | static struct sh_cmt_channel *ced_to_sh_cmt(struct clock_event_device *ced) |
3fb1b6ad | 718 | { |
7269f933 | 719 | return container_of(ced, struct sh_cmt_channel, ced); |
3fb1b6ad MD |
720 | } |
721 | ||
7269f933 | 722 | static void sh_cmt_clock_event_start(struct sh_cmt_channel *ch, int periodic) |
3fb1b6ad | 723 | { |
7269f933 | 724 | sh_cmt_start(ch, FLAG_CLOCKEVENT); |
3fb1b6ad | 725 | |
3fb1b6ad | 726 | if (periodic) |
890f423b | 727 | sh_cmt_set_next(ch, ((ch->cmt->rate + HZ/2) / HZ) - 1); |
3fb1b6ad | 728 | else |
7269f933 | 729 | sh_cmt_set_next(ch, ch->max_match_value); |
3fb1b6ad MD |
730 | } |
731 | ||
051b782e VK |
732 | static int sh_cmt_clock_event_shutdown(struct clock_event_device *ced) |
733 | { | |
734 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); | |
735 | ||
736 | sh_cmt_stop(ch, FLAG_CLOCKEVENT); | |
737 | return 0; | |
738 | } | |
739 | ||
740 | static int sh_cmt_clock_event_set_state(struct clock_event_device *ced, | |
741 | int periodic) | |
3fb1b6ad | 742 | { |
7269f933 | 743 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); |
3fb1b6ad MD |
744 | |
745 | /* deal with old setting first */ | |
051b782e | 746 | if (clockevent_state_oneshot(ced) || clockevent_state_periodic(ced)) |
7269f933 | 747 | sh_cmt_stop(ch, FLAG_CLOCKEVENT); |
3fb1b6ad | 748 | |
051b782e VK |
749 | dev_info(&ch->cmt->pdev->dev, "ch%u: used for %s clock events\n", |
750 | ch->index, periodic ? "periodic" : "oneshot"); | |
751 | sh_cmt_clock_event_start(ch, periodic); | |
752 | return 0; | |
753 | } | |
754 | ||
755 | static int sh_cmt_clock_event_set_oneshot(struct clock_event_device *ced) | |
756 | { | |
757 | return sh_cmt_clock_event_set_state(ced, 0); | |
758 | } | |
759 | ||
760 | static int sh_cmt_clock_event_set_periodic(struct clock_event_device *ced) | |
761 | { | |
762 | return sh_cmt_clock_event_set_state(ced, 1); | |
3fb1b6ad MD |
763 | } |
764 | ||
765 | static int sh_cmt_clock_event_next(unsigned long delta, | |
766 | struct clock_event_device *ced) | |
767 | { | |
7269f933 | 768 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); |
3fb1b6ad | 769 | |
051b782e | 770 | BUG_ON(!clockevent_state_oneshot(ced)); |
7269f933 LP |
771 | if (likely(ch->flags & FLAG_IRQCONTEXT)) |
772 | ch->next_match_value = delta - 1; | |
3fb1b6ad | 773 | else |
7269f933 | 774 | sh_cmt_set_next(ch, delta - 1); |
3fb1b6ad MD |
775 | |
776 | return 0; | |
777 | } | |
778 | ||
9bb5ec88 RW |
779 | static void sh_cmt_clock_event_suspend(struct clock_event_device *ced) |
780 | { | |
7269f933 | 781 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); |
57dee992 | 782 | |
7269f933 LP |
783 | pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev); |
784 | clk_unprepare(ch->cmt->clk); | |
9bb5ec88 RW |
785 | } |
786 | ||
787 | static void sh_cmt_clock_event_resume(struct clock_event_device *ced) | |
788 | { | |
7269f933 | 789 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); |
57dee992 | 790 | |
7269f933 LP |
791 | clk_prepare(ch->cmt->clk); |
792 | pm_genpd_syscore_poweron(&ch->cmt->pdev->dev); | |
9bb5ec88 RW |
793 | } |
794 | ||
bfa76bb1 LP |
795 | static int sh_cmt_register_clockevent(struct sh_cmt_channel *ch, |
796 | const char *name) | |
3fb1b6ad | 797 | { |
7269f933 | 798 | struct clock_event_device *ced = &ch->ced; |
bfa76bb1 LP |
799 | int irq; |
800 | int ret; | |
801 | ||
31e912f5 | 802 | irq = platform_get_irq(ch->cmt->pdev, ch->index); |
bfa76bb1 LP |
803 | if (irq < 0) { |
804 | dev_err(&ch->cmt->pdev->dev, "ch%u: failed to get irq\n", | |
805 | ch->index); | |
806 | return irq; | |
807 | } | |
808 | ||
809 | ret = request_irq(irq, sh_cmt_interrupt, | |
810 | IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING, | |
811 | dev_name(&ch->cmt->pdev->dev), ch); | |
812 | if (ret) { | |
813 | dev_err(&ch->cmt->pdev->dev, "ch%u: failed to request irq %d\n", | |
814 | ch->index, irq); | |
815 | return ret; | |
816 | } | |
3fb1b6ad | 817 | |
3fb1b6ad MD |
818 | ced->name = name; |
819 | ced->features = CLOCK_EVT_FEAT_PERIODIC; | |
820 | ced->features |= CLOCK_EVT_FEAT_ONESHOT; | |
b7fcbb0f | 821 | ced->rating = 125; |
f1ebe1e4 | 822 | ced->cpumask = cpu_possible_mask; |
3fb1b6ad | 823 | ced->set_next_event = sh_cmt_clock_event_next; |
051b782e VK |
824 | ced->set_state_shutdown = sh_cmt_clock_event_shutdown; |
825 | ced->set_state_periodic = sh_cmt_clock_event_set_periodic; | |
826 | ced->set_state_oneshot = sh_cmt_clock_event_set_oneshot; | |
9bb5ec88 RW |
827 | ced->suspend = sh_cmt_clock_event_suspend; |
828 | ced->resume = sh_cmt_clock_event_resume; | |
3fb1b6ad | 829 | |
890f423b NS |
830 | /* TODO: calculate good shift from rate and counter bit width */ |
831 | ced->shift = 32; | |
832 | ced->mult = div_sc(ch->cmt->rate, NSEC_PER_SEC, ced->shift); | |
833 | ced->max_delta_ns = clockevent_delta2ns(ch->max_match_value, ced); | |
bb2e94ac | 834 | ced->max_delta_ticks = ch->max_match_value; |
890f423b | 835 | ced->min_delta_ns = clockevent_delta2ns(0x1f, ced); |
bb2e94ac | 836 | ced->min_delta_ticks = 0x1f; |
890f423b | 837 | |
740a9518 LP |
838 | dev_info(&ch->cmt->pdev->dev, "ch%u: used for clock events\n", |
839 | ch->index); | |
3fb1b6ad | 840 | clockevents_register_device(ced); |
bfa76bb1 LP |
841 | |
842 | return 0; | |
3fb1b6ad MD |
843 | } |
844 | ||
1d053e1d | 845 | static int sh_cmt_register(struct sh_cmt_channel *ch, const char *name, |
fb28a659 | 846 | bool clockevent, bool clocksource) |
3fb1b6ad | 847 | { |
bfa76bb1 LP |
848 | int ret; |
849 | ||
81b3b271 LP |
850 | if (clockevent) { |
851 | ch->cmt->has_clockevent = true; | |
bfa76bb1 LP |
852 | ret = sh_cmt_register_clockevent(ch, name); |
853 | if (ret < 0) | |
854 | return ret; | |
81b3b271 | 855 | } |
3fb1b6ad | 856 | |
81b3b271 LP |
857 | if (clocksource) { |
858 | ch->cmt->has_clocksource = true; | |
fb28a659 | 859 | sh_cmt_register_clocksource(ch, name); |
81b3b271 | 860 | } |
19bdc9d0 | 861 | |
3fb1b6ad MD |
862 | return 0; |
863 | } | |
864 | ||
740a9518 | 865 | static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index, |
81b3b271 LP |
866 | unsigned int hwidx, bool clockevent, |
867 | bool clocksource, struct sh_cmt_device *cmt) | |
b882e7b1 | 868 | { |
b882e7b1 LP |
869 | int ret; |
870 | ||
81b3b271 LP |
871 | /* Skip unused channels. */ |
872 | if (!clockevent && !clocksource) | |
873 | return 0; | |
874 | ||
b882e7b1 | 875 | ch->cmt = cmt; |
740a9518 | 876 | ch->index = index; |
81b3b271 | 877 | ch->hwidx = hwidx; |
83c79a6d | 878 | ch->timer_bit = hwidx; |
81b3b271 LP |
879 | |
880 | /* | |
881 | * Compute the address of the channel control register block. For the | |
882 | * timers with a per-channel start/stop register, compute its address | |
883 | * as well. | |
81b3b271 | 884 | */ |
31e912f5 LP |
885 | switch (cmt->info->model) { |
886 | case SH_CMT_16BIT: | |
887 | ch->ioctrl = cmt->mapbase + 2 + ch->hwidx * 6; | |
888 | break; | |
889 | case SH_CMT_32BIT: | |
890 | case SH_CMT_48BIT: | |
891 | ch->ioctrl = cmt->mapbase + 0x10 + ch->hwidx * 0x10; | |
892 | break; | |
893 | case SH_CMT_32BIT_FAST: | |
894 | /* | |
895 | * The 32-bit "fast" timer has a single channel at hwidx 5 but | |
896 | * is located at offset 0x40 instead of 0x60 for some reason. | |
897 | */ | |
898 | ch->ioctrl = cmt->mapbase + 0x40; | |
899 | break; | |
83c79a6d MD |
900 | case SH_CMT0_RCAR_GEN2: |
901 | case SH_CMT1_RCAR_GEN2: | |
31e912f5 LP |
902 | ch->iostart = cmt->mapbase + ch->hwidx * 0x100; |
903 | ch->ioctrl = ch->iostart + 0x10; | |
83c79a6d | 904 | ch->timer_bit = 0; |
31e912f5 | 905 | break; |
81b3b271 LP |
906 | } |
907 | ||
2cda3ac4 | 908 | if (cmt->info->width == (sizeof(ch->max_match_value) * 8)) |
b882e7b1 LP |
909 | ch->max_match_value = ~0; |
910 | else | |
2cda3ac4 | 911 | ch->max_match_value = (1 << cmt->info->width) - 1; |
b882e7b1 LP |
912 | |
913 | ch->match_value = ch->max_match_value; | |
914 | raw_spin_lock_init(&ch->lock); | |
915 | ||
1d053e1d | 916 | ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev), |
81b3b271 | 917 | clockevent, clocksource); |
b882e7b1 | 918 | if (ret) { |
740a9518 LP |
919 | dev_err(&cmt->pdev->dev, "ch%u: registration failed\n", |
920 | ch->index); | |
b882e7b1 LP |
921 | return ret; |
922 | } | |
923 | ch->cs_enabled = false; | |
924 | ||
b882e7b1 LP |
925 | return 0; |
926 | } | |
927 | ||
81b3b271 | 928 | static int sh_cmt_map_memory(struct sh_cmt_device *cmt) |
3fb1b6ad | 929 | { |
81b3b271 | 930 | struct resource *mem; |
3fb1b6ad | 931 | |
81b3b271 LP |
932 | mem = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 0); |
933 | if (!mem) { | |
934 | dev_err(&cmt->pdev->dev, "failed to get I/O memory\n"); | |
935 | return -ENXIO; | |
936 | } | |
3fb1b6ad | 937 | |
81b3b271 LP |
938 | cmt->mapbase = ioremap_nocache(mem->start, resource_size(mem)); |
939 | if (cmt->mapbase == NULL) { | |
940 | dev_err(&cmt->pdev->dev, "failed to remap I/O memory\n"); | |
941 | return -ENXIO; | |
3fb1b6ad MD |
942 | } |
943 | ||
81b3b271 LP |
944 | return 0; |
945 | } | |
946 | ||
1768aa2f LP |
947 | static const struct platform_device_id sh_cmt_id_table[] = { |
948 | { "sh-cmt-16", (kernel_ulong_t)&sh_cmt_info[SH_CMT_16BIT] }, | |
949 | { "sh-cmt-32", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT] }, | |
1768aa2f LP |
950 | { } |
951 | }; | |
952 | MODULE_DEVICE_TABLE(platform, sh_cmt_id_table); | |
953 | ||
954 | static const struct of_device_id sh_cmt_of_table[] __maybe_unused = { | |
955 | { .compatible = "renesas,cmt-32", .data = &sh_cmt_info[SH_CMT_32BIT] }, | |
956 | { .compatible = "renesas,cmt-32-fast", .data = &sh_cmt_info[SH_CMT_32BIT_FAST] }, | |
957 | { .compatible = "renesas,cmt-48", .data = &sh_cmt_info[SH_CMT_48BIT] }, | |
83c79a6d MD |
958 | { .compatible = "renesas,cmt-48-gen2", .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2] }, |
959 | { .compatible = "renesas,rcar-gen2-cmt0", .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2] }, | |
960 | { .compatible = "renesas,rcar-gen2-cmt1", .data = &sh_cmt_info[SH_CMT1_RCAR_GEN2] }, | |
1768aa2f LP |
961 | { } |
962 | }; | |
963 | MODULE_DEVICE_TABLE(of, sh_cmt_of_table); | |
964 | ||
965 | static int sh_cmt_parse_dt(struct sh_cmt_device *cmt) | |
966 | { | |
967 | struct device_node *np = cmt->pdev->dev.of_node; | |
968 | ||
969 | return of_property_read_u32(np, "renesas,channels-mask", | |
970 | &cmt->hw_channels); | |
971 | } | |
972 | ||
81b3b271 LP |
973 | static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev) |
974 | { | |
31e912f5 LP |
975 | unsigned int mask; |
976 | unsigned int i; | |
81b3b271 LP |
977 | int ret; |
978 | ||
81b3b271 | 979 | cmt->pdev = pdev; |
de599c88 | 980 | raw_spin_lock_init(&cmt->lock); |
81b3b271 | 981 | |
1768aa2f LP |
982 | if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) { |
983 | const struct of_device_id *id; | |
984 | ||
985 | id = of_match_node(sh_cmt_of_table, pdev->dev.of_node); | |
986 | cmt->info = id->data; | |
987 | ||
464eed84 MD |
988 | /* prefer in-driver channel configuration over DT */ |
989 | if (cmt->info->channels_mask) { | |
990 | cmt->hw_channels = cmt->info->channels_mask; | |
991 | } else { | |
992 | ret = sh_cmt_parse_dt(cmt); | |
993 | if (ret < 0) | |
994 | return ret; | |
995 | } | |
1768aa2f LP |
996 | } else if (pdev->dev.platform_data) { |
997 | struct sh_timer_config *cfg = pdev->dev.platform_data; | |
998 | const struct platform_device_id *id = pdev->id_entry; | |
999 | ||
1000 | cmt->info = (const struct sh_cmt_info *)id->driver_data; | |
1001 | cmt->hw_channels = cfg->channels_mask; | |
1002 | } else { | |
81b3b271 LP |
1003 | dev_err(&cmt->pdev->dev, "missing platform data\n"); |
1004 | return -ENXIO; | |
1005 | } | |
1006 | ||
81b3b271 | 1007 | /* Get hold of clock. */ |
31e912f5 | 1008 | cmt->clk = clk_get(&cmt->pdev->dev, "fck"); |
2653caf4 LP |
1009 | if (IS_ERR(cmt->clk)) { |
1010 | dev_err(&cmt->pdev->dev, "cannot get clock\n"); | |
81b3b271 | 1011 | return PTR_ERR(cmt->clk); |
3fb1b6ad MD |
1012 | } |
1013 | ||
2653caf4 | 1014 | ret = clk_prepare(cmt->clk); |
57dee992 | 1015 | if (ret < 0) |
81b3b271 | 1016 | goto err_clk_put; |
57dee992 | 1017 | |
890f423b NS |
1018 | /* Determine clock rate. */ |
1019 | ret = clk_enable(cmt->clk); | |
1020 | if (ret < 0) | |
1021 | goto err_clk_unprepare; | |
1022 | ||
1023 | if (cmt->info->width == 16) | |
1024 | cmt->rate = clk_get_rate(cmt->clk) / 512; | |
1025 | else | |
1026 | cmt->rate = clk_get_rate(cmt->clk) / 8; | |
1027 | ||
1028 | clk_disable(cmt->clk); | |
1029 | ||
31e912f5 LP |
1030 | /* Map the memory resource(s). */ |
1031 | ret = sh_cmt_map_memory(cmt); | |
81b3b271 LP |
1032 | if (ret < 0) |
1033 | goto err_clk_unprepare; | |
1034 | ||
1035 | /* Allocate and setup the channels. */ | |
1768aa2f | 1036 | cmt->num_channels = hweight8(cmt->hw_channels); |
81b3b271 LP |
1037 | cmt->channels = kzalloc(cmt->num_channels * sizeof(*cmt->channels), |
1038 | GFP_KERNEL); | |
f5ec9b19 LP |
1039 | if (cmt->channels == NULL) { |
1040 | ret = -ENOMEM; | |
81b3b271 | 1041 | goto err_unmap; |
f5ec9b19 LP |
1042 | } |
1043 | ||
31e912f5 LP |
1044 | /* |
1045 | * Use the first channel as a clock event device and the second channel | |
1046 | * as a clock source. If only one channel is available use it for both. | |
1047 | */ | |
1768aa2f | 1048 | for (i = 0, mask = cmt->hw_channels; i < cmt->num_channels; ++i) { |
31e912f5 LP |
1049 | unsigned int hwidx = ffs(mask) - 1; |
1050 | bool clocksource = i == 1 || cmt->num_channels == 1; | |
1051 | bool clockevent = i == 0; | |
1052 | ||
1053 | ret = sh_cmt_setup_channel(&cmt->channels[i], i, hwidx, | |
1054 | clockevent, clocksource, cmt); | |
81b3b271 LP |
1055 | if (ret < 0) |
1056 | goto err_unmap; | |
f5ec9b19 | 1057 | |
31e912f5 | 1058 | mask &= ~(1 << hwidx); |
81b3b271 | 1059 | } |
da64c2a8 | 1060 | |
2653caf4 | 1061 | platform_set_drvdata(pdev, cmt); |
adccc69e | 1062 | |
da64c2a8 | 1063 | return 0; |
81b3b271 LP |
1064 | |
1065 | err_unmap: | |
f5ec9b19 | 1066 | kfree(cmt->channels); |
31e912f5 | 1067 | iounmap(cmt->mapbase); |
81b3b271 | 1068 | err_clk_unprepare: |
2653caf4 | 1069 | clk_unprepare(cmt->clk); |
81b3b271 | 1070 | err_clk_put: |
2653caf4 | 1071 | clk_put(cmt->clk); |
3fb1b6ad MD |
1072 | return ret; |
1073 | } | |
1074 | ||
1850514b | 1075 | static int sh_cmt_probe(struct platform_device *pdev) |
3fb1b6ad | 1076 | { |
2653caf4 | 1077 | struct sh_cmt_device *cmt = platform_get_drvdata(pdev); |
3fb1b6ad MD |
1078 | int ret; |
1079 | ||
9bb5ec88 | 1080 | if (!is_early_platform_device(pdev)) { |
bad81383 RW |
1081 | pm_runtime_set_active(&pdev->dev); |
1082 | pm_runtime_enable(&pdev->dev); | |
9bb5ec88 | 1083 | } |
615a445f | 1084 | |
2653caf4 | 1085 | if (cmt) { |
214a607a | 1086 | dev_info(&pdev->dev, "kept as earlytimer\n"); |
bad81383 | 1087 | goto out; |
e475eedb MD |
1088 | } |
1089 | ||
b262bc74 | 1090 | cmt = kzalloc(sizeof(*cmt), GFP_KERNEL); |
0178f41d | 1091 | if (cmt == NULL) |
3fb1b6ad | 1092 | return -ENOMEM; |
3fb1b6ad | 1093 | |
2653caf4 | 1094 | ret = sh_cmt_setup(cmt, pdev); |
3fb1b6ad | 1095 | if (ret) { |
2653caf4 | 1096 | kfree(cmt); |
bad81383 RW |
1097 | pm_runtime_idle(&pdev->dev); |
1098 | return ret; | |
3fb1b6ad | 1099 | } |
bad81383 RW |
1100 | if (is_early_platform_device(pdev)) |
1101 | return 0; | |
1102 | ||
1103 | out: | |
81b3b271 | 1104 | if (cmt->has_clockevent || cmt->has_clocksource) |
bad81383 RW |
1105 | pm_runtime_irq_safe(&pdev->dev); |
1106 | else | |
1107 | pm_runtime_idle(&pdev->dev); | |
1108 | ||
1109 | return 0; | |
3fb1b6ad MD |
1110 | } |
1111 | ||
1850514b | 1112 | static int sh_cmt_remove(struct platform_device *pdev) |
3fb1b6ad MD |
1113 | { |
1114 | return -EBUSY; /* cannot unregister clockevent and clocksource */ | |
1115 | } | |
1116 | ||
1117 | static struct platform_driver sh_cmt_device_driver = { | |
1118 | .probe = sh_cmt_probe, | |
1850514b | 1119 | .remove = sh_cmt_remove, |
3fb1b6ad MD |
1120 | .driver = { |
1121 | .name = "sh_cmt", | |
1768aa2f | 1122 | .of_match_table = of_match_ptr(sh_cmt_of_table), |
81b3b271 LP |
1123 | }, |
1124 | .id_table = sh_cmt_id_table, | |
3fb1b6ad MD |
1125 | }; |
1126 | ||
1127 | static int __init sh_cmt_init(void) | |
1128 | { | |
1129 | return platform_driver_register(&sh_cmt_device_driver); | |
1130 | } | |
1131 | ||
1132 | static void __exit sh_cmt_exit(void) | |
1133 | { | |
1134 | platform_driver_unregister(&sh_cmt_device_driver); | |
1135 | } | |
1136 | ||
e475eedb | 1137 | early_platform_init("earlytimer", &sh_cmt_device_driver); |
e903a031 | 1138 | subsys_initcall(sh_cmt_init); |
3fb1b6ad MD |
1139 | module_exit(sh_cmt_exit); |
1140 | ||
1141 | MODULE_AUTHOR("Magnus Damm"); | |
1142 | MODULE_DESCRIPTION("SuperH CMT Timer Driver"); | |
1143 | MODULE_LICENSE("GPL v2"); |