Commit | Line | Data |
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efad0117 | 1 | // SPDX-License-Identifier: GPL-2.0 |
3fb1b6ad MD |
2 | /* |
3 | * SuperH Timer Support - CMT | |
4 | * | |
5 | * Copyright (C) 2008 Magnus Damm | |
3fb1b6ad MD |
6 | */ |
7 | ||
e7a9bcc2 LP |
8 | #include <linux/clk.h> |
9 | #include <linux/clockchips.h> | |
10 | #include <linux/clocksource.h> | |
11 | #include <linux/delay.h> | |
12 | #include <linux/err.h> | |
3fb1b6ad | 13 | #include <linux/init.h> |
3fb1b6ad | 14 | #include <linux/interrupt.h> |
3fb1b6ad | 15 | #include <linux/io.h> |
3f44f715 | 16 | #include <linux/iopoll.h> |
e7a9bcc2 | 17 | #include <linux/ioport.h> |
3fb1b6ad | 18 | #include <linux/irq.h> |
7deeab5d | 19 | #include <linux/module.h> |
1768aa2f | 20 | #include <linux/of.h> |
2d1d5172 | 21 | #include <linux/of_device.h> |
e7a9bcc2 | 22 | #include <linux/platform_device.h> |
615a445f | 23 | #include <linux/pm_domain.h> |
bad81383 | 24 | #include <linux/pm_runtime.h> |
e7a9bcc2 LP |
25 | #include <linux/sh_timer.h> |
26 | #include <linux/slab.h> | |
27 | #include <linux/spinlock.h> | |
3fb1b6ad | 28 | |
507fd01d BG |
29 | #ifdef CONFIG_SUPERH |
30 | #include <asm/platform_early.h> | |
31 | #endif | |
32 | ||
2653caf4 | 33 | struct sh_cmt_device; |
7269f933 | 34 | |
2cda3ac4 LP |
35 | /* |
36 | * The CMT comes in 5 different identified flavours, depending not only on the | |
37 | * SoC but also on the particular instance. The following table lists the main | |
38 | * characteristics of those flavours. | |
39 | * | |
83c79a6d | 40 | * 16B 32B 32B-F 48B R-Car Gen2 |
2cda3ac4 LP |
41 | * ----------------------------------------------------------------------------- |
42 | * Channels 2 1/4 1 6 2/8 | |
43 | * Control Width 16 16 16 16 32 | |
44 | * Counter Width 16 32 32 32/48 32/48 | |
45 | * Shared Start/Stop Y Y Y Y N | |
46 | * | |
83c79a6d MD |
47 | * The r8a73a4 / R-Car Gen2 version has a per-channel start/stop register |
48 | * located in the channel registers block. All other versions have a shared | |
49 | * start/stop register located in the global space. | |
2cda3ac4 | 50 | * |
81b3b271 LP |
51 | * Channels are indexed from 0 to N-1 in the documentation. The channel index |
52 | * infers the start/stop bit position in the control register and the channel | |
53 | * registers block address. Some CMT instances have a subset of channels | |
54 | * available, in which case the index in the documentation doesn't match the | |
55 | * "real" index as implemented in hardware. This is for instance the case with | |
56 | * CMT0 on r8a7740, which is a 32-bit variant with a single channel numbered 0 | |
57 | * in the documentation but using start/stop bit 5 and having its registers | |
58 | * block at 0x60. | |
59 | * | |
60 | * Similarly CMT0 on r8a73a4, r8a7790 and r8a7791, while implementing 32-bit | |
2cda3ac4 LP |
61 | * channels only, is a 48-bit gen2 CMT with the 48-bit channels unavailable. |
62 | */ | |
63 | ||
64 | enum sh_cmt_model { | |
65 | SH_CMT_16BIT, | |
66 | SH_CMT_32BIT, | |
2cda3ac4 | 67 | SH_CMT_48BIT, |
83c79a6d MD |
68 | SH_CMT0_RCAR_GEN2, |
69 | SH_CMT1_RCAR_GEN2, | |
2cda3ac4 LP |
70 | }; |
71 | ||
72 | struct sh_cmt_info { | |
73 | enum sh_cmt_model model; | |
74 | ||
464eed84 MD |
75 | unsigned int channels_mask; |
76 | ||
2cda3ac4 | 77 | unsigned long width; /* 16 or 32 bit version of hardware block */ |
22627c6f SS |
78 | u32 overflow_bit; |
79 | u32 clear_bits; | |
2cda3ac4 LP |
80 | |
81 | /* callbacks for CMSTR and CMCSR access */ | |
22627c6f | 82 | u32 (*read_control)(void __iomem *base, unsigned long offs); |
2cda3ac4 | 83 | void (*write_control)(void __iomem *base, unsigned long offs, |
22627c6f | 84 | u32 value); |
2cda3ac4 LP |
85 | |
86 | /* callbacks for CMCNT and CMCOR access */ | |
22627c6f SS |
87 | u32 (*read_count)(void __iomem *base, unsigned long offs); |
88 | void (*write_count)(void __iomem *base, unsigned long offs, u32 value); | |
2cda3ac4 LP |
89 | }; |
90 | ||
7269f933 | 91 | struct sh_cmt_channel { |
2653caf4 | 92 | struct sh_cmt_device *cmt; |
3fb1b6ad | 93 | |
81b3b271 LP |
94 | unsigned int index; /* Index in the documentation */ |
95 | unsigned int hwidx; /* Real hardware index */ | |
96 | ||
97 | void __iomem *iostart; | |
98 | void __iomem *ioctrl; | |
c924d2d2 | 99 | |
81b3b271 | 100 | unsigned int timer_bit; |
3fb1b6ad | 101 | unsigned long flags; |
22627c6f SS |
102 | u32 match_value; |
103 | u32 next_match_value; | |
104 | u32 max_match_value; | |
7d0c399f | 105 | raw_spinlock_t lock; |
3fb1b6ad | 106 | struct clock_event_device ced; |
19bdc9d0 | 107 | struct clocksource cs; |
37e7742c | 108 | u64 total_cycles; |
bad81383 | 109 | bool cs_enabled; |
7269f933 LP |
110 | }; |
111 | ||
2653caf4 | 112 | struct sh_cmt_device { |
7269f933 LP |
113 | struct platform_device *pdev; |
114 | ||
2cda3ac4 LP |
115 | const struct sh_cmt_info *info; |
116 | ||
7269f933 | 117 | void __iomem *mapbase; |
7269f933 | 118 | struct clk *clk; |
890f423b | 119 | unsigned long rate; |
3f44f715 | 120 | unsigned int reg_delay; |
7269f933 | 121 | |
de599c88 LP |
122 | raw_spinlock_t lock; /* Protect the shared start/stop register */ |
123 | ||
f5ec9b19 LP |
124 | struct sh_cmt_channel *channels; |
125 | unsigned int num_channels; | |
1768aa2f | 126 | unsigned int hw_channels; |
81b3b271 LP |
127 | |
128 | bool has_clockevent; | |
129 | bool has_clocksource; | |
3fb1b6ad MD |
130 | }; |
131 | ||
d14be99b LP |
132 | #define SH_CMT16_CMCSR_CMF (1 << 7) |
133 | #define SH_CMT16_CMCSR_CMIE (1 << 6) | |
134 | #define SH_CMT16_CMCSR_CKS8 (0 << 0) | |
135 | #define SH_CMT16_CMCSR_CKS32 (1 << 0) | |
136 | #define SH_CMT16_CMCSR_CKS128 (2 << 0) | |
137 | #define SH_CMT16_CMCSR_CKS512 (3 << 0) | |
138 | #define SH_CMT16_CMCSR_CKS_MASK (3 << 0) | |
139 | ||
140 | #define SH_CMT32_CMCSR_CMF (1 << 15) | |
141 | #define SH_CMT32_CMCSR_OVF (1 << 14) | |
142 | #define SH_CMT32_CMCSR_WRFLG (1 << 13) | |
143 | #define SH_CMT32_CMCSR_STTF (1 << 12) | |
144 | #define SH_CMT32_CMCSR_STPF (1 << 11) | |
145 | #define SH_CMT32_CMCSR_SSIE (1 << 10) | |
146 | #define SH_CMT32_CMCSR_CMS (1 << 9) | |
147 | #define SH_CMT32_CMCSR_CMM (1 << 8) | |
148 | #define SH_CMT32_CMCSR_CMTOUT_IE (1 << 7) | |
149 | #define SH_CMT32_CMCSR_CMR_NONE (0 << 4) | |
150 | #define SH_CMT32_CMCSR_CMR_DMA (1 << 4) | |
151 | #define SH_CMT32_CMCSR_CMR_IRQ (2 << 4) | |
152 | #define SH_CMT32_CMCSR_CMR_MASK (3 << 4) | |
153 | #define SH_CMT32_CMCSR_DBGIVD (1 << 3) | |
154 | #define SH_CMT32_CMCSR_CKS_RCLK8 (4 << 0) | |
155 | #define SH_CMT32_CMCSR_CKS_RCLK32 (5 << 0) | |
156 | #define SH_CMT32_CMCSR_CKS_RCLK128 (6 << 0) | |
157 | #define SH_CMT32_CMCSR_CKS_RCLK1 (7 << 0) | |
158 | #define SH_CMT32_CMCSR_CKS_MASK (7 << 0) | |
159 | ||
22627c6f | 160 | static u32 sh_cmt_read16(void __iomem *base, unsigned long offs) |
587acb3d MD |
161 | { |
162 | return ioread16(base + (offs << 1)); | |
163 | } | |
164 | ||
22627c6f | 165 | static u32 sh_cmt_read32(void __iomem *base, unsigned long offs) |
a6a912ca MD |
166 | { |
167 | return ioread32(base + (offs << 2)); | |
168 | } | |
169 | ||
22627c6f | 170 | static void sh_cmt_write16(void __iomem *base, unsigned long offs, u32 value) |
587acb3d MD |
171 | { |
172 | iowrite16(value, base + (offs << 1)); | |
173 | } | |
3fb1b6ad | 174 | |
22627c6f | 175 | static void sh_cmt_write32(void __iomem *base, unsigned long offs, u32 value) |
a6a912ca MD |
176 | { |
177 | iowrite32(value, base + (offs << 2)); | |
178 | } | |
179 | ||
2cda3ac4 LP |
180 | static const struct sh_cmt_info sh_cmt_info[] = { |
181 | [SH_CMT_16BIT] = { | |
182 | .model = SH_CMT_16BIT, | |
183 | .width = 16, | |
d14be99b LP |
184 | .overflow_bit = SH_CMT16_CMCSR_CMF, |
185 | .clear_bits = ~SH_CMT16_CMCSR_CMF, | |
2cda3ac4 LP |
186 | .read_control = sh_cmt_read16, |
187 | .write_control = sh_cmt_write16, | |
188 | .read_count = sh_cmt_read16, | |
189 | .write_count = sh_cmt_write16, | |
190 | }, | |
191 | [SH_CMT_32BIT] = { | |
192 | .model = SH_CMT_32BIT, | |
193 | .width = 32, | |
d14be99b LP |
194 | .overflow_bit = SH_CMT32_CMCSR_CMF, |
195 | .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), | |
2cda3ac4 LP |
196 | .read_control = sh_cmt_read16, |
197 | .write_control = sh_cmt_write16, | |
198 | .read_count = sh_cmt_read32, | |
199 | .write_count = sh_cmt_write32, | |
200 | }, | |
2cda3ac4 LP |
201 | [SH_CMT_48BIT] = { |
202 | .model = SH_CMT_48BIT, | |
464eed84 | 203 | .channels_mask = 0x3f, |
2cda3ac4 | 204 | .width = 32, |
d14be99b LP |
205 | .overflow_bit = SH_CMT32_CMCSR_CMF, |
206 | .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), | |
2cda3ac4 LP |
207 | .read_control = sh_cmt_read32, |
208 | .write_control = sh_cmt_write32, | |
209 | .read_count = sh_cmt_read32, | |
210 | .write_count = sh_cmt_write32, | |
211 | }, | |
83c79a6d MD |
212 | [SH_CMT0_RCAR_GEN2] = { |
213 | .model = SH_CMT0_RCAR_GEN2, | |
214 | .channels_mask = 0x60, | |
215 | .width = 32, | |
216 | .overflow_bit = SH_CMT32_CMCSR_CMF, | |
217 | .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), | |
218 | .read_control = sh_cmt_read32, | |
219 | .write_control = sh_cmt_write32, | |
220 | .read_count = sh_cmt_read32, | |
221 | .write_count = sh_cmt_write32, | |
222 | }, | |
223 | [SH_CMT1_RCAR_GEN2] = { | |
224 | .model = SH_CMT1_RCAR_GEN2, | |
225 | .channels_mask = 0xff, | |
2cda3ac4 | 226 | .width = 32, |
d14be99b LP |
227 | .overflow_bit = SH_CMT32_CMCSR_CMF, |
228 | .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), | |
2cda3ac4 LP |
229 | .read_control = sh_cmt_read32, |
230 | .write_control = sh_cmt_write32, | |
231 | .read_count = sh_cmt_read32, | |
232 | .write_count = sh_cmt_write32, | |
233 | }, | |
234 | }; | |
235 | ||
3fb1b6ad MD |
236 | #define CMCSR 0 /* channel register */ |
237 | #define CMCNT 1 /* channel register */ | |
238 | #define CMCOR 2 /* channel register */ | |
239 | ||
2a97d553 GU |
240 | #define CMCLKE 0x1000 /* CLK Enable Register (R-Car Gen2) */ |
241 | ||
22627c6f | 242 | static inline u32 sh_cmt_read_cmstr(struct sh_cmt_channel *ch) |
1b56b96b | 243 | { |
81b3b271 LP |
244 | if (ch->iostart) |
245 | return ch->cmt->info->read_control(ch->iostart, 0); | |
246 | else | |
247 | return ch->cmt->info->read_control(ch->cmt->mapbase, 0); | |
1b56b96b MD |
248 | } |
249 | ||
22627c6f | 250 | static inline void sh_cmt_write_cmstr(struct sh_cmt_channel *ch, u32 value) |
1b56b96b | 251 | { |
3f44f715 WS |
252 | u32 old_value = sh_cmt_read_cmstr(ch); |
253 | ||
254 | if (value != old_value) { | |
255 | if (ch->iostart) { | |
256 | ch->cmt->info->write_control(ch->iostart, 0, value); | |
257 | udelay(ch->cmt->reg_delay); | |
258 | } else { | |
259 | ch->cmt->info->write_control(ch->cmt->mapbase, 0, value); | |
260 | udelay(ch->cmt->reg_delay); | |
261 | } | |
262 | } | |
1b56b96b MD |
263 | } |
264 | ||
22627c6f | 265 | static inline u32 sh_cmt_read_cmcsr(struct sh_cmt_channel *ch) |
1b56b96b | 266 | { |
81b3b271 | 267 | return ch->cmt->info->read_control(ch->ioctrl, CMCSR); |
3fb1b6ad MD |
268 | } |
269 | ||
22627c6f | 270 | static inline void sh_cmt_write_cmcsr(struct sh_cmt_channel *ch, u32 value) |
1b56b96b | 271 | { |
3f44f715 WS |
272 | u32 old_value = sh_cmt_read_cmcsr(ch); |
273 | ||
274 | if (value != old_value) { | |
275 | ch->cmt->info->write_control(ch->ioctrl, CMCSR, value); | |
276 | udelay(ch->cmt->reg_delay); | |
277 | } | |
1b56b96b MD |
278 | } |
279 | ||
22627c6f | 280 | static inline u32 sh_cmt_read_cmcnt(struct sh_cmt_channel *ch) |
1b56b96b | 281 | { |
81b3b271 | 282 | return ch->cmt->info->read_count(ch->ioctrl, CMCNT); |
1b56b96b MD |
283 | } |
284 | ||
3f44f715 | 285 | static inline int sh_cmt_write_cmcnt(struct sh_cmt_channel *ch, u32 value) |
1b56b96b | 286 | { |
3f44f715 WS |
287 | /* Tests showed that we need to wait 3 clocks here */ |
288 | unsigned int cmcnt_delay = DIV_ROUND_UP(3 * ch->cmt->reg_delay, 2); | |
289 | u32 reg; | |
290 | ||
291 | if (ch->cmt->info->model > SH_CMT_16BIT) { | |
292 | int ret = read_poll_timeout_atomic(sh_cmt_read_cmcsr, reg, | |
293 | !(reg & SH_CMT32_CMCSR_WRFLG), | |
294 | 1, cmcnt_delay, false, ch); | |
295 | if (ret < 0) | |
296 | return ret; | |
297 | } | |
298 | ||
81b3b271 | 299 | ch->cmt->info->write_count(ch->ioctrl, CMCNT, value); |
3f44f715 WS |
300 | udelay(cmcnt_delay); |
301 | return 0; | |
1b56b96b MD |
302 | } |
303 | ||
22627c6f | 304 | static inline void sh_cmt_write_cmcor(struct sh_cmt_channel *ch, u32 value) |
1b56b96b | 305 | { |
3f44f715 WS |
306 | u32 old_value = ch->cmt->info->read_count(ch->ioctrl, CMCOR); |
307 | ||
308 | if (value != old_value) { | |
309 | ch->cmt->info->write_count(ch->ioctrl, CMCOR, value); | |
310 | udelay(ch->cmt->reg_delay); | |
311 | } | |
1b56b96b MD |
312 | } |
313 | ||
22627c6f | 314 | static u32 sh_cmt_get_counter(struct sh_cmt_channel *ch, u32 *has_wrapped) |
3fb1b6ad | 315 | { |
22627c6f SS |
316 | u32 v1, v2, v3; |
317 | u32 o1, o2; | |
5b644c7a | 318 | |
2cda3ac4 | 319 | o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit; |
3fb1b6ad MD |
320 | |
321 | /* Make sure the timer value is stable. Stolen from acpi_pm.c */ | |
322 | do { | |
5b644c7a | 323 | o2 = o1; |
7269f933 LP |
324 | v1 = sh_cmt_read_cmcnt(ch); |
325 | v2 = sh_cmt_read_cmcnt(ch); | |
326 | v3 = sh_cmt_read_cmcnt(ch); | |
2cda3ac4 | 327 | o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit; |
5b644c7a MD |
328 | } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3) |
329 | || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2))); | |
3fb1b6ad | 330 | |
5b644c7a | 331 | *has_wrapped = o1; |
3fb1b6ad MD |
332 | return v2; |
333 | } | |
334 | ||
7269f933 | 335 | static void sh_cmt_start_stop_ch(struct sh_cmt_channel *ch, int start) |
3fb1b6ad | 336 | { |
22627c6f SS |
337 | unsigned long flags; |
338 | u32 value; | |
3fb1b6ad MD |
339 | |
340 | /* start stop register shared by multiple timer channels */ | |
de599c88 | 341 | raw_spin_lock_irqsave(&ch->cmt->lock, flags); |
7269f933 | 342 | value = sh_cmt_read_cmstr(ch); |
3fb1b6ad MD |
343 | |
344 | if (start) | |
81b3b271 | 345 | value |= 1 << ch->timer_bit; |
3fb1b6ad | 346 | else |
81b3b271 | 347 | value &= ~(1 << ch->timer_bit); |
3fb1b6ad | 348 | |
7269f933 | 349 | sh_cmt_write_cmstr(ch, value); |
de599c88 | 350 | raw_spin_unlock_irqrestore(&ch->cmt->lock, flags); |
3fb1b6ad MD |
351 | } |
352 | ||
890f423b | 353 | static int sh_cmt_enable(struct sh_cmt_channel *ch) |
3fb1b6ad | 354 | { |
3f44f715 | 355 | int ret; |
3fb1b6ad | 356 | |
7269f933 | 357 | dev_pm_syscore_device(&ch->cmt->pdev->dev, true); |
bad81383 | 358 | |
9436b4ab | 359 | /* enable clock */ |
7269f933 | 360 | ret = clk_enable(ch->cmt->clk); |
3fb1b6ad | 361 | if (ret) { |
740a9518 LP |
362 | dev_err(&ch->cmt->pdev->dev, "ch%u: cannot enable clock\n", |
363 | ch->index); | |
3f7e5e24 | 364 | goto err0; |
3fb1b6ad | 365 | } |
3fb1b6ad MD |
366 | |
367 | /* make sure channel is disabled */ | |
7269f933 | 368 | sh_cmt_start_stop_ch(ch, 0); |
3fb1b6ad MD |
369 | |
370 | /* configure channel, periodic mode and maximum timeout */ | |
2cda3ac4 | 371 | if (ch->cmt->info->width == 16) { |
d14be99b LP |
372 | sh_cmt_write_cmcsr(ch, SH_CMT16_CMCSR_CMIE | |
373 | SH_CMT16_CMCSR_CKS512); | |
3014f474 | 374 | } else { |
68c70aae WS |
375 | u32 cmtout = ch->cmt->info->model <= SH_CMT_48BIT ? |
376 | SH_CMT32_CMCSR_CMTOUT_IE : 0; | |
377 | sh_cmt_write_cmcsr(ch, cmtout | SH_CMT32_CMCSR_CMM | | |
d14be99b LP |
378 | SH_CMT32_CMCSR_CMR_IRQ | |
379 | SH_CMT32_CMCSR_CKS_RCLK8); | |
3014f474 | 380 | } |
3fb1b6ad | 381 | |
7269f933 | 382 | sh_cmt_write_cmcor(ch, 0xffffffff); |
3f44f715 | 383 | ret = sh_cmt_write_cmcnt(ch, 0); |
3f7e5e24 | 384 | |
3f44f715 | 385 | if (ret || sh_cmt_read_cmcnt(ch)) { |
740a9518 LP |
386 | dev_err(&ch->cmt->pdev->dev, "ch%u: cannot clear CMCNT\n", |
387 | ch->index); | |
3f7e5e24 MD |
388 | ret = -ETIMEDOUT; |
389 | goto err1; | |
390 | } | |
391 | ||
3fb1b6ad | 392 | /* enable channel */ |
7269f933 | 393 | sh_cmt_start_stop_ch(ch, 1); |
3fb1b6ad | 394 | return 0; |
3f7e5e24 MD |
395 | err1: |
396 | /* stop clock */ | |
7269f933 | 397 | clk_disable(ch->cmt->clk); |
3f7e5e24 MD |
398 | |
399 | err0: | |
400 | return ret; | |
3fb1b6ad MD |
401 | } |
402 | ||
7269f933 | 403 | static void sh_cmt_disable(struct sh_cmt_channel *ch) |
3fb1b6ad MD |
404 | { |
405 | /* disable channel */ | |
7269f933 | 406 | sh_cmt_start_stop_ch(ch, 0); |
3fb1b6ad | 407 | |
be890a1a | 408 | /* disable interrupts in CMT block */ |
7269f933 | 409 | sh_cmt_write_cmcsr(ch, 0); |
be890a1a | 410 | |
9436b4ab | 411 | /* stop clock */ |
7269f933 | 412 | clk_disable(ch->cmt->clk); |
bad81383 | 413 | |
7269f933 | 414 | dev_pm_syscore_device(&ch->cmt->pdev->dev, false); |
3fb1b6ad MD |
415 | } |
416 | ||
417 | /* private flags */ | |
418 | #define FLAG_CLOCKEVENT (1 << 0) | |
419 | #define FLAG_CLOCKSOURCE (1 << 1) | |
420 | #define FLAG_REPROGRAM (1 << 2) | |
421 | #define FLAG_SKIPEVENT (1 << 3) | |
422 | #define FLAG_IRQCONTEXT (1 << 4) | |
423 | ||
7269f933 | 424 | static void sh_cmt_clock_event_program_verify(struct sh_cmt_channel *ch, |
3fb1b6ad MD |
425 | int absolute) |
426 | { | |
22627c6f SS |
427 | u32 value = ch->next_match_value; |
428 | u32 new_match; | |
429 | u32 delay = 0; | |
430 | u32 now = 0; | |
431 | u32 has_wrapped; | |
3fb1b6ad | 432 | |
7269f933 LP |
433 | now = sh_cmt_get_counter(ch, &has_wrapped); |
434 | ch->flags |= FLAG_REPROGRAM; /* force reprogram */ | |
3fb1b6ad MD |
435 | |
436 | if (has_wrapped) { | |
437 | /* we're competing with the interrupt handler. | |
438 | * -> let the interrupt handler reprogram the timer. | |
439 | * -> interrupt number two handles the event. | |
440 | */ | |
7269f933 | 441 | ch->flags |= FLAG_SKIPEVENT; |
3fb1b6ad MD |
442 | return; |
443 | } | |
444 | ||
445 | if (absolute) | |
446 | now = 0; | |
447 | ||
448 | do { | |
449 | /* reprogram the timer hardware, | |
450 | * but don't save the new match value yet. | |
451 | */ | |
452 | new_match = now + value + delay; | |
7269f933 LP |
453 | if (new_match > ch->max_match_value) |
454 | new_match = ch->max_match_value; | |
3fb1b6ad | 455 | |
7269f933 | 456 | sh_cmt_write_cmcor(ch, new_match); |
3fb1b6ad | 457 | |
7269f933 LP |
458 | now = sh_cmt_get_counter(ch, &has_wrapped); |
459 | if (has_wrapped && (new_match > ch->match_value)) { | |
3fb1b6ad MD |
460 | /* we are changing to a greater match value, |
461 | * so this wrap must be caused by the counter | |
462 | * matching the old value. | |
463 | * -> first interrupt reprograms the timer. | |
464 | * -> interrupt number two handles the event. | |
465 | */ | |
7269f933 | 466 | ch->flags |= FLAG_SKIPEVENT; |
3fb1b6ad MD |
467 | break; |
468 | } | |
469 | ||
470 | if (has_wrapped) { | |
471 | /* we are changing to a smaller match value, | |
472 | * so the wrap must be caused by the counter | |
473 | * matching the new value. | |
474 | * -> save programmed match value. | |
475 | * -> let isr handle the event. | |
476 | */ | |
7269f933 | 477 | ch->match_value = new_match; |
3fb1b6ad MD |
478 | break; |
479 | } | |
480 | ||
481 | /* be safe: verify hardware settings */ | |
482 | if (now < new_match) { | |
483 | /* timer value is below match value, all good. | |
484 | * this makes sure we won't miss any match events. | |
485 | * -> save programmed match value. | |
486 | * -> let isr handle the event. | |
487 | */ | |
7269f933 | 488 | ch->match_value = new_match; |
3fb1b6ad MD |
489 | break; |
490 | } | |
491 | ||
492 | /* the counter has reached a value greater | |
493 | * than our new match value. and since the | |
494 | * has_wrapped flag isn't set we must have | |
495 | * programmed a too close event. | |
496 | * -> increase delay and retry. | |
497 | */ | |
498 | if (delay) | |
499 | delay <<= 1; | |
500 | else | |
501 | delay = 1; | |
502 | ||
503 | if (!delay) | |
740a9518 LP |
504 | dev_warn(&ch->cmt->pdev->dev, "ch%u: too long delay\n", |
505 | ch->index); | |
3fb1b6ad MD |
506 | |
507 | } while (delay); | |
508 | } | |
509 | ||
7269f933 | 510 | static void __sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta) |
3fb1b6ad | 511 | { |
7269f933 | 512 | if (delta > ch->max_match_value) |
740a9518 LP |
513 | dev_warn(&ch->cmt->pdev->dev, "ch%u: delta out of range\n", |
514 | ch->index); | |
3fb1b6ad | 515 | |
7269f933 LP |
516 | ch->next_match_value = delta; |
517 | sh_cmt_clock_event_program_verify(ch, 0); | |
65ada547 TY |
518 | } |
519 | ||
7269f933 | 520 | static void sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta) |
65ada547 TY |
521 | { |
522 | unsigned long flags; | |
523 | ||
7269f933 LP |
524 | raw_spin_lock_irqsave(&ch->lock, flags); |
525 | __sh_cmt_set_next(ch, delta); | |
526 | raw_spin_unlock_irqrestore(&ch->lock, flags); | |
3fb1b6ad MD |
527 | } |
528 | ||
529 | static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id) | |
530 | { | |
7269f933 | 531 | struct sh_cmt_channel *ch = dev_id; |
3fb1b6ad MD |
532 | |
533 | /* clear flags */ | |
2cda3ac4 LP |
534 | sh_cmt_write_cmcsr(ch, sh_cmt_read_cmcsr(ch) & |
535 | ch->cmt->info->clear_bits); | |
3fb1b6ad MD |
536 | |
537 | /* update clock source counter to begin with if enabled | |
538 | * the wrap flag should be cleared by the timer specific | |
539 | * isr before we end up here. | |
540 | */ | |
7269f933 LP |
541 | if (ch->flags & FLAG_CLOCKSOURCE) |
542 | ch->total_cycles += ch->match_value + 1; | |
3fb1b6ad | 543 | |
7269f933 LP |
544 | if (!(ch->flags & FLAG_REPROGRAM)) |
545 | ch->next_match_value = ch->max_match_value; | |
3fb1b6ad | 546 | |
7269f933 | 547 | ch->flags |= FLAG_IRQCONTEXT; |
3fb1b6ad | 548 | |
7269f933 LP |
549 | if (ch->flags & FLAG_CLOCKEVENT) { |
550 | if (!(ch->flags & FLAG_SKIPEVENT)) { | |
051b782e | 551 | if (clockevent_state_oneshot(&ch->ced)) { |
7269f933 LP |
552 | ch->next_match_value = ch->max_match_value; |
553 | ch->flags |= FLAG_REPROGRAM; | |
3fb1b6ad MD |
554 | } |
555 | ||
7269f933 | 556 | ch->ced.event_handler(&ch->ced); |
3fb1b6ad MD |
557 | } |
558 | } | |
559 | ||
7269f933 | 560 | ch->flags &= ~FLAG_SKIPEVENT; |
3fb1b6ad | 561 | |
7269f933 LP |
562 | if (ch->flags & FLAG_REPROGRAM) { |
563 | ch->flags &= ~FLAG_REPROGRAM; | |
564 | sh_cmt_clock_event_program_verify(ch, 1); | |
3fb1b6ad | 565 | |
7269f933 | 566 | if (ch->flags & FLAG_CLOCKEVENT) |
051b782e | 567 | if ((clockevent_state_shutdown(&ch->ced)) |
7269f933 LP |
568 | || (ch->match_value == ch->next_match_value)) |
569 | ch->flags &= ~FLAG_REPROGRAM; | |
3fb1b6ad MD |
570 | } |
571 | ||
7269f933 | 572 | ch->flags &= ~FLAG_IRQCONTEXT; |
3fb1b6ad MD |
573 | |
574 | return IRQ_HANDLED; | |
575 | } | |
576 | ||
7269f933 | 577 | static int sh_cmt_start(struct sh_cmt_channel *ch, unsigned long flag) |
3fb1b6ad MD |
578 | { |
579 | int ret = 0; | |
580 | unsigned long flags; | |
581 | ||
8ae954ca NS |
582 | if (flag & FLAG_CLOCKSOURCE) |
583 | pm_runtime_get_sync(&ch->cmt->pdev->dev); | |
584 | ||
7269f933 | 585 | raw_spin_lock_irqsave(&ch->lock, flags); |
3fb1b6ad | 586 | |
8ae954ca NS |
587 | if (!(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) { |
588 | if (flag & FLAG_CLOCKEVENT) | |
589 | pm_runtime_get_sync(&ch->cmt->pdev->dev); | |
890f423b | 590 | ret = sh_cmt_enable(ch); |
8ae954ca | 591 | } |
3fb1b6ad MD |
592 | |
593 | if (ret) | |
594 | goto out; | |
7269f933 | 595 | ch->flags |= flag; |
3fb1b6ad MD |
596 | |
597 | /* setup timeout if no clockevent */ | |
be83c3b6 PH |
598 | if (ch->cmt->num_channels == 1 && |
599 | flag == FLAG_CLOCKSOURCE && (!(ch->flags & FLAG_CLOCKEVENT))) | |
7269f933 | 600 | __sh_cmt_set_next(ch, ch->max_match_value); |
3fb1b6ad | 601 | out: |
7269f933 | 602 | raw_spin_unlock_irqrestore(&ch->lock, flags); |
3fb1b6ad MD |
603 | |
604 | return ret; | |
605 | } | |
606 | ||
7269f933 | 607 | static void sh_cmt_stop(struct sh_cmt_channel *ch, unsigned long flag) |
3fb1b6ad MD |
608 | { |
609 | unsigned long flags; | |
610 | unsigned long f; | |
611 | ||
7269f933 | 612 | raw_spin_lock_irqsave(&ch->lock, flags); |
3fb1b6ad | 613 | |
7269f933 LP |
614 | f = ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE); |
615 | ch->flags &= ~flag; | |
3fb1b6ad | 616 | |
8ae954ca | 617 | if (f && !(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) { |
7269f933 | 618 | sh_cmt_disable(ch); |
8ae954ca NS |
619 | if (flag & FLAG_CLOCKEVENT) |
620 | pm_runtime_put(&ch->cmt->pdev->dev); | |
621 | } | |
3fb1b6ad MD |
622 | |
623 | /* adjust the timeout to maximum if only clocksource left */ | |
7269f933 LP |
624 | if ((flag == FLAG_CLOCKEVENT) && (ch->flags & FLAG_CLOCKSOURCE)) |
625 | __sh_cmt_set_next(ch, ch->max_match_value); | |
3fb1b6ad | 626 | |
7269f933 | 627 | raw_spin_unlock_irqrestore(&ch->lock, flags); |
8ae954ca NS |
628 | |
629 | if (flag & FLAG_CLOCKSOURCE) | |
630 | pm_runtime_put(&ch->cmt->pdev->dev); | |
3fb1b6ad MD |
631 | } |
632 | ||
7269f933 | 633 | static struct sh_cmt_channel *cs_to_sh_cmt(struct clocksource *cs) |
19bdc9d0 | 634 | { |
7269f933 | 635 | return container_of(cs, struct sh_cmt_channel, cs); |
19bdc9d0 MD |
636 | } |
637 | ||
a5a1d1c2 | 638 | static u64 sh_cmt_clocksource_read(struct clocksource *cs) |
19bdc9d0 | 639 | { |
7269f933 | 640 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
22627c6f | 641 | u32 has_wrapped; |
19bdc9d0 | 642 | |
be83c3b6 PH |
643 | if (ch->cmt->num_channels == 1) { |
644 | unsigned long flags; | |
645 | u64 value; | |
646 | u32 raw; | |
19bdc9d0 | 647 | |
be83c3b6 PH |
648 | raw_spin_lock_irqsave(&ch->lock, flags); |
649 | value = ch->total_cycles; | |
650 | raw = sh_cmt_get_counter(ch, &has_wrapped); | |
651 | ||
652 | if (unlikely(has_wrapped)) | |
653 | raw += ch->match_value + 1; | |
654 | raw_spin_unlock_irqrestore(&ch->lock, flags); | |
655 | ||
656 | return value + raw; | |
657 | } | |
19bdc9d0 | 658 | |
be83c3b6 | 659 | return sh_cmt_get_counter(ch, &has_wrapped); |
19bdc9d0 MD |
660 | } |
661 | ||
662 | static int sh_cmt_clocksource_enable(struct clocksource *cs) | |
663 | { | |
3593f5fe | 664 | int ret; |
7269f933 | 665 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
19bdc9d0 | 666 | |
7269f933 | 667 | WARN_ON(ch->cs_enabled); |
bad81383 | 668 | |
7269f933 | 669 | ch->total_cycles = 0; |
19bdc9d0 | 670 | |
7269f933 | 671 | ret = sh_cmt_start(ch, FLAG_CLOCKSOURCE); |
890f423b | 672 | if (!ret) |
7269f933 | 673 | ch->cs_enabled = true; |
890f423b | 674 | |
3593f5fe | 675 | return ret; |
19bdc9d0 MD |
676 | } |
677 | ||
678 | static void sh_cmt_clocksource_disable(struct clocksource *cs) | |
679 | { | |
7269f933 | 680 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
bad81383 | 681 | |
7269f933 | 682 | WARN_ON(!ch->cs_enabled); |
bad81383 | 683 | |
7269f933 LP |
684 | sh_cmt_stop(ch, FLAG_CLOCKSOURCE); |
685 | ch->cs_enabled = false; | |
19bdc9d0 MD |
686 | } |
687 | ||
9bb5ec88 RW |
688 | static void sh_cmt_clocksource_suspend(struct clocksource *cs) |
689 | { | |
7269f933 | 690 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
9bb5ec88 | 691 | |
54d46b7f GU |
692 | if (!ch->cs_enabled) |
693 | return; | |
694 | ||
7269f933 | 695 | sh_cmt_stop(ch, FLAG_CLOCKSOURCE); |
fc519890 | 696 | dev_pm_genpd_suspend(&ch->cmt->pdev->dev); |
9bb5ec88 RW |
697 | } |
698 | ||
c8162884 MD |
699 | static void sh_cmt_clocksource_resume(struct clocksource *cs) |
700 | { | |
7269f933 | 701 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
9bb5ec88 | 702 | |
54d46b7f GU |
703 | if (!ch->cs_enabled) |
704 | return; | |
705 | ||
fc519890 | 706 | dev_pm_genpd_resume(&ch->cmt->pdev->dev); |
7269f933 | 707 | sh_cmt_start(ch, FLAG_CLOCKSOURCE); |
c8162884 MD |
708 | } |
709 | ||
7269f933 | 710 | static int sh_cmt_register_clocksource(struct sh_cmt_channel *ch, |
fb28a659 | 711 | const char *name) |
19bdc9d0 | 712 | { |
7269f933 | 713 | struct clocksource *cs = &ch->cs; |
19bdc9d0 MD |
714 | |
715 | cs->name = name; | |
fb28a659 | 716 | cs->rating = 125; |
19bdc9d0 MD |
717 | cs->read = sh_cmt_clocksource_read; |
718 | cs->enable = sh_cmt_clocksource_enable; | |
719 | cs->disable = sh_cmt_clocksource_disable; | |
9bb5ec88 | 720 | cs->suspend = sh_cmt_clocksource_suspend; |
c8162884 | 721 | cs->resume = sh_cmt_clocksource_resume; |
be83c3b6 | 722 | cs->mask = CLOCKSOURCE_MASK(ch->cmt->info->width); |
19bdc9d0 | 723 | cs->flags = CLOCK_SOURCE_IS_CONTINUOUS; |
f4d7c356 | 724 | |
740a9518 LP |
725 | dev_info(&ch->cmt->pdev->dev, "ch%u: used as clock source\n", |
726 | ch->index); | |
f4d7c356 | 727 | |
890f423b | 728 | clocksource_register_hz(cs, ch->cmt->rate); |
19bdc9d0 MD |
729 | return 0; |
730 | } | |
731 | ||
7269f933 | 732 | static struct sh_cmt_channel *ced_to_sh_cmt(struct clock_event_device *ced) |
3fb1b6ad | 733 | { |
7269f933 | 734 | return container_of(ced, struct sh_cmt_channel, ced); |
3fb1b6ad MD |
735 | } |
736 | ||
7269f933 | 737 | static void sh_cmt_clock_event_start(struct sh_cmt_channel *ch, int periodic) |
3fb1b6ad | 738 | { |
7269f933 | 739 | sh_cmt_start(ch, FLAG_CLOCKEVENT); |
3fb1b6ad | 740 | |
3fb1b6ad | 741 | if (periodic) |
890f423b | 742 | sh_cmt_set_next(ch, ((ch->cmt->rate + HZ/2) / HZ) - 1); |
3fb1b6ad | 743 | else |
7269f933 | 744 | sh_cmt_set_next(ch, ch->max_match_value); |
3fb1b6ad MD |
745 | } |
746 | ||
051b782e VK |
747 | static int sh_cmt_clock_event_shutdown(struct clock_event_device *ced) |
748 | { | |
749 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); | |
750 | ||
751 | sh_cmt_stop(ch, FLAG_CLOCKEVENT); | |
752 | return 0; | |
753 | } | |
754 | ||
755 | static int sh_cmt_clock_event_set_state(struct clock_event_device *ced, | |
756 | int periodic) | |
3fb1b6ad | 757 | { |
7269f933 | 758 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); |
3fb1b6ad MD |
759 | |
760 | /* deal with old setting first */ | |
051b782e | 761 | if (clockevent_state_oneshot(ced) || clockevent_state_periodic(ced)) |
7269f933 | 762 | sh_cmt_stop(ch, FLAG_CLOCKEVENT); |
3fb1b6ad | 763 | |
051b782e VK |
764 | dev_info(&ch->cmt->pdev->dev, "ch%u: used for %s clock events\n", |
765 | ch->index, periodic ? "periodic" : "oneshot"); | |
766 | sh_cmt_clock_event_start(ch, periodic); | |
767 | return 0; | |
768 | } | |
769 | ||
770 | static int sh_cmt_clock_event_set_oneshot(struct clock_event_device *ced) | |
771 | { | |
772 | return sh_cmt_clock_event_set_state(ced, 0); | |
773 | } | |
774 | ||
775 | static int sh_cmt_clock_event_set_periodic(struct clock_event_device *ced) | |
776 | { | |
777 | return sh_cmt_clock_event_set_state(ced, 1); | |
3fb1b6ad MD |
778 | } |
779 | ||
780 | static int sh_cmt_clock_event_next(unsigned long delta, | |
781 | struct clock_event_device *ced) | |
782 | { | |
7269f933 | 783 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); |
3fb1b6ad | 784 | |
051b782e | 785 | BUG_ON(!clockevent_state_oneshot(ced)); |
7269f933 LP |
786 | if (likely(ch->flags & FLAG_IRQCONTEXT)) |
787 | ch->next_match_value = delta - 1; | |
3fb1b6ad | 788 | else |
7269f933 | 789 | sh_cmt_set_next(ch, delta - 1); |
3fb1b6ad MD |
790 | |
791 | return 0; | |
792 | } | |
793 | ||
9bb5ec88 RW |
794 | static void sh_cmt_clock_event_suspend(struct clock_event_device *ced) |
795 | { | |
7269f933 | 796 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); |
57dee992 | 797 | |
fc519890 | 798 | dev_pm_genpd_suspend(&ch->cmt->pdev->dev); |
7269f933 | 799 | clk_unprepare(ch->cmt->clk); |
9bb5ec88 RW |
800 | } |
801 | ||
802 | static void sh_cmt_clock_event_resume(struct clock_event_device *ced) | |
803 | { | |
7269f933 | 804 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); |
57dee992 | 805 | |
7269f933 | 806 | clk_prepare(ch->cmt->clk); |
fc519890 | 807 | dev_pm_genpd_resume(&ch->cmt->pdev->dev); |
9bb5ec88 RW |
808 | } |
809 | ||
bfa76bb1 LP |
810 | static int sh_cmt_register_clockevent(struct sh_cmt_channel *ch, |
811 | const char *name) | |
3fb1b6ad | 812 | { |
7269f933 | 813 | struct clock_event_device *ced = &ch->ced; |
bfa76bb1 LP |
814 | int irq; |
815 | int ret; | |
816 | ||
31e912f5 | 817 | irq = platform_get_irq(ch->cmt->pdev, ch->index); |
9f475d08 | 818 | if (irq < 0) |
bfa76bb1 | 819 | return irq; |
bfa76bb1 LP |
820 | |
821 | ret = request_irq(irq, sh_cmt_interrupt, | |
822 | IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING, | |
823 | dev_name(&ch->cmt->pdev->dev), ch); | |
824 | if (ret) { | |
825 | dev_err(&ch->cmt->pdev->dev, "ch%u: failed to request irq %d\n", | |
826 | ch->index, irq); | |
827 | return ret; | |
828 | } | |
3fb1b6ad | 829 | |
3fb1b6ad MD |
830 | ced->name = name; |
831 | ced->features = CLOCK_EVT_FEAT_PERIODIC; | |
832 | ced->features |= CLOCK_EVT_FEAT_ONESHOT; | |
b7fcbb0f | 833 | ced->rating = 125; |
f1ebe1e4 | 834 | ced->cpumask = cpu_possible_mask; |
3fb1b6ad | 835 | ced->set_next_event = sh_cmt_clock_event_next; |
051b782e VK |
836 | ced->set_state_shutdown = sh_cmt_clock_event_shutdown; |
837 | ced->set_state_periodic = sh_cmt_clock_event_set_periodic; | |
838 | ced->set_state_oneshot = sh_cmt_clock_event_set_oneshot; | |
9bb5ec88 RW |
839 | ced->suspend = sh_cmt_clock_event_suspend; |
840 | ced->resume = sh_cmt_clock_event_resume; | |
3fb1b6ad | 841 | |
890f423b NS |
842 | /* TODO: calculate good shift from rate and counter bit width */ |
843 | ced->shift = 32; | |
844 | ced->mult = div_sc(ch->cmt->rate, NSEC_PER_SEC, ced->shift); | |
845 | ced->max_delta_ns = clockevent_delta2ns(ch->max_match_value, ced); | |
bb2e94ac | 846 | ced->max_delta_ticks = ch->max_match_value; |
890f423b | 847 | ced->min_delta_ns = clockevent_delta2ns(0x1f, ced); |
bb2e94ac | 848 | ced->min_delta_ticks = 0x1f; |
890f423b | 849 | |
740a9518 LP |
850 | dev_info(&ch->cmt->pdev->dev, "ch%u: used for clock events\n", |
851 | ch->index); | |
3fb1b6ad | 852 | clockevents_register_device(ced); |
bfa76bb1 LP |
853 | |
854 | return 0; | |
3fb1b6ad MD |
855 | } |
856 | ||
1d053e1d | 857 | static int sh_cmt_register(struct sh_cmt_channel *ch, const char *name, |
fb28a659 | 858 | bool clockevent, bool clocksource) |
3fb1b6ad | 859 | { |
bfa76bb1 LP |
860 | int ret; |
861 | ||
81b3b271 LP |
862 | if (clockevent) { |
863 | ch->cmt->has_clockevent = true; | |
bfa76bb1 LP |
864 | ret = sh_cmt_register_clockevent(ch, name); |
865 | if (ret < 0) | |
866 | return ret; | |
81b3b271 | 867 | } |
3fb1b6ad | 868 | |
81b3b271 LP |
869 | if (clocksource) { |
870 | ch->cmt->has_clocksource = true; | |
fb28a659 | 871 | sh_cmt_register_clocksource(ch, name); |
81b3b271 | 872 | } |
19bdc9d0 | 873 | |
3fb1b6ad MD |
874 | return 0; |
875 | } | |
876 | ||
740a9518 | 877 | static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index, |
81b3b271 LP |
878 | unsigned int hwidx, bool clockevent, |
879 | bool clocksource, struct sh_cmt_device *cmt) | |
b882e7b1 | 880 | { |
2a97d553 | 881 | u32 value; |
b882e7b1 LP |
882 | int ret; |
883 | ||
81b3b271 LP |
884 | /* Skip unused channels. */ |
885 | if (!clockevent && !clocksource) | |
886 | return 0; | |
887 | ||
b882e7b1 | 888 | ch->cmt = cmt; |
740a9518 | 889 | ch->index = index; |
81b3b271 | 890 | ch->hwidx = hwidx; |
83c79a6d | 891 | ch->timer_bit = hwidx; |
81b3b271 LP |
892 | |
893 | /* | |
894 | * Compute the address of the channel control register block. For the | |
895 | * timers with a per-channel start/stop register, compute its address | |
896 | * as well. | |
81b3b271 | 897 | */ |
31e912f5 LP |
898 | switch (cmt->info->model) { |
899 | case SH_CMT_16BIT: | |
900 | ch->ioctrl = cmt->mapbase + 2 + ch->hwidx * 6; | |
901 | break; | |
902 | case SH_CMT_32BIT: | |
903 | case SH_CMT_48BIT: | |
904 | ch->ioctrl = cmt->mapbase + 0x10 + ch->hwidx * 0x10; | |
905 | break; | |
83c79a6d MD |
906 | case SH_CMT0_RCAR_GEN2: |
907 | case SH_CMT1_RCAR_GEN2: | |
31e912f5 LP |
908 | ch->iostart = cmt->mapbase + ch->hwidx * 0x100; |
909 | ch->ioctrl = ch->iostart + 0x10; | |
83c79a6d | 910 | ch->timer_bit = 0; |
2a97d553 GU |
911 | |
912 | /* Enable the clock supply to the channel */ | |
913 | value = ioread32(cmt->mapbase + CMCLKE); | |
914 | value |= BIT(hwidx); | |
915 | iowrite32(value, cmt->mapbase + CMCLKE); | |
31e912f5 | 916 | break; |
81b3b271 LP |
917 | } |
918 | ||
2cda3ac4 | 919 | if (cmt->info->width == (sizeof(ch->max_match_value) * 8)) |
b882e7b1 LP |
920 | ch->max_match_value = ~0; |
921 | else | |
2cda3ac4 | 922 | ch->max_match_value = (1 << cmt->info->width) - 1; |
b882e7b1 LP |
923 | |
924 | ch->match_value = ch->max_match_value; | |
925 | raw_spin_lock_init(&ch->lock); | |
926 | ||
1d053e1d | 927 | ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev), |
81b3b271 | 928 | clockevent, clocksource); |
b882e7b1 | 929 | if (ret) { |
740a9518 LP |
930 | dev_err(&cmt->pdev->dev, "ch%u: registration failed\n", |
931 | ch->index); | |
b882e7b1 LP |
932 | return ret; |
933 | } | |
934 | ch->cs_enabled = false; | |
935 | ||
b882e7b1 LP |
936 | return 0; |
937 | } | |
938 | ||
81b3b271 | 939 | static int sh_cmt_map_memory(struct sh_cmt_device *cmt) |
3fb1b6ad | 940 | { |
81b3b271 | 941 | struct resource *mem; |
3fb1b6ad | 942 | |
81b3b271 LP |
943 | mem = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 0); |
944 | if (!mem) { | |
945 | dev_err(&cmt->pdev->dev, "failed to get I/O memory\n"); | |
946 | return -ENXIO; | |
947 | } | |
3fb1b6ad | 948 | |
4bdc0d67 | 949 | cmt->mapbase = ioremap(mem->start, resource_size(mem)); |
81b3b271 LP |
950 | if (cmt->mapbase == NULL) { |
951 | dev_err(&cmt->pdev->dev, "failed to remap I/O memory\n"); | |
952 | return -ENXIO; | |
3fb1b6ad MD |
953 | } |
954 | ||
81b3b271 LP |
955 | return 0; |
956 | } | |
957 | ||
1768aa2f LP |
958 | static const struct platform_device_id sh_cmt_id_table[] = { |
959 | { "sh-cmt-16", (kernel_ulong_t)&sh_cmt_info[SH_CMT_16BIT] }, | |
960 | { "sh-cmt-32", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT] }, | |
1768aa2f LP |
961 | { } |
962 | }; | |
963 | MODULE_DEVICE_TABLE(platform, sh_cmt_id_table); | |
964 | ||
965 | static const struct of_device_id sh_cmt_of_table[] __maybe_unused = { | |
19d60845 MD |
966 | { |
967 | /* deprecated, preserved for backward compatibility */ | |
968 | .compatible = "renesas,cmt-48", | |
969 | .data = &sh_cmt_info[SH_CMT_48BIT] | |
970 | }, | |
8d50e947 GU |
971 | { |
972 | /* deprecated, preserved for backward compatibility */ | |
973 | .compatible = "renesas,cmt-48-gen2", | |
974 | .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2] | |
8c1afba2 MD |
975 | }, |
976 | { | |
977 | .compatible = "renesas,r8a7740-cmt1", | |
978 | .data = &sh_cmt_info[SH_CMT_48BIT] | |
979 | }, | |
980 | { | |
981 | .compatible = "renesas,sh73a0-cmt1", | |
982 | .data = &sh_cmt_info[SH_CMT_48BIT] | |
8d50e947 | 983 | }, |
eceb4c49 SS |
984 | { |
985 | .compatible = "renesas,rcar-gen2-cmt0", | |
986 | .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2] | |
987 | }, | |
988 | { | |
989 | .compatible = "renesas,rcar-gen2-cmt1", | |
990 | .data = &sh_cmt_info[SH_CMT1_RCAR_GEN2] | |
991 | }, | |
ac142a7f SS |
992 | { |
993 | .compatible = "renesas,rcar-gen3-cmt0", | |
994 | .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2] | |
995 | }, | |
996 | { | |
997 | .compatible = "renesas,rcar-gen3-cmt1", | |
998 | .data = &sh_cmt_info[SH_CMT1_RCAR_GEN2] | |
999 | }, | |
aa84506e WS |
1000 | { |
1001 | .compatible = "renesas,rcar-gen4-cmt0", | |
1002 | .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2] | |
1003 | }, | |
1004 | { | |
1005 | .compatible = "renesas,rcar-gen4-cmt1", | |
1006 | .data = &sh_cmt_info[SH_CMT1_RCAR_GEN2] | |
1007 | }, | |
1768aa2f LP |
1008 | { } |
1009 | }; | |
1010 | MODULE_DEVICE_TABLE(of, sh_cmt_of_table); | |
1011 | ||
81b3b271 LP |
1012 | static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev) |
1013 | { | |
3f44f715 WS |
1014 | unsigned int mask, i; |
1015 | unsigned long rate; | |
81b3b271 LP |
1016 | int ret; |
1017 | ||
81b3b271 | 1018 | cmt->pdev = pdev; |
de599c88 | 1019 | raw_spin_lock_init(&cmt->lock); |
81b3b271 | 1020 | |
1768aa2f | 1021 | if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) { |
2d1d5172 | 1022 | cmt->info = of_device_get_match_data(&pdev->dev); |
d1d28597 | 1023 | cmt->hw_channels = cmt->info->channels_mask; |
1768aa2f LP |
1024 | } else if (pdev->dev.platform_data) { |
1025 | struct sh_timer_config *cfg = pdev->dev.platform_data; | |
1026 | const struct platform_device_id *id = pdev->id_entry; | |
1027 | ||
1028 | cmt->info = (const struct sh_cmt_info *)id->driver_data; | |
1029 | cmt->hw_channels = cfg->channels_mask; | |
1030 | } else { | |
81b3b271 LP |
1031 | dev_err(&cmt->pdev->dev, "missing platform data\n"); |
1032 | return -ENXIO; | |
1033 | } | |
1034 | ||
81b3b271 | 1035 | /* Get hold of clock. */ |
31e912f5 | 1036 | cmt->clk = clk_get(&cmt->pdev->dev, "fck"); |
2653caf4 LP |
1037 | if (IS_ERR(cmt->clk)) { |
1038 | dev_err(&cmt->pdev->dev, "cannot get clock\n"); | |
81b3b271 | 1039 | return PTR_ERR(cmt->clk); |
3fb1b6ad MD |
1040 | } |
1041 | ||
2653caf4 | 1042 | ret = clk_prepare(cmt->clk); |
57dee992 | 1043 | if (ret < 0) |
81b3b271 | 1044 | goto err_clk_put; |
57dee992 | 1045 | |
890f423b NS |
1046 | /* Determine clock rate. */ |
1047 | ret = clk_enable(cmt->clk); | |
1048 | if (ret < 0) | |
1049 | goto err_clk_unprepare; | |
1050 | ||
3f44f715 WS |
1051 | rate = clk_get_rate(cmt->clk); |
1052 | if (!rate) { | |
1053 | ret = -EINVAL; | |
1054 | goto err_clk_disable; | |
1055 | } | |
1056 | ||
1057 | /* We shall wait 2 input clks after register writes */ | |
1058 | if (cmt->info->model >= SH_CMT_48BIT) | |
1059 | cmt->reg_delay = DIV_ROUND_UP(2UL * USEC_PER_SEC, rate); | |
1060 | cmt->rate = rate / (cmt->info->width == 16 ? 512 : 8); | |
890f423b | 1061 | |
31e912f5 LP |
1062 | /* Map the memory resource(s). */ |
1063 | ret = sh_cmt_map_memory(cmt); | |
81b3b271 | 1064 | if (ret < 0) |
2a97d553 | 1065 | goto err_clk_disable; |
81b3b271 LP |
1066 | |
1067 | /* Allocate and setup the channels. */ | |
1768aa2f | 1068 | cmt->num_channels = hweight8(cmt->hw_channels); |
6396bb22 | 1069 | cmt->channels = kcalloc(cmt->num_channels, sizeof(*cmt->channels), |
81b3b271 | 1070 | GFP_KERNEL); |
f5ec9b19 LP |
1071 | if (cmt->channels == NULL) { |
1072 | ret = -ENOMEM; | |
81b3b271 | 1073 | goto err_unmap; |
f5ec9b19 LP |
1074 | } |
1075 | ||
31e912f5 LP |
1076 | /* |
1077 | * Use the first channel as a clock event device and the second channel | |
1078 | * as a clock source. If only one channel is available use it for both. | |
1079 | */ | |
1768aa2f | 1080 | for (i = 0, mask = cmt->hw_channels; i < cmt->num_channels; ++i) { |
31e912f5 LP |
1081 | unsigned int hwidx = ffs(mask) - 1; |
1082 | bool clocksource = i == 1 || cmt->num_channels == 1; | |
1083 | bool clockevent = i == 0; | |
1084 | ||
1085 | ret = sh_cmt_setup_channel(&cmt->channels[i], i, hwidx, | |
1086 | clockevent, clocksource, cmt); | |
81b3b271 LP |
1087 | if (ret < 0) |
1088 | goto err_unmap; | |
f5ec9b19 | 1089 | |
31e912f5 | 1090 | mask &= ~(1 << hwidx); |
81b3b271 | 1091 | } |
da64c2a8 | 1092 | |
2a97d553 GU |
1093 | clk_disable(cmt->clk); |
1094 | ||
2653caf4 | 1095 | platform_set_drvdata(pdev, cmt); |
adccc69e | 1096 | |
da64c2a8 | 1097 | return 0; |
81b3b271 LP |
1098 | |
1099 | err_unmap: | |
f5ec9b19 | 1100 | kfree(cmt->channels); |
31e912f5 | 1101 | iounmap(cmt->mapbase); |
2a97d553 GU |
1102 | err_clk_disable: |
1103 | clk_disable(cmt->clk); | |
81b3b271 | 1104 | err_clk_unprepare: |
2653caf4 | 1105 | clk_unprepare(cmt->clk); |
81b3b271 | 1106 | err_clk_put: |
2653caf4 | 1107 | clk_put(cmt->clk); |
3fb1b6ad MD |
1108 | return ret; |
1109 | } | |
1110 | ||
1850514b | 1111 | static int sh_cmt_probe(struct platform_device *pdev) |
3fb1b6ad | 1112 | { |
2653caf4 | 1113 | struct sh_cmt_device *cmt = platform_get_drvdata(pdev); |
3fb1b6ad MD |
1114 | int ret; |
1115 | ||
201e9109 | 1116 | if (!is_sh_early_platform_device(pdev)) { |
bad81383 RW |
1117 | pm_runtime_set_active(&pdev->dev); |
1118 | pm_runtime_enable(&pdev->dev); | |
9bb5ec88 | 1119 | } |
615a445f | 1120 | |
2653caf4 | 1121 | if (cmt) { |
214a607a | 1122 | dev_info(&pdev->dev, "kept as earlytimer\n"); |
bad81383 | 1123 | goto out; |
e475eedb MD |
1124 | } |
1125 | ||
b262bc74 | 1126 | cmt = kzalloc(sizeof(*cmt), GFP_KERNEL); |
0178f41d | 1127 | if (cmt == NULL) |
3fb1b6ad | 1128 | return -ENOMEM; |
3fb1b6ad | 1129 | |
2653caf4 | 1130 | ret = sh_cmt_setup(cmt, pdev); |
3fb1b6ad | 1131 | if (ret) { |
2653caf4 | 1132 | kfree(cmt); |
bad81383 RW |
1133 | pm_runtime_idle(&pdev->dev); |
1134 | return ret; | |
3fb1b6ad | 1135 | } |
201e9109 | 1136 | if (is_sh_early_platform_device(pdev)) |
bad81383 RW |
1137 | return 0; |
1138 | ||
1139 | out: | |
81b3b271 | 1140 | if (cmt->has_clockevent || cmt->has_clocksource) |
bad81383 RW |
1141 | pm_runtime_irq_safe(&pdev->dev); |
1142 | else | |
1143 | pm_runtime_idle(&pdev->dev); | |
1144 | ||
1145 | return 0; | |
3fb1b6ad MD |
1146 | } |
1147 | ||
3fb1b6ad MD |
1148 | static struct platform_driver sh_cmt_device_driver = { |
1149 | .probe = sh_cmt_probe, | |
3fb1b6ad MD |
1150 | .driver = { |
1151 | .name = "sh_cmt", | |
1768aa2f | 1152 | .of_match_table = of_match_ptr(sh_cmt_of_table), |
c3daa475 | 1153 | .suppress_bind_attrs = true, |
81b3b271 LP |
1154 | }, |
1155 | .id_table = sh_cmt_id_table, | |
3fb1b6ad MD |
1156 | }; |
1157 | ||
1158 | static int __init sh_cmt_init(void) | |
1159 | { | |
1160 | return platform_driver_register(&sh_cmt_device_driver); | |
1161 | } | |
1162 | ||
1163 | static void __exit sh_cmt_exit(void) | |
1164 | { | |
1165 | platform_driver_unregister(&sh_cmt_device_driver); | |
1166 | } | |
1167 | ||
507fd01d | 1168 | #ifdef CONFIG_SUPERH |
201e9109 | 1169 | sh_early_platform_init("earlytimer", &sh_cmt_device_driver); |
507fd01d BG |
1170 | #endif |
1171 | ||
e903a031 | 1172 | subsys_initcall(sh_cmt_init); |
3fb1b6ad MD |
1173 | module_exit(sh_cmt_exit); |
1174 | ||
1175 | MODULE_AUTHOR("Magnus Damm"); | |
1176 | MODULE_DESCRIPTION("SuperH CMT Timer Driver"); |