Commit | Line | Data |
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efad0117 | 1 | // SPDX-License-Identifier: GPL-2.0 |
3fb1b6ad MD |
2 | /* |
3 | * SuperH Timer Support - CMT | |
4 | * | |
5 | * Copyright (C) 2008 Magnus Damm | |
3fb1b6ad MD |
6 | */ |
7 | ||
e7a9bcc2 LP |
8 | #include <linux/clk.h> |
9 | #include <linux/clockchips.h> | |
10 | #include <linux/clocksource.h> | |
11 | #include <linux/delay.h> | |
12 | #include <linux/err.h> | |
3fb1b6ad | 13 | #include <linux/init.h> |
3fb1b6ad | 14 | #include <linux/interrupt.h> |
3fb1b6ad | 15 | #include <linux/io.h> |
e7a9bcc2 | 16 | #include <linux/ioport.h> |
3fb1b6ad | 17 | #include <linux/irq.h> |
7deeab5d | 18 | #include <linux/module.h> |
1768aa2f | 19 | #include <linux/of.h> |
2d1d5172 | 20 | #include <linux/of_device.h> |
e7a9bcc2 | 21 | #include <linux/platform_device.h> |
615a445f | 22 | #include <linux/pm_domain.h> |
bad81383 | 23 | #include <linux/pm_runtime.h> |
e7a9bcc2 LP |
24 | #include <linux/sh_timer.h> |
25 | #include <linux/slab.h> | |
26 | #include <linux/spinlock.h> | |
3fb1b6ad | 27 | |
507fd01d BG |
28 | #ifdef CONFIG_SUPERH |
29 | #include <asm/platform_early.h> | |
30 | #endif | |
31 | ||
2653caf4 | 32 | struct sh_cmt_device; |
7269f933 | 33 | |
2cda3ac4 LP |
34 | /* |
35 | * The CMT comes in 5 different identified flavours, depending not only on the | |
36 | * SoC but also on the particular instance. The following table lists the main | |
37 | * characteristics of those flavours. | |
38 | * | |
83c79a6d | 39 | * 16B 32B 32B-F 48B R-Car Gen2 |
2cda3ac4 LP |
40 | * ----------------------------------------------------------------------------- |
41 | * Channels 2 1/4 1 6 2/8 | |
42 | * Control Width 16 16 16 16 32 | |
43 | * Counter Width 16 32 32 32/48 32/48 | |
44 | * Shared Start/Stop Y Y Y Y N | |
45 | * | |
83c79a6d MD |
46 | * The r8a73a4 / R-Car Gen2 version has a per-channel start/stop register |
47 | * located in the channel registers block. All other versions have a shared | |
48 | * start/stop register located in the global space. | |
2cda3ac4 | 49 | * |
81b3b271 LP |
50 | * Channels are indexed from 0 to N-1 in the documentation. The channel index |
51 | * infers the start/stop bit position in the control register and the channel | |
52 | * registers block address. Some CMT instances have a subset of channels | |
53 | * available, in which case the index in the documentation doesn't match the | |
54 | * "real" index as implemented in hardware. This is for instance the case with | |
55 | * CMT0 on r8a7740, which is a 32-bit variant with a single channel numbered 0 | |
56 | * in the documentation but using start/stop bit 5 and having its registers | |
57 | * block at 0x60. | |
58 | * | |
59 | * Similarly CMT0 on r8a73a4, r8a7790 and r8a7791, while implementing 32-bit | |
2cda3ac4 LP |
60 | * channels only, is a 48-bit gen2 CMT with the 48-bit channels unavailable. |
61 | */ | |
62 | ||
63 | enum sh_cmt_model { | |
64 | SH_CMT_16BIT, | |
65 | SH_CMT_32BIT, | |
2cda3ac4 | 66 | SH_CMT_48BIT, |
83c79a6d MD |
67 | SH_CMT0_RCAR_GEN2, |
68 | SH_CMT1_RCAR_GEN2, | |
2cda3ac4 LP |
69 | }; |
70 | ||
71 | struct sh_cmt_info { | |
72 | enum sh_cmt_model model; | |
73 | ||
464eed84 MD |
74 | unsigned int channels_mask; |
75 | ||
2cda3ac4 | 76 | unsigned long width; /* 16 or 32 bit version of hardware block */ |
22627c6f SS |
77 | u32 overflow_bit; |
78 | u32 clear_bits; | |
2cda3ac4 LP |
79 | |
80 | /* callbacks for CMSTR and CMCSR access */ | |
22627c6f | 81 | u32 (*read_control)(void __iomem *base, unsigned long offs); |
2cda3ac4 | 82 | void (*write_control)(void __iomem *base, unsigned long offs, |
22627c6f | 83 | u32 value); |
2cda3ac4 LP |
84 | |
85 | /* callbacks for CMCNT and CMCOR access */ | |
22627c6f SS |
86 | u32 (*read_count)(void __iomem *base, unsigned long offs); |
87 | void (*write_count)(void __iomem *base, unsigned long offs, u32 value); | |
2cda3ac4 LP |
88 | }; |
89 | ||
7269f933 | 90 | struct sh_cmt_channel { |
2653caf4 | 91 | struct sh_cmt_device *cmt; |
3fb1b6ad | 92 | |
81b3b271 LP |
93 | unsigned int index; /* Index in the documentation */ |
94 | unsigned int hwidx; /* Real hardware index */ | |
95 | ||
96 | void __iomem *iostart; | |
97 | void __iomem *ioctrl; | |
c924d2d2 | 98 | |
81b3b271 | 99 | unsigned int timer_bit; |
3fb1b6ad | 100 | unsigned long flags; |
22627c6f SS |
101 | u32 match_value; |
102 | u32 next_match_value; | |
103 | u32 max_match_value; | |
7d0c399f | 104 | raw_spinlock_t lock; |
3fb1b6ad | 105 | struct clock_event_device ced; |
19bdc9d0 | 106 | struct clocksource cs; |
37e7742c | 107 | u64 total_cycles; |
bad81383 | 108 | bool cs_enabled; |
7269f933 LP |
109 | }; |
110 | ||
2653caf4 | 111 | struct sh_cmt_device { |
7269f933 LP |
112 | struct platform_device *pdev; |
113 | ||
2cda3ac4 LP |
114 | const struct sh_cmt_info *info; |
115 | ||
7269f933 | 116 | void __iomem *mapbase; |
7269f933 | 117 | struct clk *clk; |
890f423b | 118 | unsigned long rate; |
7269f933 | 119 | |
de599c88 LP |
120 | raw_spinlock_t lock; /* Protect the shared start/stop register */ |
121 | ||
f5ec9b19 LP |
122 | struct sh_cmt_channel *channels; |
123 | unsigned int num_channels; | |
1768aa2f | 124 | unsigned int hw_channels; |
81b3b271 LP |
125 | |
126 | bool has_clockevent; | |
127 | bool has_clocksource; | |
3fb1b6ad MD |
128 | }; |
129 | ||
d14be99b LP |
130 | #define SH_CMT16_CMCSR_CMF (1 << 7) |
131 | #define SH_CMT16_CMCSR_CMIE (1 << 6) | |
132 | #define SH_CMT16_CMCSR_CKS8 (0 << 0) | |
133 | #define SH_CMT16_CMCSR_CKS32 (1 << 0) | |
134 | #define SH_CMT16_CMCSR_CKS128 (2 << 0) | |
135 | #define SH_CMT16_CMCSR_CKS512 (3 << 0) | |
136 | #define SH_CMT16_CMCSR_CKS_MASK (3 << 0) | |
137 | ||
138 | #define SH_CMT32_CMCSR_CMF (1 << 15) | |
139 | #define SH_CMT32_CMCSR_OVF (1 << 14) | |
140 | #define SH_CMT32_CMCSR_WRFLG (1 << 13) | |
141 | #define SH_CMT32_CMCSR_STTF (1 << 12) | |
142 | #define SH_CMT32_CMCSR_STPF (1 << 11) | |
143 | #define SH_CMT32_CMCSR_SSIE (1 << 10) | |
144 | #define SH_CMT32_CMCSR_CMS (1 << 9) | |
145 | #define SH_CMT32_CMCSR_CMM (1 << 8) | |
146 | #define SH_CMT32_CMCSR_CMTOUT_IE (1 << 7) | |
147 | #define SH_CMT32_CMCSR_CMR_NONE (0 << 4) | |
148 | #define SH_CMT32_CMCSR_CMR_DMA (1 << 4) | |
149 | #define SH_CMT32_CMCSR_CMR_IRQ (2 << 4) | |
150 | #define SH_CMT32_CMCSR_CMR_MASK (3 << 4) | |
151 | #define SH_CMT32_CMCSR_DBGIVD (1 << 3) | |
152 | #define SH_CMT32_CMCSR_CKS_RCLK8 (4 << 0) | |
153 | #define SH_CMT32_CMCSR_CKS_RCLK32 (5 << 0) | |
154 | #define SH_CMT32_CMCSR_CKS_RCLK128 (6 << 0) | |
155 | #define SH_CMT32_CMCSR_CKS_RCLK1 (7 << 0) | |
156 | #define SH_CMT32_CMCSR_CKS_MASK (7 << 0) | |
157 | ||
22627c6f | 158 | static u32 sh_cmt_read16(void __iomem *base, unsigned long offs) |
587acb3d MD |
159 | { |
160 | return ioread16(base + (offs << 1)); | |
161 | } | |
162 | ||
22627c6f | 163 | static u32 sh_cmt_read32(void __iomem *base, unsigned long offs) |
a6a912ca MD |
164 | { |
165 | return ioread32(base + (offs << 2)); | |
166 | } | |
167 | ||
22627c6f | 168 | static void sh_cmt_write16(void __iomem *base, unsigned long offs, u32 value) |
587acb3d MD |
169 | { |
170 | iowrite16(value, base + (offs << 1)); | |
171 | } | |
3fb1b6ad | 172 | |
22627c6f | 173 | static void sh_cmt_write32(void __iomem *base, unsigned long offs, u32 value) |
a6a912ca MD |
174 | { |
175 | iowrite32(value, base + (offs << 2)); | |
176 | } | |
177 | ||
2cda3ac4 LP |
178 | static const struct sh_cmt_info sh_cmt_info[] = { |
179 | [SH_CMT_16BIT] = { | |
180 | .model = SH_CMT_16BIT, | |
181 | .width = 16, | |
d14be99b LP |
182 | .overflow_bit = SH_CMT16_CMCSR_CMF, |
183 | .clear_bits = ~SH_CMT16_CMCSR_CMF, | |
2cda3ac4 LP |
184 | .read_control = sh_cmt_read16, |
185 | .write_control = sh_cmt_write16, | |
186 | .read_count = sh_cmt_read16, | |
187 | .write_count = sh_cmt_write16, | |
188 | }, | |
189 | [SH_CMT_32BIT] = { | |
190 | .model = SH_CMT_32BIT, | |
191 | .width = 32, | |
d14be99b LP |
192 | .overflow_bit = SH_CMT32_CMCSR_CMF, |
193 | .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), | |
2cda3ac4 LP |
194 | .read_control = sh_cmt_read16, |
195 | .write_control = sh_cmt_write16, | |
196 | .read_count = sh_cmt_read32, | |
197 | .write_count = sh_cmt_write32, | |
198 | }, | |
2cda3ac4 LP |
199 | [SH_CMT_48BIT] = { |
200 | .model = SH_CMT_48BIT, | |
464eed84 | 201 | .channels_mask = 0x3f, |
2cda3ac4 | 202 | .width = 32, |
d14be99b LP |
203 | .overflow_bit = SH_CMT32_CMCSR_CMF, |
204 | .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), | |
2cda3ac4 LP |
205 | .read_control = sh_cmt_read32, |
206 | .write_control = sh_cmt_write32, | |
207 | .read_count = sh_cmt_read32, | |
208 | .write_count = sh_cmt_write32, | |
209 | }, | |
83c79a6d MD |
210 | [SH_CMT0_RCAR_GEN2] = { |
211 | .model = SH_CMT0_RCAR_GEN2, | |
212 | .channels_mask = 0x60, | |
213 | .width = 32, | |
214 | .overflow_bit = SH_CMT32_CMCSR_CMF, | |
215 | .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), | |
216 | .read_control = sh_cmt_read32, | |
217 | .write_control = sh_cmt_write32, | |
218 | .read_count = sh_cmt_read32, | |
219 | .write_count = sh_cmt_write32, | |
220 | }, | |
221 | [SH_CMT1_RCAR_GEN2] = { | |
222 | .model = SH_CMT1_RCAR_GEN2, | |
223 | .channels_mask = 0xff, | |
2cda3ac4 | 224 | .width = 32, |
d14be99b LP |
225 | .overflow_bit = SH_CMT32_CMCSR_CMF, |
226 | .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), | |
2cda3ac4 LP |
227 | .read_control = sh_cmt_read32, |
228 | .write_control = sh_cmt_write32, | |
229 | .read_count = sh_cmt_read32, | |
230 | .write_count = sh_cmt_write32, | |
231 | }, | |
232 | }; | |
233 | ||
3fb1b6ad MD |
234 | #define CMCSR 0 /* channel register */ |
235 | #define CMCNT 1 /* channel register */ | |
236 | #define CMCOR 2 /* channel register */ | |
237 | ||
2a97d553 GU |
238 | #define CMCLKE 0x1000 /* CLK Enable Register (R-Car Gen2) */ |
239 | ||
22627c6f | 240 | static inline u32 sh_cmt_read_cmstr(struct sh_cmt_channel *ch) |
1b56b96b | 241 | { |
81b3b271 LP |
242 | if (ch->iostart) |
243 | return ch->cmt->info->read_control(ch->iostart, 0); | |
244 | else | |
245 | return ch->cmt->info->read_control(ch->cmt->mapbase, 0); | |
1b56b96b MD |
246 | } |
247 | ||
22627c6f | 248 | static inline void sh_cmt_write_cmstr(struct sh_cmt_channel *ch, u32 value) |
1b56b96b | 249 | { |
81b3b271 LP |
250 | if (ch->iostart) |
251 | ch->cmt->info->write_control(ch->iostart, 0, value); | |
252 | else | |
253 | ch->cmt->info->write_control(ch->cmt->mapbase, 0, value); | |
1b56b96b MD |
254 | } |
255 | ||
22627c6f | 256 | static inline u32 sh_cmt_read_cmcsr(struct sh_cmt_channel *ch) |
1b56b96b | 257 | { |
81b3b271 | 258 | return ch->cmt->info->read_control(ch->ioctrl, CMCSR); |
3fb1b6ad MD |
259 | } |
260 | ||
22627c6f | 261 | static inline void sh_cmt_write_cmcsr(struct sh_cmt_channel *ch, u32 value) |
1b56b96b | 262 | { |
81b3b271 | 263 | ch->cmt->info->write_control(ch->ioctrl, CMCSR, value); |
1b56b96b MD |
264 | } |
265 | ||
22627c6f | 266 | static inline u32 sh_cmt_read_cmcnt(struct sh_cmt_channel *ch) |
1b56b96b | 267 | { |
81b3b271 | 268 | return ch->cmt->info->read_count(ch->ioctrl, CMCNT); |
1b56b96b MD |
269 | } |
270 | ||
22627c6f | 271 | static inline void sh_cmt_write_cmcnt(struct sh_cmt_channel *ch, u32 value) |
1b56b96b | 272 | { |
81b3b271 | 273 | ch->cmt->info->write_count(ch->ioctrl, CMCNT, value); |
1b56b96b MD |
274 | } |
275 | ||
22627c6f | 276 | static inline void sh_cmt_write_cmcor(struct sh_cmt_channel *ch, u32 value) |
1b56b96b | 277 | { |
81b3b271 | 278 | ch->cmt->info->write_count(ch->ioctrl, CMCOR, value); |
1b56b96b MD |
279 | } |
280 | ||
22627c6f | 281 | static u32 sh_cmt_get_counter(struct sh_cmt_channel *ch, u32 *has_wrapped) |
3fb1b6ad | 282 | { |
22627c6f SS |
283 | u32 v1, v2, v3; |
284 | u32 o1, o2; | |
5b644c7a | 285 | |
2cda3ac4 | 286 | o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit; |
3fb1b6ad MD |
287 | |
288 | /* Make sure the timer value is stable. Stolen from acpi_pm.c */ | |
289 | do { | |
5b644c7a | 290 | o2 = o1; |
7269f933 LP |
291 | v1 = sh_cmt_read_cmcnt(ch); |
292 | v2 = sh_cmt_read_cmcnt(ch); | |
293 | v3 = sh_cmt_read_cmcnt(ch); | |
2cda3ac4 | 294 | o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit; |
5b644c7a MD |
295 | } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3) |
296 | || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2))); | |
3fb1b6ad | 297 | |
5b644c7a | 298 | *has_wrapped = o1; |
3fb1b6ad MD |
299 | return v2; |
300 | } | |
301 | ||
7269f933 | 302 | static void sh_cmt_start_stop_ch(struct sh_cmt_channel *ch, int start) |
3fb1b6ad | 303 | { |
22627c6f SS |
304 | unsigned long flags; |
305 | u32 value; | |
3fb1b6ad MD |
306 | |
307 | /* start stop register shared by multiple timer channels */ | |
de599c88 | 308 | raw_spin_lock_irqsave(&ch->cmt->lock, flags); |
7269f933 | 309 | value = sh_cmt_read_cmstr(ch); |
3fb1b6ad MD |
310 | |
311 | if (start) | |
81b3b271 | 312 | value |= 1 << ch->timer_bit; |
3fb1b6ad | 313 | else |
81b3b271 | 314 | value &= ~(1 << ch->timer_bit); |
3fb1b6ad | 315 | |
7269f933 | 316 | sh_cmt_write_cmstr(ch, value); |
de599c88 | 317 | raw_spin_unlock_irqrestore(&ch->cmt->lock, flags); |
3fb1b6ad MD |
318 | } |
319 | ||
890f423b | 320 | static int sh_cmt_enable(struct sh_cmt_channel *ch) |
3fb1b6ad | 321 | { |
3f7e5e24 | 322 | int k, ret; |
3fb1b6ad | 323 | |
7269f933 | 324 | dev_pm_syscore_device(&ch->cmt->pdev->dev, true); |
bad81383 | 325 | |
9436b4ab | 326 | /* enable clock */ |
7269f933 | 327 | ret = clk_enable(ch->cmt->clk); |
3fb1b6ad | 328 | if (ret) { |
740a9518 LP |
329 | dev_err(&ch->cmt->pdev->dev, "ch%u: cannot enable clock\n", |
330 | ch->index); | |
3f7e5e24 | 331 | goto err0; |
3fb1b6ad | 332 | } |
3fb1b6ad MD |
333 | |
334 | /* make sure channel is disabled */ | |
7269f933 | 335 | sh_cmt_start_stop_ch(ch, 0); |
3fb1b6ad MD |
336 | |
337 | /* configure channel, periodic mode and maximum timeout */ | |
2cda3ac4 | 338 | if (ch->cmt->info->width == 16) { |
d14be99b LP |
339 | sh_cmt_write_cmcsr(ch, SH_CMT16_CMCSR_CMIE | |
340 | SH_CMT16_CMCSR_CKS512); | |
3014f474 | 341 | } else { |
68c70aae WS |
342 | u32 cmtout = ch->cmt->info->model <= SH_CMT_48BIT ? |
343 | SH_CMT32_CMCSR_CMTOUT_IE : 0; | |
344 | sh_cmt_write_cmcsr(ch, cmtout | SH_CMT32_CMCSR_CMM | | |
d14be99b LP |
345 | SH_CMT32_CMCSR_CMR_IRQ | |
346 | SH_CMT32_CMCSR_CKS_RCLK8); | |
3014f474 | 347 | } |
3fb1b6ad | 348 | |
7269f933 LP |
349 | sh_cmt_write_cmcor(ch, 0xffffffff); |
350 | sh_cmt_write_cmcnt(ch, 0); | |
3fb1b6ad | 351 | |
3f7e5e24 MD |
352 | /* |
353 | * According to the sh73a0 user's manual, as CMCNT can be operated | |
ad7794d4 | 354 | * only by the RCLK (Pseudo 32 kHz), there's one restriction on |
3f7e5e24 MD |
355 | * modifying CMCNT register; two RCLK cycles are necessary before |
356 | * this register is either read or any modification of the value | |
357 | * it holds is reflected in the LSI's actual operation. | |
358 | * | |
359 | * While at it, we're supposed to clear out the CMCNT as of this | |
360 | * moment, so make sure it's processed properly here. This will | |
361 | * take RCLKx2 at maximum. | |
362 | */ | |
363 | for (k = 0; k < 100; k++) { | |
7269f933 | 364 | if (!sh_cmt_read_cmcnt(ch)) |
3f7e5e24 MD |
365 | break; |
366 | udelay(1); | |
367 | } | |
368 | ||
7269f933 | 369 | if (sh_cmt_read_cmcnt(ch)) { |
740a9518 LP |
370 | dev_err(&ch->cmt->pdev->dev, "ch%u: cannot clear CMCNT\n", |
371 | ch->index); | |
3f7e5e24 MD |
372 | ret = -ETIMEDOUT; |
373 | goto err1; | |
374 | } | |
375 | ||
3fb1b6ad | 376 | /* enable channel */ |
7269f933 | 377 | sh_cmt_start_stop_ch(ch, 1); |
3fb1b6ad | 378 | return 0; |
3f7e5e24 MD |
379 | err1: |
380 | /* stop clock */ | |
7269f933 | 381 | clk_disable(ch->cmt->clk); |
3f7e5e24 MD |
382 | |
383 | err0: | |
384 | return ret; | |
3fb1b6ad MD |
385 | } |
386 | ||
7269f933 | 387 | static void sh_cmt_disable(struct sh_cmt_channel *ch) |
3fb1b6ad MD |
388 | { |
389 | /* disable channel */ | |
7269f933 | 390 | sh_cmt_start_stop_ch(ch, 0); |
3fb1b6ad | 391 | |
be890a1a | 392 | /* disable interrupts in CMT block */ |
7269f933 | 393 | sh_cmt_write_cmcsr(ch, 0); |
be890a1a | 394 | |
9436b4ab | 395 | /* stop clock */ |
7269f933 | 396 | clk_disable(ch->cmt->clk); |
bad81383 | 397 | |
7269f933 | 398 | dev_pm_syscore_device(&ch->cmt->pdev->dev, false); |
3fb1b6ad MD |
399 | } |
400 | ||
401 | /* private flags */ | |
402 | #define FLAG_CLOCKEVENT (1 << 0) | |
403 | #define FLAG_CLOCKSOURCE (1 << 1) | |
404 | #define FLAG_REPROGRAM (1 << 2) | |
405 | #define FLAG_SKIPEVENT (1 << 3) | |
406 | #define FLAG_IRQCONTEXT (1 << 4) | |
407 | ||
7269f933 | 408 | static void sh_cmt_clock_event_program_verify(struct sh_cmt_channel *ch, |
3fb1b6ad MD |
409 | int absolute) |
410 | { | |
22627c6f SS |
411 | u32 value = ch->next_match_value; |
412 | u32 new_match; | |
413 | u32 delay = 0; | |
414 | u32 now = 0; | |
415 | u32 has_wrapped; | |
3fb1b6ad | 416 | |
7269f933 LP |
417 | now = sh_cmt_get_counter(ch, &has_wrapped); |
418 | ch->flags |= FLAG_REPROGRAM; /* force reprogram */ | |
3fb1b6ad MD |
419 | |
420 | if (has_wrapped) { | |
421 | /* we're competing with the interrupt handler. | |
422 | * -> let the interrupt handler reprogram the timer. | |
423 | * -> interrupt number two handles the event. | |
424 | */ | |
7269f933 | 425 | ch->flags |= FLAG_SKIPEVENT; |
3fb1b6ad MD |
426 | return; |
427 | } | |
428 | ||
429 | if (absolute) | |
430 | now = 0; | |
431 | ||
432 | do { | |
433 | /* reprogram the timer hardware, | |
434 | * but don't save the new match value yet. | |
435 | */ | |
436 | new_match = now + value + delay; | |
7269f933 LP |
437 | if (new_match > ch->max_match_value) |
438 | new_match = ch->max_match_value; | |
3fb1b6ad | 439 | |
7269f933 | 440 | sh_cmt_write_cmcor(ch, new_match); |
3fb1b6ad | 441 | |
7269f933 LP |
442 | now = sh_cmt_get_counter(ch, &has_wrapped); |
443 | if (has_wrapped && (new_match > ch->match_value)) { | |
3fb1b6ad MD |
444 | /* we are changing to a greater match value, |
445 | * so this wrap must be caused by the counter | |
446 | * matching the old value. | |
447 | * -> first interrupt reprograms the timer. | |
448 | * -> interrupt number two handles the event. | |
449 | */ | |
7269f933 | 450 | ch->flags |= FLAG_SKIPEVENT; |
3fb1b6ad MD |
451 | break; |
452 | } | |
453 | ||
454 | if (has_wrapped) { | |
455 | /* we are changing to a smaller match value, | |
456 | * so the wrap must be caused by the counter | |
457 | * matching the new value. | |
458 | * -> save programmed match value. | |
459 | * -> let isr handle the event. | |
460 | */ | |
7269f933 | 461 | ch->match_value = new_match; |
3fb1b6ad MD |
462 | break; |
463 | } | |
464 | ||
465 | /* be safe: verify hardware settings */ | |
466 | if (now < new_match) { | |
467 | /* timer value is below match value, all good. | |
468 | * this makes sure we won't miss any match events. | |
469 | * -> save programmed match value. | |
470 | * -> let isr handle the event. | |
471 | */ | |
7269f933 | 472 | ch->match_value = new_match; |
3fb1b6ad MD |
473 | break; |
474 | } | |
475 | ||
476 | /* the counter has reached a value greater | |
477 | * than our new match value. and since the | |
478 | * has_wrapped flag isn't set we must have | |
479 | * programmed a too close event. | |
480 | * -> increase delay and retry. | |
481 | */ | |
482 | if (delay) | |
483 | delay <<= 1; | |
484 | else | |
485 | delay = 1; | |
486 | ||
487 | if (!delay) | |
740a9518 LP |
488 | dev_warn(&ch->cmt->pdev->dev, "ch%u: too long delay\n", |
489 | ch->index); | |
3fb1b6ad MD |
490 | |
491 | } while (delay); | |
492 | } | |
493 | ||
7269f933 | 494 | static void __sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta) |
3fb1b6ad | 495 | { |
7269f933 | 496 | if (delta > ch->max_match_value) |
740a9518 LP |
497 | dev_warn(&ch->cmt->pdev->dev, "ch%u: delta out of range\n", |
498 | ch->index); | |
3fb1b6ad | 499 | |
7269f933 LP |
500 | ch->next_match_value = delta; |
501 | sh_cmt_clock_event_program_verify(ch, 0); | |
65ada547 TY |
502 | } |
503 | ||
7269f933 | 504 | static void sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta) |
65ada547 TY |
505 | { |
506 | unsigned long flags; | |
507 | ||
7269f933 LP |
508 | raw_spin_lock_irqsave(&ch->lock, flags); |
509 | __sh_cmt_set_next(ch, delta); | |
510 | raw_spin_unlock_irqrestore(&ch->lock, flags); | |
3fb1b6ad MD |
511 | } |
512 | ||
513 | static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id) | |
514 | { | |
7269f933 | 515 | struct sh_cmt_channel *ch = dev_id; |
3fb1b6ad MD |
516 | |
517 | /* clear flags */ | |
2cda3ac4 LP |
518 | sh_cmt_write_cmcsr(ch, sh_cmt_read_cmcsr(ch) & |
519 | ch->cmt->info->clear_bits); | |
3fb1b6ad MD |
520 | |
521 | /* update clock source counter to begin with if enabled | |
522 | * the wrap flag should be cleared by the timer specific | |
523 | * isr before we end up here. | |
524 | */ | |
7269f933 LP |
525 | if (ch->flags & FLAG_CLOCKSOURCE) |
526 | ch->total_cycles += ch->match_value + 1; | |
3fb1b6ad | 527 | |
7269f933 LP |
528 | if (!(ch->flags & FLAG_REPROGRAM)) |
529 | ch->next_match_value = ch->max_match_value; | |
3fb1b6ad | 530 | |
7269f933 | 531 | ch->flags |= FLAG_IRQCONTEXT; |
3fb1b6ad | 532 | |
7269f933 LP |
533 | if (ch->flags & FLAG_CLOCKEVENT) { |
534 | if (!(ch->flags & FLAG_SKIPEVENT)) { | |
051b782e | 535 | if (clockevent_state_oneshot(&ch->ced)) { |
7269f933 LP |
536 | ch->next_match_value = ch->max_match_value; |
537 | ch->flags |= FLAG_REPROGRAM; | |
3fb1b6ad MD |
538 | } |
539 | ||
7269f933 | 540 | ch->ced.event_handler(&ch->ced); |
3fb1b6ad MD |
541 | } |
542 | } | |
543 | ||
7269f933 | 544 | ch->flags &= ~FLAG_SKIPEVENT; |
3fb1b6ad | 545 | |
7269f933 LP |
546 | if (ch->flags & FLAG_REPROGRAM) { |
547 | ch->flags &= ~FLAG_REPROGRAM; | |
548 | sh_cmt_clock_event_program_verify(ch, 1); | |
3fb1b6ad | 549 | |
7269f933 | 550 | if (ch->flags & FLAG_CLOCKEVENT) |
051b782e | 551 | if ((clockevent_state_shutdown(&ch->ced)) |
7269f933 LP |
552 | || (ch->match_value == ch->next_match_value)) |
553 | ch->flags &= ~FLAG_REPROGRAM; | |
3fb1b6ad MD |
554 | } |
555 | ||
7269f933 | 556 | ch->flags &= ~FLAG_IRQCONTEXT; |
3fb1b6ad MD |
557 | |
558 | return IRQ_HANDLED; | |
559 | } | |
560 | ||
7269f933 | 561 | static int sh_cmt_start(struct sh_cmt_channel *ch, unsigned long flag) |
3fb1b6ad MD |
562 | { |
563 | int ret = 0; | |
564 | unsigned long flags; | |
565 | ||
8ae954ca NS |
566 | if (flag & FLAG_CLOCKSOURCE) |
567 | pm_runtime_get_sync(&ch->cmt->pdev->dev); | |
568 | ||
7269f933 | 569 | raw_spin_lock_irqsave(&ch->lock, flags); |
3fb1b6ad | 570 | |
8ae954ca NS |
571 | if (!(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) { |
572 | if (flag & FLAG_CLOCKEVENT) | |
573 | pm_runtime_get_sync(&ch->cmt->pdev->dev); | |
890f423b | 574 | ret = sh_cmt_enable(ch); |
8ae954ca | 575 | } |
3fb1b6ad MD |
576 | |
577 | if (ret) | |
578 | goto out; | |
7269f933 | 579 | ch->flags |= flag; |
3fb1b6ad MD |
580 | |
581 | /* setup timeout if no clockevent */ | |
7269f933 LP |
582 | if ((flag == FLAG_CLOCKSOURCE) && (!(ch->flags & FLAG_CLOCKEVENT))) |
583 | __sh_cmt_set_next(ch, ch->max_match_value); | |
3fb1b6ad | 584 | out: |
7269f933 | 585 | raw_spin_unlock_irqrestore(&ch->lock, flags); |
3fb1b6ad MD |
586 | |
587 | return ret; | |
588 | } | |
589 | ||
7269f933 | 590 | static void sh_cmt_stop(struct sh_cmt_channel *ch, unsigned long flag) |
3fb1b6ad MD |
591 | { |
592 | unsigned long flags; | |
593 | unsigned long f; | |
594 | ||
7269f933 | 595 | raw_spin_lock_irqsave(&ch->lock, flags); |
3fb1b6ad | 596 | |
7269f933 LP |
597 | f = ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE); |
598 | ch->flags &= ~flag; | |
3fb1b6ad | 599 | |
8ae954ca | 600 | if (f && !(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) { |
7269f933 | 601 | sh_cmt_disable(ch); |
8ae954ca NS |
602 | if (flag & FLAG_CLOCKEVENT) |
603 | pm_runtime_put(&ch->cmt->pdev->dev); | |
604 | } | |
3fb1b6ad MD |
605 | |
606 | /* adjust the timeout to maximum if only clocksource left */ | |
7269f933 LP |
607 | if ((flag == FLAG_CLOCKEVENT) && (ch->flags & FLAG_CLOCKSOURCE)) |
608 | __sh_cmt_set_next(ch, ch->max_match_value); | |
3fb1b6ad | 609 | |
7269f933 | 610 | raw_spin_unlock_irqrestore(&ch->lock, flags); |
8ae954ca NS |
611 | |
612 | if (flag & FLAG_CLOCKSOURCE) | |
613 | pm_runtime_put(&ch->cmt->pdev->dev); | |
3fb1b6ad MD |
614 | } |
615 | ||
7269f933 | 616 | static struct sh_cmt_channel *cs_to_sh_cmt(struct clocksource *cs) |
19bdc9d0 | 617 | { |
7269f933 | 618 | return container_of(cs, struct sh_cmt_channel, cs); |
19bdc9d0 MD |
619 | } |
620 | ||
a5a1d1c2 | 621 | static u64 sh_cmt_clocksource_read(struct clocksource *cs) |
19bdc9d0 | 622 | { |
7269f933 | 623 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
22627c6f | 624 | unsigned long flags; |
22627c6f | 625 | u32 has_wrapped; |
37e7742c | 626 | u64 value; |
22627c6f | 627 | u32 raw; |
19bdc9d0 | 628 | |
7269f933 LP |
629 | raw_spin_lock_irqsave(&ch->lock, flags); |
630 | value = ch->total_cycles; | |
631 | raw = sh_cmt_get_counter(ch, &has_wrapped); | |
19bdc9d0 MD |
632 | |
633 | if (unlikely(has_wrapped)) | |
7269f933 LP |
634 | raw += ch->match_value + 1; |
635 | raw_spin_unlock_irqrestore(&ch->lock, flags); | |
19bdc9d0 MD |
636 | |
637 | return value + raw; | |
638 | } | |
639 | ||
640 | static int sh_cmt_clocksource_enable(struct clocksource *cs) | |
641 | { | |
3593f5fe | 642 | int ret; |
7269f933 | 643 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
19bdc9d0 | 644 | |
7269f933 | 645 | WARN_ON(ch->cs_enabled); |
bad81383 | 646 | |
7269f933 | 647 | ch->total_cycles = 0; |
19bdc9d0 | 648 | |
7269f933 | 649 | ret = sh_cmt_start(ch, FLAG_CLOCKSOURCE); |
890f423b | 650 | if (!ret) |
7269f933 | 651 | ch->cs_enabled = true; |
890f423b | 652 | |
3593f5fe | 653 | return ret; |
19bdc9d0 MD |
654 | } |
655 | ||
656 | static void sh_cmt_clocksource_disable(struct clocksource *cs) | |
657 | { | |
7269f933 | 658 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
bad81383 | 659 | |
7269f933 | 660 | WARN_ON(!ch->cs_enabled); |
bad81383 | 661 | |
7269f933 LP |
662 | sh_cmt_stop(ch, FLAG_CLOCKSOURCE); |
663 | ch->cs_enabled = false; | |
19bdc9d0 MD |
664 | } |
665 | ||
9bb5ec88 RW |
666 | static void sh_cmt_clocksource_suspend(struct clocksource *cs) |
667 | { | |
7269f933 | 668 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
9bb5ec88 | 669 | |
54d46b7f GU |
670 | if (!ch->cs_enabled) |
671 | return; | |
672 | ||
7269f933 | 673 | sh_cmt_stop(ch, FLAG_CLOCKSOURCE); |
fc519890 | 674 | dev_pm_genpd_suspend(&ch->cmt->pdev->dev); |
9bb5ec88 RW |
675 | } |
676 | ||
c8162884 MD |
677 | static void sh_cmt_clocksource_resume(struct clocksource *cs) |
678 | { | |
7269f933 | 679 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
9bb5ec88 | 680 | |
54d46b7f GU |
681 | if (!ch->cs_enabled) |
682 | return; | |
683 | ||
fc519890 | 684 | dev_pm_genpd_resume(&ch->cmt->pdev->dev); |
7269f933 | 685 | sh_cmt_start(ch, FLAG_CLOCKSOURCE); |
c8162884 MD |
686 | } |
687 | ||
7269f933 | 688 | static int sh_cmt_register_clocksource(struct sh_cmt_channel *ch, |
fb28a659 | 689 | const char *name) |
19bdc9d0 | 690 | { |
7269f933 | 691 | struct clocksource *cs = &ch->cs; |
19bdc9d0 MD |
692 | |
693 | cs->name = name; | |
fb28a659 | 694 | cs->rating = 125; |
19bdc9d0 MD |
695 | cs->read = sh_cmt_clocksource_read; |
696 | cs->enable = sh_cmt_clocksource_enable; | |
697 | cs->disable = sh_cmt_clocksource_disable; | |
9bb5ec88 | 698 | cs->suspend = sh_cmt_clocksource_suspend; |
c8162884 | 699 | cs->resume = sh_cmt_clocksource_resume; |
37e7742c | 700 | cs->mask = CLOCKSOURCE_MASK(sizeof(u64) * 8); |
19bdc9d0 | 701 | cs->flags = CLOCK_SOURCE_IS_CONTINUOUS; |
f4d7c356 | 702 | |
740a9518 LP |
703 | dev_info(&ch->cmt->pdev->dev, "ch%u: used as clock source\n", |
704 | ch->index); | |
f4d7c356 | 705 | |
890f423b | 706 | clocksource_register_hz(cs, ch->cmt->rate); |
19bdc9d0 MD |
707 | return 0; |
708 | } | |
709 | ||
7269f933 | 710 | static struct sh_cmt_channel *ced_to_sh_cmt(struct clock_event_device *ced) |
3fb1b6ad | 711 | { |
7269f933 | 712 | return container_of(ced, struct sh_cmt_channel, ced); |
3fb1b6ad MD |
713 | } |
714 | ||
7269f933 | 715 | static void sh_cmt_clock_event_start(struct sh_cmt_channel *ch, int periodic) |
3fb1b6ad | 716 | { |
7269f933 | 717 | sh_cmt_start(ch, FLAG_CLOCKEVENT); |
3fb1b6ad | 718 | |
3fb1b6ad | 719 | if (periodic) |
890f423b | 720 | sh_cmt_set_next(ch, ((ch->cmt->rate + HZ/2) / HZ) - 1); |
3fb1b6ad | 721 | else |
7269f933 | 722 | sh_cmt_set_next(ch, ch->max_match_value); |
3fb1b6ad MD |
723 | } |
724 | ||
051b782e VK |
725 | static int sh_cmt_clock_event_shutdown(struct clock_event_device *ced) |
726 | { | |
727 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); | |
728 | ||
729 | sh_cmt_stop(ch, FLAG_CLOCKEVENT); | |
730 | return 0; | |
731 | } | |
732 | ||
733 | static int sh_cmt_clock_event_set_state(struct clock_event_device *ced, | |
734 | int periodic) | |
3fb1b6ad | 735 | { |
7269f933 | 736 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); |
3fb1b6ad MD |
737 | |
738 | /* deal with old setting first */ | |
051b782e | 739 | if (clockevent_state_oneshot(ced) || clockevent_state_periodic(ced)) |
7269f933 | 740 | sh_cmt_stop(ch, FLAG_CLOCKEVENT); |
3fb1b6ad | 741 | |
051b782e VK |
742 | dev_info(&ch->cmt->pdev->dev, "ch%u: used for %s clock events\n", |
743 | ch->index, periodic ? "periodic" : "oneshot"); | |
744 | sh_cmt_clock_event_start(ch, periodic); | |
745 | return 0; | |
746 | } | |
747 | ||
748 | static int sh_cmt_clock_event_set_oneshot(struct clock_event_device *ced) | |
749 | { | |
750 | return sh_cmt_clock_event_set_state(ced, 0); | |
751 | } | |
752 | ||
753 | static int sh_cmt_clock_event_set_periodic(struct clock_event_device *ced) | |
754 | { | |
755 | return sh_cmt_clock_event_set_state(ced, 1); | |
3fb1b6ad MD |
756 | } |
757 | ||
758 | static int sh_cmt_clock_event_next(unsigned long delta, | |
759 | struct clock_event_device *ced) | |
760 | { | |
7269f933 | 761 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); |
3fb1b6ad | 762 | |
051b782e | 763 | BUG_ON(!clockevent_state_oneshot(ced)); |
7269f933 LP |
764 | if (likely(ch->flags & FLAG_IRQCONTEXT)) |
765 | ch->next_match_value = delta - 1; | |
3fb1b6ad | 766 | else |
7269f933 | 767 | sh_cmt_set_next(ch, delta - 1); |
3fb1b6ad MD |
768 | |
769 | return 0; | |
770 | } | |
771 | ||
9bb5ec88 RW |
772 | static void sh_cmt_clock_event_suspend(struct clock_event_device *ced) |
773 | { | |
7269f933 | 774 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); |
57dee992 | 775 | |
fc519890 | 776 | dev_pm_genpd_suspend(&ch->cmt->pdev->dev); |
7269f933 | 777 | clk_unprepare(ch->cmt->clk); |
9bb5ec88 RW |
778 | } |
779 | ||
780 | static void sh_cmt_clock_event_resume(struct clock_event_device *ced) | |
781 | { | |
7269f933 | 782 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); |
57dee992 | 783 | |
7269f933 | 784 | clk_prepare(ch->cmt->clk); |
fc519890 | 785 | dev_pm_genpd_resume(&ch->cmt->pdev->dev); |
9bb5ec88 RW |
786 | } |
787 | ||
bfa76bb1 LP |
788 | static int sh_cmt_register_clockevent(struct sh_cmt_channel *ch, |
789 | const char *name) | |
3fb1b6ad | 790 | { |
7269f933 | 791 | struct clock_event_device *ced = &ch->ced; |
bfa76bb1 LP |
792 | int irq; |
793 | int ret; | |
794 | ||
31e912f5 | 795 | irq = platform_get_irq(ch->cmt->pdev, ch->index); |
9f475d08 | 796 | if (irq < 0) |
bfa76bb1 | 797 | return irq; |
bfa76bb1 LP |
798 | |
799 | ret = request_irq(irq, sh_cmt_interrupt, | |
800 | IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING, | |
801 | dev_name(&ch->cmt->pdev->dev), ch); | |
802 | if (ret) { | |
803 | dev_err(&ch->cmt->pdev->dev, "ch%u: failed to request irq %d\n", | |
804 | ch->index, irq); | |
805 | return ret; | |
806 | } | |
3fb1b6ad | 807 | |
3fb1b6ad MD |
808 | ced->name = name; |
809 | ced->features = CLOCK_EVT_FEAT_PERIODIC; | |
810 | ced->features |= CLOCK_EVT_FEAT_ONESHOT; | |
b7fcbb0f | 811 | ced->rating = 125; |
f1ebe1e4 | 812 | ced->cpumask = cpu_possible_mask; |
3fb1b6ad | 813 | ced->set_next_event = sh_cmt_clock_event_next; |
051b782e VK |
814 | ced->set_state_shutdown = sh_cmt_clock_event_shutdown; |
815 | ced->set_state_periodic = sh_cmt_clock_event_set_periodic; | |
816 | ced->set_state_oneshot = sh_cmt_clock_event_set_oneshot; | |
9bb5ec88 RW |
817 | ced->suspend = sh_cmt_clock_event_suspend; |
818 | ced->resume = sh_cmt_clock_event_resume; | |
3fb1b6ad | 819 | |
890f423b NS |
820 | /* TODO: calculate good shift from rate and counter bit width */ |
821 | ced->shift = 32; | |
822 | ced->mult = div_sc(ch->cmt->rate, NSEC_PER_SEC, ced->shift); | |
823 | ced->max_delta_ns = clockevent_delta2ns(ch->max_match_value, ced); | |
bb2e94ac | 824 | ced->max_delta_ticks = ch->max_match_value; |
890f423b | 825 | ced->min_delta_ns = clockevent_delta2ns(0x1f, ced); |
bb2e94ac | 826 | ced->min_delta_ticks = 0x1f; |
890f423b | 827 | |
740a9518 LP |
828 | dev_info(&ch->cmt->pdev->dev, "ch%u: used for clock events\n", |
829 | ch->index); | |
3fb1b6ad | 830 | clockevents_register_device(ced); |
bfa76bb1 LP |
831 | |
832 | return 0; | |
3fb1b6ad MD |
833 | } |
834 | ||
1d053e1d | 835 | static int sh_cmt_register(struct sh_cmt_channel *ch, const char *name, |
fb28a659 | 836 | bool clockevent, bool clocksource) |
3fb1b6ad | 837 | { |
bfa76bb1 LP |
838 | int ret; |
839 | ||
81b3b271 LP |
840 | if (clockevent) { |
841 | ch->cmt->has_clockevent = true; | |
bfa76bb1 LP |
842 | ret = sh_cmt_register_clockevent(ch, name); |
843 | if (ret < 0) | |
844 | return ret; | |
81b3b271 | 845 | } |
3fb1b6ad | 846 | |
81b3b271 LP |
847 | if (clocksource) { |
848 | ch->cmt->has_clocksource = true; | |
fb28a659 | 849 | sh_cmt_register_clocksource(ch, name); |
81b3b271 | 850 | } |
19bdc9d0 | 851 | |
3fb1b6ad MD |
852 | return 0; |
853 | } | |
854 | ||
740a9518 | 855 | static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index, |
81b3b271 LP |
856 | unsigned int hwidx, bool clockevent, |
857 | bool clocksource, struct sh_cmt_device *cmt) | |
b882e7b1 | 858 | { |
2a97d553 | 859 | u32 value; |
b882e7b1 LP |
860 | int ret; |
861 | ||
81b3b271 LP |
862 | /* Skip unused channels. */ |
863 | if (!clockevent && !clocksource) | |
864 | return 0; | |
865 | ||
b882e7b1 | 866 | ch->cmt = cmt; |
740a9518 | 867 | ch->index = index; |
81b3b271 | 868 | ch->hwidx = hwidx; |
83c79a6d | 869 | ch->timer_bit = hwidx; |
81b3b271 LP |
870 | |
871 | /* | |
872 | * Compute the address of the channel control register block. For the | |
873 | * timers with a per-channel start/stop register, compute its address | |
874 | * as well. | |
81b3b271 | 875 | */ |
31e912f5 LP |
876 | switch (cmt->info->model) { |
877 | case SH_CMT_16BIT: | |
878 | ch->ioctrl = cmt->mapbase + 2 + ch->hwidx * 6; | |
879 | break; | |
880 | case SH_CMT_32BIT: | |
881 | case SH_CMT_48BIT: | |
882 | ch->ioctrl = cmt->mapbase + 0x10 + ch->hwidx * 0x10; | |
883 | break; | |
83c79a6d MD |
884 | case SH_CMT0_RCAR_GEN2: |
885 | case SH_CMT1_RCAR_GEN2: | |
31e912f5 LP |
886 | ch->iostart = cmt->mapbase + ch->hwidx * 0x100; |
887 | ch->ioctrl = ch->iostart + 0x10; | |
83c79a6d | 888 | ch->timer_bit = 0; |
2a97d553 GU |
889 | |
890 | /* Enable the clock supply to the channel */ | |
891 | value = ioread32(cmt->mapbase + CMCLKE); | |
892 | value |= BIT(hwidx); | |
893 | iowrite32(value, cmt->mapbase + CMCLKE); | |
31e912f5 | 894 | break; |
81b3b271 LP |
895 | } |
896 | ||
2cda3ac4 | 897 | if (cmt->info->width == (sizeof(ch->max_match_value) * 8)) |
b882e7b1 LP |
898 | ch->max_match_value = ~0; |
899 | else | |
2cda3ac4 | 900 | ch->max_match_value = (1 << cmt->info->width) - 1; |
b882e7b1 LP |
901 | |
902 | ch->match_value = ch->max_match_value; | |
903 | raw_spin_lock_init(&ch->lock); | |
904 | ||
1d053e1d | 905 | ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev), |
81b3b271 | 906 | clockevent, clocksource); |
b882e7b1 | 907 | if (ret) { |
740a9518 LP |
908 | dev_err(&cmt->pdev->dev, "ch%u: registration failed\n", |
909 | ch->index); | |
b882e7b1 LP |
910 | return ret; |
911 | } | |
912 | ch->cs_enabled = false; | |
913 | ||
b882e7b1 LP |
914 | return 0; |
915 | } | |
916 | ||
81b3b271 | 917 | static int sh_cmt_map_memory(struct sh_cmt_device *cmt) |
3fb1b6ad | 918 | { |
81b3b271 | 919 | struct resource *mem; |
3fb1b6ad | 920 | |
81b3b271 LP |
921 | mem = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 0); |
922 | if (!mem) { | |
923 | dev_err(&cmt->pdev->dev, "failed to get I/O memory\n"); | |
924 | return -ENXIO; | |
925 | } | |
3fb1b6ad | 926 | |
4bdc0d67 | 927 | cmt->mapbase = ioremap(mem->start, resource_size(mem)); |
81b3b271 LP |
928 | if (cmt->mapbase == NULL) { |
929 | dev_err(&cmt->pdev->dev, "failed to remap I/O memory\n"); | |
930 | return -ENXIO; | |
3fb1b6ad MD |
931 | } |
932 | ||
81b3b271 LP |
933 | return 0; |
934 | } | |
935 | ||
1768aa2f LP |
936 | static const struct platform_device_id sh_cmt_id_table[] = { |
937 | { "sh-cmt-16", (kernel_ulong_t)&sh_cmt_info[SH_CMT_16BIT] }, | |
938 | { "sh-cmt-32", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT] }, | |
1768aa2f LP |
939 | { } |
940 | }; | |
941 | MODULE_DEVICE_TABLE(platform, sh_cmt_id_table); | |
942 | ||
943 | static const struct of_device_id sh_cmt_of_table[] __maybe_unused = { | |
19d60845 MD |
944 | { |
945 | /* deprecated, preserved for backward compatibility */ | |
946 | .compatible = "renesas,cmt-48", | |
947 | .data = &sh_cmt_info[SH_CMT_48BIT] | |
948 | }, | |
8d50e947 GU |
949 | { |
950 | /* deprecated, preserved for backward compatibility */ | |
951 | .compatible = "renesas,cmt-48-gen2", | |
952 | .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2] | |
8c1afba2 MD |
953 | }, |
954 | { | |
955 | .compatible = "renesas,r8a7740-cmt1", | |
956 | .data = &sh_cmt_info[SH_CMT_48BIT] | |
957 | }, | |
958 | { | |
959 | .compatible = "renesas,sh73a0-cmt1", | |
960 | .data = &sh_cmt_info[SH_CMT_48BIT] | |
8d50e947 | 961 | }, |
eceb4c49 SS |
962 | { |
963 | .compatible = "renesas,rcar-gen2-cmt0", | |
964 | .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2] | |
965 | }, | |
966 | { | |
967 | .compatible = "renesas,rcar-gen2-cmt1", | |
968 | .data = &sh_cmt_info[SH_CMT1_RCAR_GEN2] | |
969 | }, | |
ac142a7f SS |
970 | { |
971 | .compatible = "renesas,rcar-gen3-cmt0", | |
972 | .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2] | |
973 | }, | |
974 | { | |
975 | .compatible = "renesas,rcar-gen3-cmt1", | |
976 | .data = &sh_cmt_info[SH_CMT1_RCAR_GEN2] | |
977 | }, | |
1768aa2f LP |
978 | { } |
979 | }; | |
980 | MODULE_DEVICE_TABLE(of, sh_cmt_of_table); | |
981 | ||
81b3b271 LP |
982 | static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev) |
983 | { | |
31e912f5 LP |
984 | unsigned int mask; |
985 | unsigned int i; | |
81b3b271 LP |
986 | int ret; |
987 | ||
81b3b271 | 988 | cmt->pdev = pdev; |
de599c88 | 989 | raw_spin_lock_init(&cmt->lock); |
81b3b271 | 990 | |
1768aa2f | 991 | if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) { |
2d1d5172 | 992 | cmt->info = of_device_get_match_data(&pdev->dev); |
d1d28597 | 993 | cmt->hw_channels = cmt->info->channels_mask; |
1768aa2f LP |
994 | } else if (pdev->dev.platform_data) { |
995 | struct sh_timer_config *cfg = pdev->dev.platform_data; | |
996 | const struct platform_device_id *id = pdev->id_entry; | |
997 | ||
998 | cmt->info = (const struct sh_cmt_info *)id->driver_data; | |
999 | cmt->hw_channels = cfg->channels_mask; | |
1000 | } else { | |
81b3b271 LP |
1001 | dev_err(&cmt->pdev->dev, "missing platform data\n"); |
1002 | return -ENXIO; | |
1003 | } | |
1004 | ||
81b3b271 | 1005 | /* Get hold of clock. */ |
31e912f5 | 1006 | cmt->clk = clk_get(&cmt->pdev->dev, "fck"); |
2653caf4 LP |
1007 | if (IS_ERR(cmt->clk)) { |
1008 | dev_err(&cmt->pdev->dev, "cannot get clock\n"); | |
81b3b271 | 1009 | return PTR_ERR(cmt->clk); |
3fb1b6ad MD |
1010 | } |
1011 | ||
2653caf4 | 1012 | ret = clk_prepare(cmt->clk); |
57dee992 | 1013 | if (ret < 0) |
81b3b271 | 1014 | goto err_clk_put; |
57dee992 | 1015 | |
890f423b NS |
1016 | /* Determine clock rate. */ |
1017 | ret = clk_enable(cmt->clk); | |
1018 | if (ret < 0) | |
1019 | goto err_clk_unprepare; | |
1020 | ||
1021 | if (cmt->info->width == 16) | |
1022 | cmt->rate = clk_get_rate(cmt->clk) / 512; | |
1023 | else | |
1024 | cmt->rate = clk_get_rate(cmt->clk) / 8; | |
1025 | ||
31e912f5 LP |
1026 | /* Map the memory resource(s). */ |
1027 | ret = sh_cmt_map_memory(cmt); | |
81b3b271 | 1028 | if (ret < 0) |
2a97d553 | 1029 | goto err_clk_disable; |
81b3b271 LP |
1030 | |
1031 | /* Allocate and setup the channels. */ | |
1768aa2f | 1032 | cmt->num_channels = hweight8(cmt->hw_channels); |
6396bb22 | 1033 | cmt->channels = kcalloc(cmt->num_channels, sizeof(*cmt->channels), |
81b3b271 | 1034 | GFP_KERNEL); |
f5ec9b19 LP |
1035 | if (cmt->channels == NULL) { |
1036 | ret = -ENOMEM; | |
81b3b271 | 1037 | goto err_unmap; |
f5ec9b19 LP |
1038 | } |
1039 | ||
31e912f5 LP |
1040 | /* |
1041 | * Use the first channel as a clock event device and the second channel | |
1042 | * as a clock source. If only one channel is available use it for both. | |
1043 | */ | |
1768aa2f | 1044 | for (i = 0, mask = cmt->hw_channels; i < cmt->num_channels; ++i) { |
31e912f5 LP |
1045 | unsigned int hwidx = ffs(mask) - 1; |
1046 | bool clocksource = i == 1 || cmt->num_channels == 1; | |
1047 | bool clockevent = i == 0; | |
1048 | ||
1049 | ret = sh_cmt_setup_channel(&cmt->channels[i], i, hwidx, | |
1050 | clockevent, clocksource, cmt); | |
81b3b271 LP |
1051 | if (ret < 0) |
1052 | goto err_unmap; | |
f5ec9b19 | 1053 | |
31e912f5 | 1054 | mask &= ~(1 << hwidx); |
81b3b271 | 1055 | } |
da64c2a8 | 1056 | |
2a97d553 GU |
1057 | clk_disable(cmt->clk); |
1058 | ||
2653caf4 | 1059 | platform_set_drvdata(pdev, cmt); |
adccc69e | 1060 | |
da64c2a8 | 1061 | return 0; |
81b3b271 LP |
1062 | |
1063 | err_unmap: | |
f5ec9b19 | 1064 | kfree(cmt->channels); |
31e912f5 | 1065 | iounmap(cmt->mapbase); |
2a97d553 GU |
1066 | err_clk_disable: |
1067 | clk_disable(cmt->clk); | |
81b3b271 | 1068 | err_clk_unprepare: |
2653caf4 | 1069 | clk_unprepare(cmt->clk); |
81b3b271 | 1070 | err_clk_put: |
2653caf4 | 1071 | clk_put(cmt->clk); |
3fb1b6ad MD |
1072 | return ret; |
1073 | } | |
1074 | ||
1850514b | 1075 | static int sh_cmt_probe(struct platform_device *pdev) |
3fb1b6ad | 1076 | { |
2653caf4 | 1077 | struct sh_cmt_device *cmt = platform_get_drvdata(pdev); |
3fb1b6ad MD |
1078 | int ret; |
1079 | ||
201e9109 | 1080 | if (!is_sh_early_platform_device(pdev)) { |
bad81383 RW |
1081 | pm_runtime_set_active(&pdev->dev); |
1082 | pm_runtime_enable(&pdev->dev); | |
9bb5ec88 | 1083 | } |
615a445f | 1084 | |
2653caf4 | 1085 | if (cmt) { |
214a607a | 1086 | dev_info(&pdev->dev, "kept as earlytimer\n"); |
bad81383 | 1087 | goto out; |
e475eedb MD |
1088 | } |
1089 | ||
b262bc74 | 1090 | cmt = kzalloc(sizeof(*cmt), GFP_KERNEL); |
0178f41d | 1091 | if (cmt == NULL) |
3fb1b6ad | 1092 | return -ENOMEM; |
3fb1b6ad | 1093 | |
2653caf4 | 1094 | ret = sh_cmt_setup(cmt, pdev); |
3fb1b6ad | 1095 | if (ret) { |
2653caf4 | 1096 | kfree(cmt); |
bad81383 RW |
1097 | pm_runtime_idle(&pdev->dev); |
1098 | return ret; | |
3fb1b6ad | 1099 | } |
201e9109 | 1100 | if (is_sh_early_platform_device(pdev)) |
bad81383 RW |
1101 | return 0; |
1102 | ||
1103 | out: | |
81b3b271 | 1104 | if (cmt->has_clockevent || cmt->has_clocksource) |
bad81383 RW |
1105 | pm_runtime_irq_safe(&pdev->dev); |
1106 | else | |
1107 | pm_runtime_idle(&pdev->dev); | |
1108 | ||
1109 | return 0; | |
3fb1b6ad MD |
1110 | } |
1111 | ||
1850514b | 1112 | static int sh_cmt_remove(struct platform_device *pdev) |
3fb1b6ad MD |
1113 | { |
1114 | return -EBUSY; /* cannot unregister clockevent and clocksource */ | |
1115 | } | |
1116 | ||
1117 | static struct platform_driver sh_cmt_device_driver = { | |
1118 | .probe = sh_cmt_probe, | |
1850514b | 1119 | .remove = sh_cmt_remove, |
3fb1b6ad MD |
1120 | .driver = { |
1121 | .name = "sh_cmt", | |
1768aa2f | 1122 | .of_match_table = of_match_ptr(sh_cmt_of_table), |
81b3b271 LP |
1123 | }, |
1124 | .id_table = sh_cmt_id_table, | |
3fb1b6ad MD |
1125 | }; |
1126 | ||
1127 | static int __init sh_cmt_init(void) | |
1128 | { | |
1129 | return platform_driver_register(&sh_cmt_device_driver); | |
1130 | } | |
1131 | ||
1132 | static void __exit sh_cmt_exit(void) | |
1133 | { | |
1134 | platform_driver_unregister(&sh_cmt_device_driver); | |
1135 | } | |
1136 | ||
507fd01d | 1137 | #ifdef CONFIG_SUPERH |
201e9109 | 1138 | sh_early_platform_init("earlytimer", &sh_cmt_device_driver); |
507fd01d BG |
1139 | #endif |
1140 | ||
e903a031 | 1141 | subsys_initcall(sh_cmt_init); |
3fb1b6ad MD |
1142 | module_exit(sh_cmt_exit); |
1143 | ||
1144 | MODULE_AUTHOR("Magnus Damm"); | |
1145 | MODULE_DESCRIPTION("SuperH CMT Timer Driver"); | |
1146 | MODULE_LICENSE("GPL v2"); |