Commit | Line | Data |
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efad0117 | 1 | // SPDX-License-Identifier: GPL-2.0 |
3fb1b6ad MD |
2 | /* |
3 | * SuperH Timer Support - CMT | |
4 | * | |
5 | * Copyright (C) 2008 Magnus Damm | |
3fb1b6ad MD |
6 | */ |
7 | ||
e7a9bcc2 LP |
8 | #include <linux/clk.h> |
9 | #include <linux/clockchips.h> | |
10 | #include <linux/clocksource.h> | |
11 | #include <linux/delay.h> | |
12 | #include <linux/err.h> | |
3fb1b6ad | 13 | #include <linux/init.h> |
3fb1b6ad | 14 | #include <linux/interrupt.h> |
3fb1b6ad | 15 | #include <linux/io.h> |
e7a9bcc2 | 16 | #include <linux/ioport.h> |
3fb1b6ad | 17 | #include <linux/irq.h> |
7deeab5d | 18 | #include <linux/module.h> |
1768aa2f | 19 | #include <linux/of.h> |
2d1d5172 | 20 | #include <linux/of_device.h> |
e7a9bcc2 | 21 | #include <linux/platform_device.h> |
615a445f | 22 | #include <linux/pm_domain.h> |
bad81383 | 23 | #include <linux/pm_runtime.h> |
e7a9bcc2 LP |
24 | #include <linux/sh_timer.h> |
25 | #include <linux/slab.h> | |
26 | #include <linux/spinlock.h> | |
3fb1b6ad | 27 | |
2653caf4 | 28 | struct sh_cmt_device; |
7269f933 | 29 | |
2cda3ac4 LP |
30 | /* |
31 | * The CMT comes in 5 different identified flavours, depending not only on the | |
32 | * SoC but also on the particular instance. The following table lists the main | |
33 | * characteristics of those flavours. | |
34 | * | |
83c79a6d | 35 | * 16B 32B 32B-F 48B R-Car Gen2 |
2cda3ac4 LP |
36 | * ----------------------------------------------------------------------------- |
37 | * Channels 2 1/4 1 6 2/8 | |
38 | * Control Width 16 16 16 16 32 | |
39 | * Counter Width 16 32 32 32/48 32/48 | |
40 | * Shared Start/Stop Y Y Y Y N | |
41 | * | |
83c79a6d MD |
42 | * The r8a73a4 / R-Car Gen2 version has a per-channel start/stop register |
43 | * located in the channel registers block. All other versions have a shared | |
44 | * start/stop register located in the global space. | |
2cda3ac4 | 45 | * |
81b3b271 LP |
46 | * Channels are indexed from 0 to N-1 in the documentation. The channel index |
47 | * infers the start/stop bit position in the control register and the channel | |
48 | * registers block address. Some CMT instances have a subset of channels | |
49 | * available, in which case the index in the documentation doesn't match the | |
50 | * "real" index as implemented in hardware. This is for instance the case with | |
51 | * CMT0 on r8a7740, which is a 32-bit variant with a single channel numbered 0 | |
52 | * in the documentation but using start/stop bit 5 and having its registers | |
53 | * block at 0x60. | |
54 | * | |
55 | * Similarly CMT0 on r8a73a4, r8a7790 and r8a7791, while implementing 32-bit | |
2cda3ac4 LP |
56 | * channels only, is a 48-bit gen2 CMT with the 48-bit channels unavailable. |
57 | */ | |
58 | ||
59 | enum sh_cmt_model { | |
60 | SH_CMT_16BIT, | |
61 | SH_CMT_32BIT, | |
2cda3ac4 | 62 | SH_CMT_48BIT, |
83c79a6d MD |
63 | SH_CMT0_RCAR_GEN2, |
64 | SH_CMT1_RCAR_GEN2, | |
2cda3ac4 LP |
65 | }; |
66 | ||
67 | struct sh_cmt_info { | |
68 | enum sh_cmt_model model; | |
69 | ||
464eed84 MD |
70 | unsigned int channels_mask; |
71 | ||
2cda3ac4 | 72 | unsigned long width; /* 16 or 32 bit version of hardware block */ |
22627c6f SS |
73 | u32 overflow_bit; |
74 | u32 clear_bits; | |
2cda3ac4 LP |
75 | |
76 | /* callbacks for CMSTR and CMCSR access */ | |
22627c6f | 77 | u32 (*read_control)(void __iomem *base, unsigned long offs); |
2cda3ac4 | 78 | void (*write_control)(void __iomem *base, unsigned long offs, |
22627c6f | 79 | u32 value); |
2cda3ac4 LP |
80 | |
81 | /* callbacks for CMCNT and CMCOR access */ | |
22627c6f SS |
82 | u32 (*read_count)(void __iomem *base, unsigned long offs); |
83 | void (*write_count)(void __iomem *base, unsigned long offs, u32 value); | |
2cda3ac4 LP |
84 | }; |
85 | ||
7269f933 | 86 | struct sh_cmt_channel { |
2653caf4 | 87 | struct sh_cmt_device *cmt; |
3fb1b6ad | 88 | |
81b3b271 LP |
89 | unsigned int index; /* Index in the documentation */ |
90 | unsigned int hwidx; /* Real hardware index */ | |
91 | ||
92 | void __iomem *iostart; | |
93 | void __iomem *ioctrl; | |
c924d2d2 | 94 | |
81b3b271 | 95 | unsigned int timer_bit; |
3fb1b6ad | 96 | unsigned long flags; |
22627c6f SS |
97 | u32 match_value; |
98 | u32 next_match_value; | |
99 | u32 max_match_value; | |
7d0c399f | 100 | raw_spinlock_t lock; |
3fb1b6ad | 101 | struct clock_event_device ced; |
19bdc9d0 | 102 | struct clocksource cs; |
37e7742c | 103 | u64 total_cycles; |
bad81383 | 104 | bool cs_enabled; |
7269f933 LP |
105 | }; |
106 | ||
2653caf4 | 107 | struct sh_cmt_device { |
7269f933 LP |
108 | struct platform_device *pdev; |
109 | ||
2cda3ac4 LP |
110 | const struct sh_cmt_info *info; |
111 | ||
7269f933 | 112 | void __iomem *mapbase; |
7269f933 | 113 | struct clk *clk; |
890f423b | 114 | unsigned long rate; |
7269f933 | 115 | |
de599c88 LP |
116 | raw_spinlock_t lock; /* Protect the shared start/stop register */ |
117 | ||
f5ec9b19 LP |
118 | struct sh_cmt_channel *channels; |
119 | unsigned int num_channels; | |
1768aa2f | 120 | unsigned int hw_channels; |
81b3b271 LP |
121 | |
122 | bool has_clockevent; | |
123 | bool has_clocksource; | |
3fb1b6ad MD |
124 | }; |
125 | ||
d14be99b LP |
126 | #define SH_CMT16_CMCSR_CMF (1 << 7) |
127 | #define SH_CMT16_CMCSR_CMIE (1 << 6) | |
128 | #define SH_CMT16_CMCSR_CKS8 (0 << 0) | |
129 | #define SH_CMT16_CMCSR_CKS32 (1 << 0) | |
130 | #define SH_CMT16_CMCSR_CKS128 (2 << 0) | |
131 | #define SH_CMT16_CMCSR_CKS512 (3 << 0) | |
132 | #define SH_CMT16_CMCSR_CKS_MASK (3 << 0) | |
133 | ||
134 | #define SH_CMT32_CMCSR_CMF (1 << 15) | |
135 | #define SH_CMT32_CMCSR_OVF (1 << 14) | |
136 | #define SH_CMT32_CMCSR_WRFLG (1 << 13) | |
137 | #define SH_CMT32_CMCSR_STTF (1 << 12) | |
138 | #define SH_CMT32_CMCSR_STPF (1 << 11) | |
139 | #define SH_CMT32_CMCSR_SSIE (1 << 10) | |
140 | #define SH_CMT32_CMCSR_CMS (1 << 9) | |
141 | #define SH_CMT32_CMCSR_CMM (1 << 8) | |
142 | #define SH_CMT32_CMCSR_CMTOUT_IE (1 << 7) | |
143 | #define SH_CMT32_CMCSR_CMR_NONE (0 << 4) | |
144 | #define SH_CMT32_CMCSR_CMR_DMA (1 << 4) | |
145 | #define SH_CMT32_CMCSR_CMR_IRQ (2 << 4) | |
146 | #define SH_CMT32_CMCSR_CMR_MASK (3 << 4) | |
147 | #define SH_CMT32_CMCSR_DBGIVD (1 << 3) | |
148 | #define SH_CMT32_CMCSR_CKS_RCLK8 (4 << 0) | |
149 | #define SH_CMT32_CMCSR_CKS_RCLK32 (5 << 0) | |
150 | #define SH_CMT32_CMCSR_CKS_RCLK128 (6 << 0) | |
151 | #define SH_CMT32_CMCSR_CKS_RCLK1 (7 << 0) | |
152 | #define SH_CMT32_CMCSR_CKS_MASK (7 << 0) | |
153 | ||
22627c6f | 154 | static u32 sh_cmt_read16(void __iomem *base, unsigned long offs) |
587acb3d MD |
155 | { |
156 | return ioread16(base + (offs << 1)); | |
157 | } | |
158 | ||
22627c6f | 159 | static u32 sh_cmt_read32(void __iomem *base, unsigned long offs) |
a6a912ca MD |
160 | { |
161 | return ioread32(base + (offs << 2)); | |
162 | } | |
163 | ||
22627c6f | 164 | static void sh_cmt_write16(void __iomem *base, unsigned long offs, u32 value) |
587acb3d MD |
165 | { |
166 | iowrite16(value, base + (offs << 1)); | |
167 | } | |
3fb1b6ad | 168 | |
22627c6f | 169 | static void sh_cmt_write32(void __iomem *base, unsigned long offs, u32 value) |
a6a912ca MD |
170 | { |
171 | iowrite32(value, base + (offs << 2)); | |
172 | } | |
173 | ||
2cda3ac4 LP |
174 | static const struct sh_cmt_info sh_cmt_info[] = { |
175 | [SH_CMT_16BIT] = { | |
176 | .model = SH_CMT_16BIT, | |
177 | .width = 16, | |
d14be99b LP |
178 | .overflow_bit = SH_CMT16_CMCSR_CMF, |
179 | .clear_bits = ~SH_CMT16_CMCSR_CMF, | |
2cda3ac4 LP |
180 | .read_control = sh_cmt_read16, |
181 | .write_control = sh_cmt_write16, | |
182 | .read_count = sh_cmt_read16, | |
183 | .write_count = sh_cmt_write16, | |
184 | }, | |
185 | [SH_CMT_32BIT] = { | |
186 | .model = SH_CMT_32BIT, | |
187 | .width = 32, | |
d14be99b LP |
188 | .overflow_bit = SH_CMT32_CMCSR_CMF, |
189 | .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), | |
2cda3ac4 LP |
190 | .read_control = sh_cmt_read16, |
191 | .write_control = sh_cmt_write16, | |
192 | .read_count = sh_cmt_read32, | |
193 | .write_count = sh_cmt_write32, | |
194 | }, | |
2cda3ac4 LP |
195 | [SH_CMT_48BIT] = { |
196 | .model = SH_CMT_48BIT, | |
464eed84 | 197 | .channels_mask = 0x3f, |
2cda3ac4 | 198 | .width = 32, |
d14be99b LP |
199 | .overflow_bit = SH_CMT32_CMCSR_CMF, |
200 | .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), | |
2cda3ac4 LP |
201 | .read_control = sh_cmt_read32, |
202 | .write_control = sh_cmt_write32, | |
203 | .read_count = sh_cmt_read32, | |
204 | .write_count = sh_cmt_write32, | |
205 | }, | |
83c79a6d MD |
206 | [SH_CMT0_RCAR_GEN2] = { |
207 | .model = SH_CMT0_RCAR_GEN2, | |
208 | .channels_mask = 0x60, | |
209 | .width = 32, | |
210 | .overflow_bit = SH_CMT32_CMCSR_CMF, | |
211 | .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), | |
212 | .read_control = sh_cmt_read32, | |
213 | .write_control = sh_cmt_write32, | |
214 | .read_count = sh_cmt_read32, | |
215 | .write_count = sh_cmt_write32, | |
216 | }, | |
217 | [SH_CMT1_RCAR_GEN2] = { | |
218 | .model = SH_CMT1_RCAR_GEN2, | |
219 | .channels_mask = 0xff, | |
2cda3ac4 | 220 | .width = 32, |
d14be99b LP |
221 | .overflow_bit = SH_CMT32_CMCSR_CMF, |
222 | .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), | |
2cda3ac4 LP |
223 | .read_control = sh_cmt_read32, |
224 | .write_control = sh_cmt_write32, | |
225 | .read_count = sh_cmt_read32, | |
226 | .write_count = sh_cmt_write32, | |
227 | }, | |
228 | }; | |
229 | ||
3fb1b6ad MD |
230 | #define CMCSR 0 /* channel register */ |
231 | #define CMCNT 1 /* channel register */ | |
232 | #define CMCOR 2 /* channel register */ | |
233 | ||
22627c6f | 234 | static inline u32 sh_cmt_read_cmstr(struct sh_cmt_channel *ch) |
1b56b96b | 235 | { |
81b3b271 LP |
236 | if (ch->iostart) |
237 | return ch->cmt->info->read_control(ch->iostart, 0); | |
238 | else | |
239 | return ch->cmt->info->read_control(ch->cmt->mapbase, 0); | |
1b56b96b MD |
240 | } |
241 | ||
22627c6f | 242 | static inline void sh_cmt_write_cmstr(struct sh_cmt_channel *ch, u32 value) |
1b56b96b | 243 | { |
81b3b271 LP |
244 | if (ch->iostart) |
245 | ch->cmt->info->write_control(ch->iostart, 0, value); | |
246 | else | |
247 | ch->cmt->info->write_control(ch->cmt->mapbase, 0, value); | |
1b56b96b MD |
248 | } |
249 | ||
22627c6f | 250 | static inline u32 sh_cmt_read_cmcsr(struct sh_cmt_channel *ch) |
1b56b96b | 251 | { |
81b3b271 | 252 | return ch->cmt->info->read_control(ch->ioctrl, CMCSR); |
3fb1b6ad MD |
253 | } |
254 | ||
22627c6f | 255 | static inline void sh_cmt_write_cmcsr(struct sh_cmt_channel *ch, u32 value) |
1b56b96b | 256 | { |
81b3b271 | 257 | ch->cmt->info->write_control(ch->ioctrl, CMCSR, value); |
1b56b96b MD |
258 | } |
259 | ||
22627c6f | 260 | static inline u32 sh_cmt_read_cmcnt(struct sh_cmt_channel *ch) |
1b56b96b | 261 | { |
81b3b271 | 262 | return ch->cmt->info->read_count(ch->ioctrl, CMCNT); |
1b56b96b MD |
263 | } |
264 | ||
22627c6f | 265 | static inline void sh_cmt_write_cmcnt(struct sh_cmt_channel *ch, u32 value) |
1b56b96b | 266 | { |
81b3b271 | 267 | ch->cmt->info->write_count(ch->ioctrl, CMCNT, value); |
1b56b96b MD |
268 | } |
269 | ||
22627c6f | 270 | static inline void sh_cmt_write_cmcor(struct sh_cmt_channel *ch, u32 value) |
1b56b96b | 271 | { |
81b3b271 | 272 | ch->cmt->info->write_count(ch->ioctrl, CMCOR, value); |
1b56b96b MD |
273 | } |
274 | ||
22627c6f | 275 | static u32 sh_cmt_get_counter(struct sh_cmt_channel *ch, u32 *has_wrapped) |
3fb1b6ad | 276 | { |
22627c6f SS |
277 | u32 v1, v2, v3; |
278 | u32 o1, o2; | |
5b644c7a | 279 | |
2cda3ac4 | 280 | o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit; |
3fb1b6ad MD |
281 | |
282 | /* Make sure the timer value is stable. Stolen from acpi_pm.c */ | |
283 | do { | |
5b644c7a | 284 | o2 = o1; |
7269f933 LP |
285 | v1 = sh_cmt_read_cmcnt(ch); |
286 | v2 = sh_cmt_read_cmcnt(ch); | |
287 | v3 = sh_cmt_read_cmcnt(ch); | |
2cda3ac4 | 288 | o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit; |
5b644c7a MD |
289 | } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3) |
290 | || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2))); | |
3fb1b6ad | 291 | |
5b644c7a | 292 | *has_wrapped = o1; |
3fb1b6ad MD |
293 | return v2; |
294 | } | |
295 | ||
7269f933 | 296 | static void sh_cmt_start_stop_ch(struct sh_cmt_channel *ch, int start) |
3fb1b6ad | 297 | { |
22627c6f SS |
298 | unsigned long flags; |
299 | u32 value; | |
3fb1b6ad MD |
300 | |
301 | /* start stop register shared by multiple timer channels */ | |
de599c88 | 302 | raw_spin_lock_irqsave(&ch->cmt->lock, flags); |
7269f933 | 303 | value = sh_cmt_read_cmstr(ch); |
3fb1b6ad MD |
304 | |
305 | if (start) | |
81b3b271 | 306 | value |= 1 << ch->timer_bit; |
3fb1b6ad | 307 | else |
81b3b271 | 308 | value &= ~(1 << ch->timer_bit); |
3fb1b6ad | 309 | |
7269f933 | 310 | sh_cmt_write_cmstr(ch, value); |
de599c88 | 311 | raw_spin_unlock_irqrestore(&ch->cmt->lock, flags); |
3fb1b6ad MD |
312 | } |
313 | ||
890f423b | 314 | static int sh_cmt_enable(struct sh_cmt_channel *ch) |
3fb1b6ad | 315 | { |
3f7e5e24 | 316 | int k, ret; |
3fb1b6ad | 317 | |
7269f933 LP |
318 | pm_runtime_get_sync(&ch->cmt->pdev->dev); |
319 | dev_pm_syscore_device(&ch->cmt->pdev->dev, true); | |
bad81383 | 320 | |
9436b4ab | 321 | /* enable clock */ |
7269f933 | 322 | ret = clk_enable(ch->cmt->clk); |
3fb1b6ad | 323 | if (ret) { |
740a9518 LP |
324 | dev_err(&ch->cmt->pdev->dev, "ch%u: cannot enable clock\n", |
325 | ch->index); | |
3f7e5e24 | 326 | goto err0; |
3fb1b6ad | 327 | } |
3fb1b6ad MD |
328 | |
329 | /* make sure channel is disabled */ | |
7269f933 | 330 | sh_cmt_start_stop_ch(ch, 0); |
3fb1b6ad MD |
331 | |
332 | /* configure channel, periodic mode and maximum timeout */ | |
2cda3ac4 | 333 | if (ch->cmt->info->width == 16) { |
d14be99b LP |
334 | sh_cmt_write_cmcsr(ch, SH_CMT16_CMCSR_CMIE | |
335 | SH_CMT16_CMCSR_CKS512); | |
3014f474 | 336 | } else { |
d14be99b LP |
337 | sh_cmt_write_cmcsr(ch, SH_CMT32_CMCSR_CMM | |
338 | SH_CMT32_CMCSR_CMTOUT_IE | | |
339 | SH_CMT32_CMCSR_CMR_IRQ | | |
340 | SH_CMT32_CMCSR_CKS_RCLK8); | |
3014f474 | 341 | } |
3fb1b6ad | 342 | |
7269f933 LP |
343 | sh_cmt_write_cmcor(ch, 0xffffffff); |
344 | sh_cmt_write_cmcnt(ch, 0); | |
3fb1b6ad | 345 | |
3f7e5e24 MD |
346 | /* |
347 | * According to the sh73a0 user's manual, as CMCNT can be operated | |
348 | * only by the RCLK (Pseudo 32 KHz), there's one restriction on | |
349 | * modifying CMCNT register; two RCLK cycles are necessary before | |
350 | * this register is either read or any modification of the value | |
351 | * it holds is reflected in the LSI's actual operation. | |
352 | * | |
353 | * While at it, we're supposed to clear out the CMCNT as of this | |
354 | * moment, so make sure it's processed properly here. This will | |
355 | * take RCLKx2 at maximum. | |
356 | */ | |
357 | for (k = 0; k < 100; k++) { | |
7269f933 | 358 | if (!sh_cmt_read_cmcnt(ch)) |
3f7e5e24 MD |
359 | break; |
360 | udelay(1); | |
361 | } | |
362 | ||
7269f933 | 363 | if (sh_cmt_read_cmcnt(ch)) { |
740a9518 LP |
364 | dev_err(&ch->cmt->pdev->dev, "ch%u: cannot clear CMCNT\n", |
365 | ch->index); | |
3f7e5e24 MD |
366 | ret = -ETIMEDOUT; |
367 | goto err1; | |
368 | } | |
369 | ||
3fb1b6ad | 370 | /* enable channel */ |
7269f933 | 371 | sh_cmt_start_stop_ch(ch, 1); |
3fb1b6ad | 372 | return 0; |
3f7e5e24 MD |
373 | err1: |
374 | /* stop clock */ | |
7269f933 | 375 | clk_disable(ch->cmt->clk); |
3f7e5e24 MD |
376 | |
377 | err0: | |
378 | return ret; | |
3fb1b6ad MD |
379 | } |
380 | ||
7269f933 | 381 | static void sh_cmt_disable(struct sh_cmt_channel *ch) |
3fb1b6ad MD |
382 | { |
383 | /* disable channel */ | |
7269f933 | 384 | sh_cmt_start_stop_ch(ch, 0); |
3fb1b6ad | 385 | |
be890a1a | 386 | /* disable interrupts in CMT block */ |
7269f933 | 387 | sh_cmt_write_cmcsr(ch, 0); |
be890a1a | 388 | |
9436b4ab | 389 | /* stop clock */ |
7269f933 | 390 | clk_disable(ch->cmt->clk); |
bad81383 | 391 | |
7269f933 LP |
392 | dev_pm_syscore_device(&ch->cmt->pdev->dev, false); |
393 | pm_runtime_put(&ch->cmt->pdev->dev); | |
3fb1b6ad MD |
394 | } |
395 | ||
396 | /* private flags */ | |
397 | #define FLAG_CLOCKEVENT (1 << 0) | |
398 | #define FLAG_CLOCKSOURCE (1 << 1) | |
399 | #define FLAG_REPROGRAM (1 << 2) | |
400 | #define FLAG_SKIPEVENT (1 << 3) | |
401 | #define FLAG_IRQCONTEXT (1 << 4) | |
402 | ||
7269f933 | 403 | static void sh_cmt_clock_event_program_verify(struct sh_cmt_channel *ch, |
3fb1b6ad MD |
404 | int absolute) |
405 | { | |
22627c6f SS |
406 | u32 value = ch->next_match_value; |
407 | u32 new_match; | |
408 | u32 delay = 0; | |
409 | u32 now = 0; | |
410 | u32 has_wrapped; | |
3fb1b6ad | 411 | |
7269f933 LP |
412 | now = sh_cmt_get_counter(ch, &has_wrapped); |
413 | ch->flags |= FLAG_REPROGRAM; /* force reprogram */ | |
3fb1b6ad MD |
414 | |
415 | if (has_wrapped) { | |
416 | /* we're competing with the interrupt handler. | |
417 | * -> let the interrupt handler reprogram the timer. | |
418 | * -> interrupt number two handles the event. | |
419 | */ | |
7269f933 | 420 | ch->flags |= FLAG_SKIPEVENT; |
3fb1b6ad MD |
421 | return; |
422 | } | |
423 | ||
424 | if (absolute) | |
425 | now = 0; | |
426 | ||
427 | do { | |
428 | /* reprogram the timer hardware, | |
429 | * but don't save the new match value yet. | |
430 | */ | |
431 | new_match = now + value + delay; | |
7269f933 LP |
432 | if (new_match > ch->max_match_value) |
433 | new_match = ch->max_match_value; | |
3fb1b6ad | 434 | |
7269f933 | 435 | sh_cmt_write_cmcor(ch, new_match); |
3fb1b6ad | 436 | |
7269f933 LP |
437 | now = sh_cmt_get_counter(ch, &has_wrapped); |
438 | if (has_wrapped && (new_match > ch->match_value)) { | |
3fb1b6ad MD |
439 | /* we are changing to a greater match value, |
440 | * so this wrap must be caused by the counter | |
441 | * matching the old value. | |
442 | * -> first interrupt reprograms the timer. | |
443 | * -> interrupt number two handles the event. | |
444 | */ | |
7269f933 | 445 | ch->flags |= FLAG_SKIPEVENT; |
3fb1b6ad MD |
446 | break; |
447 | } | |
448 | ||
449 | if (has_wrapped) { | |
450 | /* we are changing to a smaller match value, | |
451 | * so the wrap must be caused by the counter | |
452 | * matching the new value. | |
453 | * -> save programmed match value. | |
454 | * -> let isr handle the event. | |
455 | */ | |
7269f933 | 456 | ch->match_value = new_match; |
3fb1b6ad MD |
457 | break; |
458 | } | |
459 | ||
460 | /* be safe: verify hardware settings */ | |
461 | if (now < new_match) { | |
462 | /* timer value is below match value, all good. | |
463 | * this makes sure we won't miss any match events. | |
464 | * -> save programmed match value. | |
465 | * -> let isr handle the event. | |
466 | */ | |
7269f933 | 467 | ch->match_value = new_match; |
3fb1b6ad MD |
468 | break; |
469 | } | |
470 | ||
471 | /* the counter has reached a value greater | |
472 | * than our new match value. and since the | |
473 | * has_wrapped flag isn't set we must have | |
474 | * programmed a too close event. | |
475 | * -> increase delay and retry. | |
476 | */ | |
477 | if (delay) | |
478 | delay <<= 1; | |
479 | else | |
480 | delay = 1; | |
481 | ||
482 | if (!delay) | |
740a9518 LP |
483 | dev_warn(&ch->cmt->pdev->dev, "ch%u: too long delay\n", |
484 | ch->index); | |
3fb1b6ad MD |
485 | |
486 | } while (delay); | |
487 | } | |
488 | ||
7269f933 | 489 | static void __sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta) |
3fb1b6ad | 490 | { |
7269f933 | 491 | if (delta > ch->max_match_value) |
740a9518 LP |
492 | dev_warn(&ch->cmt->pdev->dev, "ch%u: delta out of range\n", |
493 | ch->index); | |
3fb1b6ad | 494 | |
7269f933 LP |
495 | ch->next_match_value = delta; |
496 | sh_cmt_clock_event_program_verify(ch, 0); | |
65ada547 TY |
497 | } |
498 | ||
7269f933 | 499 | static void sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta) |
65ada547 TY |
500 | { |
501 | unsigned long flags; | |
502 | ||
7269f933 LP |
503 | raw_spin_lock_irqsave(&ch->lock, flags); |
504 | __sh_cmt_set_next(ch, delta); | |
505 | raw_spin_unlock_irqrestore(&ch->lock, flags); | |
3fb1b6ad MD |
506 | } |
507 | ||
508 | static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id) | |
509 | { | |
7269f933 | 510 | struct sh_cmt_channel *ch = dev_id; |
3fb1b6ad MD |
511 | |
512 | /* clear flags */ | |
2cda3ac4 LP |
513 | sh_cmt_write_cmcsr(ch, sh_cmt_read_cmcsr(ch) & |
514 | ch->cmt->info->clear_bits); | |
3fb1b6ad MD |
515 | |
516 | /* update clock source counter to begin with if enabled | |
517 | * the wrap flag should be cleared by the timer specific | |
518 | * isr before we end up here. | |
519 | */ | |
7269f933 LP |
520 | if (ch->flags & FLAG_CLOCKSOURCE) |
521 | ch->total_cycles += ch->match_value + 1; | |
3fb1b6ad | 522 | |
7269f933 LP |
523 | if (!(ch->flags & FLAG_REPROGRAM)) |
524 | ch->next_match_value = ch->max_match_value; | |
3fb1b6ad | 525 | |
7269f933 | 526 | ch->flags |= FLAG_IRQCONTEXT; |
3fb1b6ad | 527 | |
7269f933 LP |
528 | if (ch->flags & FLAG_CLOCKEVENT) { |
529 | if (!(ch->flags & FLAG_SKIPEVENT)) { | |
051b782e | 530 | if (clockevent_state_oneshot(&ch->ced)) { |
7269f933 LP |
531 | ch->next_match_value = ch->max_match_value; |
532 | ch->flags |= FLAG_REPROGRAM; | |
3fb1b6ad MD |
533 | } |
534 | ||
7269f933 | 535 | ch->ced.event_handler(&ch->ced); |
3fb1b6ad MD |
536 | } |
537 | } | |
538 | ||
7269f933 | 539 | ch->flags &= ~FLAG_SKIPEVENT; |
3fb1b6ad | 540 | |
7269f933 LP |
541 | if (ch->flags & FLAG_REPROGRAM) { |
542 | ch->flags &= ~FLAG_REPROGRAM; | |
543 | sh_cmt_clock_event_program_verify(ch, 1); | |
3fb1b6ad | 544 | |
7269f933 | 545 | if (ch->flags & FLAG_CLOCKEVENT) |
051b782e | 546 | if ((clockevent_state_shutdown(&ch->ced)) |
7269f933 LP |
547 | || (ch->match_value == ch->next_match_value)) |
548 | ch->flags &= ~FLAG_REPROGRAM; | |
3fb1b6ad MD |
549 | } |
550 | ||
7269f933 | 551 | ch->flags &= ~FLAG_IRQCONTEXT; |
3fb1b6ad MD |
552 | |
553 | return IRQ_HANDLED; | |
554 | } | |
555 | ||
7269f933 | 556 | static int sh_cmt_start(struct sh_cmt_channel *ch, unsigned long flag) |
3fb1b6ad MD |
557 | { |
558 | int ret = 0; | |
559 | unsigned long flags; | |
560 | ||
7269f933 | 561 | raw_spin_lock_irqsave(&ch->lock, flags); |
3fb1b6ad | 562 | |
7269f933 | 563 | if (!(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) |
890f423b | 564 | ret = sh_cmt_enable(ch); |
3fb1b6ad MD |
565 | |
566 | if (ret) | |
567 | goto out; | |
7269f933 | 568 | ch->flags |= flag; |
3fb1b6ad MD |
569 | |
570 | /* setup timeout if no clockevent */ | |
7269f933 LP |
571 | if ((flag == FLAG_CLOCKSOURCE) && (!(ch->flags & FLAG_CLOCKEVENT))) |
572 | __sh_cmt_set_next(ch, ch->max_match_value); | |
3fb1b6ad | 573 | out: |
7269f933 | 574 | raw_spin_unlock_irqrestore(&ch->lock, flags); |
3fb1b6ad MD |
575 | |
576 | return ret; | |
577 | } | |
578 | ||
7269f933 | 579 | static void sh_cmt_stop(struct sh_cmt_channel *ch, unsigned long flag) |
3fb1b6ad MD |
580 | { |
581 | unsigned long flags; | |
582 | unsigned long f; | |
583 | ||
7269f933 | 584 | raw_spin_lock_irqsave(&ch->lock, flags); |
3fb1b6ad | 585 | |
7269f933 LP |
586 | f = ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE); |
587 | ch->flags &= ~flag; | |
3fb1b6ad | 588 | |
7269f933 LP |
589 | if (f && !(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) |
590 | sh_cmt_disable(ch); | |
3fb1b6ad MD |
591 | |
592 | /* adjust the timeout to maximum if only clocksource left */ | |
7269f933 LP |
593 | if ((flag == FLAG_CLOCKEVENT) && (ch->flags & FLAG_CLOCKSOURCE)) |
594 | __sh_cmt_set_next(ch, ch->max_match_value); | |
3fb1b6ad | 595 | |
7269f933 | 596 | raw_spin_unlock_irqrestore(&ch->lock, flags); |
3fb1b6ad MD |
597 | } |
598 | ||
7269f933 | 599 | static struct sh_cmt_channel *cs_to_sh_cmt(struct clocksource *cs) |
19bdc9d0 | 600 | { |
7269f933 | 601 | return container_of(cs, struct sh_cmt_channel, cs); |
19bdc9d0 MD |
602 | } |
603 | ||
a5a1d1c2 | 604 | static u64 sh_cmt_clocksource_read(struct clocksource *cs) |
19bdc9d0 | 605 | { |
7269f933 | 606 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
22627c6f | 607 | unsigned long flags; |
22627c6f | 608 | u32 has_wrapped; |
37e7742c | 609 | u64 value; |
22627c6f | 610 | u32 raw; |
19bdc9d0 | 611 | |
7269f933 LP |
612 | raw_spin_lock_irqsave(&ch->lock, flags); |
613 | value = ch->total_cycles; | |
614 | raw = sh_cmt_get_counter(ch, &has_wrapped); | |
19bdc9d0 MD |
615 | |
616 | if (unlikely(has_wrapped)) | |
7269f933 LP |
617 | raw += ch->match_value + 1; |
618 | raw_spin_unlock_irqrestore(&ch->lock, flags); | |
19bdc9d0 MD |
619 | |
620 | return value + raw; | |
621 | } | |
622 | ||
623 | static int sh_cmt_clocksource_enable(struct clocksource *cs) | |
624 | { | |
3593f5fe | 625 | int ret; |
7269f933 | 626 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
19bdc9d0 | 627 | |
7269f933 | 628 | WARN_ON(ch->cs_enabled); |
bad81383 | 629 | |
7269f933 | 630 | ch->total_cycles = 0; |
19bdc9d0 | 631 | |
7269f933 | 632 | ret = sh_cmt_start(ch, FLAG_CLOCKSOURCE); |
890f423b | 633 | if (!ret) |
7269f933 | 634 | ch->cs_enabled = true; |
890f423b | 635 | |
3593f5fe | 636 | return ret; |
19bdc9d0 MD |
637 | } |
638 | ||
639 | static void sh_cmt_clocksource_disable(struct clocksource *cs) | |
640 | { | |
7269f933 | 641 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
bad81383 | 642 | |
7269f933 | 643 | WARN_ON(!ch->cs_enabled); |
bad81383 | 644 | |
7269f933 LP |
645 | sh_cmt_stop(ch, FLAG_CLOCKSOURCE); |
646 | ch->cs_enabled = false; | |
19bdc9d0 MD |
647 | } |
648 | ||
9bb5ec88 RW |
649 | static void sh_cmt_clocksource_suspend(struct clocksource *cs) |
650 | { | |
7269f933 | 651 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
9bb5ec88 | 652 | |
54d46b7f GU |
653 | if (!ch->cs_enabled) |
654 | return; | |
655 | ||
7269f933 LP |
656 | sh_cmt_stop(ch, FLAG_CLOCKSOURCE); |
657 | pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev); | |
9bb5ec88 RW |
658 | } |
659 | ||
c8162884 MD |
660 | static void sh_cmt_clocksource_resume(struct clocksource *cs) |
661 | { | |
7269f933 | 662 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
9bb5ec88 | 663 | |
54d46b7f GU |
664 | if (!ch->cs_enabled) |
665 | return; | |
666 | ||
7269f933 LP |
667 | pm_genpd_syscore_poweron(&ch->cmt->pdev->dev); |
668 | sh_cmt_start(ch, FLAG_CLOCKSOURCE); | |
c8162884 MD |
669 | } |
670 | ||
7269f933 | 671 | static int sh_cmt_register_clocksource(struct sh_cmt_channel *ch, |
fb28a659 | 672 | const char *name) |
19bdc9d0 | 673 | { |
7269f933 | 674 | struct clocksource *cs = &ch->cs; |
19bdc9d0 MD |
675 | |
676 | cs->name = name; | |
fb28a659 | 677 | cs->rating = 125; |
19bdc9d0 MD |
678 | cs->read = sh_cmt_clocksource_read; |
679 | cs->enable = sh_cmt_clocksource_enable; | |
680 | cs->disable = sh_cmt_clocksource_disable; | |
9bb5ec88 | 681 | cs->suspend = sh_cmt_clocksource_suspend; |
c8162884 | 682 | cs->resume = sh_cmt_clocksource_resume; |
37e7742c | 683 | cs->mask = CLOCKSOURCE_MASK(sizeof(u64) * 8); |
19bdc9d0 | 684 | cs->flags = CLOCK_SOURCE_IS_CONTINUOUS; |
f4d7c356 | 685 | |
740a9518 LP |
686 | dev_info(&ch->cmt->pdev->dev, "ch%u: used as clock source\n", |
687 | ch->index); | |
f4d7c356 | 688 | |
890f423b | 689 | clocksource_register_hz(cs, ch->cmt->rate); |
19bdc9d0 MD |
690 | return 0; |
691 | } | |
692 | ||
7269f933 | 693 | static struct sh_cmt_channel *ced_to_sh_cmt(struct clock_event_device *ced) |
3fb1b6ad | 694 | { |
7269f933 | 695 | return container_of(ced, struct sh_cmt_channel, ced); |
3fb1b6ad MD |
696 | } |
697 | ||
7269f933 | 698 | static void sh_cmt_clock_event_start(struct sh_cmt_channel *ch, int periodic) |
3fb1b6ad | 699 | { |
7269f933 | 700 | sh_cmt_start(ch, FLAG_CLOCKEVENT); |
3fb1b6ad | 701 | |
3fb1b6ad | 702 | if (periodic) |
890f423b | 703 | sh_cmt_set_next(ch, ((ch->cmt->rate + HZ/2) / HZ) - 1); |
3fb1b6ad | 704 | else |
7269f933 | 705 | sh_cmt_set_next(ch, ch->max_match_value); |
3fb1b6ad MD |
706 | } |
707 | ||
051b782e VK |
708 | static int sh_cmt_clock_event_shutdown(struct clock_event_device *ced) |
709 | { | |
710 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); | |
711 | ||
712 | sh_cmt_stop(ch, FLAG_CLOCKEVENT); | |
713 | return 0; | |
714 | } | |
715 | ||
716 | static int sh_cmt_clock_event_set_state(struct clock_event_device *ced, | |
717 | int periodic) | |
3fb1b6ad | 718 | { |
7269f933 | 719 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); |
3fb1b6ad MD |
720 | |
721 | /* deal with old setting first */ | |
051b782e | 722 | if (clockevent_state_oneshot(ced) || clockevent_state_periodic(ced)) |
7269f933 | 723 | sh_cmt_stop(ch, FLAG_CLOCKEVENT); |
3fb1b6ad | 724 | |
051b782e VK |
725 | dev_info(&ch->cmt->pdev->dev, "ch%u: used for %s clock events\n", |
726 | ch->index, periodic ? "periodic" : "oneshot"); | |
727 | sh_cmt_clock_event_start(ch, periodic); | |
728 | return 0; | |
729 | } | |
730 | ||
731 | static int sh_cmt_clock_event_set_oneshot(struct clock_event_device *ced) | |
732 | { | |
733 | return sh_cmt_clock_event_set_state(ced, 0); | |
734 | } | |
735 | ||
736 | static int sh_cmt_clock_event_set_periodic(struct clock_event_device *ced) | |
737 | { | |
738 | return sh_cmt_clock_event_set_state(ced, 1); | |
3fb1b6ad MD |
739 | } |
740 | ||
741 | static int sh_cmt_clock_event_next(unsigned long delta, | |
742 | struct clock_event_device *ced) | |
743 | { | |
7269f933 | 744 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); |
3fb1b6ad | 745 | |
051b782e | 746 | BUG_ON(!clockevent_state_oneshot(ced)); |
7269f933 LP |
747 | if (likely(ch->flags & FLAG_IRQCONTEXT)) |
748 | ch->next_match_value = delta - 1; | |
3fb1b6ad | 749 | else |
7269f933 | 750 | sh_cmt_set_next(ch, delta - 1); |
3fb1b6ad MD |
751 | |
752 | return 0; | |
753 | } | |
754 | ||
9bb5ec88 RW |
755 | static void sh_cmt_clock_event_suspend(struct clock_event_device *ced) |
756 | { | |
7269f933 | 757 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); |
57dee992 | 758 | |
7269f933 LP |
759 | pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev); |
760 | clk_unprepare(ch->cmt->clk); | |
9bb5ec88 RW |
761 | } |
762 | ||
763 | static void sh_cmt_clock_event_resume(struct clock_event_device *ced) | |
764 | { | |
7269f933 | 765 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); |
57dee992 | 766 | |
7269f933 LP |
767 | clk_prepare(ch->cmt->clk); |
768 | pm_genpd_syscore_poweron(&ch->cmt->pdev->dev); | |
9bb5ec88 RW |
769 | } |
770 | ||
bfa76bb1 LP |
771 | static int sh_cmt_register_clockevent(struct sh_cmt_channel *ch, |
772 | const char *name) | |
3fb1b6ad | 773 | { |
7269f933 | 774 | struct clock_event_device *ced = &ch->ced; |
bfa76bb1 LP |
775 | int irq; |
776 | int ret; | |
777 | ||
31e912f5 | 778 | irq = platform_get_irq(ch->cmt->pdev, ch->index); |
bfa76bb1 LP |
779 | if (irq < 0) { |
780 | dev_err(&ch->cmt->pdev->dev, "ch%u: failed to get irq\n", | |
781 | ch->index); | |
782 | return irq; | |
783 | } | |
784 | ||
785 | ret = request_irq(irq, sh_cmt_interrupt, | |
786 | IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING, | |
787 | dev_name(&ch->cmt->pdev->dev), ch); | |
788 | if (ret) { | |
789 | dev_err(&ch->cmt->pdev->dev, "ch%u: failed to request irq %d\n", | |
790 | ch->index, irq); | |
791 | return ret; | |
792 | } | |
3fb1b6ad | 793 | |
3fb1b6ad MD |
794 | ced->name = name; |
795 | ced->features = CLOCK_EVT_FEAT_PERIODIC; | |
796 | ced->features |= CLOCK_EVT_FEAT_ONESHOT; | |
b7fcbb0f | 797 | ced->rating = 125; |
f1ebe1e4 | 798 | ced->cpumask = cpu_possible_mask; |
3fb1b6ad | 799 | ced->set_next_event = sh_cmt_clock_event_next; |
051b782e VK |
800 | ced->set_state_shutdown = sh_cmt_clock_event_shutdown; |
801 | ced->set_state_periodic = sh_cmt_clock_event_set_periodic; | |
802 | ced->set_state_oneshot = sh_cmt_clock_event_set_oneshot; | |
9bb5ec88 RW |
803 | ced->suspend = sh_cmt_clock_event_suspend; |
804 | ced->resume = sh_cmt_clock_event_resume; | |
3fb1b6ad | 805 | |
890f423b NS |
806 | /* TODO: calculate good shift from rate and counter bit width */ |
807 | ced->shift = 32; | |
808 | ced->mult = div_sc(ch->cmt->rate, NSEC_PER_SEC, ced->shift); | |
809 | ced->max_delta_ns = clockevent_delta2ns(ch->max_match_value, ced); | |
bb2e94ac | 810 | ced->max_delta_ticks = ch->max_match_value; |
890f423b | 811 | ced->min_delta_ns = clockevent_delta2ns(0x1f, ced); |
bb2e94ac | 812 | ced->min_delta_ticks = 0x1f; |
890f423b | 813 | |
740a9518 LP |
814 | dev_info(&ch->cmt->pdev->dev, "ch%u: used for clock events\n", |
815 | ch->index); | |
3fb1b6ad | 816 | clockevents_register_device(ced); |
bfa76bb1 LP |
817 | |
818 | return 0; | |
3fb1b6ad MD |
819 | } |
820 | ||
1d053e1d | 821 | static int sh_cmt_register(struct sh_cmt_channel *ch, const char *name, |
fb28a659 | 822 | bool clockevent, bool clocksource) |
3fb1b6ad | 823 | { |
bfa76bb1 LP |
824 | int ret; |
825 | ||
81b3b271 LP |
826 | if (clockevent) { |
827 | ch->cmt->has_clockevent = true; | |
bfa76bb1 LP |
828 | ret = sh_cmt_register_clockevent(ch, name); |
829 | if (ret < 0) | |
830 | return ret; | |
81b3b271 | 831 | } |
3fb1b6ad | 832 | |
81b3b271 LP |
833 | if (clocksource) { |
834 | ch->cmt->has_clocksource = true; | |
fb28a659 | 835 | sh_cmt_register_clocksource(ch, name); |
81b3b271 | 836 | } |
19bdc9d0 | 837 | |
3fb1b6ad MD |
838 | return 0; |
839 | } | |
840 | ||
740a9518 | 841 | static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index, |
81b3b271 LP |
842 | unsigned int hwidx, bool clockevent, |
843 | bool clocksource, struct sh_cmt_device *cmt) | |
b882e7b1 | 844 | { |
b882e7b1 LP |
845 | int ret; |
846 | ||
81b3b271 LP |
847 | /* Skip unused channels. */ |
848 | if (!clockevent && !clocksource) | |
849 | return 0; | |
850 | ||
b882e7b1 | 851 | ch->cmt = cmt; |
740a9518 | 852 | ch->index = index; |
81b3b271 | 853 | ch->hwidx = hwidx; |
83c79a6d | 854 | ch->timer_bit = hwidx; |
81b3b271 LP |
855 | |
856 | /* | |
857 | * Compute the address of the channel control register block. For the | |
858 | * timers with a per-channel start/stop register, compute its address | |
859 | * as well. | |
81b3b271 | 860 | */ |
31e912f5 LP |
861 | switch (cmt->info->model) { |
862 | case SH_CMT_16BIT: | |
863 | ch->ioctrl = cmt->mapbase + 2 + ch->hwidx * 6; | |
864 | break; | |
865 | case SH_CMT_32BIT: | |
866 | case SH_CMT_48BIT: | |
867 | ch->ioctrl = cmt->mapbase + 0x10 + ch->hwidx * 0x10; | |
868 | break; | |
83c79a6d MD |
869 | case SH_CMT0_RCAR_GEN2: |
870 | case SH_CMT1_RCAR_GEN2: | |
31e912f5 LP |
871 | ch->iostart = cmt->mapbase + ch->hwidx * 0x100; |
872 | ch->ioctrl = ch->iostart + 0x10; | |
83c79a6d | 873 | ch->timer_bit = 0; |
31e912f5 | 874 | break; |
81b3b271 LP |
875 | } |
876 | ||
2cda3ac4 | 877 | if (cmt->info->width == (sizeof(ch->max_match_value) * 8)) |
b882e7b1 LP |
878 | ch->max_match_value = ~0; |
879 | else | |
2cda3ac4 | 880 | ch->max_match_value = (1 << cmt->info->width) - 1; |
b882e7b1 LP |
881 | |
882 | ch->match_value = ch->max_match_value; | |
883 | raw_spin_lock_init(&ch->lock); | |
884 | ||
1d053e1d | 885 | ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev), |
81b3b271 | 886 | clockevent, clocksource); |
b882e7b1 | 887 | if (ret) { |
740a9518 LP |
888 | dev_err(&cmt->pdev->dev, "ch%u: registration failed\n", |
889 | ch->index); | |
b882e7b1 LP |
890 | return ret; |
891 | } | |
892 | ch->cs_enabled = false; | |
893 | ||
b882e7b1 LP |
894 | return 0; |
895 | } | |
896 | ||
81b3b271 | 897 | static int sh_cmt_map_memory(struct sh_cmt_device *cmt) |
3fb1b6ad | 898 | { |
81b3b271 | 899 | struct resource *mem; |
3fb1b6ad | 900 | |
81b3b271 LP |
901 | mem = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 0); |
902 | if (!mem) { | |
903 | dev_err(&cmt->pdev->dev, "failed to get I/O memory\n"); | |
904 | return -ENXIO; | |
905 | } | |
3fb1b6ad | 906 | |
81b3b271 LP |
907 | cmt->mapbase = ioremap_nocache(mem->start, resource_size(mem)); |
908 | if (cmt->mapbase == NULL) { | |
909 | dev_err(&cmt->pdev->dev, "failed to remap I/O memory\n"); | |
910 | return -ENXIO; | |
3fb1b6ad MD |
911 | } |
912 | ||
81b3b271 LP |
913 | return 0; |
914 | } | |
915 | ||
1768aa2f LP |
916 | static const struct platform_device_id sh_cmt_id_table[] = { |
917 | { "sh-cmt-16", (kernel_ulong_t)&sh_cmt_info[SH_CMT_16BIT] }, | |
918 | { "sh-cmt-32", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT] }, | |
1768aa2f LP |
919 | { } |
920 | }; | |
921 | MODULE_DEVICE_TABLE(platform, sh_cmt_id_table); | |
922 | ||
923 | static const struct of_device_id sh_cmt_of_table[] __maybe_unused = { | |
1768aa2f | 924 | { .compatible = "renesas,cmt-48", .data = &sh_cmt_info[SH_CMT_48BIT] }, |
8d50e947 GU |
925 | { |
926 | /* deprecated, preserved for backward compatibility */ | |
927 | .compatible = "renesas,cmt-48-gen2", | |
928 | .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2] | |
929 | }, | |
eceb4c49 SS |
930 | { |
931 | .compatible = "renesas,rcar-gen2-cmt0", | |
932 | .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2] | |
933 | }, | |
934 | { | |
935 | .compatible = "renesas,rcar-gen2-cmt1", | |
936 | .data = &sh_cmt_info[SH_CMT1_RCAR_GEN2] | |
937 | }, | |
ac142a7f SS |
938 | { |
939 | .compatible = "renesas,rcar-gen3-cmt0", | |
940 | .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2] | |
941 | }, | |
942 | { | |
943 | .compatible = "renesas,rcar-gen3-cmt1", | |
944 | .data = &sh_cmt_info[SH_CMT1_RCAR_GEN2] | |
945 | }, | |
1768aa2f LP |
946 | { } |
947 | }; | |
948 | MODULE_DEVICE_TABLE(of, sh_cmt_of_table); | |
949 | ||
81b3b271 LP |
950 | static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev) |
951 | { | |
31e912f5 LP |
952 | unsigned int mask; |
953 | unsigned int i; | |
81b3b271 LP |
954 | int ret; |
955 | ||
81b3b271 | 956 | cmt->pdev = pdev; |
de599c88 | 957 | raw_spin_lock_init(&cmt->lock); |
81b3b271 | 958 | |
1768aa2f | 959 | if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) { |
2d1d5172 | 960 | cmt->info = of_device_get_match_data(&pdev->dev); |
d1d28597 | 961 | cmt->hw_channels = cmt->info->channels_mask; |
1768aa2f LP |
962 | } else if (pdev->dev.platform_data) { |
963 | struct sh_timer_config *cfg = pdev->dev.platform_data; | |
964 | const struct platform_device_id *id = pdev->id_entry; | |
965 | ||
966 | cmt->info = (const struct sh_cmt_info *)id->driver_data; | |
967 | cmt->hw_channels = cfg->channels_mask; | |
968 | } else { | |
81b3b271 LP |
969 | dev_err(&cmt->pdev->dev, "missing platform data\n"); |
970 | return -ENXIO; | |
971 | } | |
972 | ||
81b3b271 | 973 | /* Get hold of clock. */ |
31e912f5 | 974 | cmt->clk = clk_get(&cmt->pdev->dev, "fck"); |
2653caf4 LP |
975 | if (IS_ERR(cmt->clk)) { |
976 | dev_err(&cmt->pdev->dev, "cannot get clock\n"); | |
81b3b271 | 977 | return PTR_ERR(cmt->clk); |
3fb1b6ad MD |
978 | } |
979 | ||
2653caf4 | 980 | ret = clk_prepare(cmt->clk); |
57dee992 | 981 | if (ret < 0) |
81b3b271 | 982 | goto err_clk_put; |
57dee992 | 983 | |
890f423b NS |
984 | /* Determine clock rate. */ |
985 | ret = clk_enable(cmt->clk); | |
986 | if (ret < 0) | |
987 | goto err_clk_unprepare; | |
988 | ||
989 | if (cmt->info->width == 16) | |
990 | cmt->rate = clk_get_rate(cmt->clk) / 512; | |
991 | else | |
992 | cmt->rate = clk_get_rate(cmt->clk) / 8; | |
993 | ||
994 | clk_disable(cmt->clk); | |
995 | ||
31e912f5 LP |
996 | /* Map the memory resource(s). */ |
997 | ret = sh_cmt_map_memory(cmt); | |
81b3b271 LP |
998 | if (ret < 0) |
999 | goto err_clk_unprepare; | |
1000 | ||
1001 | /* Allocate and setup the channels. */ | |
1768aa2f | 1002 | cmt->num_channels = hweight8(cmt->hw_channels); |
6396bb22 | 1003 | cmt->channels = kcalloc(cmt->num_channels, sizeof(*cmt->channels), |
81b3b271 | 1004 | GFP_KERNEL); |
f5ec9b19 LP |
1005 | if (cmt->channels == NULL) { |
1006 | ret = -ENOMEM; | |
81b3b271 | 1007 | goto err_unmap; |
f5ec9b19 LP |
1008 | } |
1009 | ||
31e912f5 LP |
1010 | /* |
1011 | * Use the first channel as a clock event device and the second channel | |
1012 | * as a clock source. If only one channel is available use it for both. | |
1013 | */ | |
1768aa2f | 1014 | for (i = 0, mask = cmt->hw_channels; i < cmt->num_channels; ++i) { |
31e912f5 LP |
1015 | unsigned int hwidx = ffs(mask) - 1; |
1016 | bool clocksource = i == 1 || cmt->num_channels == 1; | |
1017 | bool clockevent = i == 0; | |
1018 | ||
1019 | ret = sh_cmt_setup_channel(&cmt->channels[i], i, hwidx, | |
1020 | clockevent, clocksource, cmt); | |
81b3b271 LP |
1021 | if (ret < 0) |
1022 | goto err_unmap; | |
f5ec9b19 | 1023 | |
31e912f5 | 1024 | mask &= ~(1 << hwidx); |
81b3b271 | 1025 | } |
da64c2a8 | 1026 | |
2653caf4 | 1027 | platform_set_drvdata(pdev, cmt); |
adccc69e | 1028 | |
da64c2a8 | 1029 | return 0; |
81b3b271 LP |
1030 | |
1031 | err_unmap: | |
f5ec9b19 | 1032 | kfree(cmt->channels); |
31e912f5 | 1033 | iounmap(cmt->mapbase); |
81b3b271 | 1034 | err_clk_unprepare: |
2653caf4 | 1035 | clk_unprepare(cmt->clk); |
81b3b271 | 1036 | err_clk_put: |
2653caf4 | 1037 | clk_put(cmt->clk); |
3fb1b6ad MD |
1038 | return ret; |
1039 | } | |
1040 | ||
1850514b | 1041 | static int sh_cmt_probe(struct platform_device *pdev) |
3fb1b6ad | 1042 | { |
2653caf4 | 1043 | struct sh_cmt_device *cmt = platform_get_drvdata(pdev); |
3fb1b6ad MD |
1044 | int ret; |
1045 | ||
9bb5ec88 | 1046 | if (!is_early_platform_device(pdev)) { |
bad81383 RW |
1047 | pm_runtime_set_active(&pdev->dev); |
1048 | pm_runtime_enable(&pdev->dev); | |
9bb5ec88 | 1049 | } |
615a445f | 1050 | |
2653caf4 | 1051 | if (cmt) { |
214a607a | 1052 | dev_info(&pdev->dev, "kept as earlytimer\n"); |
bad81383 | 1053 | goto out; |
e475eedb MD |
1054 | } |
1055 | ||
b262bc74 | 1056 | cmt = kzalloc(sizeof(*cmt), GFP_KERNEL); |
0178f41d | 1057 | if (cmt == NULL) |
3fb1b6ad | 1058 | return -ENOMEM; |
3fb1b6ad | 1059 | |
2653caf4 | 1060 | ret = sh_cmt_setup(cmt, pdev); |
3fb1b6ad | 1061 | if (ret) { |
2653caf4 | 1062 | kfree(cmt); |
bad81383 RW |
1063 | pm_runtime_idle(&pdev->dev); |
1064 | return ret; | |
3fb1b6ad | 1065 | } |
bad81383 RW |
1066 | if (is_early_platform_device(pdev)) |
1067 | return 0; | |
1068 | ||
1069 | out: | |
81b3b271 | 1070 | if (cmt->has_clockevent || cmt->has_clocksource) |
bad81383 RW |
1071 | pm_runtime_irq_safe(&pdev->dev); |
1072 | else | |
1073 | pm_runtime_idle(&pdev->dev); | |
1074 | ||
1075 | return 0; | |
3fb1b6ad MD |
1076 | } |
1077 | ||
1850514b | 1078 | static int sh_cmt_remove(struct platform_device *pdev) |
3fb1b6ad MD |
1079 | { |
1080 | return -EBUSY; /* cannot unregister clockevent and clocksource */ | |
1081 | } | |
1082 | ||
1083 | static struct platform_driver sh_cmt_device_driver = { | |
1084 | .probe = sh_cmt_probe, | |
1850514b | 1085 | .remove = sh_cmt_remove, |
3fb1b6ad MD |
1086 | .driver = { |
1087 | .name = "sh_cmt", | |
1768aa2f | 1088 | .of_match_table = of_match_ptr(sh_cmt_of_table), |
81b3b271 LP |
1089 | }, |
1090 | .id_table = sh_cmt_id_table, | |
3fb1b6ad MD |
1091 | }; |
1092 | ||
1093 | static int __init sh_cmt_init(void) | |
1094 | { | |
1095 | return platform_driver_register(&sh_cmt_device_driver); | |
1096 | } | |
1097 | ||
1098 | static void __exit sh_cmt_exit(void) | |
1099 | { | |
1100 | platform_driver_unregister(&sh_cmt_device_driver); | |
1101 | } | |
1102 | ||
e475eedb | 1103 | early_platform_init("earlytimer", &sh_cmt_device_driver); |
e903a031 | 1104 | subsys_initcall(sh_cmt_init); |
3fb1b6ad MD |
1105 | module_exit(sh_cmt_exit); |
1106 | ||
1107 | MODULE_AUTHOR("Magnus Damm"); | |
1108 | MODULE_DESCRIPTION("SuperH CMT Timer Driver"); | |
1109 | MODULE_LICENSE("GPL v2"); |