Commit | Line | Data |
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efad0117 | 1 | // SPDX-License-Identifier: GPL-2.0 |
3fb1b6ad MD |
2 | /* |
3 | * SuperH Timer Support - CMT | |
4 | * | |
5 | * Copyright (C) 2008 Magnus Damm | |
3fb1b6ad MD |
6 | */ |
7 | ||
e7a9bcc2 LP |
8 | #include <linux/clk.h> |
9 | #include <linux/clockchips.h> | |
10 | #include <linux/clocksource.h> | |
11 | #include <linux/delay.h> | |
12 | #include <linux/err.h> | |
3fb1b6ad | 13 | #include <linux/init.h> |
3fb1b6ad | 14 | #include <linux/interrupt.h> |
3fb1b6ad | 15 | #include <linux/io.h> |
3f44f715 | 16 | #include <linux/iopoll.h> |
e7a9bcc2 | 17 | #include <linux/ioport.h> |
3fb1b6ad | 18 | #include <linux/irq.h> |
7deeab5d | 19 | #include <linux/module.h> |
1768aa2f | 20 | #include <linux/of.h> |
e7a9bcc2 | 21 | #include <linux/platform_device.h> |
615a445f | 22 | #include <linux/pm_domain.h> |
bad81383 | 23 | #include <linux/pm_runtime.h> |
e7a9bcc2 LP |
24 | #include <linux/sh_timer.h> |
25 | #include <linux/slab.h> | |
26 | #include <linux/spinlock.h> | |
3fb1b6ad | 27 | |
507fd01d BG |
28 | #ifdef CONFIG_SUPERH |
29 | #include <asm/platform_early.h> | |
30 | #endif | |
31 | ||
2653caf4 | 32 | struct sh_cmt_device; |
7269f933 | 33 | |
2cda3ac4 LP |
34 | /* |
35 | * The CMT comes in 5 different identified flavours, depending not only on the | |
36 | * SoC but also on the particular instance. The following table lists the main | |
37 | * characteristics of those flavours. | |
38 | * | |
83c79a6d | 39 | * 16B 32B 32B-F 48B R-Car Gen2 |
2cda3ac4 LP |
40 | * ----------------------------------------------------------------------------- |
41 | * Channels 2 1/4 1 6 2/8 | |
42 | * Control Width 16 16 16 16 32 | |
43 | * Counter Width 16 32 32 32/48 32/48 | |
44 | * Shared Start/Stop Y Y Y Y N | |
45 | * | |
83c79a6d MD |
46 | * The r8a73a4 / R-Car Gen2 version has a per-channel start/stop register |
47 | * located in the channel registers block. All other versions have a shared | |
48 | * start/stop register located in the global space. | |
2cda3ac4 | 49 | * |
81b3b271 LP |
50 | * Channels are indexed from 0 to N-1 in the documentation. The channel index |
51 | * infers the start/stop bit position in the control register and the channel | |
52 | * registers block address. Some CMT instances have a subset of channels | |
53 | * available, in which case the index in the documentation doesn't match the | |
54 | * "real" index as implemented in hardware. This is for instance the case with | |
55 | * CMT0 on r8a7740, which is a 32-bit variant with a single channel numbered 0 | |
56 | * in the documentation but using start/stop bit 5 and having its registers | |
57 | * block at 0x60. | |
58 | * | |
59 | * Similarly CMT0 on r8a73a4, r8a7790 and r8a7791, while implementing 32-bit | |
2cda3ac4 LP |
60 | * channels only, is a 48-bit gen2 CMT with the 48-bit channels unavailable. |
61 | */ | |
62 | ||
63 | enum sh_cmt_model { | |
64 | SH_CMT_16BIT, | |
65 | SH_CMT_32BIT, | |
2cda3ac4 | 66 | SH_CMT_48BIT, |
83c79a6d MD |
67 | SH_CMT0_RCAR_GEN2, |
68 | SH_CMT1_RCAR_GEN2, | |
2cda3ac4 LP |
69 | }; |
70 | ||
71 | struct sh_cmt_info { | |
72 | enum sh_cmt_model model; | |
73 | ||
464eed84 MD |
74 | unsigned int channels_mask; |
75 | ||
2cda3ac4 | 76 | unsigned long width; /* 16 or 32 bit version of hardware block */ |
22627c6f SS |
77 | u32 overflow_bit; |
78 | u32 clear_bits; | |
2cda3ac4 LP |
79 | |
80 | /* callbacks for CMSTR and CMCSR access */ | |
22627c6f | 81 | u32 (*read_control)(void __iomem *base, unsigned long offs); |
2cda3ac4 | 82 | void (*write_control)(void __iomem *base, unsigned long offs, |
22627c6f | 83 | u32 value); |
2cda3ac4 LP |
84 | |
85 | /* callbacks for CMCNT and CMCOR access */ | |
22627c6f SS |
86 | u32 (*read_count)(void __iomem *base, unsigned long offs); |
87 | void (*write_count)(void __iomem *base, unsigned long offs, u32 value); | |
2cda3ac4 LP |
88 | }; |
89 | ||
7269f933 | 90 | struct sh_cmt_channel { |
2653caf4 | 91 | struct sh_cmt_device *cmt; |
3fb1b6ad | 92 | |
81b3b271 LP |
93 | unsigned int index; /* Index in the documentation */ |
94 | unsigned int hwidx; /* Real hardware index */ | |
95 | ||
96 | void __iomem *iostart; | |
97 | void __iomem *ioctrl; | |
c924d2d2 | 98 | |
81b3b271 | 99 | unsigned int timer_bit; |
3fb1b6ad | 100 | unsigned long flags; |
22627c6f SS |
101 | u32 match_value; |
102 | u32 next_match_value; | |
103 | u32 max_match_value; | |
7d0c399f | 104 | raw_spinlock_t lock; |
3fb1b6ad | 105 | struct clock_event_device ced; |
19bdc9d0 | 106 | struct clocksource cs; |
37e7742c | 107 | u64 total_cycles; |
bad81383 | 108 | bool cs_enabled; |
7269f933 LP |
109 | }; |
110 | ||
2653caf4 | 111 | struct sh_cmt_device { |
7269f933 LP |
112 | struct platform_device *pdev; |
113 | ||
2cda3ac4 LP |
114 | const struct sh_cmt_info *info; |
115 | ||
7269f933 | 116 | void __iomem *mapbase; |
7269f933 | 117 | struct clk *clk; |
890f423b | 118 | unsigned long rate; |
3f44f715 | 119 | unsigned int reg_delay; |
7269f933 | 120 | |
de599c88 LP |
121 | raw_spinlock_t lock; /* Protect the shared start/stop register */ |
122 | ||
f5ec9b19 LP |
123 | struct sh_cmt_channel *channels; |
124 | unsigned int num_channels; | |
1768aa2f | 125 | unsigned int hw_channels; |
81b3b271 LP |
126 | |
127 | bool has_clockevent; | |
128 | bool has_clocksource; | |
3fb1b6ad MD |
129 | }; |
130 | ||
d14be99b LP |
131 | #define SH_CMT16_CMCSR_CMF (1 << 7) |
132 | #define SH_CMT16_CMCSR_CMIE (1 << 6) | |
133 | #define SH_CMT16_CMCSR_CKS8 (0 << 0) | |
134 | #define SH_CMT16_CMCSR_CKS32 (1 << 0) | |
135 | #define SH_CMT16_CMCSR_CKS128 (2 << 0) | |
136 | #define SH_CMT16_CMCSR_CKS512 (3 << 0) | |
137 | #define SH_CMT16_CMCSR_CKS_MASK (3 << 0) | |
138 | ||
139 | #define SH_CMT32_CMCSR_CMF (1 << 15) | |
140 | #define SH_CMT32_CMCSR_OVF (1 << 14) | |
141 | #define SH_CMT32_CMCSR_WRFLG (1 << 13) | |
142 | #define SH_CMT32_CMCSR_STTF (1 << 12) | |
143 | #define SH_CMT32_CMCSR_STPF (1 << 11) | |
144 | #define SH_CMT32_CMCSR_SSIE (1 << 10) | |
145 | #define SH_CMT32_CMCSR_CMS (1 << 9) | |
146 | #define SH_CMT32_CMCSR_CMM (1 << 8) | |
147 | #define SH_CMT32_CMCSR_CMTOUT_IE (1 << 7) | |
148 | #define SH_CMT32_CMCSR_CMR_NONE (0 << 4) | |
149 | #define SH_CMT32_CMCSR_CMR_DMA (1 << 4) | |
150 | #define SH_CMT32_CMCSR_CMR_IRQ (2 << 4) | |
151 | #define SH_CMT32_CMCSR_CMR_MASK (3 << 4) | |
152 | #define SH_CMT32_CMCSR_DBGIVD (1 << 3) | |
153 | #define SH_CMT32_CMCSR_CKS_RCLK8 (4 << 0) | |
154 | #define SH_CMT32_CMCSR_CKS_RCLK32 (5 << 0) | |
155 | #define SH_CMT32_CMCSR_CKS_RCLK128 (6 << 0) | |
156 | #define SH_CMT32_CMCSR_CKS_RCLK1 (7 << 0) | |
157 | #define SH_CMT32_CMCSR_CKS_MASK (7 << 0) | |
158 | ||
22627c6f | 159 | static u32 sh_cmt_read16(void __iomem *base, unsigned long offs) |
587acb3d MD |
160 | { |
161 | return ioread16(base + (offs << 1)); | |
162 | } | |
163 | ||
22627c6f | 164 | static u32 sh_cmt_read32(void __iomem *base, unsigned long offs) |
a6a912ca MD |
165 | { |
166 | return ioread32(base + (offs << 2)); | |
167 | } | |
168 | ||
22627c6f | 169 | static void sh_cmt_write16(void __iomem *base, unsigned long offs, u32 value) |
587acb3d MD |
170 | { |
171 | iowrite16(value, base + (offs << 1)); | |
172 | } | |
3fb1b6ad | 173 | |
22627c6f | 174 | static void sh_cmt_write32(void __iomem *base, unsigned long offs, u32 value) |
a6a912ca MD |
175 | { |
176 | iowrite32(value, base + (offs << 2)); | |
177 | } | |
178 | ||
2cda3ac4 LP |
179 | static const struct sh_cmt_info sh_cmt_info[] = { |
180 | [SH_CMT_16BIT] = { | |
181 | .model = SH_CMT_16BIT, | |
182 | .width = 16, | |
d14be99b LP |
183 | .overflow_bit = SH_CMT16_CMCSR_CMF, |
184 | .clear_bits = ~SH_CMT16_CMCSR_CMF, | |
2cda3ac4 LP |
185 | .read_control = sh_cmt_read16, |
186 | .write_control = sh_cmt_write16, | |
187 | .read_count = sh_cmt_read16, | |
188 | .write_count = sh_cmt_write16, | |
189 | }, | |
190 | [SH_CMT_32BIT] = { | |
191 | .model = SH_CMT_32BIT, | |
192 | .width = 32, | |
d14be99b LP |
193 | .overflow_bit = SH_CMT32_CMCSR_CMF, |
194 | .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), | |
2cda3ac4 LP |
195 | .read_control = sh_cmt_read16, |
196 | .write_control = sh_cmt_write16, | |
197 | .read_count = sh_cmt_read32, | |
198 | .write_count = sh_cmt_write32, | |
199 | }, | |
2cda3ac4 LP |
200 | [SH_CMT_48BIT] = { |
201 | .model = SH_CMT_48BIT, | |
464eed84 | 202 | .channels_mask = 0x3f, |
2cda3ac4 | 203 | .width = 32, |
d14be99b LP |
204 | .overflow_bit = SH_CMT32_CMCSR_CMF, |
205 | .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), | |
2cda3ac4 LP |
206 | .read_control = sh_cmt_read32, |
207 | .write_control = sh_cmt_write32, | |
208 | .read_count = sh_cmt_read32, | |
209 | .write_count = sh_cmt_write32, | |
210 | }, | |
83c79a6d MD |
211 | [SH_CMT0_RCAR_GEN2] = { |
212 | .model = SH_CMT0_RCAR_GEN2, | |
213 | .channels_mask = 0x60, | |
214 | .width = 32, | |
215 | .overflow_bit = SH_CMT32_CMCSR_CMF, | |
216 | .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), | |
217 | .read_control = sh_cmt_read32, | |
218 | .write_control = sh_cmt_write32, | |
219 | .read_count = sh_cmt_read32, | |
220 | .write_count = sh_cmt_write32, | |
221 | }, | |
222 | [SH_CMT1_RCAR_GEN2] = { | |
223 | .model = SH_CMT1_RCAR_GEN2, | |
224 | .channels_mask = 0xff, | |
2cda3ac4 | 225 | .width = 32, |
d14be99b LP |
226 | .overflow_bit = SH_CMT32_CMCSR_CMF, |
227 | .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), | |
2cda3ac4 LP |
228 | .read_control = sh_cmt_read32, |
229 | .write_control = sh_cmt_write32, | |
230 | .read_count = sh_cmt_read32, | |
231 | .write_count = sh_cmt_write32, | |
232 | }, | |
233 | }; | |
234 | ||
3fb1b6ad MD |
235 | #define CMCSR 0 /* channel register */ |
236 | #define CMCNT 1 /* channel register */ | |
237 | #define CMCOR 2 /* channel register */ | |
238 | ||
2a97d553 GU |
239 | #define CMCLKE 0x1000 /* CLK Enable Register (R-Car Gen2) */ |
240 | ||
22627c6f | 241 | static inline u32 sh_cmt_read_cmstr(struct sh_cmt_channel *ch) |
1b56b96b | 242 | { |
81b3b271 LP |
243 | if (ch->iostart) |
244 | return ch->cmt->info->read_control(ch->iostart, 0); | |
245 | else | |
246 | return ch->cmt->info->read_control(ch->cmt->mapbase, 0); | |
1b56b96b MD |
247 | } |
248 | ||
22627c6f | 249 | static inline void sh_cmt_write_cmstr(struct sh_cmt_channel *ch, u32 value) |
1b56b96b | 250 | { |
3f44f715 WS |
251 | u32 old_value = sh_cmt_read_cmstr(ch); |
252 | ||
253 | if (value != old_value) { | |
254 | if (ch->iostart) { | |
255 | ch->cmt->info->write_control(ch->iostart, 0, value); | |
256 | udelay(ch->cmt->reg_delay); | |
257 | } else { | |
258 | ch->cmt->info->write_control(ch->cmt->mapbase, 0, value); | |
259 | udelay(ch->cmt->reg_delay); | |
260 | } | |
261 | } | |
1b56b96b MD |
262 | } |
263 | ||
22627c6f | 264 | static inline u32 sh_cmt_read_cmcsr(struct sh_cmt_channel *ch) |
1b56b96b | 265 | { |
81b3b271 | 266 | return ch->cmt->info->read_control(ch->ioctrl, CMCSR); |
3fb1b6ad MD |
267 | } |
268 | ||
22627c6f | 269 | static inline void sh_cmt_write_cmcsr(struct sh_cmt_channel *ch, u32 value) |
1b56b96b | 270 | { |
3f44f715 WS |
271 | u32 old_value = sh_cmt_read_cmcsr(ch); |
272 | ||
273 | if (value != old_value) { | |
274 | ch->cmt->info->write_control(ch->ioctrl, CMCSR, value); | |
275 | udelay(ch->cmt->reg_delay); | |
276 | } | |
1b56b96b MD |
277 | } |
278 | ||
22627c6f | 279 | static inline u32 sh_cmt_read_cmcnt(struct sh_cmt_channel *ch) |
1b56b96b | 280 | { |
81b3b271 | 281 | return ch->cmt->info->read_count(ch->ioctrl, CMCNT); |
1b56b96b MD |
282 | } |
283 | ||
3f44f715 | 284 | static inline int sh_cmt_write_cmcnt(struct sh_cmt_channel *ch, u32 value) |
1b56b96b | 285 | { |
3f44f715 WS |
286 | /* Tests showed that we need to wait 3 clocks here */ |
287 | unsigned int cmcnt_delay = DIV_ROUND_UP(3 * ch->cmt->reg_delay, 2); | |
288 | u32 reg; | |
289 | ||
290 | if (ch->cmt->info->model > SH_CMT_16BIT) { | |
291 | int ret = read_poll_timeout_atomic(sh_cmt_read_cmcsr, reg, | |
292 | !(reg & SH_CMT32_CMCSR_WRFLG), | |
293 | 1, cmcnt_delay, false, ch); | |
294 | if (ret < 0) | |
295 | return ret; | |
296 | } | |
297 | ||
81b3b271 | 298 | ch->cmt->info->write_count(ch->ioctrl, CMCNT, value); |
3f44f715 WS |
299 | udelay(cmcnt_delay); |
300 | return 0; | |
1b56b96b MD |
301 | } |
302 | ||
22627c6f | 303 | static inline void sh_cmt_write_cmcor(struct sh_cmt_channel *ch, u32 value) |
1b56b96b | 304 | { |
3f44f715 WS |
305 | u32 old_value = ch->cmt->info->read_count(ch->ioctrl, CMCOR); |
306 | ||
307 | if (value != old_value) { | |
308 | ch->cmt->info->write_count(ch->ioctrl, CMCOR, value); | |
309 | udelay(ch->cmt->reg_delay); | |
310 | } | |
1b56b96b MD |
311 | } |
312 | ||
22627c6f | 313 | static u32 sh_cmt_get_counter(struct sh_cmt_channel *ch, u32 *has_wrapped) |
3fb1b6ad | 314 | { |
22627c6f SS |
315 | u32 v1, v2, v3; |
316 | u32 o1, o2; | |
5b644c7a | 317 | |
2cda3ac4 | 318 | o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit; |
3fb1b6ad MD |
319 | |
320 | /* Make sure the timer value is stable. Stolen from acpi_pm.c */ | |
321 | do { | |
5b644c7a | 322 | o2 = o1; |
7269f933 LP |
323 | v1 = sh_cmt_read_cmcnt(ch); |
324 | v2 = sh_cmt_read_cmcnt(ch); | |
325 | v3 = sh_cmt_read_cmcnt(ch); | |
2cda3ac4 | 326 | o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit; |
5b644c7a MD |
327 | } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3) |
328 | || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2))); | |
3fb1b6ad | 329 | |
5b644c7a | 330 | *has_wrapped = o1; |
3fb1b6ad MD |
331 | return v2; |
332 | } | |
333 | ||
7269f933 | 334 | static void sh_cmt_start_stop_ch(struct sh_cmt_channel *ch, int start) |
3fb1b6ad | 335 | { |
22627c6f SS |
336 | unsigned long flags; |
337 | u32 value; | |
3fb1b6ad MD |
338 | |
339 | /* start stop register shared by multiple timer channels */ | |
de599c88 | 340 | raw_spin_lock_irqsave(&ch->cmt->lock, flags); |
7269f933 | 341 | value = sh_cmt_read_cmstr(ch); |
3fb1b6ad MD |
342 | |
343 | if (start) | |
81b3b271 | 344 | value |= 1 << ch->timer_bit; |
3fb1b6ad | 345 | else |
81b3b271 | 346 | value &= ~(1 << ch->timer_bit); |
3fb1b6ad | 347 | |
7269f933 | 348 | sh_cmt_write_cmstr(ch, value); |
de599c88 | 349 | raw_spin_unlock_irqrestore(&ch->cmt->lock, flags); |
3fb1b6ad MD |
350 | } |
351 | ||
890f423b | 352 | static int sh_cmt_enable(struct sh_cmt_channel *ch) |
3fb1b6ad | 353 | { |
3f44f715 | 354 | int ret; |
3fb1b6ad | 355 | |
7269f933 | 356 | dev_pm_syscore_device(&ch->cmt->pdev->dev, true); |
bad81383 | 357 | |
9436b4ab | 358 | /* enable clock */ |
7269f933 | 359 | ret = clk_enable(ch->cmt->clk); |
3fb1b6ad | 360 | if (ret) { |
740a9518 LP |
361 | dev_err(&ch->cmt->pdev->dev, "ch%u: cannot enable clock\n", |
362 | ch->index); | |
3f7e5e24 | 363 | goto err0; |
3fb1b6ad | 364 | } |
3fb1b6ad MD |
365 | |
366 | /* make sure channel is disabled */ | |
7269f933 | 367 | sh_cmt_start_stop_ch(ch, 0); |
3fb1b6ad MD |
368 | |
369 | /* configure channel, periodic mode and maximum timeout */ | |
2cda3ac4 | 370 | if (ch->cmt->info->width == 16) { |
d14be99b LP |
371 | sh_cmt_write_cmcsr(ch, SH_CMT16_CMCSR_CMIE | |
372 | SH_CMT16_CMCSR_CKS512); | |
3014f474 | 373 | } else { |
68c70aae WS |
374 | u32 cmtout = ch->cmt->info->model <= SH_CMT_48BIT ? |
375 | SH_CMT32_CMCSR_CMTOUT_IE : 0; | |
376 | sh_cmt_write_cmcsr(ch, cmtout | SH_CMT32_CMCSR_CMM | | |
d14be99b LP |
377 | SH_CMT32_CMCSR_CMR_IRQ | |
378 | SH_CMT32_CMCSR_CKS_RCLK8); | |
3014f474 | 379 | } |
3fb1b6ad | 380 | |
7269f933 | 381 | sh_cmt_write_cmcor(ch, 0xffffffff); |
3f44f715 | 382 | ret = sh_cmt_write_cmcnt(ch, 0); |
3f7e5e24 | 383 | |
3f44f715 | 384 | if (ret || sh_cmt_read_cmcnt(ch)) { |
740a9518 LP |
385 | dev_err(&ch->cmt->pdev->dev, "ch%u: cannot clear CMCNT\n", |
386 | ch->index); | |
3f7e5e24 MD |
387 | ret = -ETIMEDOUT; |
388 | goto err1; | |
389 | } | |
390 | ||
3fb1b6ad | 391 | /* enable channel */ |
7269f933 | 392 | sh_cmt_start_stop_ch(ch, 1); |
3fb1b6ad | 393 | return 0; |
3f7e5e24 MD |
394 | err1: |
395 | /* stop clock */ | |
7269f933 | 396 | clk_disable(ch->cmt->clk); |
3f7e5e24 MD |
397 | |
398 | err0: | |
399 | return ret; | |
3fb1b6ad MD |
400 | } |
401 | ||
7269f933 | 402 | static void sh_cmt_disable(struct sh_cmt_channel *ch) |
3fb1b6ad MD |
403 | { |
404 | /* disable channel */ | |
7269f933 | 405 | sh_cmt_start_stop_ch(ch, 0); |
3fb1b6ad | 406 | |
be890a1a | 407 | /* disable interrupts in CMT block */ |
7269f933 | 408 | sh_cmt_write_cmcsr(ch, 0); |
be890a1a | 409 | |
9436b4ab | 410 | /* stop clock */ |
7269f933 | 411 | clk_disable(ch->cmt->clk); |
bad81383 | 412 | |
7269f933 | 413 | dev_pm_syscore_device(&ch->cmt->pdev->dev, false); |
3fb1b6ad MD |
414 | } |
415 | ||
416 | /* private flags */ | |
417 | #define FLAG_CLOCKEVENT (1 << 0) | |
418 | #define FLAG_CLOCKSOURCE (1 << 1) | |
419 | #define FLAG_REPROGRAM (1 << 2) | |
420 | #define FLAG_SKIPEVENT (1 << 3) | |
421 | #define FLAG_IRQCONTEXT (1 << 4) | |
422 | ||
7269f933 | 423 | static void sh_cmt_clock_event_program_verify(struct sh_cmt_channel *ch, |
3fb1b6ad MD |
424 | int absolute) |
425 | { | |
22627c6f SS |
426 | u32 value = ch->next_match_value; |
427 | u32 new_match; | |
428 | u32 delay = 0; | |
429 | u32 now = 0; | |
430 | u32 has_wrapped; | |
3fb1b6ad | 431 | |
7269f933 LP |
432 | now = sh_cmt_get_counter(ch, &has_wrapped); |
433 | ch->flags |= FLAG_REPROGRAM; /* force reprogram */ | |
3fb1b6ad MD |
434 | |
435 | if (has_wrapped) { | |
436 | /* we're competing with the interrupt handler. | |
437 | * -> let the interrupt handler reprogram the timer. | |
438 | * -> interrupt number two handles the event. | |
439 | */ | |
7269f933 | 440 | ch->flags |= FLAG_SKIPEVENT; |
3fb1b6ad MD |
441 | return; |
442 | } | |
443 | ||
444 | if (absolute) | |
445 | now = 0; | |
446 | ||
447 | do { | |
448 | /* reprogram the timer hardware, | |
449 | * but don't save the new match value yet. | |
450 | */ | |
451 | new_match = now + value + delay; | |
7269f933 LP |
452 | if (new_match > ch->max_match_value) |
453 | new_match = ch->max_match_value; | |
3fb1b6ad | 454 | |
7269f933 | 455 | sh_cmt_write_cmcor(ch, new_match); |
3fb1b6ad | 456 | |
7269f933 LP |
457 | now = sh_cmt_get_counter(ch, &has_wrapped); |
458 | if (has_wrapped && (new_match > ch->match_value)) { | |
3fb1b6ad MD |
459 | /* we are changing to a greater match value, |
460 | * so this wrap must be caused by the counter | |
461 | * matching the old value. | |
462 | * -> first interrupt reprograms the timer. | |
463 | * -> interrupt number two handles the event. | |
464 | */ | |
7269f933 | 465 | ch->flags |= FLAG_SKIPEVENT; |
3fb1b6ad MD |
466 | break; |
467 | } | |
468 | ||
469 | if (has_wrapped) { | |
470 | /* we are changing to a smaller match value, | |
471 | * so the wrap must be caused by the counter | |
472 | * matching the new value. | |
473 | * -> save programmed match value. | |
474 | * -> let isr handle the event. | |
475 | */ | |
7269f933 | 476 | ch->match_value = new_match; |
3fb1b6ad MD |
477 | break; |
478 | } | |
479 | ||
480 | /* be safe: verify hardware settings */ | |
481 | if (now < new_match) { | |
482 | /* timer value is below match value, all good. | |
483 | * this makes sure we won't miss any match events. | |
484 | * -> save programmed match value. | |
485 | * -> let isr handle the event. | |
486 | */ | |
7269f933 | 487 | ch->match_value = new_match; |
3fb1b6ad MD |
488 | break; |
489 | } | |
490 | ||
491 | /* the counter has reached a value greater | |
492 | * than our new match value. and since the | |
493 | * has_wrapped flag isn't set we must have | |
494 | * programmed a too close event. | |
495 | * -> increase delay and retry. | |
496 | */ | |
497 | if (delay) | |
498 | delay <<= 1; | |
499 | else | |
500 | delay = 1; | |
501 | ||
502 | if (!delay) | |
740a9518 LP |
503 | dev_warn(&ch->cmt->pdev->dev, "ch%u: too long delay\n", |
504 | ch->index); | |
3fb1b6ad MD |
505 | |
506 | } while (delay); | |
507 | } | |
508 | ||
7269f933 | 509 | static void __sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta) |
3fb1b6ad | 510 | { |
7269f933 | 511 | if (delta > ch->max_match_value) |
740a9518 LP |
512 | dev_warn(&ch->cmt->pdev->dev, "ch%u: delta out of range\n", |
513 | ch->index); | |
3fb1b6ad | 514 | |
7269f933 LP |
515 | ch->next_match_value = delta; |
516 | sh_cmt_clock_event_program_verify(ch, 0); | |
65ada547 TY |
517 | } |
518 | ||
7269f933 | 519 | static void sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta) |
65ada547 TY |
520 | { |
521 | unsigned long flags; | |
522 | ||
7269f933 LP |
523 | raw_spin_lock_irqsave(&ch->lock, flags); |
524 | __sh_cmt_set_next(ch, delta); | |
525 | raw_spin_unlock_irqrestore(&ch->lock, flags); | |
3fb1b6ad MD |
526 | } |
527 | ||
528 | static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id) | |
529 | { | |
7269f933 | 530 | struct sh_cmt_channel *ch = dev_id; |
3fb1b6ad MD |
531 | |
532 | /* clear flags */ | |
2cda3ac4 LP |
533 | sh_cmt_write_cmcsr(ch, sh_cmt_read_cmcsr(ch) & |
534 | ch->cmt->info->clear_bits); | |
3fb1b6ad MD |
535 | |
536 | /* update clock source counter to begin with if enabled | |
537 | * the wrap flag should be cleared by the timer specific | |
538 | * isr before we end up here. | |
539 | */ | |
7269f933 LP |
540 | if (ch->flags & FLAG_CLOCKSOURCE) |
541 | ch->total_cycles += ch->match_value + 1; | |
3fb1b6ad | 542 | |
7269f933 LP |
543 | if (!(ch->flags & FLAG_REPROGRAM)) |
544 | ch->next_match_value = ch->max_match_value; | |
3fb1b6ad | 545 | |
7269f933 | 546 | ch->flags |= FLAG_IRQCONTEXT; |
3fb1b6ad | 547 | |
7269f933 LP |
548 | if (ch->flags & FLAG_CLOCKEVENT) { |
549 | if (!(ch->flags & FLAG_SKIPEVENT)) { | |
051b782e | 550 | if (clockevent_state_oneshot(&ch->ced)) { |
7269f933 LP |
551 | ch->next_match_value = ch->max_match_value; |
552 | ch->flags |= FLAG_REPROGRAM; | |
3fb1b6ad MD |
553 | } |
554 | ||
7269f933 | 555 | ch->ced.event_handler(&ch->ced); |
3fb1b6ad MD |
556 | } |
557 | } | |
558 | ||
7269f933 | 559 | ch->flags &= ~FLAG_SKIPEVENT; |
3fb1b6ad | 560 | |
7269f933 LP |
561 | if (ch->flags & FLAG_REPROGRAM) { |
562 | ch->flags &= ~FLAG_REPROGRAM; | |
563 | sh_cmt_clock_event_program_verify(ch, 1); | |
3fb1b6ad | 564 | |
7269f933 | 565 | if (ch->flags & FLAG_CLOCKEVENT) |
051b782e | 566 | if ((clockevent_state_shutdown(&ch->ced)) |
7269f933 LP |
567 | || (ch->match_value == ch->next_match_value)) |
568 | ch->flags &= ~FLAG_REPROGRAM; | |
3fb1b6ad MD |
569 | } |
570 | ||
7269f933 | 571 | ch->flags &= ~FLAG_IRQCONTEXT; |
3fb1b6ad MD |
572 | |
573 | return IRQ_HANDLED; | |
574 | } | |
575 | ||
7269f933 | 576 | static int sh_cmt_start(struct sh_cmt_channel *ch, unsigned long flag) |
3fb1b6ad MD |
577 | { |
578 | int ret = 0; | |
579 | unsigned long flags; | |
580 | ||
8ae954ca NS |
581 | if (flag & FLAG_CLOCKSOURCE) |
582 | pm_runtime_get_sync(&ch->cmt->pdev->dev); | |
583 | ||
7269f933 | 584 | raw_spin_lock_irqsave(&ch->lock, flags); |
3fb1b6ad | 585 | |
8ae954ca NS |
586 | if (!(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) { |
587 | if (flag & FLAG_CLOCKEVENT) | |
588 | pm_runtime_get_sync(&ch->cmt->pdev->dev); | |
890f423b | 589 | ret = sh_cmt_enable(ch); |
8ae954ca | 590 | } |
3fb1b6ad MD |
591 | |
592 | if (ret) | |
593 | goto out; | |
7269f933 | 594 | ch->flags |= flag; |
3fb1b6ad MD |
595 | |
596 | /* setup timeout if no clockevent */ | |
be83c3b6 PH |
597 | if (ch->cmt->num_channels == 1 && |
598 | flag == FLAG_CLOCKSOURCE && (!(ch->flags & FLAG_CLOCKEVENT))) | |
7269f933 | 599 | __sh_cmt_set_next(ch, ch->max_match_value); |
3fb1b6ad | 600 | out: |
7269f933 | 601 | raw_spin_unlock_irqrestore(&ch->lock, flags); |
3fb1b6ad MD |
602 | |
603 | return ret; | |
604 | } | |
605 | ||
7269f933 | 606 | static void sh_cmt_stop(struct sh_cmt_channel *ch, unsigned long flag) |
3fb1b6ad MD |
607 | { |
608 | unsigned long flags; | |
609 | unsigned long f; | |
610 | ||
7269f933 | 611 | raw_spin_lock_irqsave(&ch->lock, flags); |
3fb1b6ad | 612 | |
7269f933 LP |
613 | f = ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE); |
614 | ch->flags &= ~flag; | |
3fb1b6ad | 615 | |
8ae954ca | 616 | if (f && !(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) { |
7269f933 | 617 | sh_cmt_disable(ch); |
8ae954ca NS |
618 | if (flag & FLAG_CLOCKEVENT) |
619 | pm_runtime_put(&ch->cmt->pdev->dev); | |
620 | } | |
3fb1b6ad MD |
621 | |
622 | /* adjust the timeout to maximum if only clocksource left */ | |
7269f933 LP |
623 | if ((flag == FLAG_CLOCKEVENT) && (ch->flags & FLAG_CLOCKSOURCE)) |
624 | __sh_cmt_set_next(ch, ch->max_match_value); | |
3fb1b6ad | 625 | |
7269f933 | 626 | raw_spin_unlock_irqrestore(&ch->lock, flags); |
8ae954ca NS |
627 | |
628 | if (flag & FLAG_CLOCKSOURCE) | |
629 | pm_runtime_put(&ch->cmt->pdev->dev); | |
3fb1b6ad MD |
630 | } |
631 | ||
7269f933 | 632 | static struct sh_cmt_channel *cs_to_sh_cmt(struct clocksource *cs) |
19bdc9d0 | 633 | { |
7269f933 | 634 | return container_of(cs, struct sh_cmt_channel, cs); |
19bdc9d0 MD |
635 | } |
636 | ||
a5a1d1c2 | 637 | static u64 sh_cmt_clocksource_read(struct clocksource *cs) |
19bdc9d0 | 638 | { |
7269f933 | 639 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
22627c6f | 640 | u32 has_wrapped; |
19bdc9d0 | 641 | |
be83c3b6 PH |
642 | if (ch->cmt->num_channels == 1) { |
643 | unsigned long flags; | |
644 | u64 value; | |
645 | u32 raw; | |
19bdc9d0 | 646 | |
be83c3b6 PH |
647 | raw_spin_lock_irqsave(&ch->lock, flags); |
648 | value = ch->total_cycles; | |
649 | raw = sh_cmt_get_counter(ch, &has_wrapped); | |
650 | ||
651 | if (unlikely(has_wrapped)) | |
652 | raw += ch->match_value + 1; | |
653 | raw_spin_unlock_irqrestore(&ch->lock, flags); | |
654 | ||
655 | return value + raw; | |
656 | } | |
19bdc9d0 | 657 | |
be83c3b6 | 658 | return sh_cmt_get_counter(ch, &has_wrapped); |
19bdc9d0 MD |
659 | } |
660 | ||
661 | static int sh_cmt_clocksource_enable(struct clocksource *cs) | |
662 | { | |
3593f5fe | 663 | int ret; |
7269f933 | 664 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
19bdc9d0 | 665 | |
7269f933 | 666 | WARN_ON(ch->cs_enabled); |
bad81383 | 667 | |
7269f933 | 668 | ch->total_cycles = 0; |
19bdc9d0 | 669 | |
7269f933 | 670 | ret = sh_cmt_start(ch, FLAG_CLOCKSOURCE); |
890f423b | 671 | if (!ret) |
7269f933 | 672 | ch->cs_enabled = true; |
890f423b | 673 | |
3593f5fe | 674 | return ret; |
19bdc9d0 MD |
675 | } |
676 | ||
677 | static void sh_cmt_clocksource_disable(struct clocksource *cs) | |
678 | { | |
7269f933 | 679 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
bad81383 | 680 | |
7269f933 | 681 | WARN_ON(!ch->cs_enabled); |
bad81383 | 682 | |
7269f933 LP |
683 | sh_cmt_stop(ch, FLAG_CLOCKSOURCE); |
684 | ch->cs_enabled = false; | |
19bdc9d0 MD |
685 | } |
686 | ||
9bb5ec88 RW |
687 | static void sh_cmt_clocksource_suspend(struct clocksource *cs) |
688 | { | |
7269f933 | 689 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
9bb5ec88 | 690 | |
54d46b7f GU |
691 | if (!ch->cs_enabled) |
692 | return; | |
693 | ||
7269f933 | 694 | sh_cmt_stop(ch, FLAG_CLOCKSOURCE); |
fc519890 | 695 | dev_pm_genpd_suspend(&ch->cmt->pdev->dev); |
9bb5ec88 RW |
696 | } |
697 | ||
c8162884 MD |
698 | static void sh_cmt_clocksource_resume(struct clocksource *cs) |
699 | { | |
7269f933 | 700 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
9bb5ec88 | 701 | |
54d46b7f GU |
702 | if (!ch->cs_enabled) |
703 | return; | |
704 | ||
fc519890 | 705 | dev_pm_genpd_resume(&ch->cmt->pdev->dev); |
7269f933 | 706 | sh_cmt_start(ch, FLAG_CLOCKSOURCE); |
c8162884 MD |
707 | } |
708 | ||
7269f933 | 709 | static int sh_cmt_register_clocksource(struct sh_cmt_channel *ch, |
fb28a659 | 710 | const char *name) |
19bdc9d0 | 711 | { |
7269f933 | 712 | struct clocksource *cs = &ch->cs; |
19bdc9d0 MD |
713 | |
714 | cs->name = name; | |
fb28a659 | 715 | cs->rating = 125; |
19bdc9d0 MD |
716 | cs->read = sh_cmt_clocksource_read; |
717 | cs->enable = sh_cmt_clocksource_enable; | |
718 | cs->disable = sh_cmt_clocksource_disable; | |
9bb5ec88 | 719 | cs->suspend = sh_cmt_clocksource_suspend; |
c8162884 | 720 | cs->resume = sh_cmt_clocksource_resume; |
be83c3b6 | 721 | cs->mask = CLOCKSOURCE_MASK(ch->cmt->info->width); |
19bdc9d0 | 722 | cs->flags = CLOCK_SOURCE_IS_CONTINUOUS; |
f4d7c356 | 723 | |
740a9518 LP |
724 | dev_info(&ch->cmt->pdev->dev, "ch%u: used as clock source\n", |
725 | ch->index); | |
f4d7c356 | 726 | |
890f423b | 727 | clocksource_register_hz(cs, ch->cmt->rate); |
19bdc9d0 MD |
728 | return 0; |
729 | } | |
730 | ||
7269f933 | 731 | static struct sh_cmt_channel *ced_to_sh_cmt(struct clock_event_device *ced) |
3fb1b6ad | 732 | { |
7269f933 | 733 | return container_of(ced, struct sh_cmt_channel, ced); |
3fb1b6ad MD |
734 | } |
735 | ||
7269f933 | 736 | static void sh_cmt_clock_event_start(struct sh_cmt_channel *ch, int periodic) |
3fb1b6ad | 737 | { |
7269f933 | 738 | sh_cmt_start(ch, FLAG_CLOCKEVENT); |
3fb1b6ad | 739 | |
3fb1b6ad | 740 | if (periodic) |
890f423b | 741 | sh_cmt_set_next(ch, ((ch->cmt->rate + HZ/2) / HZ) - 1); |
3fb1b6ad | 742 | else |
7269f933 | 743 | sh_cmt_set_next(ch, ch->max_match_value); |
3fb1b6ad MD |
744 | } |
745 | ||
051b782e VK |
746 | static int sh_cmt_clock_event_shutdown(struct clock_event_device *ced) |
747 | { | |
748 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); | |
749 | ||
750 | sh_cmt_stop(ch, FLAG_CLOCKEVENT); | |
751 | return 0; | |
752 | } | |
753 | ||
754 | static int sh_cmt_clock_event_set_state(struct clock_event_device *ced, | |
755 | int periodic) | |
3fb1b6ad | 756 | { |
7269f933 | 757 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); |
3fb1b6ad MD |
758 | |
759 | /* deal with old setting first */ | |
051b782e | 760 | if (clockevent_state_oneshot(ced) || clockevent_state_periodic(ced)) |
7269f933 | 761 | sh_cmt_stop(ch, FLAG_CLOCKEVENT); |
3fb1b6ad | 762 | |
051b782e VK |
763 | dev_info(&ch->cmt->pdev->dev, "ch%u: used for %s clock events\n", |
764 | ch->index, periodic ? "periodic" : "oneshot"); | |
765 | sh_cmt_clock_event_start(ch, periodic); | |
766 | return 0; | |
767 | } | |
768 | ||
769 | static int sh_cmt_clock_event_set_oneshot(struct clock_event_device *ced) | |
770 | { | |
771 | return sh_cmt_clock_event_set_state(ced, 0); | |
772 | } | |
773 | ||
774 | static int sh_cmt_clock_event_set_periodic(struct clock_event_device *ced) | |
775 | { | |
776 | return sh_cmt_clock_event_set_state(ced, 1); | |
3fb1b6ad MD |
777 | } |
778 | ||
779 | static int sh_cmt_clock_event_next(unsigned long delta, | |
780 | struct clock_event_device *ced) | |
781 | { | |
7269f933 | 782 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); |
3fb1b6ad | 783 | |
051b782e | 784 | BUG_ON(!clockevent_state_oneshot(ced)); |
7269f933 LP |
785 | if (likely(ch->flags & FLAG_IRQCONTEXT)) |
786 | ch->next_match_value = delta - 1; | |
3fb1b6ad | 787 | else |
7269f933 | 788 | sh_cmt_set_next(ch, delta - 1); |
3fb1b6ad MD |
789 | |
790 | return 0; | |
791 | } | |
792 | ||
9bb5ec88 RW |
793 | static void sh_cmt_clock_event_suspend(struct clock_event_device *ced) |
794 | { | |
7269f933 | 795 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); |
57dee992 | 796 | |
fc519890 | 797 | dev_pm_genpd_suspend(&ch->cmt->pdev->dev); |
7269f933 | 798 | clk_unprepare(ch->cmt->clk); |
9bb5ec88 RW |
799 | } |
800 | ||
801 | static void sh_cmt_clock_event_resume(struct clock_event_device *ced) | |
802 | { | |
7269f933 | 803 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); |
57dee992 | 804 | |
7269f933 | 805 | clk_prepare(ch->cmt->clk); |
fc519890 | 806 | dev_pm_genpd_resume(&ch->cmt->pdev->dev); |
9bb5ec88 RW |
807 | } |
808 | ||
bfa76bb1 LP |
809 | static int sh_cmt_register_clockevent(struct sh_cmt_channel *ch, |
810 | const char *name) | |
3fb1b6ad | 811 | { |
7269f933 | 812 | struct clock_event_device *ced = &ch->ced; |
bfa76bb1 LP |
813 | int irq; |
814 | int ret; | |
815 | ||
31e912f5 | 816 | irq = platform_get_irq(ch->cmt->pdev, ch->index); |
9f475d08 | 817 | if (irq < 0) |
bfa76bb1 | 818 | return irq; |
bfa76bb1 LP |
819 | |
820 | ret = request_irq(irq, sh_cmt_interrupt, | |
821 | IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING, | |
822 | dev_name(&ch->cmt->pdev->dev), ch); | |
823 | if (ret) { | |
824 | dev_err(&ch->cmt->pdev->dev, "ch%u: failed to request irq %d\n", | |
825 | ch->index, irq); | |
826 | return ret; | |
827 | } | |
3fb1b6ad | 828 | |
3fb1b6ad MD |
829 | ced->name = name; |
830 | ced->features = CLOCK_EVT_FEAT_PERIODIC; | |
831 | ced->features |= CLOCK_EVT_FEAT_ONESHOT; | |
b7fcbb0f | 832 | ced->rating = 125; |
f1ebe1e4 | 833 | ced->cpumask = cpu_possible_mask; |
3fb1b6ad | 834 | ced->set_next_event = sh_cmt_clock_event_next; |
051b782e VK |
835 | ced->set_state_shutdown = sh_cmt_clock_event_shutdown; |
836 | ced->set_state_periodic = sh_cmt_clock_event_set_periodic; | |
837 | ced->set_state_oneshot = sh_cmt_clock_event_set_oneshot; | |
9bb5ec88 RW |
838 | ced->suspend = sh_cmt_clock_event_suspend; |
839 | ced->resume = sh_cmt_clock_event_resume; | |
3fb1b6ad | 840 | |
890f423b NS |
841 | /* TODO: calculate good shift from rate and counter bit width */ |
842 | ced->shift = 32; | |
843 | ced->mult = div_sc(ch->cmt->rate, NSEC_PER_SEC, ced->shift); | |
844 | ced->max_delta_ns = clockevent_delta2ns(ch->max_match_value, ced); | |
bb2e94ac | 845 | ced->max_delta_ticks = ch->max_match_value; |
890f423b | 846 | ced->min_delta_ns = clockevent_delta2ns(0x1f, ced); |
bb2e94ac | 847 | ced->min_delta_ticks = 0x1f; |
890f423b | 848 | |
740a9518 LP |
849 | dev_info(&ch->cmt->pdev->dev, "ch%u: used for clock events\n", |
850 | ch->index); | |
3fb1b6ad | 851 | clockevents_register_device(ced); |
bfa76bb1 LP |
852 | |
853 | return 0; | |
3fb1b6ad MD |
854 | } |
855 | ||
1d053e1d | 856 | static int sh_cmt_register(struct sh_cmt_channel *ch, const char *name, |
fb28a659 | 857 | bool clockevent, bool clocksource) |
3fb1b6ad | 858 | { |
bfa76bb1 LP |
859 | int ret; |
860 | ||
81b3b271 LP |
861 | if (clockevent) { |
862 | ch->cmt->has_clockevent = true; | |
bfa76bb1 LP |
863 | ret = sh_cmt_register_clockevent(ch, name); |
864 | if (ret < 0) | |
865 | return ret; | |
81b3b271 | 866 | } |
3fb1b6ad | 867 | |
81b3b271 LP |
868 | if (clocksource) { |
869 | ch->cmt->has_clocksource = true; | |
fb28a659 | 870 | sh_cmt_register_clocksource(ch, name); |
81b3b271 | 871 | } |
19bdc9d0 | 872 | |
3fb1b6ad MD |
873 | return 0; |
874 | } | |
875 | ||
740a9518 | 876 | static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index, |
81b3b271 LP |
877 | unsigned int hwidx, bool clockevent, |
878 | bool clocksource, struct sh_cmt_device *cmt) | |
b882e7b1 | 879 | { |
2a97d553 | 880 | u32 value; |
b882e7b1 LP |
881 | int ret; |
882 | ||
81b3b271 LP |
883 | /* Skip unused channels. */ |
884 | if (!clockevent && !clocksource) | |
885 | return 0; | |
886 | ||
b882e7b1 | 887 | ch->cmt = cmt; |
740a9518 | 888 | ch->index = index; |
81b3b271 | 889 | ch->hwidx = hwidx; |
83c79a6d | 890 | ch->timer_bit = hwidx; |
81b3b271 LP |
891 | |
892 | /* | |
893 | * Compute the address of the channel control register block. For the | |
894 | * timers with a per-channel start/stop register, compute its address | |
895 | * as well. | |
81b3b271 | 896 | */ |
31e912f5 LP |
897 | switch (cmt->info->model) { |
898 | case SH_CMT_16BIT: | |
899 | ch->ioctrl = cmt->mapbase + 2 + ch->hwidx * 6; | |
900 | break; | |
901 | case SH_CMT_32BIT: | |
902 | case SH_CMT_48BIT: | |
903 | ch->ioctrl = cmt->mapbase + 0x10 + ch->hwidx * 0x10; | |
904 | break; | |
83c79a6d MD |
905 | case SH_CMT0_RCAR_GEN2: |
906 | case SH_CMT1_RCAR_GEN2: | |
31e912f5 LP |
907 | ch->iostart = cmt->mapbase + ch->hwidx * 0x100; |
908 | ch->ioctrl = ch->iostart + 0x10; | |
83c79a6d | 909 | ch->timer_bit = 0; |
2a97d553 GU |
910 | |
911 | /* Enable the clock supply to the channel */ | |
912 | value = ioread32(cmt->mapbase + CMCLKE); | |
913 | value |= BIT(hwidx); | |
914 | iowrite32(value, cmt->mapbase + CMCLKE); | |
31e912f5 | 915 | break; |
81b3b271 LP |
916 | } |
917 | ||
2cda3ac4 | 918 | if (cmt->info->width == (sizeof(ch->max_match_value) * 8)) |
b882e7b1 LP |
919 | ch->max_match_value = ~0; |
920 | else | |
2cda3ac4 | 921 | ch->max_match_value = (1 << cmt->info->width) - 1; |
b882e7b1 LP |
922 | |
923 | ch->match_value = ch->max_match_value; | |
924 | raw_spin_lock_init(&ch->lock); | |
925 | ||
1d053e1d | 926 | ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev), |
81b3b271 | 927 | clockevent, clocksource); |
b882e7b1 | 928 | if (ret) { |
740a9518 LP |
929 | dev_err(&cmt->pdev->dev, "ch%u: registration failed\n", |
930 | ch->index); | |
b882e7b1 LP |
931 | return ret; |
932 | } | |
933 | ch->cs_enabled = false; | |
934 | ||
b882e7b1 LP |
935 | return 0; |
936 | } | |
937 | ||
81b3b271 | 938 | static int sh_cmt_map_memory(struct sh_cmt_device *cmt) |
3fb1b6ad | 939 | { |
81b3b271 | 940 | struct resource *mem; |
3fb1b6ad | 941 | |
81b3b271 LP |
942 | mem = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 0); |
943 | if (!mem) { | |
944 | dev_err(&cmt->pdev->dev, "failed to get I/O memory\n"); | |
945 | return -ENXIO; | |
946 | } | |
3fb1b6ad | 947 | |
4bdc0d67 | 948 | cmt->mapbase = ioremap(mem->start, resource_size(mem)); |
81b3b271 LP |
949 | if (cmt->mapbase == NULL) { |
950 | dev_err(&cmt->pdev->dev, "failed to remap I/O memory\n"); | |
951 | return -ENXIO; | |
3fb1b6ad MD |
952 | } |
953 | ||
81b3b271 LP |
954 | return 0; |
955 | } | |
956 | ||
1768aa2f LP |
957 | static const struct platform_device_id sh_cmt_id_table[] = { |
958 | { "sh-cmt-16", (kernel_ulong_t)&sh_cmt_info[SH_CMT_16BIT] }, | |
959 | { "sh-cmt-32", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT] }, | |
1768aa2f LP |
960 | { } |
961 | }; | |
962 | MODULE_DEVICE_TABLE(platform, sh_cmt_id_table); | |
963 | ||
964 | static const struct of_device_id sh_cmt_of_table[] __maybe_unused = { | |
19d60845 MD |
965 | { |
966 | /* deprecated, preserved for backward compatibility */ | |
967 | .compatible = "renesas,cmt-48", | |
968 | .data = &sh_cmt_info[SH_CMT_48BIT] | |
969 | }, | |
8d50e947 GU |
970 | { |
971 | /* deprecated, preserved for backward compatibility */ | |
972 | .compatible = "renesas,cmt-48-gen2", | |
973 | .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2] | |
8c1afba2 MD |
974 | }, |
975 | { | |
976 | .compatible = "renesas,r8a7740-cmt1", | |
977 | .data = &sh_cmt_info[SH_CMT_48BIT] | |
978 | }, | |
979 | { | |
980 | .compatible = "renesas,sh73a0-cmt1", | |
981 | .data = &sh_cmt_info[SH_CMT_48BIT] | |
8d50e947 | 982 | }, |
eceb4c49 SS |
983 | { |
984 | .compatible = "renesas,rcar-gen2-cmt0", | |
985 | .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2] | |
986 | }, | |
987 | { | |
988 | .compatible = "renesas,rcar-gen2-cmt1", | |
989 | .data = &sh_cmt_info[SH_CMT1_RCAR_GEN2] | |
990 | }, | |
ac142a7f SS |
991 | { |
992 | .compatible = "renesas,rcar-gen3-cmt0", | |
993 | .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2] | |
994 | }, | |
995 | { | |
996 | .compatible = "renesas,rcar-gen3-cmt1", | |
997 | .data = &sh_cmt_info[SH_CMT1_RCAR_GEN2] | |
998 | }, | |
aa84506e WS |
999 | { |
1000 | .compatible = "renesas,rcar-gen4-cmt0", | |
1001 | .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2] | |
1002 | }, | |
1003 | { | |
1004 | .compatible = "renesas,rcar-gen4-cmt1", | |
1005 | .data = &sh_cmt_info[SH_CMT1_RCAR_GEN2] | |
1006 | }, | |
1768aa2f LP |
1007 | { } |
1008 | }; | |
1009 | MODULE_DEVICE_TABLE(of, sh_cmt_of_table); | |
1010 | ||
81b3b271 LP |
1011 | static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev) |
1012 | { | |
3f44f715 WS |
1013 | unsigned int mask, i; |
1014 | unsigned long rate; | |
81b3b271 LP |
1015 | int ret; |
1016 | ||
81b3b271 | 1017 | cmt->pdev = pdev; |
de599c88 | 1018 | raw_spin_lock_init(&cmt->lock); |
81b3b271 | 1019 | |
1768aa2f | 1020 | if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) { |
2d1d5172 | 1021 | cmt->info = of_device_get_match_data(&pdev->dev); |
d1d28597 | 1022 | cmt->hw_channels = cmt->info->channels_mask; |
1768aa2f LP |
1023 | } else if (pdev->dev.platform_data) { |
1024 | struct sh_timer_config *cfg = pdev->dev.platform_data; | |
1025 | const struct platform_device_id *id = pdev->id_entry; | |
1026 | ||
1027 | cmt->info = (const struct sh_cmt_info *)id->driver_data; | |
1028 | cmt->hw_channels = cfg->channels_mask; | |
1029 | } else { | |
81b3b271 LP |
1030 | dev_err(&cmt->pdev->dev, "missing platform data\n"); |
1031 | return -ENXIO; | |
1032 | } | |
1033 | ||
81b3b271 | 1034 | /* Get hold of clock. */ |
31e912f5 | 1035 | cmt->clk = clk_get(&cmt->pdev->dev, "fck"); |
2653caf4 LP |
1036 | if (IS_ERR(cmt->clk)) { |
1037 | dev_err(&cmt->pdev->dev, "cannot get clock\n"); | |
81b3b271 | 1038 | return PTR_ERR(cmt->clk); |
3fb1b6ad MD |
1039 | } |
1040 | ||
2653caf4 | 1041 | ret = clk_prepare(cmt->clk); |
57dee992 | 1042 | if (ret < 0) |
81b3b271 | 1043 | goto err_clk_put; |
57dee992 | 1044 | |
890f423b NS |
1045 | /* Determine clock rate. */ |
1046 | ret = clk_enable(cmt->clk); | |
1047 | if (ret < 0) | |
1048 | goto err_clk_unprepare; | |
1049 | ||
3f44f715 WS |
1050 | rate = clk_get_rate(cmt->clk); |
1051 | if (!rate) { | |
1052 | ret = -EINVAL; | |
1053 | goto err_clk_disable; | |
1054 | } | |
1055 | ||
1056 | /* We shall wait 2 input clks after register writes */ | |
1057 | if (cmt->info->model >= SH_CMT_48BIT) | |
1058 | cmt->reg_delay = DIV_ROUND_UP(2UL * USEC_PER_SEC, rate); | |
1059 | cmt->rate = rate / (cmt->info->width == 16 ? 512 : 8); | |
890f423b | 1060 | |
31e912f5 LP |
1061 | /* Map the memory resource(s). */ |
1062 | ret = sh_cmt_map_memory(cmt); | |
81b3b271 | 1063 | if (ret < 0) |
2a97d553 | 1064 | goto err_clk_disable; |
81b3b271 LP |
1065 | |
1066 | /* Allocate and setup the channels. */ | |
1768aa2f | 1067 | cmt->num_channels = hweight8(cmt->hw_channels); |
6396bb22 | 1068 | cmt->channels = kcalloc(cmt->num_channels, sizeof(*cmt->channels), |
81b3b271 | 1069 | GFP_KERNEL); |
f5ec9b19 LP |
1070 | if (cmt->channels == NULL) { |
1071 | ret = -ENOMEM; | |
81b3b271 | 1072 | goto err_unmap; |
f5ec9b19 LP |
1073 | } |
1074 | ||
31e912f5 LP |
1075 | /* |
1076 | * Use the first channel as a clock event device and the second channel | |
1077 | * as a clock source. If only one channel is available use it for both. | |
1078 | */ | |
1768aa2f | 1079 | for (i = 0, mask = cmt->hw_channels; i < cmt->num_channels; ++i) { |
31e912f5 LP |
1080 | unsigned int hwidx = ffs(mask) - 1; |
1081 | bool clocksource = i == 1 || cmt->num_channels == 1; | |
1082 | bool clockevent = i == 0; | |
1083 | ||
1084 | ret = sh_cmt_setup_channel(&cmt->channels[i], i, hwidx, | |
1085 | clockevent, clocksource, cmt); | |
81b3b271 LP |
1086 | if (ret < 0) |
1087 | goto err_unmap; | |
f5ec9b19 | 1088 | |
31e912f5 | 1089 | mask &= ~(1 << hwidx); |
81b3b271 | 1090 | } |
da64c2a8 | 1091 | |
2a97d553 GU |
1092 | clk_disable(cmt->clk); |
1093 | ||
2653caf4 | 1094 | platform_set_drvdata(pdev, cmt); |
adccc69e | 1095 | |
da64c2a8 | 1096 | return 0; |
81b3b271 LP |
1097 | |
1098 | err_unmap: | |
f5ec9b19 | 1099 | kfree(cmt->channels); |
31e912f5 | 1100 | iounmap(cmt->mapbase); |
2a97d553 GU |
1101 | err_clk_disable: |
1102 | clk_disable(cmt->clk); | |
81b3b271 | 1103 | err_clk_unprepare: |
2653caf4 | 1104 | clk_unprepare(cmt->clk); |
81b3b271 | 1105 | err_clk_put: |
2653caf4 | 1106 | clk_put(cmt->clk); |
3fb1b6ad MD |
1107 | return ret; |
1108 | } | |
1109 | ||
1850514b | 1110 | static int sh_cmt_probe(struct platform_device *pdev) |
3fb1b6ad | 1111 | { |
2653caf4 | 1112 | struct sh_cmt_device *cmt = platform_get_drvdata(pdev); |
3fb1b6ad MD |
1113 | int ret; |
1114 | ||
201e9109 | 1115 | if (!is_sh_early_platform_device(pdev)) { |
bad81383 RW |
1116 | pm_runtime_set_active(&pdev->dev); |
1117 | pm_runtime_enable(&pdev->dev); | |
9bb5ec88 | 1118 | } |
615a445f | 1119 | |
2653caf4 | 1120 | if (cmt) { |
214a607a | 1121 | dev_info(&pdev->dev, "kept as earlytimer\n"); |
bad81383 | 1122 | goto out; |
e475eedb MD |
1123 | } |
1124 | ||
b262bc74 | 1125 | cmt = kzalloc(sizeof(*cmt), GFP_KERNEL); |
0178f41d | 1126 | if (cmt == NULL) |
3fb1b6ad | 1127 | return -ENOMEM; |
3fb1b6ad | 1128 | |
2653caf4 | 1129 | ret = sh_cmt_setup(cmt, pdev); |
3fb1b6ad | 1130 | if (ret) { |
2653caf4 | 1131 | kfree(cmt); |
bad81383 RW |
1132 | pm_runtime_idle(&pdev->dev); |
1133 | return ret; | |
3fb1b6ad | 1134 | } |
201e9109 | 1135 | if (is_sh_early_platform_device(pdev)) |
bad81383 RW |
1136 | return 0; |
1137 | ||
1138 | out: | |
81b3b271 | 1139 | if (cmt->has_clockevent || cmt->has_clocksource) |
bad81383 RW |
1140 | pm_runtime_irq_safe(&pdev->dev); |
1141 | else | |
1142 | pm_runtime_idle(&pdev->dev); | |
1143 | ||
1144 | return 0; | |
3fb1b6ad MD |
1145 | } |
1146 | ||
3fb1b6ad MD |
1147 | static struct platform_driver sh_cmt_device_driver = { |
1148 | .probe = sh_cmt_probe, | |
3fb1b6ad MD |
1149 | .driver = { |
1150 | .name = "sh_cmt", | |
1768aa2f | 1151 | .of_match_table = of_match_ptr(sh_cmt_of_table), |
c3daa475 | 1152 | .suppress_bind_attrs = true, |
81b3b271 LP |
1153 | }, |
1154 | .id_table = sh_cmt_id_table, | |
3fb1b6ad MD |
1155 | }; |
1156 | ||
1157 | static int __init sh_cmt_init(void) | |
1158 | { | |
1159 | return platform_driver_register(&sh_cmt_device_driver); | |
1160 | } | |
1161 | ||
1162 | static void __exit sh_cmt_exit(void) | |
1163 | { | |
1164 | platform_driver_unregister(&sh_cmt_device_driver); | |
1165 | } | |
1166 | ||
507fd01d | 1167 | #ifdef CONFIG_SUPERH |
201e9109 | 1168 | sh_early_platform_init("earlytimer", &sh_cmt_device_driver); |
507fd01d BG |
1169 | #endif |
1170 | ||
e903a031 | 1171 | subsys_initcall(sh_cmt_init); |
3fb1b6ad MD |
1172 | module_exit(sh_cmt_exit); |
1173 | ||
1174 | MODULE_AUTHOR("Magnus Damm"); | |
1175 | MODULE_DESCRIPTION("SuperH CMT Timer Driver"); |