[linux-block.git] / drivers / clocksource / samsung_pwm_timer.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com/
 *
 * samsung - Common hr-timer support (s3c and s5p)
*/

#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/sched_clock.h>

#include <clocksource/samsung_pwm.h>


/*
 * Clocksource driver
 */

#define REG_TCFG0			0x00
#define REG_TCFG1			0x04
#define REG_TCON			0x08
#define REG_TINT_CSTAT			0x44

#define REG_TCNTB(chan)			(0x0c + 12 * (chan))
#define REG_TCMPB(chan)			(0x10 + 12 * (chan))

#define TCFG0_PRESCALER_MASK		0xff
#define TCFG0_PRESCALER1_SHIFT		8

#define TCFG1_SHIFT(x)	  		((x) * 4)
#define TCFG1_MUX_MASK	  		0xf

/*
 * Each channel occupies 4 bits in TCON register, but there is a gap of 4
 * bits (one channel) after channel 0, so channels have different numbering
 * when accessing TCON register.
 *
 * In addition, the location of autoreload bit for channel 4 (TCON channel 5)
 * in its set of bits is 2 as opposed to 3 for other channels.
 */
#define TCON_START(chan)		(1 << (4 * (chan) + 0))
#define TCON_MANUALUPDATE(chan)		(1 << (4 * (chan) + 1))
#define TCON_INVERT(chan)		(1 << (4 * (chan) + 2))
#define _TCON_AUTORELOAD(chan)		(1 << (4 * (chan) + 3))
#define _TCON_AUTORELOAD4(chan)		(1 << (4 * (chan) + 2))
#define TCON_AUTORELOAD(chan)		\
	((chan < 5) ? _TCON_AUTORELOAD(chan) : _TCON_AUTORELOAD4(chan))

DEFINE_SPINLOCK(samsung_pwm_lock);
EXPORT_SYMBOL(samsung_pwm_lock);

struct samsung_pwm_clocksource {
	void __iomem *base;
	void __iomem *source_reg;
	unsigned int irq[SAMSUNG_PWM_NUM];
	struct samsung_pwm_variant variant;

	struct clk *timerclk;

	unsigned int event_id;
	unsigned int source_id;
	unsigned int tcnt_max;
	unsigned int tscaler_div;
	unsigned int tdiv;

	unsigned long clock_count_per_tick;
};

static struct samsung_pwm_clocksource pwm;

static void samsung_timer_set_prescale(unsigned int channel, u16 prescale)
{
	unsigned long flags;
	u8 shift = 0;
	u32 reg;

	if (channel >= 2)
		shift = TCFG0_PRESCALER1_SHIFT;

	spin_lock_irqsave(&samsung_pwm_lock, flags);

	reg = readl(pwm.base + REG_TCFG0);
	reg &= ~(TCFG0_PRESCALER_MASK << shift);
	reg |= (prescale - 1) << shift;
	writel(reg, pwm.base + REG_TCFG0);

	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
}

static void samsung_timer_set_divisor(unsigned int channel, u8 divisor)
{
	u8 shift = TCFG1_SHIFT(channel);
	unsigned long flags;
	u32 reg;
	u8 bits;

	bits = (fls(divisor) - 1) - pwm.variant.div_base;

	spin_lock_irqsave(&samsung_pwm_lock, flags);

	reg = readl(pwm.base + REG_TCFG1);
	reg &= ~(TCFG1_MUX_MASK << shift);
	reg |= bits << shift;
	writel(reg, pwm.base + REG_TCFG1);

	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
}

static void samsung_time_stop(unsigned int channel)
{
	unsigned long tcon;
	unsigned long flags;

	if (channel > 0)
		++channel;

	spin_lock_irqsave(&samsung_pwm_lock, flags);

	tcon = readl_relaxed(pwm.base + REG_TCON);
	tcon &= ~TCON_START(channel);
	writel_relaxed(tcon, pwm.base + REG_TCON);

	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
}

static void samsung_time_setup(unsigned int channel, unsigned long tcnt)
{
	unsigned long tcon;
	unsigned long flags;
	unsigned int tcon_chan = channel;

	if (tcon_chan > 0)
		++tcon_chan;

	spin_lock_irqsave(&samsung_pwm_lock, flags);

	tcon = readl_relaxed(pwm.base + REG_TCON);

	tcon &= ~(TCON_START(tcon_chan) | TCON_AUTORELOAD(tcon_chan));
	tcon |= TCON_MANUALUPDATE(tcon_chan);

	writel_relaxed(tcnt, pwm.base + REG_TCNTB(channel));
	writel_relaxed(tcnt, pwm.base + REG_TCMPB(channel));
	writel_relaxed(tcon, pwm.base + REG_TCON);

	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
}

static void samsung_time_start(unsigned int channel, bool periodic)
{
	unsigned long tcon;
	unsigned long flags;

	if (channel > 0)
		++channel;

	spin_lock_irqsave(&samsung_pwm_lock, flags);

	tcon = readl_relaxed(pwm.base + REG_TCON);

	tcon &= ~TCON_MANUALUPDATE(channel);
	tcon |= TCON_START(channel);

	if (periodic)
		tcon |= TCON_AUTORELOAD(channel);
	else
		tcon &= ~TCON_AUTORELOAD(channel);

	writel_relaxed(tcon, pwm.base + REG_TCON);

	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
}

static int samsung_set_next_event(unsigned long cycles,
				struct clock_event_device *evt)
{
	/*
	 * This check is needed to account for internal rounding
	 * errors inside clockevents core, which might result in
	 * passing cycles = 0, which in turn would not generate any
	 * timer interrupt and hang the system.
	 *
	 * Another solution would be to set up the clockevent device
	 * with min_delta = 2, but this would unnecessarily increase
	 * the minimum sleep period.
	 */
	if (!cycles)
		cycles = 1;

	samsung_time_setup(pwm.event_id, cycles);
	samsung_time_start(pwm.event_id, false);

	return 0;
}

static int samsung_shutdown(struct clock_event_device *evt)
{
	samsung_time_stop(pwm.event_id);
	return 0;
}

static int samsung_set_periodic(struct clock_event_device *evt)
{
	samsung_time_stop(pwm.event_id);
	samsung_time_setup(pwm.event_id, pwm.clock_count_per_tick - 1);
	samsung_time_start(pwm.event_id, true);
	return 0;
}

static void samsung_clockevent_resume(struct clock_event_device *cev)
{
	samsung_timer_set_prescale(pwm.event_id, pwm.tscaler_div);
	samsung_timer_set_divisor(pwm.event_id, pwm.tdiv);

	if (pwm.variant.has_tint_cstat) {
		u32 mask = (1 << pwm.event_id);
		writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT);
	}
}

static struct clock_event_device time_event_device = {
	.name			= "samsung_event_timer",
	.features		= CLOCK_EVT_FEAT_PERIODIC |
				  CLOCK_EVT_FEAT_ONESHOT,
	.rating			= 200,
	.set_next_event		= samsung_set_next_event,
	.set_state_shutdown	= samsung_shutdown,
	.set_state_periodic	= samsung_set_periodic,
	.set_state_oneshot	= samsung_shutdown,
	.tick_resume		= samsung_shutdown,
	.resume			= samsung_clockevent_resume,
};

static irqreturn_t samsung_clock_event_isr(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;

	if (pwm.variant.has_tint_cstat) {
		u32 mask = (1 << pwm.event_id);
		writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT);
	}

	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static void __init samsung_clockevent_init(void)
{
	unsigned long pclk;
	unsigned long clock_rate;
	unsigned int irq_number;

	pclk = clk_get_rate(pwm.timerclk);

	samsung_timer_set_prescale(pwm.event_id, pwm.tscaler_div);
	samsung_timer_set_divisor(pwm.event_id, pwm.tdiv);

	clock_rate = pclk / (pwm.tscaler_div * pwm.tdiv);
	pwm.clock_count_per_tick = clock_rate / HZ;

	time_event_device.cpumask = cpumask_of(0);
	clockevents_config_and_register(&time_event_device,
						clock_rate, 1, pwm.tcnt_max);

	irq_number = pwm.irq[pwm.event_id];
	if (request_irq(irq_number, samsung_clock_event_isr,
			IRQF_TIMER | IRQF_IRQPOLL, "samsung_time_irq",
			&time_event_device))
		pr_err("%s: request_irq() failed\n", "samsung_time_irq");

	if (pwm.variant.has_tint_cstat) {
		u32 mask = (1 << pwm.event_id);
		writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT);
	}
}

static void samsung_clocksource_suspend(struct clocksource *cs)
{
	samsung_time_stop(pwm.source_id);
}

static void samsung_clocksource_resume(struct clocksource *cs)
{
	samsung_timer_set_prescale(pwm.source_id, pwm.tscaler_div);
	samsung_timer_set_divisor(pwm.source_id, pwm.tdiv);

	samsung_time_setup(pwm.source_id, pwm.tcnt_max);
	samsung_time_start(pwm.source_id, true);
}

static u64 notrace samsung_clocksource_read(struct clocksource *c)
{
	return ~readl_relaxed(pwm.source_reg);
}

static struct clocksource samsung_clocksource = {
	.name		= "samsung_clocksource_timer",
	.rating		= 250,
	.read		= samsung_clocksource_read,
	.suspend	= samsung_clocksource_suspend,
	.resume		= samsung_clocksource_resume,
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
};

/*
 * Override the global weak sched_clock symbol with this
 * local implementation which uses the clocksource to get some
 * better resolution when scheduling the kernel. We accept that
 * this wraps around for now, since it is just a relative time
 * stamp. (Inspired by U300 implementation.)
 */
static u64 notrace samsung_read_sched_clock(void)
{
	return samsung_clocksource_read(NULL);
}

static int __init samsung_clocksource_init(void)
{
	unsigned long pclk;
	unsigned long clock_rate;

	pclk = clk_get_rate(pwm.timerclk);

	samsung_timer_set_prescale(pwm.source_id, pwm.tscaler_div);
	samsung_timer_set_divisor(pwm.source_id, pwm.tdiv);

	clock_rate = pclk / (pwm.tscaler_div * pwm.tdiv);

	samsung_time_setup(pwm.source_id, pwm.tcnt_max);
	samsung_time_start(pwm.source_id, true);

	if (pwm.source_id == 4)
		pwm.source_reg = pwm.base + 0x40;
	else
		pwm.source_reg = pwm.base + pwm.source_id * 0x0c + 0x14;

	sched_clock_register(samsung_read_sched_clock,
						pwm.variant.bits, clock_rate);

	samsung_clocksource.mask = CLOCKSOURCE_MASK(pwm.variant.bits);
	return clocksource_register_hz(&samsung_clocksource, clock_rate);
}

static void __init samsung_timer_resources(void)
{
	clk_prepare_enable(pwm.timerclk);

	pwm.tcnt_max = (1UL << pwm.variant.bits) - 1;
	if (pwm.variant.bits == 16) {
		pwm.tscaler_div = 25;
		pwm.tdiv = 2;
	} else {
		pwm.tscaler_div = 2;
		pwm.tdiv = 1;
	}
}

/*
 * PWM master driver
 */
static int __init _samsung_pwm_clocksource_init(void)
{
	u8 mask;
	int channel;

	mask = ~pwm.variant.output_mask & ((1 << SAMSUNG_PWM_NUM) - 1);
	channel = fls(mask) - 1;
	if (channel < 0) {
		pr_crit("failed to find PWM channel for clocksource\n");
		return -EINVAL;
	}
	pwm.source_id = channel;

	mask &= ~(1 << channel);
	channel = fls(mask) - 1;
	if (channel < 0) {
		pr_crit("failed to find PWM channel for clock event\n");
		return -EINVAL;
	}
	pwm.event_id = channel;

	samsung_timer_resources();
	samsung_clockevent_init();

	return samsung_clocksource_init();
}

void __init samsung_pwm_clocksource_init(void __iomem *base,
			unsigned int *irqs, struct samsung_pwm_variant *variant)
{
	pwm.base = base;
	memcpy(&pwm.variant, variant, sizeof(pwm.variant));
	memcpy(pwm.irq, irqs, SAMSUNG_PWM_NUM * sizeof(*irqs));

	pwm.timerclk = clk_get(NULL, "timers");
	if (IS_ERR(pwm.timerclk))
		panic("failed to get timers clock for timer");

	_samsung_pwm_clocksource_init();
}

#ifdef CONFIG_TIMER_OF
static int __init samsung_pwm_alloc(struct device_node *np,
				    const struct samsung_pwm_variant *variant)
{
	struct property *prop;
	const __be32 *cur;
	u32 val;
	int i;

	memcpy(&pwm.variant, variant, sizeof(pwm.variant));
	for (i = 0; i < SAMSUNG_PWM_NUM; ++i)
		pwm.irq[i] = irq_of_parse_and_map(np, i);

	of_property_for_each_u32(np, "samsung,pwm-outputs", prop, cur, val) {
		if (val >= SAMSUNG_PWM_NUM) {
			pr_warn("%s: invalid channel index in samsung,pwm-outputs property\n", __func__);
			continue;
		}
		pwm.variant.output_mask |= 1 << val;
	}

	pwm.base = of_iomap(np, 0);
	if (!pwm.base) {
		pr_err("%s: failed to map PWM registers\n", __func__);
		return -ENXIO;
	}

	pwm.timerclk = of_clk_get_by_name(np, "timers");
	if (IS_ERR(pwm.timerclk)) {
		pr_crit("failed to get timers clock for timer\n");
		return PTR_ERR(pwm.timerclk);
	}

	return _samsung_pwm_clocksource_init();
}

static const struct samsung_pwm_variant s3c24xx_variant = {
	.bits		= 16,
	.div_base	= 1,
	.has_tint_cstat	= false,
	.tclk_mask	= (1 << 4),
};

static int __init s3c2410_pwm_clocksource_init(struct device_node *np)
{
	return samsung_pwm_alloc(np, &s3c24xx_variant);
}
TIMER_OF_DECLARE(s3c2410_pwm, "samsung,s3c2410-pwm", s3c2410_pwm_clocksource_init);

static const struct samsung_pwm_variant s3c64xx_variant = {
	.bits		= 32,
	.div_base	= 0,
	.has_tint_cstat	= true,
	.tclk_mask	= (1 << 7) | (1 << 6) | (1 << 5),
};

static int __init s3c64xx_pwm_clocksource_init(struct device_node *np)
{
	return samsung_pwm_alloc(np, &s3c64xx_variant);
}
TIMER_OF_DECLARE(s3c6400_pwm, "samsung,s3c6400-pwm", s3c64xx_pwm_clocksource_init);

static const struct samsung_pwm_variant s5p64x0_variant = {
	.bits		= 32,
	.div_base	= 0,
	.has_tint_cstat	= true,
	.tclk_mask	= 0,
};

static int __init s5p64x0_pwm_clocksource_init(struct device_node *np)
{
	return samsung_pwm_alloc(np, &s5p64x0_variant);
}
TIMER_OF_DECLARE(s5p6440_pwm, "samsung,s5p6440-pwm", s5p64x0_pwm_clocksource_init);

static const struct samsung_pwm_variant s5p_variant = {
	.bits		= 32,
	.div_base	= 0,
	.has_tint_cstat	= true,
	.tclk_mask	= (1 << 5),
};

static int __init s5p_pwm_clocksource_init(struct device_node *np)
{
	return samsung_pwm_alloc(np, &s5p_variant);
}
TIMER_OF_DECLARE(s5pc100_pwm, "samsung,s5pc100-pwm", s5p_pwm_clocksource_init);
#endif
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
f1189989 TF	2	/*
	3	* Copyright (c) 2011 Samsung Electronics Co., Ltd.
	4	* http://www.samsung.com/
	5	*
	6	* samsung - Common hr-timer support (s3c and s5p)
f1189989 TF	7	*/
	8
	9	#include <linux/interrupt.h>
	10	#include <linux/irq.h>
	11	#include <linux/err.h>
	12	#include <linux/clk.h>
	13	#include <linux/clockchips.h>
	14	#include <linux/list.h>
	15	#include <linux/module.h>
	16	#include <linux/of.h>
	17	#include <linux/of_address.h>
	18	#include <linux/of_irq.h>
	19	#include <linux/platform_device.h>
	20	#include <linux/slab.h>
38ff87f7	21	#include <linux/sched_clock.h>
f1189989 TF	22
	23	#include <clocksource/samsung_pwm.h>
	24
f1189989 TF	25
	26	/*
	27	* Clocksource driver
	28	*/
	29
	30	#define REG_TCFG0 0x00
	31	#define REG_TCFG1 0x04
	32	#define REG_TCON 0x08
	33	#define REG_TINT_CSTAT 0x44
	34
	35	#define REG_TCNTB(chan) (0x0c + 12 * (chan))
	36	#define REG_TCMPB(chan) (0x10 + 12 * (chan))
	37
	38	#define TCFG0_PRESCALER_MASK 0xff
	39	#define TCFG0_PRESCALER1_SHIFT 8
	40
	41	#define TCFG1_SHIFT(x) ((x) * 4)
	42	#define TCFG1_MUX_MASK 0xf
	43
ceea1241 TF	44	/*
	45	* Each channel occupies 4 bits in TCON register, but there is a gap of 4
	46	* bits (one channel) after channel 0, so channels have different numbering
	47	* when accessing TCON register.
	48	*
	49	* In addition, the location of autoreload bit for channel 4 (TCON channel 5)
	50	* in its set of bits is 2 as opposed to 3 for other channels.
	51	*/
f1189989 TF	52	#define TCON_START(chan) (1 << (4 * (chan) + 0))
	53	#define TCON_MANUALUPDATE(chan) (1 << (4 * (chan) + 1))
	54	#define TCON_INVERT(chan) (1 << (4 * (chan) + 2))
ceea1241 TF	55	#define _TCON_AUTORELOAD(chan) (1 << (4 * (chan) + 3))
	56	#define _TCON_AUTORELOAD4(chan) (1 << (4 * (chan) + 2))
	57	#define TCON_AUTORELOAD(chan) \
	58	((chan < 5) ? _TCON_AUTORELOAD(chan) : _TCON_AUTORELOAD4(chan))
f1189989	59
7aac482e TF	60	DEFINE_SPINLOCK(samsung_pwm_lock);
	61	EXPORT_SYMBOL(samsung_pwm_lock);
	62
030c2a1e TF	63	struct samsung_pwm_clocksource {
030c2a1e TF	64	void __iomem *base;
61d7e205	65	void __iomem *source_reg;
030c2a1e TF	66	unsigned int irq[SAMSUNG_PWM_NUM];
	67	struct samsung_pwm_variant variant;
	68
	69	struct clk *timerclk;
	70
f1189989 TF	71	unsigned int event_id;
	72	unsigned int source_id;
	73	unsigned int tcnt_max;
	74	unsigned int tscaler_div;
	75	unsigned int tdiv;
030c2a1e TF	76
030c2a1e TF	77	unsigned long clock_count_per_tick;
f1189989 TF	78	};
f1189989 TF	79
030c2a1e	80	static struct samsung_pwm_clocksource pwm;
f1189989	81
030c2a1e	82	static void samsung_timer_set_prescale(unsigned int channel, u16 prescale)
f1189989 TF	83	{
	84	unsigned long flags;
	85	u8 shift = 0;
	86	u32 reg;
	87
	88	if (channel >= 2)
	89	shift = TCFG0_PRESCALER1_SHIFT;
	90
7aac482e	91	spin_lock_irqsave(&samsung_pwm_lock, flags);
f1189989	92
030c2a1e	93	reg = readl(pwm.base + REG_TCFG0);
f1189989 TF	94	reg &= ~(TCFG0_PRESCALER_MASK << shift);
f1189989 TF	95	reg \|= (prescale - 1) << shift;
030c2a1e	96	writel(reg, pwm.base + REG_TCFG0);
f1189989	97
7aac482e	98	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
f1189989 TF	99	}
f1189989 TF	100
030c2a1e	101	static void samsung_timer_set_divisor(unsigned int channel, u8 divisor)
f1189989 TF	102	{
	103	u8 shift = TCFG1_SHIFT(channel);
	104	unsigned long flags;
	105	u32 reg;
	106	u8 bits;
	107
030c2a1e	108	bits = (fls(divisor) - 1) - pwm.variant.div_base;
f1189989	109
7aac482e	110	spin_lock_irqsave(&samsung_pwm_lock, flags);
f1189989	111
030c2a1e	112	reg = readl(pwm.base + REG_TCFG1);
f1189989 TF	113	reg &= ~(TCFG1_MUX_MASK << shift);
f1189989 TF	114	reg \|= bits << shift;
030c2a1e	115	writel(reg, pwm.base + REG_TCFG1);
f1189989	116
7aac482e	117	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
f1189989 TF	118	}
	119
	120	static void samsung_time_stop(unsigned int channel)
	121	{
	122	unsigned long tcon;
	123	unsigned long flags;
	124
	125	if (channel > 0)
	126	++channel;
	127
7aac482e	128	spin_lock_irqsave(&samsung_pwm_lock, flags);
f1189989	129
7cc06179	130	tcon = readl_relaxed(pwm.base + REG_TCON);
f1189989	131	tcon &= ~TCON_START(channel);
7cc06179	132	writel_relaxed(tcon, pwm.base + REG_TCON);
f1189989	133
7aac482e	134	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
f1189989 TF	135	}
	136
	137	static void samsung_time_setup(unsigned int channel, unsigned long tcnt)
	138	{
	139	unsigned long tcon;
	140	unsigned long flags;
	141	unsigned int tcon_chan = channel;
	142
	143	if (tcon_chan > 0)
	144	++tcon_chan;
	145
7aac482e	146	spin_lock_irqsave(&samsung_pwm_lock, flags);
f1189989	147
7cc06179	148	tcon = readl_relaxed(pwm.base + REG_TCON);
f1189989	149
f1189989 TF	150	tcon &= ~(TCON_START(tcon_chan) \| TCON_AUTORELOAD(tcon_chan));
	151	tcon \|= TCON_MANUALUPDATE(tcon_chan);
	152
7cc06179 ML	153	writel_relaxed(tcnt, pwm.base + REG_TCNTB(channel));
	154	writel_relaxed(tcnt, pwm.base + REG_TCMPB(channel));
	155	writel_relaxed(tcon, pwm.base + REG_TCON);
f1189989	156
7aac482e	157	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
f1189989 TF	158	}
	159
	160	static void samsung_time_start(unsigned int channel, bool periodic)
	161	{
	162	unsigned long tcon;
	163	unsigned long flags;
	164
	165	if (channel > 0)
	166	++channel;
	167
7aac482e	168	spin_lock_irqsave(&samsung_pwm_lock, flags);
f1189989	169
7cc06179	170	tcon = readl_relaxed(pwm.base + REG_TCON);
f1189989 TF	171
	172	tcon &= ~TCON_MANUALUPDATE(channel);
	173	tcon \|= TCON_START(channel);
	174
	175	if (periodic)
	176	tcon \|= TCON_AUTORELOAD(channel);
	177	else
	178	tcon &= ~TCON_AUTORELOAD(channel);
	179
7cc06179	180	writel_relaxed(tcon, pwm.base + REG_TCON);
f1189989	181
7aac482e	182	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
f1189989 TF	183	}
	184
	185	static int samsung_set_next_event(unsigned long cycles,
	186	struct clock_event_device *evt)
	187	{
81d4f7bf TF	188	/*
	189	* This check is needed to account for internal rounding
	190	* errors inside clockevents core, which might result in
	191	* passing cycles = 0, which in turn would not generate any
	192	* timer interrupt and hang the system.
	193	*
	194	* Another solution would be to set up the clockevent device
	195	* with min_delta = 2, but this would unnecessarily increase
	196	* the minimum sleep period.
	197	*/
	198	if (!cycles)
	199	cycles = 1;
	200
030c2a1e TF	201	samsung_time_setup(pwm.event_id, cycles);
030c2a1e TF	202	samsung_time_start(pwm.event_id, false);
f1189989 TF	203
	204	return 0;
	205	}
	206
b49b5704	207	static int samsung_shutdown(struct clock_event_device *evt)
f1189989	208	{
030c2a1e	209	samsung_time_stop(pwm.event_id);
b49b5704 VK	210	return 0;
b49b5704 VK	211	}
f1189989	212
b49b5704 VK	213	static int samsung_set_periodic(struct clock_event_device *evt)
	214	{
	215	samsung_time_stop(pwm.event_id);
	216	samsung_time_setup(pwm.event_id, pwm.clock_count_per_tick - 1);
	217	samsung_time_start(pwm.event_id, true);
	218	return 0;
f1189989 TF	219	}
f1189989 TF	220
0b96258b TF	221	static void samsung_clockevent_resume(struct clock_event_device *cev)
	222	{
	223	samsung_timer_set_prescale(pwm.event_id, pwm.tscaler_div);
	224	samsung_timer_set_divisor(pwm.event_id, pwm.tdiv);
	225
	226	if (pwm.variant.has_tint_cstat) {
	227	u32 mask = (1 << pwm.event_id);
	228	writel(mask \| (mask << 5), pwm.base + REG_TINT_CSTAT);
	229	}
	230	}
	231
f1189989	232	static struct clock_event_device time_event_device = {
b49b5704 VK	233	.name = "samsung_event_timer",
	234	.features = CLOCK_EVT_FEAT_PERIODIC \|
	235	CLOCK_EVT_FEAT_ONESHOT,
	236	.rating = 200,
	237	.set_next_event = samsung_set_next_event,
	238	.set_state_shutdown = samsung_shutdown,
	239	.set_state_periodic = samsung_set_periodic,
	240	.set_state_oneshot = samsung_shutdown,
	241	.tick_resume = samsung_shutdown,
	242	.resume = samsung_clockevent_resume,
f1189989 TF	243	};
	244
	245	static irqreturn_t samsung_clock_event_isr(int irq, void *dev_id)
	246	{
	247	struct clock_event_device *evt = dev_id;
	248
030c2a1e TF	249	if (pwm.variant.has_tint_cstat) {
	250	u32 mask = (1 << pwm.event_id);
	251	writel(mask \| (mask << 5), pwm.base + REG_TINT_CSTAT);
f1189989 TF	252	}
	253
	254	evt->event_handler(evt);
	255
	256	return IRQ_HANDLED;
	257	}
	258
f1189989 TF	259	static void __init samsung_clockevent_init(void)
	260	{
	261	unsigned long pclk;
	262	unsigned long clock_rate;
	263	unsigned int irq_number;
	264
030c2a1e	265	pclk = clk_get_rate(pwm.timerclk);
f1189989	266
030c2a1e TF	267	samsung_timer_set_prescale(pwm.event_id, pwm.tscaler_div);
030c2a1e TF	268	samsung_timer_set_divisor(pwm.event_id, pwm.tdiv);
f1189989	269
030c2a1e TF	270	clock_rate = pclk / (pwm.tscaler_div * pwm.tdiv);
030c2a1e TF	271	pwm.clock_count_per_tick = clock_rate / HZ;
f1189989 TF	272
f1189989 TF	273	time_event_device.cpumask = cpumask_of(0);
e9b852b8 TF	274	clockevents_config_and_register(&time_event_device,
e9b852b8 TF	275	clock_rate, 1, pwm.tcnt_max);
f1189989	276
030c2a1e	277	irq_number = pwm.irq[pwm.event_id];
cc2550b4	278	if (request_irq(irq_number, samsung_clock_event_isr,
	279	IRQF_TIMER \| IRQF_IRQPOLL, "samsung_time_irq",
	280	&time_event_device))
	281	pr_err("%s: request_irq() failed\n", "samsung_time_irq");
f1189989	282
030c2a1e TF	283	if (pwm.variant.has_tint_cstat) {
	284	u32 mask = (1 << pwm.event_id);
	285	writel(mask \| (mask << 5), pwm.base + REG_TINT_CSTAT);
f1189989 TF	286	}
	287	}
	288
0b96258b	289	static void samsung_clocksource_suspend(struct clocksource *cs)
f1189989	290	{
0b96258b	291	samsung_time_stop(pwm.source_id);
f1189989 TF	292	}
f1189989 TF	293
0b96258b TF	294	static void samsung_clocksource_resume(struct clocksource *cs)
	295	{
	296	samsung_timer_set_prescale(pwm.source_id, pwm.tscaler_div);
	297	samsung_timer_set_divisor(pwm.source_id, pwm.tdiv);
	298
	299	samsung_time_setup(pwm.source_id, pwm.tcnt_max);
	300	samsung_time_start(pwm.source_id, true);
	301	}
	302
a5a1d1c2	303	static u64 notrace samsung_clocksource_read(struct clocksource *c)
6792e636 TF	304	{
	305	return ~readl_relaxed(pwm.source_reg);
	306	}
	307
	308	static struct clocksource samsung_clocksource = {
	309	.name = "samsung_clocksource_timer",
	310	.rating = 250,
	311	.read = samsung_clocksource_read,
0b96258b TF	312	.suspend = samsung_clocksource_suspend,
0b96258b TF	313	.resume = samsung_clocksource_resume,
6792e636 TF	314	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	315	};
	316
f1189989 TF	317	/*
	318	* Override the global weak sched_clock symbol with this
	319	* local implementation which uses the clocksource to get some
	320	* better resolution when scheduling the kernel. We accept that
	321	* this wraps around for now, since it is just a relative time
	322	* stamp. (Inspired by U300 implementation.)
	323	*/
2902b30e	324	static u64 notrace samsung_read_sched_clock(void)
f1189989	325	{
6792e636	326	return samsung_clocksource_read(NULL);
f1189989 TF	327	}
f1189989 TF	328
0993f57b	329	static int __init samsung_clocksource_init(void)
f1189989	330	{
f1189989 TF	331	unsigned long pclk;
f1189989 TF	332	unsigned long clock_rate;
f1189989	333
030c2a1e	334	pclk = clk_get_rate(pwm.timerclk);
f1189989	335
030c2a1e TF	336	samsung_timer_set_prescale(pwm.source_id, pwm.tscaler_div);
030c2a1e TF	337	samsung_timer_set_divisor(pwm.source_id, pwm.tdiv);
f1189989	338
030c2a1e	339	clock_rate = pclk / (pwm.tscaler_div * pwm.tdiv);
f1189989	340
030c2a1e TF	341	samsung_time_setup(pwm.source_id, pwm.tcnt_max);
030c2a1e TF	342	samsung_time_start(pwm.source_id, true);
f1189989	343
61d7e205 TF	344	if (pwm.source_id == 4)
	345	pwm.source_reg = pwm.base + 0x40;
	346	else
	347	pwm.source_reg = pwm.base + pwm.source_id * 0x0c + 0x14;
	348
2902b30e	349	sched_clock_register(samsung_read_sched_clock,
030c2a1e	350	pwm.variant.bits, clock_rate);
f1189989	351
6792e636	352	samsung_clocksource.mask = CLOCKSOURCE_MASK(pwm.variant.bits);
0993f57b	353	return clocksource_register_hz(&samsung_clocksource, clock_rate);
f1189989 TF	354	}
	355
	356	static void __init samsung_timer_resources(void)
	357	{
030c2a1e	358	clk_prepare_enable(pwm.timerclk);
f1189989	359
030c2a1e TF	360	pwm.tcnt_max = (1UL << pwm.variant.bits) - 1;
	361	if (pwm.variant.bits == 16) {
	362	pwm.tscaler_div = 25;
	363	pwm.tdiv = 2;
f1189989	364	} else {
030c2a1e TF	365	pwm.tscaler_div = 2;
030c2a1e TF	366	pwm.tdiv = 1;
f1189989 TF	367	}
	368	}
	369
	370	/*
	371	* PWM master driver
	372	*/
0993f57b	373	static int __init _samsung_pwm_clocksource_init(void)
f1189989 TF	374	{
	375	u8 mask;
	376	int channel;
	377
030c2a1e	378	mask = ~pwm.variant.output_mask & ((1 << SAMSUNG_PWM_NUM) - 1);
f1189989	379	channel = fls(mask) - 1;
0993f57b	380	if (channel < 0) {
ac9ce6d1	381	pr_crit("failed to find PWM channel for clocksource\n");
0993f57b DL	382	return -EINVAL;
0993f57b DL	383	}
030c2a1e	384	pwm.source_id = channel;
f1189989 TF	385
	386	mask &= ~(1 << channel);
	387	channel = fls(mask) - 1;
0993f57b	388	if (channel < 0) {
ac9ce6d1	389	pr_crit("failed to find PWM channel for clock event\n");
0993f57b DL	390	return -EINVAL;
0993f57b DL	391	}
030c2a1e	392	pwm.event_id = channel;
f1189989 TF	393
	394	samsung_timer_resources();
	395	samsung_clockevent_init();
0993f57b DL	396
0993f57b DL	397	return samsung_clocksource_init();
f1189989 TF	398	}
f1189989 TF	399
f9bb48a2 TF	400	void __init samsung_pwm_clocksource_init(void __iomem *base,
	401	unsigned int irqs, struct samsung_pwm_variant variant)
	402	{
	403	pwm.base = base;
	404	memcpy(&pwm.variant, variant, sizeof(pwm.variant));
	405	memcpy(pwm.irq, irqs, SAMSUNG_PWM_NUM * sizeof(*irqs));
	406
a1fa6f50 TF	407	pwm.timerclk = clk_get(NULL, "timers");
	408	if (IS_ERR(pwm.timerclk))
	409	panic("failed to get timers clock for timer");
	410
f9bb48a2 TF	411	_samsung_pwm_clocksource_init();
	412	}
	413
bb0eb050	414	#ifdef CONFIG_TIMER_OF
0993f57b DL	415	static int __init samsung_pwm_alloc(struct device_node *np,
0993f57b DL	416	const struct samsung_pwm_variant *variant)
f1189989	417	{
f1189989 TF	418	struct property *prop;
	419	const __be32 *cur;
	420	u32 val;
	421	int i;
	422
030c2a1e	423	memcpy(&pwm.variant, variant, sizeof(pwm.variant));
f1189989	424	for (i = 0; i < SAMSUNG_PWM_NUM; ++i)
030c2a1e	425	pwm.irq[i] = irq_of_parse_and_map(np, i);
f1189989 TF	426
	427	of_property_for_each_u32(np, "samsung,pwm-outputs", prop, cur, val) {
	428	if (val >= SAMSUNG_PWM_NUM) {
43fc6b25	429	pr_warn("%s: invalid channel index in samsung,pwm-outputs property\n", __func__);
f1189989 TF	430	continue;
f1189989 TF	431	}
030c2a1e	432	pwm.variant.output_mask \|= 1 << val;
f1189989 TF	433	}
f1189989 TF	434
e2415489	435	pwm.base = of_iomap(np, 0);
030c2a1e	436	if (!pwm.base) {
f1189989	437	pr_err("%s: failed to map PWM registers\n", __func__);
0993f57b	438	return -ENXIO;
f1189989 TF	439	}
f1189989 TF	440
a1fa6f50	441	pwm.timerclk = of_clk_get_by_name(np, "timers");
0993f57b	442	if (IS_ERR(pwm.timerclk)) {
ac9ce6d1	443	pr_crit("failed to get timers clock for timer\n");
0993f57b DL	444	return PTR_ERR(pwm.timerclk);
0993f57b DL	445	}
a1fa6f50	446
0993f57b	447	return _samsung_pwm_clocksource_init();
f1189989 TF	448	}
	449
	450	static const struct samsung_pwm_variant s3c24xx_variant = {
	451	.bits = 16,
	452	.div_base = 1,
	453	.has_tint_cstat = false,
	454	.tclk_mask = (1 << 4),
	455	};
	456
0993f57b	457	static int __init s3c2410_pwm_clocksource_init(struct device_node *np)
f1189989	458	{
0993f57b	459	return samsung_pwm_alloc(np, &s3c24xx_variant);
f1189989	460	}
17273395	461	TIMER_OF_DECLARE(s3c2410_pwm, "samsung,s3c2410-pwm", s3c2410_pwm_clocksource_init);
f1189989 TF	462
	463	static const struct samsung_pwm_variant s3c64xx_variant = {
	464	.bits = 32,
	465	.div_base = 0,
	466	.has_tint_cstat = true,
	467	.tclk_mask = (1 << 7) \| (1 << 6) \| (1 << 5),
	468	};
	469
0993f57b	470	static int __init s3c64xx_pwm_clocksource_init(struct device_node *np)
f1189989	471	{
0993f57b	472	return samsung_pwm_alloc(np, &s3c64xx_variant);
f1189989	473	}
17273395	474	TIMER_OF_DECLARE(s3c6400_pwm, "samsung,s3c6400-pwm", s3c64xx_pwm_clocksource_init);
f1189989 TF	475
	476	static const struct samsung_pwm_variant s5p64x0_variant = {
	477	.bits = 32,
	478	.div_base = 0,
	479	.has_tint_cstat = true,
	480	.tclk_mask = 0,
	481	};
	482
0993f57b	483	static int __init s5p64x0_pwm_clocksource_init(struct device_node *np)
f1189989	484	{
0993f57b	485	return samsung_pwm_alloc(np, &s5p64x0_variant);
f1189989	486	}
17273395	487	TIMER_OF_DECLARE(s5p6440_pwm, "samsung,s5p6440-pwm", s5p64x0_pwm_clocksource_init);
f1189989 TF	488
	489	static const struct samsung_pwm_variant s5p_variant = {
	490	.bits = 32,
	491	.div_base = 0,
	492	.has_tint_cstat = true,
	493	.tclk_mask = (1 << 5),
	494	};
	495
0993f57b	496	static int __init s5p_pwm_clocksource_init(struct device_node *np)
f1189989	497	{
0993f57b	498	return samsung_pwm_alloc(np, &s5p_variant);
f1189989	499	}
17273395	500	TIMER_OF_DECLARE(s5pc100_pwm, "samsung,s5pc100-pwm", s5p_pwm_clocksource_init);
f9bb48a2	501	#endif