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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
f1189989 TF |
2 | /* |
3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | |
4 | * http://www.samsung.com/ | |
5 | * | |
6 | * samsung - Common hr-timer support (s3c and s5p) | |
f1189989 TF |
7 | */ |
8 | ||
9 | #include <linux/interrupt.h> | |
10 | #include <linux/irq.h> | |
11 | #include <linux/err.h> | |
12 | #include <linux/clk.h> | |
13 | #include <linux/clockchips.h> | |
14 | #include <linux/list.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/of.h> | |
17 | #include <linux/of_address.h> | |
18 | #include <linux/of_irq.h> | |
19 | #include <linux/platform_device.h> | |
20 | #include <linux/slab.h> | |
38ff87f7 | 21 | #include <linux/sched_clock.h> |
f1189989 TF |
22 | |
23 | #include <clocksource/samsung_pwm.h> | |
24 | ||
f1189989 TF |
25 | |
26 | /* | |
27 | * Clocksource driver | |
28 | */ | |
29 | ||
30 | #define REG_TCFG0 0x00 | |
31 | #define REG_TCFG1 0x04 | |
32 | #define REG_TCON 0x08 | |
33 | #define REG_TINT_CSTAT 0x44 | |
34 | ||
35 | #define REG_TCNTB(chan) (0x0c + 12 * (chan)) | |
36 | #define REG_TCMPB(chan) (0x10 + 12 * (chan)) | |
37 | ||
38 | #define TCFG0_PRESCALER_MASK 0xff | |
39 | #define TCFG0_PRESCALER1_SHIFT 8 | |
40 | ||
41 | #define TCFG1_SHIFT(x) ((x) * 4) | |
42 | #define TCFG1_MUX_MASK 0xf | |
43 | ||
ceea1241 TF |
44 | /* |
45 | * Each channel occupies 4 bits in TCON register, but there is a gap of 4 | |
46 | * bits (one channel) after channel 0, so channels have different numbering | |
47 | * when accessing TCON register. | |
48 | * | |
49 | * In addition, the location of autoreload bit for channel 4 (TCON channel 5) | |
50 | * in its set of bits is 2 as opposed to 3 for other channels. | |
51 | */ | |
f1189989 TF |
52 | #define TCON_START(chan) (1 << (4 * (chan) + 0)) |
53 | #define TCON_MANUALUPDATE(chan) (1 << (4 * (chan) + 1)) | |
54 | #define TCON_INVERT(chan) (1 << (4 * (chan) + 2)) | |
ceea1241 TF |
55 | #define _TCON_AUTORELOAD(chan) (1 << (4 * (chan) + 3)) |
56 | #define _TCON_AUTORELOAD4(chan) (1 << (4 * (chan) + 2)) | |
57 | #define TCON_AUTORELOAD(chan) \ | |
58 | ((chan < 5) ? _TCON_AUTORELOAD(chan) : _TCON_AUTORELOAD4(chan)) | |
f1189989 | 59 | |
7aac482e TF |
60 | DEFINE_SPINLOCK(samsung_pwm_lock); |
61 | EXPORT_SYMBOL(samsung_pwm_lock); | |
62 | ||
030c2a1e TF |
63 | struct samsung_pwm_clocksource { |
64 | void __iomem *base; | |
61d7e205 | 65 | void __iomem *source_reg; |
030c2a1e TF |
66 | unsigned int irq[SAMSUNG_PWM_NUM]; |
67 | struct samsung_pwm_variant variant; | |
68 | ||
69 | struct clk *timerclk; | |
70 | ||
f1189989 TF |
71 | unsigned int event_id; |
72 | unsigned int source_id; | |
73 | unsigned int tcnt_max; | |
74 | unsigned int tscaler_div; | |
75 | unsigned int tdiv; | |
030c2a1e TF |
76 | |
77 | unsigned long clock_count_per_tick; | |
f1189989 TF |
78 | }; |
79 | ||
030c2a1e | 80 | static struct samsung_pwm_clocksource pwm; |
f1189989 | 81 | |
030c2a1e | 82 | static void samsung_timer_set_prescale(unsigned int channel, u16 prescale) |
f1189989 TF |
83 | { |
84 | unsigned long flags; | |
85 | u8 shift = 0; | |
86 | u32 reg; | |
87 | ||
88 | if (channel >= 2) | |
89 | shift = TCFG0_PRESCALER1_SHIFT; | |
90 | ||
7aac482e | 91 | spin_lock_irqsave(&samsung_pwm_lock, flags); |
f1189989 | 92 | |
030c2a1e | 93 | reg = readl(pwm.base + REG_TCFG0); |
f1189989 TF |
94 | reg &= ~(TCFG0_PRESCALER_MASK << shift); |
95 | reg |= (prescale - 1) << shift; | |
030c2a1e | 96 | writel(reg, pwm.base + REG_TCFG0); |
f1189989 | 97 | |
7aac482e | 98 | spin_unlock_irqrestore(&samsung_pwm_lock, flags); |
f1189989 TF |
99 | } |
100 | ||
030c2a1e | 101 | static void samsung_timer_set_divisor(unsigned int channel, u8 divisor) |
f1189989 TF |
102 | { |
103 | u8 shift = TCFG1_SHIFT(channel); | |
104 | unsigned long flags; | |
105 | u32 reg; | |
106 | u8 bits; | |
107 | ||
030c2a1e | 108 | bits = (fls(divisor) - 1) - pwm.variant.div_base; |
f1189989 | 109 | |
7aac482e | 110 | spin_lock_irqsave(&samsung_pwm_lock, flags); |
f1189989 | 111 | |
030c2a1e | 112 | reg = readl(pwm.base + REG_TCFG1); |
f1189989 TF |
113 | reg &= ~(TCFG1_MUX_MASK << shift); |
114 | reg |= bits << shift; | |
030c2a1e | 115 | writel(reg, pwm.base + REG_TCFG1); |
f1189989 | 116 | |
7aac482e | 117 | spin_unlock_irqrestore(&samsung_pwm_lock, flags); |
f1189989 TF |
118 | } |
119 | ||
120 | static void samsung_time_stop(unsigned int channel) | |
121 | { | |
122 | unsigned long tcon; | |
123 | unsigned long flags; | |
124 | ||
125 | if (channel > 0) | |
126 | ++channel; | |
127 | ||
7aac482e | 128 | spin_lock_irqsave(&samsung_pwm_lock, flags); |
f1189989 | 129 | |
7cc06179 | 130 | tcon = readl_relaxed(pwm.base + REG_TCON); |
f1189989 | 131 | tcon &= ~TCON_START(channel); |
7cc06179 | 132 | writel_relaxed(tcon, pwm.base + REG_TCON); |
f1189989 | 133 | |
7aac482e | 134 | spin_unlock_irqrestore(&samsung_pwm_lock, flags); |
f1189989 TF |
135 | } |
136 | ||
137 | static void samsung_time_setup(unsigned int channel, unsigned long tcnt) | |
138 | { | |
139 | unsigned long tcon; | |
140 | unsigned long flags; | |
141 | unsigned int tcon_chan = channel; | |
142 | ||
143 | if (tcon_chan > 0) | |
144 | ++tcon_chan; | |
145 | ||
7aac482e | 146 | spin_lock_irqsave(&samsung_pwm_lock, flags); |
f1189989 | 147 | |
7cc06179 | 148 | tcon = readl_relaxed(pwm.base + REG_TCON); |
f1189989 | 149 | |
f1189989 TF |
150 | tcon &= ~(TCON_START(tcon_chan) | TCON_AUTORELOAD(tcon_chan)); |
151 | tcon |= TCON_MANUALUPDATE(tcon_chan); | |
152 | ||
7cc06179 ML |
153 | writel_relaxed(tcnt, pwm.base + REG_TCNTB(channel)); |
154 | writel_relaxed(tcnt, pwm.base + REG_TCMPB(channel)); | |
155 | writel_relaxed(tcon, pwm.base + REG_TCON); | |
f1189989 | 156 | |
7aac482e | 157 | spin_unlock_irqrestore(&samsung_pwm_lock, flags); |
f1189989 TF |
158 | } |
159 | ||
160 | static void samsung_time_start(unsigned int channel, bool periodic) | |
161 | { | |
162 | unsigned long tcon; | |
163 | unsigned long flags; | |
164 | ||
165 | if (channel > 0) | |
166 | ++channel; | |
167 | ||
7aac482e | 168 | spin_lock_irqsave(&samsung_pwm_lock, flags); |
f1189989 | 169 | |
7cc06179 | 170 | tcon = readl_relaxed(pwm.base + REG_TCON); |
f1189989 TF |
171 | |
172 | tcon &= ~TCON_MANUALUPDATE(channel); | |
173 | tcon |= TCON_START(channel); | |
174 | ||
175 | if (periodic) | |
176 | tcon |= TCON_AUTORELOAD(channel); | |
177 | else | |
178 | tcon &= ~TCON_AUTORELOAD(channel); | |
179 | ||
7cc06179 | 180 | writel_relaxed(tcon, pwm.base + REG_TCON); |
f1189989 | 181 | |
7aac482e | 182 | spin_unlock_irqrestore(&samsung_pwm_lock, flags); |
f1189989 TF |
183 | } |
184 | ||
185 | static int samsung_set_next_event(unsigned long cycles, | |
186 | struct clock_event_device *evt) | |
187 | { | |
81d4f7bf TF |
188 | /* |
189 | * This check is needed to account for internal rounding | |
190 | * errors inside clockevents core, which might result in | |
191 | * passing cycles = 0, which in turn would not generate any | |
192 | * timer interrupt and hang the system. | |
193 | * | |
194 | * Another solution would be to set up the clockevent device | |
195 | * with min_delta = 2, but this would unnecessarily increase | |
196 | * the minimum sleep period. | |
197 | */ | |
198 | if (!cycles) | |
199 | cycles = 1; | |
200 | ||
030c2a1e TF |
201 | samsung_time_setup(pwm.event_id, cycles); |
202 | samsung_time_start(pwm.event_id, false); | |
f1189989 TF |
203 | |
204 | return 0; | |
205 | } | |
206 | ||
b49b5704 | 207 | static int samsung_shutdown(struct clock_event_device *evt) |
f1189989 | 208 | { |
030c2a1e | 209 | samsung_time_stop(pwm.event_id); |
b49b5704 VK |
210 | return 0; |
211 | } | |
f1189989 | 212 | |
b49b5704 VK |
213 | static int samsung_set_periodic(struct clock_event_device *evt) |
214 | { | |
215 | samsung_time_stop(pwm.event_id); | |
216 | samsung_time_setup(pwm.event_id, pwm.clock_count_per_tick - 1); | |
217 | samsung_time_start(pwm.event_id, true); | |
218 | return 0; | |
f1189989 TF |
219 | } |
220 | ||
0b96258b TF |
221 | static void samsung_clockevent_resume(struct clock_event_device *cev) |
222 | { | |
223 | samsung_timer_set_prescale(pwm.event_id, pwm.tscaler_div); | |
224 | samsung_timer_set_divisor(pwm.event_id, pwm.tdiv); | |
225 | ||
226 | if (pwm.variant.has_tint_cstat) { | |
227 | u32 mask = (1 << pwm.event_id); | |
228 | writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT); | |
229 | } | |
230 | } | |
231 | ||
f1189989 | 232 | static struct clock_event_device time_event_device = { |
b49b5704 VK |
233 | .name = "samsung_event_timer", |
234 | .features = CLOCK_EVT_FEAT_PERIODIC | | |
235 | CLOCK_EVT_FEAT_ONESHOT, | |
236 | .rating = 200, | |
237 | .set_next_event = samsung_set_next_event, | |
238 | .set_state_shutdown = samsung_shutdown, | |
239 | .set_state_periodic = samsung_set_periodic, | |
240 | .set_state_oneshot = samsung_shutdown, | |
241 | .tick_resume = samsung_shutdown, | |
242 | .resume = samsung_clockevent_resume, | |
f1189989 TF |
243 | }; |
244 | ||
245 | static irqreturn_t samsung_clock_event_isr(int irq, void *dev_id) | |
246 | { | |
247 | struct clock_event_device *evt = dev_id; | |
248 | ||
030c2a1e TF |
249 | if (pwm.variant.has_tint_cstat) { |
250 | u32 mask = (1 << pwm.event_id); | |
251 | writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT); | |
f1189989 TF |
252 | } |
253 | ||
254 | evt->event_handler(evt); | |
255 | ||
256 | return IRQ_HANDLED; | |
257 | } | |
258 | ||
259 | static struct irqaction samsung_clock_event_irq = { | |
260 | .name = "samsung_time_irq", | |
38c30a84 | 261 | .flags = IRQF_TIMER | IRQF_IRQPOLL, |
f1189989 TF |
262 | .handler = samsung_clock_event_isr, |
263 | .dev_id = &time_event_device, | |
264 | }; | |
265 | ||
266 | static void __init samsung_clockevent_init(void) | |
267 | { | |
268 | unsigned long pclk; | |
269 | unsigned long clock_rate; | |
270 | unsigned int irq_number; | |
271 | ||
030c2a1e | 272 | pclk = clk_get_rate(pwm.timerclk); |
f1189989 | 273 | |
030c2a1e TF |
274 | samsung_timer_set_prescale(pwm.event_id, pwm.tscaler_div); |
275 | samsung_timer_set_divisor(pwm.event_id, pwm.tdiv); | |
f1189989 | 276 | |
030c2a1e TF |
277 | clock_rate = pclk / (pwm.tscaler_div * pwm.tdiv); |
278 | pwm.clock_count_per_tick = clock_rate / HZ; | |
f1189989 TF |
279 | |
280 | time_event_device.cpumask = cpumask_of(0); | |
e9b852b8 TF |
281 | clockevents_config_and_register(&time_event_device, |
282 | clock_rate, 1, pwm.tcnt_max); | |
f1189989 | 283 | |
030c2a1e | 284 | irq_number = pwm.irq[pwm.event_id]; |
f1189989 TF |
285 | setup_irq(irq_number, &samsung_clock_event_irq); |
286 | ||
030c2a1e TF |
287 | if (pwm.variant.has_tint_cstat) { |
288 | u32 mask = (1 << pwm.event_id); | |
289 | writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT); | |
f1189989 TF |
290 | } |
291 | } | |
292 | ||
0b96258b | 293 | static void samsung_clocksource_suspend(struct clocksource *cs) |
f1189989 | 294 | { |
0b96258b | 295 | samsung_time_stop(pwm.source_id); |
f1189989 TF |
296 | } |
297 | ||
0b96258b TF |
298 | static void samsung_clocksource_resume(struct clocksource *cs) |
299 | { | |
300 | samsung_timer_set_prescale(pwm.source_id, pwm.tscaler_div); | |
301 | samsung_timer_set_divisor(pwm.source_id, pwm.tdiv); | |
302 | ||
303 | samsung_time_setup(pwm.source_id, pwm.tcnt_max); | |
304 | samsung_time_start(pwm.source_id, true); | |
305 | } | |
306 | ||
a5a1d1c2 | 307 | static u64 notrace samsung_clocksource_read(struct clocksource *c) |
6792e636 TF |
308 | { |
309 | return ~readl_relaxed(pwm.source_reg); | |
310 | } | |
311 | ||
312 | static struct clocksource samsung_clocksource = { | |
313 | .name = "samsung_clocksource_timer", | |
314 | .rating = 250, | |
315 | .read = samsung_clocksource_read, | |
0b96258b TF |
316 | .suspend = samsung_clocksource_suspend, |
317 | .resume = samsung_clocksource_resume, | |
6792e636 TF |
318 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
319 | }; | |
320 | ||
f1189989 TF |
321 | /* |
322 | * Override the global weak sched_clock symbol with this | |
323 | * local implementation which uses the clocksource to get some | |
324 | * better resolution when scheduling the kernel. We accept that | |
325 | * this wraps around for now, since it is just a relative time | |
326 | * stamp. (Inspired by U300 implementation.) | |
327 | */ | |
2902b30e | 328 | static u64 notrace samsung_read_sched_clock(void) |
f1189989 | 329 | { |
6792e636 | 330 | return samsung_clocksource_read(NULL); |
f1189989 TF |
331 | } |
332 | ||
0993f57b | 333 | static int __init samsung_clocksource_init(void) |
f1189989 | 334 | { |
f1189989 TF |
335 | unsigned long pclk; |
336 | unsigned long clock_rate; | |
f1189989 | 337 | |
030c2a1e | 338 | pclk = clk_get_rate(pwm.timerclk); |
f1189989 | 339 | |
030c2a1e TF |
340 | samsung_timer_set_prescale(pwm.source_id, pwm.tscaler_div); |
341 | samsung_timer_set_divisor(pwm.source_id, pwm.tdiv); | |
f1189989 | 342 | |
030c2a1e | 343 | clock_rate = pclk / (pwm.tscaler_div * pwm.tdiv); |
f1189989 | 344 | |
030c2a1e TF |
345 | samsung_time_setup(pwm.source_id, pwm.tcnt_max); |
346 | samsung_time_start(pwm.source_id, true); | |
f1189989 | 347 | |
61d7e205 TF |
348 | if (pwm.source_id == 4) |
349 | pwm.source_reg = pwm.base + 0x40; | |
350 | else | |
351 | pwm.source_reg = pwm.base + pwm.source_id * 0x0c + 0x14; | |
352 | ||
2902b30e | 353 | sched_clock_register(samsung_read_sched_clock, |
030c2a1e | 354 | pwm.variant.bits, clock_rate); |
f1189989 | 355 | |
6792e636 | 356 | samsung_clocksource.mask = CLOCKSOURCE_MASK(pwm.variant.bits); |
0993f57b | 357 | return clocksource_register_hz(&samsung_clocksource, clock_rate); |
f1189989 TF |
358 | } |
359 | ||
360 | static void __init samsung_timer_resources(void) | |
361 | { | |
030c2a1e | 362 | clk_prepare_enable(pwm.timerclk); |
f1189989 | 363 | |
030c2a1e TF |
364 | pwm.tcnt_max = (1UL << pwm.variant.bits) - 1; |
365 | if (pwm.variant.bits == 16) { | |
366 | pwm.tscaler_div = 25; | |
367 | pwm.tdiv = 2; | |
f1189989 | 368 | } else { |
030c2a1e TF |
369 | pwm.tscaler_div = 2; |
370 | pwm.tdiv = 1; | |
f1189989 TF |
371 | } |
372 | } | |
373 | ||
374 | /* | |
375 | * PWM master driver | |
376 | */ | |
0993f57b | 377 | static int __init _samsung_pwm_clocksource_init(void) |
f1189989 TF |
378 | { |
379 | u8 mask; | |
380 | int channel; | |
381 | ||
030c2a1e | 382 | mask = ~pwm.variant.output_mask & ((1 << SAMSUNG_PWM_NUM) - 1); |
f1189989 | 383 | channel = fls(mask) - 1; |
0993f57b | 384 | if (channel < 0) { |
ac9ce6d1 | 385 | pr_crit("failed to find PWM channel for clocksource\n"); |
0993f57b DL |
386 | return -EINVAL; |
387 | } | |
030c2a1e | 388 | pwm.source_id = channel; |
f1189989 TF |
389 | |
390 | mask &= ~(1 << channel); | |
391 | channel = fls(mask) - 1; | |
0993f57b | 392 | if (channel < 0) { |
ac9ce6d1 | 393 | pr_crit("failed to find PWM channel for clock event\n"); |
0993f57b DL |
394 | return -EINVAL; |
395 | } | |
030c2a1e | 396 | pwm.event_id = channel; |
f1189989 TF |
397 | |
398 | samsung_timer_resources(); | |
399 | samsung_clockevent_init(); | |
0993f57b DL |
400 | |
401 | return samsung_clocksource_init(); | |
f1189989 TF |
402 | } |
403 | ||
f9bb48a2 TF |
404 | void __init samsung_pwm_clocksource_init(void __iomem *base, |
405 | unsigned int *irqs, struct samsung_pwm_variant *variant) | |
406 | { | |
407 | pwm.base = base; | |
408 | memcpy(&pwm.variant, variant, sizeof(pwm.variant)); | |
409 | memcpy(pwm.irq, irqs, SAMSUNG_PWM_NUM * sizeof(*irqs)); | |
410 | ||
a1fa6f50 TF |
411 | pwm.timerclk = clk_get(NULL, "timers"); |
412 | if (IS_ERR(pwm.timerclk)) | |
413 | panic("failed to get timers clock for timer"); | |
414 | ||
f9bb48a2 TF |
415 | _samsung_pwm_clocksource_init(); |
416 | } | |
417 | ||
bb0eb050 | 418 | #ifdef CONFIG_TIMER_OF |
0993f57b DL |
419 | static int __init samsung_pwm_alloc(struct device_node *np, |
420 | const struct samsung_pwm_variant *variant) | |
f1189989 | 421 | { |
f1189989 TF |
422 | struct property *prop; |
423 | const __be32 *cur; | |
424 | u32 val; | |
425 | int i; | |
426 | ||
030c2a1e | 427 | memcpy(&pwm.variant, variant, sizeof(pwm.variant)); |
f1189989 | 428 | for (i = 0; i < SAMSUNG_PWM_NUM; ++i) |
030c2a1e | 429 | pwm.irq[i] = irq_of_parse_and_map(np, i); |
f1189989 TF |
430 | |
431 | of_property_for_each_u32(np, "samsung,pwm-outputs", prop, cur, val) { | |
432 | if (val >= SAMSUNG_PWM_NUM) { | |
433 | pr_warning("%s: invalid channel index in samsung,pwm-outputs property\n", | |
434 | __func__); | |
435 | continue; | |
436 | } | |
030c2a1e | 437 | pwm.variant.output_mask |= 1 << val; |
f1189989 TF |
438 | } |
439 | ||
e2415489 | 440 | pwm.base = of_iomap(np, 0); |
030c2a1e | 441 | if (!pwm.base) { |
f1189989 | 442 | pr_err("%s: failed to map PWM registers\n", __func__); |
0993f57b | 443 | return -ENXIO; |
f1189989 TF |
444 | } |
445 | ||
a1fa6f50 | 446 | pwm.timerclk = of_clk_get_by_name(np, "timers"); |
0993f57b | 447 | if (IS_ERR(pwm.timerclk)) { |
ac9ce6d1 | 448 | pr_crit("failed to get timers clock for timer\n"); |
0993f57b DL |
449 | return PTR_ERR(pwm.timerclk); |
450 | } | |
a1fa6f50 | 451 | |
0993f57b | 452 | return _samsung_pwm_clocksource_init(); |
f1189989 TF |
453 | } |
454 | ||
455 | static const struct samsung_pwm_variant s3c24xx_variant = { | |
456 | .bits = 16, | |
457 | .div_base = 1, | |
458 | .has_tint_cstat = false, | |
459 | .tclk_mask = (1 << 4), | |
460 | }; | |
461 | ||
0993f57b | 462 | static int __init s3c2410_pwm_clocksource_init(struct device_node *np) |
f1189989 | 463 | { |
0993f57b | 464 | return samsung_pwm_alloc(np, &s3c24xx_variant); |
f1189989 | 465 | } |
17273395 | 466 | TIMER_OF_DECLARE(s3c2410_pwm, "samsung,s3c2410-pwm", s3c2410_pwm_clocksource_init); |
f1189989 TF |
467 | |
468 | static const struct samsung_pwm_variant s3c64xx_variant = { | |
469 | .bits = 32, | |
470 | .div_base = 0, | |
471 | .has_tint_cstat = true, | |
472 | .tclk_mask = (1 << 7) | (1 << 6) | (1 << 5), | |
473 | }; | |
474 | ||
0993f57b | 475 | static int __init s3c64xx_pwm_clocksource_init(struct device_node *np) |
f1189989 | 476 | { |
0993f57b | 477 | return samsung_pwm_alloc(np, &s3c64xx_variant); |
f1189989 | 478 | } |
17273395 | 479 | TIMER_OF_DECLARE(s3c6400_pwm, "samsung,s3c6400-pwm", s3c64xx_pwm_clocksource_init); |
f1189989 TF |
480 | |
481 | static const struct samsung_pwm_variant s5p64x0_variant = { | |
482 | .bits = 32, | |
483 | .div_base = 0, | |
484 | .has_tint_cstat = true, | |
485 | .tclk_mask = 0, | |
486 | }; | |
487 | ||
0993f57b | 488 | static int __init s5p64x0_pwm_clocksource_init(struct device_node *np) |
f1189989 | 489 | { |
0993f57b | 490 | return samsung_pwm_alloc(np, &s5p64x0_variant); |
f1189989 | 491 | } |
17273395 | 492 | TIMER_OF_DECLARE(s5p6440_pwm, "samsung,s5p6440-pwm", s5p64x0_pwm_clocksource_init); |
f1189989 TF |
493 | |
494 | static const struct samsung_pwm_variant s5p_variant = { | |
495 | .bits = 32, | |
496 | .div_base = 0, | |
497 | .has_tint_cstat = true, | |
498 | .tclk_mask = (1 << 5), | |
499 | }; | |
500 | ||
0993f57b | 501 | static int __init s5p_pwm_clocksource_init(struct device_node *np) |
f1189989 | 502 | { |
0993f57b | 503 | return samsung_pwm_alloc(np, &s5p_variant); |
f1189989 | 504 | } |
17273395 | 505 | TIMER_OF_DECLARE(s5pc100_pwm, "samsung,s5pc100-pwm", s5p_pwm_clocksource_init); |
f9bb48a2 | 506 | #endif |