[linux-2.6-block.git] / drivers / clocksource / samsung_pwm_timer.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com/
 *
 * samsung - Common hr-timer support (s3c and s5p)
 */

#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/sched_clock.h>

#include <clocksource/samsung_pwm.h>

/*
 * Clocksource driver
 */

#define REG_TCFG0			0x00
#define REG_TCFG1			0x04
#define REG_TCON			0x08
#define REG_TINT_CSTAT			0x44

#define REG_TCNTB(chan)			(0x0c + 12 * (chan))
#define REG_TCMPB(chan)			(0x10 + 12 * (chan))

#define TCFG0_PRESCALER_MASK		0xff
#define TCFG0_PRESCALER1_SHIFT		8

#define TCFG1_SHIFT(x)			((x) * 4)
#define TCFG1_MUX_MASK			0xf

/*
 * Each channel occupies 4 bits in TCON register, but there is a gap of 4
 * bits (one channel) after channel 0, so channels have different numbering
 * when accessing TCON register.
 *
 * In addition, the location of autoreload bit for channel 4 (TCON channel 5)
 * in its set of bits is 2 as opposed to 3 for other channels.
 */
#define TCON_START(chan)		(1 << (4 * (chan) + 0))
#define TCON_MANUALUPDATE(chan)		(1 << (4 * (chan) + 1))
#define TCON_INVERT(chan)		(1 << (4 * (chan) + 2))
#define _TCON_AUTORELOAD(chan)		(1 << (4 * (chan) + 3))
#define _TCON_AUTORELOAD4(chan)		(1 << (4 * (chan) + 2))
#define TCON_AUTORELOAD(chan)		\
	((chan < 5) ? _TCON_AUTORELOAD(chan) : _TCON_AUTORELOAD4(chan))

DEFINE_SPINLOCK(samsung_pwm_lock);
EXPORT_SYMBOL(samsung_pwm_lock);

struct samsung_pwm_clocksource {
	void __iomem *base;
	const void __iomem *source_reg;
	unsigned int irq[SAMSUNG_PWM_NUM];
	struct samsung_pwm_variant variant;

	struct clk *timerclk;

	unsigned int event_id;
	unsigned int source_id;
	unsigned int tcnt_max;
	unsigned int tscaler_div;
	unsigned int tdiv;

	unsigned long clock_count_per_tick;
};

static struct samsung_pwm_clocksource pwm;

static void samsung_timer_set_prescale(unsigned int channel, u16 prescale)
{
	unsigned long flags;
	u8 shift = 0;
	u32 reg;

	if (channel >= 2)
		shift = TCFG0_PRESCALER1_SHIFT;

	spin_lock_irqsave(&samsung_pwm_lock, flags);

	reg = readl(pwm.base + REG_TCFG0);
	reg &= ~(TCFG0_PRESCALER_MASK << shift);
	reg |= (prescale - 1) << shift;
	writel(reg, pwm.base + REG_TCFG0);

	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
}

static void samsung_timer_set_divisor(unsigned int channel, u8 divisor)
{
	u8 shift = TCFG1_SHIFT(channel);
	unsigned long flags;
	u32 reg;
	u8 bits;

	bits = (fls(divisor) - 1) - pwm.variant.div_base;

	spin_lock_irqsave(&samsung_pwm_lock, flags);

	reg = readl(pwm.base + REG_TCFG1);
	reg &= ~(TCFG1_MUX_MASK << shift);
	reg |= bits << shift;
	writel(reg, pwm.base + REG_TCFG1);

	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
}

static void samsung_time_stop(unsigned int channel)
{
	unsigned long tcon;
	unsigned long flags;

	if (channel > 0)
		++channel;

	spin_lock_irqsave(&samsung_pwm_lock, flags);

	tcon = readl_relaxed(pwm.base + REG_TCON);
	tcon &= ~TCON_START(channel);
	writel_relaxed(tcon, pwm.base + REG_TCON);

	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
}

static void samsung_time_setup(unsigned int channel, unsigned long tcnt)
{
	unsigned long tcon;
	unsigned long flags;
	unsigned int tcon_chan = channel;

	if (tcon_chan > 0)
		++tcon_chan;

	spin_lock_irqsave(&samsung_pwm_lock, flags);

	tcon = readl_relaxed(pwm.base + REG_TCON);

	tcon &= ~(TCON_START(tcon_chan) | TCON_AUTORELOAD(tcon_chan));
	tcon |= TCON_MANUALUPDATE(tcon_chan);

	writel_relaxed(tcnt, pwm.base + REG_TCNTB(channel));
	writel_relaxed(tcnt, pwm.base + REG_TCMPB(channel));
	writel_relaxed(tcon, pwm.base + REG_TCON);

	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
}

static void samsung_time_start(unsigned int channel, bool periodic)
{
	unsigned long tcon;
	unsigned long flags;

	if (channel > 0)
		++channel;

	spin_lock_irqsave(&samsung_pwm_lock, flags);

	tcon = readl_relaxed(pwm.base + REG_TCON);

	tcon &= ~TCON_MANUALUPDATE(channel);
	tcon |= TCON_START(channel);

	if (periodic)
		tcon |= TCON_AUTORELOAD(channel);
	else
		tcon &= ~TCON_AUTORELOAD(channel);

	writel_relaxed(tcon, pwm.base + REG_TCON);

	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
}

static int samsung_set_next_event(unsigned long cycles,
				  struct clock_event_device *evt)
{
	/*
	 * This check is needed to account for internal rounding
	 * errors inside clockevents core, which might result in
	 * passing cycles = 0, which in turn would not generate any
	 * timer interrupt and hang the system.
	 *
	 * Another solution would be to set up the clockevent device
	 * with min_delta = 2, but this would unnecessarily increase
	 * the minimum sleep period.
	 */
	if (!cycles)
		cycles = 1;

	samsung_time_setup(pwm.event_id, cycles);
	samsung_time_start(pwm.event_id, false);

	return 0;
}

static int samsung_shutdown(struct clock_event_device *evt)
{
	samsung_time_stop(pwm.event_id);
	return 0;
}

static int samsung_set_periodic(struct clock_event_device *evt)
{
	samsung_time_stop(pwm.event_id);
	samsung_time_setup(pwm.event_id, pwm.clock_count_per_tick - 1);
	samsung_time_start(pwm.event_id, true);
	return 0;
}

static void samsung_clockevent_resume(struct clock_event_device *cev)
{
	samsung_timer_set_prescale(pwm.event_id, pwm.tscaler_div);
	samsung_timer_set_divisor(pwm.event_id, pwm.tdiv);

	if (pwm.variant.has_tint_cstat) {
		u32 mask = (1 << pwm.event_id);

		writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT);
	}
}

static struct clock_event_device time_event_device = {
	.name			= "samsung_event_timer",
	.features		= CLOCK_EVT_FEAT_PERIODIC |
				  CLOCK_EVT_FEAT_ONESHOT,
	.rating			= 200,
	.set_next_event		= samsung_set_next_event,
	.set_state_shutdown	= samsung_shutdown,
	.set_state_periodic	= samsung_set_periodic,
	.set_state_oneshot	= samsung_shutdown,
	.tick_resume		= samsung_shutdown,
	.resume			= samsung_clockevent_resume,
};

static irqreturn_t samsung_clock_event_isr(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;

	if (pwm.variant.has_tint_cstat) {
		u32 mask = (1 << pwm.event_id);

		writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT);
	}

	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static void __init samsung_clockevent_init(void)
{
	unsigned long pclk;
	unsigned long clock_rate;
	unsigned int irq_number;

	pclk = clk_get_rate(pwm.timerclk);

	samsung_timer_set_prescale(pwm.event_id, pwm.tscaler_div);
	samsung_timer_set_divisor(pwm.event_id, pwm.tdiv);

	clock_rate = pclk / (pwm.tscaler_div * pwm.tdiv);
	pwm.clock_count_per_tick = clock_rate / HZ;

	time_event_device.cpumask = cpumask_of(0);
	clockevents_config_and_register(&time_event_device,
					clock_rate, 1, pwm.tcnt_max);

	irq_number = pwm.irq[pwm.event_id];
	if (request_irq(irq_number, samsung_clock_event_isr,
			IRQF_TIMER | IRQF_IRQPOLL, "samsung_time_irq",
			&time_event_device))
		pr_err("%s: request_irq() failed\n", "samsung_time_irq");

	if (pwm.variant.has_tint_cstat) {
		u32 mask = (1 << pwm.event_id);

		writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT);
	}
}

static void samsung_clocksource_suspend(struct clocksource *cs)
{
	samsung_time_stop(pwm.source_id);
}

static void samsung_clocksource_resume(struct clocksource *cs)
{
	samsung_timer_set_prescale(pwm.source_id, pwm.tscaler_div);
	samsung_timer_set_divisor(pwm.source_id, pwm.tdiv);

	samsung_time_setup(pwm.source_id, pwm.tcnt_max);
	samsung_time_start(pwm.source_id, true);
}

static u64 notrace samsung_clocksource_read(struct clocksource *c)
{
	return ~readl_relaxed(pwm.source_reg);
}

static struct clocksource samsung_clocksource = {
	.name		= "samsung_clocksource_timer",
	.rating		= 250,
	.read		= samsung_clocksource_read,
	.suspend	= samsung_clocksource_suspend,
	.resume		= samsung_clocksource_resume,
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
};

/*
 * Override the global weak sched_clock symbol with this
 * local implementation which uses the clocksource to get some
 * better resolution when scheduling the kernel. We accept that
 * this wraps around for now, since it is just a relative time
 * stamp. (Inspired by U300 implementation.)
 */
static u64 notrace samsung_read_sched_clock(void)
{
	return samsung_clocksource_read(NULL);
}

static int __init samsung_clocksource_init(void)
{
	unsigned long pclk;
	unsigned long clock_rate;

	pclk = clk_get_rate(pwm.timerclk);

	samsung_timer_set_prescale(pwm.source_id, pwm.tscaler_div);
	samsung_timer_set_divisor(pwm.source_id, pwm.tdiv);

	clock_rate = pclk / (pwm.tscaler_div * pwm.tdiv);

	samsung_time_setup(pwm.source_id, pwm.tcnt_max);
	samsung_time_start(pwm.source_id, true);

	if (pwm.source_id == 4)
		pwm.source_reg = pwm.base + 0x40;
	else
		pwm.source_reg = pwm.base + pwm.source_id * 0x0c + 0x14;

	sched_clock_register(samsung_read_sched_clock,
			     pwm.variant.bits, clock_rate);

	samsung_clocksource.mask = CLOCKSOURCE_MASK(pwm.variant.bits);
	return clocksource_register_hz(&samsung_clocksource, clock_rate);
}

static void __init samsung_timer_resources(void)
{
	clk_prepare_enable(pwm.timerclk);

	pwm.tcnt_max = (1UL << pwm.variant.bits) - 1;
	if (pwm.variant.bits == 16) {
		pwm.tscaler_div = 25;
		pwm.tdiv = 2;
	} else {
		pwm.tscaler_div = 2;
		pwm.tdiv = 1;
	}
}

/*
 * PWM master driver
 */
static int __init _samsung_pwm_clocksource_init(void)
{
	u8 mask;
	int channel;

	mask = ~pwm.variant.output_mask & ((1 << SAMSUNG_PWM_NUM) - 1);
	channel = fls(mask) - 1;
	if (channel < 0) {
		pr_crit("failed to find PWM channel for clocksource\n");
		return -EINVAL;
	}
	pwm.source_id = channel;

	mask &= ~(1 << channel);
	channel = fls(mask) - 1;
	if (channel < 0) {
		pr_crit("failed to find PWM channel for clock event\n");
		return -EINVAL;
	}
	pwm.event_id = channel;

	samsung_timer_resources();
	samsung_clockevent_init();

	return samsung_clocksource_init();
}

void __init samsung_pwm_clocksource_init(void __iomem *base,
					 unsigned int *irqs,
					 const struct samsung_pwm_variant *variant)
{
	pwm.base = base;
	memcpy(&pwm.variant, variant, sizeof(pwm.variant));
	memcpy(pwm.irq, irqs, SAMSUNG_PWM_NUM * sizeof(*irqs));

	pwm.timerclk = clk_get(NULL, "timers");
	if (IS_ERR(pwm.timerclk))
		panic("failed to get timers clock for timer");

	_samsung_pwm_clocksource_init();
}

#ifdef CONFIG_TIMER_OF
static int __init samsung_pwm_alloc(struct device_node *np,
				    const struct samsung_pwm_variant *variant)
{
	struct property *prop;
	const __be32 *cur;
	u32 val;
	int i, ret;

	memcpy(&pwm.variant, variant, sizeof(pwm.variant));
	for (i = 0; i < SAMSUNG_PWM_NUM; ++i)
		pwm.irq[i] = irq_of_parse_and_map(np, i);

	of_property_for_each_u32(np, "samsung,pwm-outputs", prop, cur, val) {
		if (val >= SAMSUNG_PWM_NUM) {
			pr_warn("%s: invalid channel index in samsung,pwm-outputs property\n", __func__);
			continue;
		}
		pwm.variant.output_mask |= 1 << val;
	}

	pwm.base = of_iomap(np, 0);
	if (!pwm.base) {
		pr_err("%s: failed to map PWM registers\n", __func__);
		return -ENXIO;
	}

	pwm.timerclk = of_clk_get_by_name(np, "timers");
	if (IS_ERR(pwm.timerclk)) {
		pr_crit("failed to get timers clock for timer\n");
		ret = PTR_ERR(pwm.timerclk);
		goto err_clk;
	}

	ret = _samsung_pwm_clocksource_init();
	if (ret)
		goto err_clocksource;

	return 0;

err_clocksource:
	clk_put(pwm.timerclk);
	pwm.timerclk = NULL;
err_clk:
	iounmap(pwm.base);
	pwm.base = NULL;

	return ret;
}

static const struct samsung_pwm_variant s3c24xx_variant = {
	.bits		= 16,
	.div_base	= 1,
	.has_tint_cstat	= false,
	.tclk_mask	= (1 << 4),
};

static int __init s3c2410_pwm_clocksource_init(struct device_node *np)
{
	return samsung_pwm_alloc(np, &s3c24xx_variant);
}
TIMER_OF_DECLARE(s3c2410_pwm, "samsung,s3c2410-pwm", s3c2410_pwm_clocksource_init);

static const struct samsung_pwm_variant s3c64xx_variant = {
	.bits		= 32,
	.div_base	= 0,
	.has_tint_cstat	= true,
	.tclk_mask	= (1 << 7) | (1 << 6) | (1 << 5),
};

static int __init s3c64xx_pwm_clocksource_init(struct device_node *np)
{
	return samsung_pwm_alloc(np, &s3c64xx_variant);
}
TIMER_OF_DECLARE(s3c6400_pwm, "samsung,s3c6400-pwm", s3c64xx_pwm_clocksource_init);

static const struct samsung_pwm_variant s5p64x0_variant = {
	.bits		= 32,
	.div_base	= 0,
	.has_tint_cstat	= true,
	.tclk_mask	= 0,
};

static int __init s5p64x0_pwm_clocksource_init(struct device_node *np)
{
	return samsung_pwm_alloc(np, &s5p64x0_variant);
}
TIMER_OF_DECLARE(s5p6440_pwm, "samsung,s5p6440-pwm", s5p64x0_pwm_clocksource_init);

static const struct samsung_pwm_variant s5p_variant = {
	.bits		= 32,
	.div_base	= 0,
	.has_tint_cstat	= true,
	.tclk_mask	= (1 << 5),
};

static int __init s5p_pwm_clocksource_init(struct device_node *np)
{
	return samsung_pwm_alloc(np, &s5p_variant);
}
TIMER_OF_DECLARE(s5pc100_pwm, "samsung,s5pc100-pwm", s5p_pwm_clocksource_init);
#endif
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
f1189989 TF	2	/*
	3	* Copyright (c) 2011 Samsung Electronics Co., Ltd.
	4	* http://www.samsung.com/
	5	*
	6	* samsung - Common hr-timer support (s3c and s5p)
a0143f5a	7	*/
f1189989 TF	8
	9	#include <linux/interrupt.h>
	10	#include <linux/irq.h>
	11	#include <linux/err.h>
	12	#include <linux/clk.h>
	13	#include <linux/clockchips.h>
	14	#include <linux/list.h>
	15	#include <linux/module.h>
	16	#include <linux/of.h>
	17	#include <linux/of_address.h>
	18	#include <linux/of_irq.h>
	19	#include <linux/platform_device.h>
	20	#include <linux/slab.h>
38ff87f7	21	#include <linux/sched_clock.h>
f1189989 TF	22
	23	#include <clocksource/samsung_pwm.h>
	24
f1189989 TF	25	/*
	26	* Clocksource driver
	27	*/
	28
	29	#define REG_TCFG0 0x00
	30	#define REG_TCFG1 0x04
	31	#define REG_TCON 0x08
	32	#define REG_TINT_CSTAT 0x44
	33
	34	#define REG_TCNTB(chan) (0x0c + 12 * (chan))
	35	#define REG_TCMPB(chan) (0x10 + 12 * (chan))
	36
	37	#define TCFG0_PRESCALER_MASK 0xff
	38	#define TCFG0_PRESCALER1_SHIFT 8
	39
a0143f5a KK	40	#define TCFG1_SHIFT(x) ((x) * 4)
a0143f5a KK	41	#define TCFG1_MUX_MASK 0xf
f1189989	42
ceea1241 TF	43	/*
	44	* Each channel occupies 4 bits in TCON register, but there is a gap of 4
	45	* bits (one channel) after channel 0, so channels have different numbering
	46	* when accessing TCON register.
	47	*
	48	* In addition, the location of autoreload bit for channel 4 (TCON channel 5)
	49	* in its set of bits is 2 as opposed to 3 for other channels.
	50	*/
f1189989 TF	51	#define TCON_START(chan) (1 << (4 * (chan) + 0))
	52	#define TCON_MANUALUPDATE(chan) (1 << (4 * (chan) + 1))
	53	#define TCON_INVERT(chan) (1 << (4 * (chan) + 2))
ceea1241 TF	54	#define _TCON_AUTORELOAD(chan) (1 << (4 * (chan) + 3))
	55	#define _TCON_AUTORELOAD4(chan) (1 << (4 * (chan) + 2))
	56	#define TCON_AUTORELOAD(chan) \
	57	((chan < 5) ? _TCON_AUTORELOAD(chan) : _TCON_AUTORELOAD4(chan))
f1189989	58
7aac482e TF	59	DEFINE_SPINLOCK(samsung_pwm_lock);
	60	EXPORT_SYMBOL(samsung_pwm_lock);
	61
030c2a1e TF	62	struct samsung_pwm_clocksource {
030c2a1e TF	63	void __iomem *base;
b4318ce2	64	const void __iomem *source_reg;
030c2a1e TF	65	unsigned int irq[SAMSUNG_PWM_NUM];
	66	struct samsung_pwm_variant variant;
	67
	68	struct clk *timerclk;
	69
f1189989 TF	70	unsigned int event_id;
	71	unsigned int source_id;
	72	unsigned int tcnt_max;
	73	unsigned int tscaler_div;
	74	unsigned int tdiv;
030c2a1e TF	75
030c2a1e TF	76	unsigned long clock_count_per_tick;
f1189989 TF	77	};
f1189989 TF	78
030c2a1e	79	static struct samsung_pwm_clocksource pwm;
f1189989	80
030c2a1e	81	static void samsung_timer_set_prescale(unsigned int channel, u16 prescale)
f1189989 TF	82	{
	83	unsigned long flags;
	84	u8 shift = 0;
	85	u32 reg;
	86
	87	if (channel >= 2)
	88	shift = TCFG0_PRESCALER1_SHIFT;
	89
7aac482e	90	spin_lock_irqsave(&samsung_pwm_lock, flags);
f1189989	91
030c2a1e	92	reg = readl(pwm.base + REG_TCFG0);
f1189989 TF	93	reg &= ~(TCFG0_PRESCALER_MASK << shift);
f1189989 TF	94	reg \|= (prescale - 1) << shift;
030c2a1e	95	writel(reg, pwm.base + REG_TCFG0);
f1189989	96
7aac482e	97	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
f1189989 TF	98	}
f1189989 TF	99
030c2a1e	100	static void samsung_timer_set_divisor(unsigned int channel, u8 divisor)
f1189989 TF	101	{
	102	u8 shift = TCFG1_SHIFT(channel);
	103	unsigned long flags;
	104	u32 reg;
	105	u8 bits;
	106
030c2a1e	107	bits = (fls(divisor) - 1) - pwm.variant.div_base;
f1189989	108
7aac482e	109	spin_lock_irqsave(&samsung_pwm_lock, flags);
f1189989	110
030c2a1e	111	reg = readl(pwm.base + REG_TCFG1);
f1189989 TF	112	reg &= ~(TCFG1_MUX_MASK << shift);
f1189989 TF	113	reg \|= bits << shift;
030c2a1e	114	writel(reg, pwm.base + REG_TCFG1);
f1189989	115
7aac482e	116	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
f1189989 TF	117	}
	118
	119	static void samsung_time_stop(unsigned int channel)
	120	{
	121	unsigned long tcon;
	122	unsigned long flags;
	123
	124	if (channel > 0)
	125	++channel;
	126
7aac482e	127	spin_lock_irqsave(&samsung_pwm_lock, flags);
f1189989	128
7cc06179	129	tcon = readl_relaxed(pwm.base + REG_TCON);
f1189989	130	tcon &= ~TCON_START(channel);
7cc06179	131	writel_relaxed(tcon, pwm.base + REG_TCON);
f1189989	132
7aac482e	133	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
f1189989 TF	134	}
	135
	136	static void samsung_time_setup(unsigned int channel, unsigned long tcnt)
	137	{
	138	unsigned long tcon;
	139	unsigned long flags;
	140	unsigned int tcon_chan = channel;
	141
	142	if (tcon_chan > 0)
	143	++tcon_chan;
	144
7aac482e	145	spin_lock_irqsave(&samsung_pwm_lock, flags);
f1189989	146
7cc06179	147	tcon = readl_relaxed(pwm.base + REG_TCON);
f1189989	148
f1189989 TF	149	tcon &= ~(TCON_START(tcon_chan) \| TCON_AUTORELOAD(tcon_chan));
	150	tcon \|= TCON_MANUALUPDATE(tcon_chan);
	151
7cc06179 ML	152	writel_relaxed(tcnt, pwm.base + REG_TCNTB(channel));
	153	writel_relaxed(tcnt, pwm.base + REG_TCMPB(channel));
	154	writel_relaxed(tcon, pwm.base + REG_TCON);
f1189989	155
7aac482e	156	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
f1189989 TF	157	}
	158
	159	static void samsung_time_start(unsigned int channel, bool periodic)
	160	{
	161	unsigned long tcon;
	162	unsigned long flags;
	163
	164	if (channel > 0)
	165	++channel;
	166
7aac482e	167	spin_lock_irqsave(&samsung_pwm_lock, flags);
f1189989	168
7cc06179	169	tcon = readl_relaxed(pwm.base + REG_TCON);
f1189989 TF	170
	171	tcon &= ~TCON_MANUALUPDATE(channel);
	172	tcon \|= TCON_START(channel);
	173
	174	if (periodic)
	175	tcon \|= TCON_AUTORELOAD(channel);
	176	else
	177	tcon &= ~TCON_AUTORELOAD(channel);
	178
7cc06179	179	writel_relaxed(tcon, pwm.base + REG_TCON);
f1189989	180
7aac482e	181	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
f1189989 TF	182	}
	183
	184	static int samsung_set_next_event(unsigned long cycles,
a0143f5a	185	struct clock_event_device *evt)
f1189989	186	{
81d4f7bf TF	187	/*
	188	* This check is needed to account for internal rounding
	189	* errors inside clockevents core, which might result in
	190	* passing cycles = 0, which in turn would not generate any
	191	* timer interrupt and hang the system.
	192	*
	193	* Another solution would be to set up the clockevent device
	194	* with min_delta = 2, but this would unnecessarily increase
	195	* the minimum sleep period.
	196	*/
	197	if (!cycles)
	198	cycles = 1;
	199
030c2a1e TF	200	samsung_time_setup(pwm.event_id, cycles);
030c2a1e TF	201	samsung_time_start(pwm.event_id, false);
f1189989 TF	202
	203	return 0;
	204	}
	205
b49b5704	206	static int samsung_shutdown(struct clock_event_device *evt)
f1189989	207	{
030c2a1e	208	samsung_time_stop(pwm.event_id);
b49b5704 VK	209	return 0;
b49b5704 VK	210	}
f1189989	211
b49b5704 VK	212	static int samsung_set_periodic(struct clock_event_device *evt)
	213	{
	214	samsung_time_stop(pwm.event_id);
	215	samsung_time_setup(pwm.event_id, pwm.clock_count_per_tick - 1);
	216	samsung_time_start(pwm.event_id, true);
	217	return 0;
f1189989 TF	218	}
f1189989 TF	219
0b96258b TF	220	static void samsung_clockevent_resume(struct clock_event_device *cev)
	221	{
	222	samsung_timer_set_prescale(pwm.event_id, pwm.tscaler_div);
	223	samsung_timer_set_divisor(pwm.event_id, pwm.tdiv);
	224
	225	if (pwm.variant.has_tint_cstat) {
	226	u32 mask = (1 << pwm.event_id);
a0143f5a	227
0b96258b TF	228	writel(mask \| (mask << 5), pwm.base + REG_TINT_CSTAT);
	229	}
	230	}
	231
f1189989	232	static struct clock_event_device time_event_device = {
b49b5704 VK	233	.name = "samsung_event_timer",
	234	.features = CLOCK_EVT_FEAT_PERIODIC \|
	235	CLOCK_EVT_FEAT_ONESHOT,
	236	.rating = 200,
	237	.set_next_event = samsung_set_next_event,
	238	.set_state_shutdown = samsung_shutdown,
	239	.set_state_periodic = samsung_set_periodic,
	240	.set_state_oneshot = samsung_shutdown,
	241	.tick_resume = samsung_shutdown,
	242	.resume = samsung_clockevent_resume,
f1189989 TF	243	};
	244
	245	static irqreturn_t samsung_clock_event_isr(int irq, void *dev_id)
	246	{
	247	struct clock_event_device *evt = dev_id;
	248
030c2a1e TF	249	if (pwm.variant.has_tint_cstat) {
030c2a1e TF	250	u32 mask = (1 << pwm.event_id);
a0143f5a	251
030c2a1e	252	writel(mask \| (mask << 5), pwm.base + REG_TINT_CSTAT);
f1189989 TF	253	}
	254
	255	evt->event_handler(evt);
	256
	257	return IRQ_HANDLED;
	258	}
	259
f1189989 TF	260	static void __init samsung_clockevent_init(void)
	261	{
	262	unsigned long pclk;
	263	unsigned long clock_rate;
	264	unsigned int irq_number;
	265
030c2a1e	266	pclk = clk_get_rate(pwm.timerclk);
f1189989	267
030c2a1e TF	268	samsung_timer_set_prescale(pwm.event_id, pwm.tscaler_div);
030c2a1e TF	269	samsung_timer_set_divisor(pwm.event_id, pwm.tdiv);
f1189989	270
030c2a1e TF	271	clock_rate = pclk / (pwm.tscaler_div * pwm.tdiv);
030c2a1e TF	272	pwm.clock_count_per_tick = clock_rate / HZ;
f1189989 TF	273
f1189989 TF	274	time_event_device.cpumask = cpumask_of(0);
e9b852b8	275	clockevents_config_and_register(&time_event_device,
a0143f5a	276	clock_rate, 1, pwm.tcnt_max);
f1189989	277
030c2a1e	278	irq_number = pwm.irq[pwm.event_id];
cc2550b4	279	if (request_irq(irq_number, samsung_clock_event_isr,
	280	IRQF_TIMER \| IRQF_IRQPOLL, "samsung_time_irq",
	281	&time_event_device))
	282	pr_err("%s: request_irq() failed\n", "samsung_time_irq");
f1189989	283
030c2a1e TF	284	if (pwm.variant.has_tint_cstat) {
030c2a1e TF	285	u32 mask = (1 << pwm.event_id);
a0143f5a	286
030c2a1e	287	writel(mask \| (mask << 5), pwm.base + REG_TINT_CSTAT);
f1189989 TF	288	}
	289	}
	290
0b96258b	291	static void samsung_clocksource_suspend(struct clocksource *cs)
f1189989	292	{
0b96258b	293	samsung_time_stop(pwm.source_id);
f1189989 TF	294	}
f1189989 TF	295
0b96258b TF	296	static void samsung_clocksource_resume(struct clocksource *cs)
	297	{
	298	samsung_timer_set_prescale(pwm.source_id, pwm.tscaler_div);
	299	samsung_timer_set_divisor(pwm.source_id, pwm.tdiv);
	300
	301	samsung_time_setup(pwm.source_id, pwm.tcnt_max);
	302	samsung_time_start(pwm.source_id, true);
	303	}
	304
a5a1d1c2	305	static u64 notrace samsung_clocksource_read(struct clocksource *c)
6792e636 TF	306	{
	307	return ~readl_relaxed(pwm.source_reg);
	308	}
	309
	310	static struct clocksource samsung_clocksource = {
	311	.name = "samsung_clocksource_timer",
	312	.rating = 250,
	313	.read = samsung_clocksource_read,
0b96258b TF	314	.suspend = samsung_clocksource_suspend,
0b96258b TF	315	.resume = samsung_clocksource_resume,
6792e636 TF	316	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	317	};
	318
f1189989 TF	319	/*
	320	* Override the global weak sched_clock symbol with this
	321	* local implementation which uses the clocksource to get some
	322	* better resolution when scheduling the kernel. We accept that
	323	* this wraps around for now, since it is just a relative time
	324	* stamp. (Inspired by U300 implementation.)
	325	*/
2902b30e	326	static u64 notrace samsung_read_sched_clock(void)
f1189989	327	{
6792e636	328	return samsung_clocksource_read(NULL);
f1189989 TF	329	}
f1189989 TF	330
0993f57b	331	static int __init samsung_clocksource_init(void)
f1189989	332	{
f1189989 TF	333	unsigned long pclk;
f1189989 TF	334	unsigned long clock_rate;
f1189989	335
030c2a1e	336	pclk = clk_get_rate(pwm.timerclk);
f1189989	337
030c2a1e TF	338	samsung_timer_set_prescale(pwm.source_id, pwm.tscaler_div);
030c2a1e TF	339	samsung_timer_set_divisor(pwm.source_id, pwm.tdiv);
f1189989	340
030c2a1e	341	clock_rate = pclk / (pwm.tscaler_div * pwm.tdiv);
f1189989	342
030c2a1e TF	343	samsung_time_setup(pwm.source_id, pwm.tcnt_max);
030c2a1e TF	344	samsung_time_start(pwm.source_id, true);
f1189989	345
61d7e205 TF	346	if (pwm.source_id == 4)
	347	pwm.source_reg = pwm.base + 0x40;
	348	else
	349	pwm.source_reg = pwm.base + pwm.source_id * 0x0c + 0x14;
	350
2902b30e	351	sched_clock_register(samsung_read_sched_clock,
a0143f5a	352	pwm.variant.bits, clock_rate);
f1189989	353
6792e636	354	samsung_clocksource.mask = CLOCKSOURCE_MASK(pwm.variant.bits);
0993f57b	355	return clocksource_register_hz(&samsung_clocksource, clock_rate);
f1189989 TF	356	}
	357
	358	static void __init samsung_timer_resources(void)
	359	{
030c2a1e	360	clk_prepare_enable(pwm.timerclk);
f1189989	361
030c2a1e TF	362	pwm.tcnt_max = (1UL << pwm.variant.bits) - 1;
	363	if (pwm.variant.bits == 16) {
	364	pwm.tscaler_div = 25;
	365	pwm.tdiv = 2;
f1189989	366	} else {
030c2a1e TF	367	pwm.tscaler_div = 2;
030c2a1e TF	368	pwm.tdiv = 1;
f1189989 TF	369	}
	370	}
	371
	372	/*
	373	* PWM master driver
	374	*/
0993f57b	375	static int __init _samsung_pwm_clocksource_init(void)
f1189989 TF	376	{
	377	u8 mask;
	378	int channel;
	379
030c2a1e	380	mask = ~pwm.variant.output_mask & ((1 << SAMSUNG_PWM_NUM) - 1);
f1189989	381	channel = fls(mask) - 1;
0993f57b	382	if (channel < 0) {
ac9ce6d1	383	pr_crit("failed to find PWM channel for clocksource\n");
0993f57b DL	384	return -EINVAL;
0993f57b DL	385	}
030c2a1e	386	pwm.source_id = channel;
f1189989 TF	387
	388	mask &= ~(1 << channel);
	389	channel = fls(mask) - 1;
0993f57b	390	if (channel < 0) {
ac9ce6d1	391	pr_crit("failed to find PWM channel for clock event\n");
0993f57b DL	392	return -EINVAL;
0993f57b DL	393	}
030c2a1e	394	pwm.event_id = channel;
f1189989 TF	395
	396	samsung_timer_resources();
	397	samsung_clockevent_init();
0993f57b DL	398
0993f57b DL	399	return samsung_clocksource_init();
f1189989 TF	400	}
f1189989 TF	401
f9bb48a2	402	void __init samsung_pwm_clocksource_init(void __iomem *base,
a0143f5a	403	unsigned int *irqs,
bb08e965	404	const struct samsung_pwm_variant *variant)
f9bb48a2 TF	405	{
	406	pwm.base = base;
	407	memcpy(&pwm.variant, variant, sizeof(pwm.variant));
	408	memcpy(pwm.irq, irqs, SAMSUNG_PWM_NUM * sizeof(*irqs));
	409
a1fa6f50 TF	410	pwm.timerclk = clk_get(NULL, "timers");
	411	if (IS_ERR(pwm.timerclk))
	412	panic("failed to get timers clock for timer");
	413
f9bb48a2 TF	414	_samsung_pwm_clocksource_init();
	415	}
	416
bb0eb050	417	#ifdef CONFIG_TIMER_OF
0993f57b DL	418	static int __init samsung_pwm_alloc(struct device_node *np,
0993f57b DL	419	const struct samsung_pwm_variant *variant)
f1189989	420	{
f1189989 TF	421	struct property *prop;
	422	const __be32 *cur;
	423	u32 val;
63e83bd8	424	int i, ret;
f1189989	425
030c2a1e	426	memcpy(&pwm.variant, variant, sizeof(pwm.variant));
f1189989	427	for (i = 0; i < SAMSUNG_PWM_NUM; ++i)
030c2a1e	428	pwm.irq[i] = irq_of_parse_and_map(np, i);
f1189989 TF	429
	430	of_property_for_each_u32(np, "samsung,pwm-outputs", prop, cur, val) {
	431	if (val >= SAMSUNG_PWM_NUM) {
43fc6b25	432	pr_warn("%s: invalid channel index in samsung,pwm-outputs property\n", __func__);
f1189989 TF	433	continue;
f1189989 TF	434	}
030c2a1e	435	pwm.variant.output_mask \|= 1 << val;
f1189989 TF	436	}
f1189989 TF	437
e2415489	438	pwm.base = of_iomap(np, 0);
030c2a1e	439	if (!pwm.base) {
f1189989	440	pr_err("%s: failed to map PWM registers\n", __func__);
0993f57b	441	return -ENXIO;
f1189989 TF	442	}
f1189989 TF	443
a1fa6f50	444	pwm.timerclk = of_clk_get_by_name(np, "timers");
0993f57b	445	if (IS_ERR(pwm.timerclk)) {
ac9ce6d1	446	pr_crit("failed to get timers clock for timer\n");
63e83bd8 KK	447	ret = PTR_ERR(pwm.timerclk);
63e83bd8 KK	448	goto err_clk;
0993f57b	449	}
a1fa6f50	450
63e83bd8 KK	451	ret = _samsung_pwm_clocksource_init();
	452	if (ret)
	453	goto err_clocksource;
	454
	455	return 0;
	456
	457	err_clocksource:
	458	clk_put(pwm.timerclk);
	459	pwm.timerclk = NULL;
	460	err_clk:
	461	iounmap(pwm.base);
	462	pwm.base = NULL;
	463
	464	return ret;
f1189989 TF	465	}
	466
	467	static const struct samsung_pwm_variant s3c24xx_variant = {
	468	.bits = 16,
	469	.div_base = 1,
	470	.has_tint_cstat = false,
	471	.tclk_mask = (1 << 4),
	472	};
	473
0993f57b	474	static int __init s3c2410_pwm_clocksource_init(struct device_node *np)
f1189989	475	{
0993f57b	476	return samsung_pwm_alloc(np, &s3c24xx_variant);
f1189989	477	}
17273395	478	TIMER_OF_DECLARE(s3c2410_pwm, "samsung,s3c2410-pwm", s3c2410_pwm_clocksource_init);
f1189989 TF	479
	480	static const struct samsung_pwm_variant s3c64xx_variant = {
	481	.bits = 32,
	482	.div_base = 0,
	483	.has_tint_cstat = true,
	484	.tclk_mask = (1 << 7) \| (1 << 6) \| (1 << 5),
	485	};
	486
0993f57b	487	static int __init s3c64xx_pwm_clocksource_init(struct device_node *np)
f1189989	488	{
0993f57b	489	return samsung_pwm_alloc(np, &s3c64xx_variant);
f1189989	490	}
17273395	491	TIMER_OF_DECLARE(s3c6400_pwm, "samsung,s3c6400-pwm", s3c64xx_pwm_clocksource_init);
f1189989 TF	492
	493	static const struct samsung_pwm_variant s5p64x0_variant = {
	494	.bits = 32,
	495	.div_base = 0,
	496	.has_tint_cstat = true,
	497	.tclk_mask = 0,
	498	};
	499
0993f57b	500	static int __init s5p64x0_pwm_clocksource_init(struct device_node *np)
f1189989	501	{
0993f57b	502	return samsung_pwm_alloc(np, &s5p64x0_variant);
f1189989	503	}
17273395	504	TIMER_OF_DECLARE(s5p6440_pwm, "samsung,s5p6440-pwm", s5p64x0_pwm_clocksource_init);
f1189989 TF	505
	506	static const struct samsung_pwm_variant s5p_variant = {
	507	.bits = 32,
	508	.div_base = 0,
	509	.has_tint_cstat = true,
	510	.tclk_mask = (1 << 5),
	511	};
	512
0993f57b	513	static int __init s5p_pwm_clocksource_init(struct device_node *np)
f1189989	514	{
0993f57b	515	return samsung_pwm_alloc(np, &s5p_variant);
f1189989	516	}
17273395	517	TIMER_OF_DECLARE(s5pc100_pwm, "samsung,s5pc100-pwm", s5p_pwm_clocksource_init);
f9bb48a2	518	#endif