[linux-2.6-block.git] / drivers / clocksource / nomadik-mtu.c

/*
 * Copyright (C) 2008 STMicroelectronics
 * Copyright (C) 2010 Alessandro Rubini
 * Copyright (C) 2010 Linus Walleij for ST-Ericsson
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2, as
 * published by the Free Software Foundation.
 */
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/clockchips.h>
#include <linux/clocksource.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/clk.h>
#include <linux/jiffies.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/sched_clock.h>
#include <asm/mach/time.h>

/*
 * The MTU device hosts four different counters, with 4 set of
 * registers. These are register names.
 */

#define MTU_IMSC	0x00	/* Interrupt mask set/clear */
#define MTU_RIS		0x04	/* Raw interrupt status */
#define MTU_MIS		0x08	/* Masked interrupt status */
#define MTU_ICR		0x0C	/* Interrupt clear register */

/* per-timer registers take 0..3 as argument */
#define MTU_LR(x)	(0x10 + 0x10 * (x) + 0x00)	/* Load value */
#define MTU_VAL(x)	(0x10 + 0x10 * (x) + 0x04)	/* Current value */
#define MTU_CR(x)	(0x10 + 0x10 * (x) + 0x08)	/* Control reg */
#define MTU_BGLR(x)	(0x10 + 0x10 * (x) + 0x0c)	/* At next overflow */

/* bits for the control register */
#define MTU_CRn_ENA		0x80
#define MTU_CRn_PERIODIC	0x40	/* if 0 = free-running */
#define MTU_CRn_PRESCALE_MASK	0x0c
#define MTU_CRn_PRESCALE_1		0x00
#define MTU_CRn_PRESCALE_16		0x04
#define MTU_CRn_PRESCALE_256		0x08
#define MTU_CRn_32BITS		0x02
#define MTU_CRn_ONESHOT		0x01	/* if 0 = wraps reloading from BGLR*/

/* Other registers are usual amba/primecell registers, currently not used */
#define MTU_ITCR	0xff0
#define MTU_ITOP	0xff4

#define MTU_PERIPH_ID0	0xfe0
#define MTU_PERIPH_ID1	0xfe4
#define MTU_PERIPH_ID2	0xfe8
#define MTU_PERIPH_ID3	0xfeC

#define MTU_PCELL0	0xff0
#define MTU_PCELL1	0xff4
#define MTU_PCELL2	0xff8
#define MTU_PCELL3	0xffC

static void __iomem *mtu_base;
static bool clkevt_periodic;
static u32 clk_prescale;
static u32 nmdk_cycle;		/* write-once */
static struct delay_timer mtu_delay_timer;

#ifdef CONFIG_CLKSRC_NOMADIK_MTU_SCHED_CLOCK
/*
 * Override the global weak sched_clock symbol with this
 * local implementation which uses the clocksource to get some
 * better resolution when scheduling the kernel.
 */
static u64 notrace nomadik_read_sched_clock(void)
{
	if (unlikely(!mtu_base))
		return 0;

	return -readl(mtu_base + MTU_VAL(0));
}
#endif

static unsigned long nmdk_timer_read_current_timer(void)
{
	return ~readl_relaxed(mtu_base + MTU_VAL(0));
}

/* Clockevent device: use one-shot mode */
static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev)
{
	writel(1 << 1, mtu_base + MTU_IMSC);
	writel(evt, mtu_base + MTU_LR(1));
	/* Load highest value, enable device, enable interrupts */
	writel(MTU_CRn_ONESHOT | clk_prescale |
	       MTU_CRn_32BITS | MTU_CRn_ENA,
	       mtu_base + MTU_CR(1));

	return 0;
}

static void nmdk_clkevt_reset(void)
{
	if (clkevt_periodic) {
		/* Timer: configure load and background-load, and fire it up */
		writel(nmdk_cycle, mtu_base + MTU_LR(1));
		writel(nmdk_cycle, mtu_base + MTU_BGLR(1));

		writel(MTU_CRn_PERIODIC | clk_prescale |
		       MTU_CRn_32BITS | MTU_CRn_ENA,
		       mtu_base + MTU_CR(1));
		writel(1 << 1, mtu_base + MTU_IMSC);
	} else {
		/* Generate an interrupt to start the clockevent again */
		(void) nmdk_clkevt_next(nmdk_cycle, NULL);
	}
}

static void nmdk_clkevt_mode(enum clock_event_mode mode,
			     struct clock_event_device *dev)
{
	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		clkevt_periodic = true;
		nmdk_clkevt_reset();
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		clkevt_periodic = false;
		break;
	case CLOCK_EVT_MODE_SHUTDOWN:
	case CLOCK_EVT_MODE_UNUSED:
		writel(0, mtu_base + MTU_IMSC);
		/* disable timer */
		writel(0, mtu_base + MTU_CR(1));
		/* load some high default value */
		writel(0xffffffff, mtu_base + MTU_LR(1));
		break;
	case CLOCK_EVT_MODE_RESUME:
		break;
	}
}

static void nmdk_clksrc_reset(void)
{
	/* Disable */
	writel(0, mtu_base + MTU_CR(0));

	/* ClockSource: configure load and background-load, and fire it up */
	writel(nmdk_cycle, mtu_base + MTU_LR(0));
	writel(nmdk_cycle, mtu_base + MTU_BGLR(0));

	writel(clk_prescale | MTU_CRn_32BITS | MTU_CRn_ENA,
	       mtu_base + MTU_CR(0));
}

static void nmdk_clkevt_resume(struct clock_event_device *cedev)
{
	nmdk_clkevt_reset();
	nmdk_clksrc_reset();
}

static struct clock_event_device nmdk_clkevt = {
	.name		= "mtu_1",
	.features	= CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC |
	                  CLOCK_EVT_FEAT_DYNIRQ,
	.rating		= 200,
	.set_mode	= nmdk_clkevt_mode,
	.set_next_event	= nmdk_clkevt_next,
	.resume		= nmdk_clkevt_resume,
};

/*
 * IRQ Handler for timer 1 of the MTU block.
 */
static irqreturn_t nmdk_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evdev = dev_id;

	writel(1 << 1, mtu_base + MTU_ICR); /* Interrupt clear reg */
	evdev->event_handler(evdev);
	return IRQ_HANDLED;
}

static struct irqaction nmdk_timer_irq = {
	.name		= "Nomadik Timer Tick",
	.flags		= IRQF_TIMER,
	.handler	= nmdk_timer_interrupt,
	.dev_id		= &nmdk_clkevt,
};

static void __init nmdk_timer_init(void __iomem *base, int irq,
				   struct clk *pclk, struct clk *clk)
{
	unsigned long rate;

	mtu_base = base;

	BUG_ON(clk_prepare_enable(pclk));
	BUG_ON(clk_prepare_enable(clk));

	/*
	 * Tick rate is 2.4MHz for Nomadik and 2.4Mhz, 100MHz or 133 MHz
	 * for ux500.
	 * Use a divide-by-16 counter if the tick rate is more than 32MHz.
	 * At 32 MHz, the timer (with 32 bit counter) can be programmed
	 * to wake-up at a max 127s a head in time. Dividing a 2.4 MHz timer
	 * with 16 gives too low timer resolution.
	 */
	rate = clk_get_rate(clk);
	if (rate > 32000000) {
		rate /= 16;
		clk_prescale = MTU_CRn_PRESCALE_16;
	} else {
		clk_prescale = MTU_CRn_PRESCALE_1;
	}

	/* Cycles for periodic mode */
	nmdk_cycle = DIV_ROUND_CLOSEST(rate, HZ);


	/* Timer 0 is the free running clocksource */
	nmdk_clksrc_reset();

	if (clocksource_mmio_init(mtu_base + MTU_VAL(0), "mtu_0",
			rate, 200, 32, clocksource_mmio_readl_down))
		pr_err("timer: failed to initialize clock source %s\n",
		       "mtu_0");

#ifdef CONFIG_CLKSRC_NOMADIK_MTU_SCHED_CLOCK
	sched_clock_register(nomadik_read_sched_clock, 32, rate);
#endif

	/* Timer 1 is used for events, register irq and clockevents */
	setup_irq(irq, &nmdk_timer_irq);
	nmdk_clkevt.cpumask = cpumask_of(0);
	nmdk_clkevt.irq = irq;
	clockevents_config_and_register(&nmdk_clkevt, rate, 2, 0xffffffffU);

	mtu_delay_timer.read_current_timer = &nmdk_timer_read_current_timer;
	mtu_delay_timer.freq = rate;
	register_current_timer_delay(&mtu_delay_timer);
}

static void __init nmdk_timer_of_init(struct device_node *node)
{
	struct clk *pclk;
	struct clk *clk;
	void __iomem *base;
	int irq;

	base = of_iomap(node, 0);
	if (!base)
		panic("Can't remap registers");

	pclk = of_clk_get_by_name(node, "apb_pclk");
	if (IS_ERR(pclk))
		panic("could not get apb_pclk");

	clk = of_clk_get_by_name(node, "timclk");
	if (IS_ERR(clk))
		panic("could not get timclk");

	irq = irq_of_parse_and_map(node, 0);
	if (irq <= 0)
		panic("Can't parse IRQ");

	nmdk_timer_init(base, irq, pclk, clk);
}
CLOCKSOURCE_OF_DECLARE(nomadik_mtu, "st,nomadik-mtu",
		       nmdk_timer_of_init);
Commit	Line	Data
28ad94ec	1	/*
28ad94ec	2	* Copyright (C) 2008 STMicroelectronics
b102c01f	3	* Copyright (C) 2010 Alessandro Rubini
8fbb97a2	4	* Copyright (C) 2010 Linus Walleij for ST-Ericsson
28ad94ec AR	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2, as
	8	* published by the Free Software Foundation.
	9	*/
	10	#include <linux/init.h>
	11	#include <linux/interrupt.h>
	12	#include <linux/irq.h>
	13	#include <linux/io.h>
	14	#include <linux/clockchips.h>
694e33a7	15	#include <linux/clocksource.h>
c7785ea0 RV	16	#include <linux/of_address.h>
	17	#include <linux/of_irq.h>
	18	#include <linux/of_platform.h>
ba327b1e	19	#include <linux/clk.h>
28ad94ec	20	#include <linux/jiffies.h>
6f179b72	21	#include <linux/delay.h>
ba327b1e	22	#include <linux/err.h>
38ff87f7	23	#include <linux/sched_clock.h>
28ad94ec	24	#include <asm/mach/time.h>
28ad94ec	25
05387a9f JA	26	/*
	27	* The MTU device hosts four different counters, with 4 set of
	28	* registers. These are register names.
	29	*/
	30
	31	#define MTU_IMSC 0x00 /* Interrupt mask set/clear */
	32	#define MTU_RIS 0x04 /* Raw interrupt status */
	33	#define MTU_MIS 0x08 /* Masked interrupt status */
	34	#define MTU_ICR 0x0C /* Interrupt clear register */
	35
	36	/* per-timer registers take 0..3 as argument */
	37	#define MTU_LR(x) (0x10 + 0x10 * (x) + 0x00) /* Load value */
	38	#define MTU_VAL(x) (0x10 + 0x10 * (x) + 0x04) /* Current value */
	39	#define MTU_CR(x) (0x10 + 0x10 * (x) + 0x08) /* Control reg */
	40	#define MTU_BGLR(x) (0x10 + 0x10 * (x) + 0x0c) /* At next overflow */
	41
	42	/* bits for the control register */
	43	#define MTU_CRn_ENA 0x80
	44	#define MTU_CRn_PERIODIC 0x40 /* if 0 = free-running */
	45	#define MTU_CRn_PRESCALE_MASK 0x0c
	46	#define MTU_CRn_PRESCALE_1 0x00
	47	#define MTU_CRn_PRESCALE_16 0x04
	48	#define MTU_CRn_PRESCALE_256 0x08
	49	#define MTU_CRn_32BITS 0x02
	50	#define MTU_CRn_ONESHOT 0x01 /* if 0 = wraps reloading from BGLR*/
	51
	52	/* Other registers are usual amba/primecell registers, currently not used */
	53	#define MTU_ITCR 0xff0
	54	#define MTU_ITOP 0xff4
	55
	56	#define MTU_PERIPH_ID0 0xfe0
	57	#define MTU_PERIPH_ID1 0xfe4
	58	#define MTU_PERIPH_ID2 0xfe8
	59	#define MTU_PERIPH_ID3 0xfeC
	60
	61	#define MTU_PCELL0 0xff0
	62	#define MTU_PCELL1 0xff4
	63	#define MTU_PCELL2 0xff8
	64	#define MTU_PCELL3 0xffC
28ad94ec	65
b9576623	66	static void __iomem *mtu_base;
2f73a068 JA	67	static bool clkevt_periodic;
	68	static u32 clk_prescale;
	69	static u32 nmdk_cycle; /* write-once */
6f179b72	70	static struct delay_timer mtu_delay_timer;
2f73a068	71
ea7113f7	72	#ifdef CONFIG_CLKSRC_NOMADIK_MTU_SCHED_CLOCK
2a847513 LW	73	/*
	74	* Override the global weak sched_clock symbol with this
	75	* local implementation which uses the clocksource to get some
8fbb97a2	76	* better resolution when scheduling the kernel.
2a847513	77	*/
e25bc5f5	78	static u64 notrace nomadik_read_sched_clock(void)
2a847513	79	{
8fbb97a2 LW	80	if (unlikely(!mtu_base))
	81	return 0;
	82
2f0778af	83	return -readl(mtu_base + MTU_VAL(0));
2a847513	84	}
cba13830	85	#endif
2f73a068	86
6f179b72 FB	87	static unsigned long nmdk_timer_read_current_timer(void)
	88	{
	89	return ~readl_relaxed(mtu_base + MTU_VAL(0));
	90	}
	91
b102c01f	92	/* Clockevent device: use one-shot mode */
2f73a068 JA	93	static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev)
	94	{
	95	writel(1 << 1, mtu_base + MTU_IMSC);
	96	writel(evt, mtu_base + MTU_LR(1));
	97	/* Load highest value, enable device, enable interrupts */
	98	writel(MTU_CRn_ONESHOT \| clk_prescale \|
	99	MTU_CRn_32BITS \| MTU_CRn_ENA,
	100	mtu_base + MTU_CR(1));
	101
	102	return 0;
	103	}
	104
7172c19a	105	static void nmdk_clkevt_reset(void)
2f73a068 JA	106	{
2f73a068 JA	107	if (clkevt_periodic) {
2f73a068 JA	108	/* Timer: configure load and background-load, and fire it up */
	109	writel(nmdk_cycle, mtu_base + MTU_LR(1));
	110	writel(nmdk_cycle, mtu_base + MTU_BGLR(1));
	111
	112	writel(MTU_CRn_PERIODIC \| clk_prescale \|
	113	MTU_CRn_32BITS \| MTU_CRn_ENA,
	114	mtu_base + MTU_CR(1));
	115	writel(1 << 1, mtu_base + MTU_IMSC);
	116	} else {
	117	/* Generate an interrupt to start the clockevent again */
	118	(void) nmdk_clkevt_next(nmdk_cycle, NULL);
	119	}
	120	}
	121
28ad94ec AR	122	static void nmdk_clkevt_mode(enum clock_event_mode mode,
	123	struct clock_event_device *dev)
	124	{
28ad94ec AR	125	switch (mode) {
28ad94ec AR	126	case CLOCK_EVT_MODE_PERIODIC:
2f73a068 JA	127	clkevt_periodic = true;
2f73a068 JA	128	nmdk_clkevt_reset();
28ad94ec AR	129	break;
28ad94ec AR	130	case CLOCK_EVT_MODE_ONESHOT:
2f73a068	131	clkevt_periodic = false;
b102c01f	132	break;
28ad94ec AR	133	case CLOCK_EVT_MODE_SHUTDOWN:
28ad94ec AR	134	case CLOCK_EVT_MODE_UNUSED:
b102c01f	135	writel(0, mtu_base + MTU_IMSC);
2917947a	136	/* disable timer */
2f73a068	137	writel(0, mtu_base + MTU_CR(1));
2917947a LW	138	/* load some high default value */
2917947a LW	139	writel(0xffffffff, mtu_base + MTU_LR(1));
28ad94ec AR	140	break;
	141	case CLOCK_EVT_MODE_RESUME:
	142	break;
	143	}
	144	}
	145
7172c19a	146	static void nmdk_clksrc_reset(void)
8726e96f SW	147	{
	148	/* Disable */
	149	writel(0, mtu_base + MTU_CR(0));
	150
	151	/* ClockSource: configure load and background-load, and fire it up */
	152	writel(nmdk_cycle, mtu_base + MTU_LR(0));
	153	writel(nmdk_cycle, mtu_base + MTU_BGLR(0));
	154
	155	writel(clk_prescale \| MTU_CRn_32BITS \| MTU_CRn_ENA,
	156	mtu_base + MTU_CR(0));
	157	}
	158
	159	static void nmdk_clkevt_resume(struct clock_event_device *cedev)
	160	{
	161	nmdk_clkevt_reset();
	162	nmdk_clksrc_reset();
	163	}
	164
28ad94ec	165	static struct clock_event_device nmdk_clkevt = {
b102c01f	166	.name = "mtu_1",
74adcbff DL	167	.features = CLOCK_EVT_FEAT_ONESHOT \| CLOCK_EVT_FEAT_PERIODIC \|
74adcbff DL	168	CLOCK_EVT_FEAT_DYNIRQ,
b102c01f	169	.rating = 200,
28ad94ec	170	.set_mode = nmdk_clkevt_mode,
b102c01f	171	.set_next_event = nmdk_clkevt_next,
8726e96f	172	.resume = nmdk_clkevt_resume,
28ad94ec AR	173	};
	174
	175	/*
b102c01f	176	* IRQ Handler for timer 1 of the MTU block.
28ad94ec AR	177	*/
	178	static irqreturn_t nmdk_timer_interrupt(int irq, void *dev_id)
	179	{
b102c01f	180	struct clock_event_device *evdev = dev_id;
28ad94ec	181
b102c01f AR	182	writel(1 << 1, mtu_base + MTU_ICR); /* Interrupt clear reg */
b102c01f AR	183	evdev->event_handler(evdev);
28ad94ec AR	184	return IRQ_HANDLED;
	185	}
	186
28ad94ec AR	187	static struct irqaction nmdk_timer_irq = {
28ad94ec AR	188	.name = "Nomadik Timer Tick",
38c30a84	189	.flags = IRQF_TIMER,
28ad94ec	190	.handler = nmdk_timer_interrupt,
b102c01f	191	.dev_id = &nmdk_clkevt,
28ad94ec AR	192	};
28ad94ec AR	193
7172c19a LW	194	static void __init nmdk_timer_init(void __iomem *base, int irq,
7172c19a LW	195	struct clk pclk, struct clk clk)
28ad94ec	196	{
28ad94ec	197	unsigned long rate;
ba327b1e	198
b9576623	199	mtu_base = base;
16defa66	200
c7785ea0 RV	201	BUG_ON(clk_prepare_enable(pclk));
c7785ea0 RV	202	BUG_ON(clk_prepare_enable(clk));
b102c01f AR	203
b102c01f AR	204	/*
a0719f52 LW	205	* Tick rate is 2.4MHz for Nomadik and 2.4Mhz, 100MHz or 133 MHz
	206	* for ux500.
	207	* Use a divide-by-16 counter if the tick rate is more than 32MHz.
	208	* At 32 MHz, the timer (with 32 bit counter) can be programmed
	209	* to wake-up at a max 127s a head in time. Dividing a 2.4 MHz timer
	210	* with 16 gives too low timer resolution.
b102c01f	211	*/
c7785ea0	212	rate = clk_get_rate(clk);
a0719f52	213	if (rate > 32000000) {
b102c01f	214	rate /= 16;
2f73a068	215	clk_prescale = MTU_CRn_PRESCALE_16;
b102c01f	216	} else {
2f73a068	217	clk_prescale = MTU_CRn_PRESCALE_1;
b102c01f	218	}
28ad94ec	219
21366831 LW	220	/* Cycles for periodic mode */
21366831 LW	221	nmdk_cycle = DIV_ROUND_CLOSEST(rate, HZ);
2f73a068 JA	222
2f73a068 JA	223
b102c01f	224	/* Timer 0 is the free running clocksource */
2f73a068	225	nmdk_clksrc_reset();
28ad94ec	226
bfe45e0b RK	227	if (clocksource_mmio_init(mtu_base + MTU_VAL(0), "mtu_0",
bfe45e0b RK	228	rate, 200, 32, clocksource_mmio_readl_down))
b102c01f	229	pr_err("timer: failed to initialize clock source %s\n",
bfe45e0b	230	"mtu_0");
2f0778af	231
ea7113f7	232	#ifdef CONFIG_CLKSRC_NOMADIK_MTU_SCHED_CLOCK
e25bc5f5	233	sched_clock_register(nomadik_read_sched_clock, 32, rate);
cba13830	234	#endif
2f0778af	235
a3b86a6d	236	/* Timer 1 is used for events, register irq and clockevents */
0813069d	237	setup_irq(irq, &nmdk_timer_irq);
a3b86a6d	238	nmdk_clkevt.cpumask = cpumask_of(0);
00f4e13c	239	nmdk_clkevt.irq = irq;
a3b86a6d	240	clockevents_config_and_register(&nmdk_clkevt, rate, 2, 0xffffffffU);
6f179b72 FB	241
	242	mtu_delay_timer.read_current_timer = &nmdk_timer_read_current_timer;
	243	mtu_delay_timer.freq = rate;
	244	register_current_timer_delay(&mtu_delay_timer);
28ad94ec	245	}
c7785ea0	246
3c09f4da	247	static void __init nmdk_timer_of_init(struct device_node *node)
c7785ea0	248	{
c7785ea0 RV	249	struct clk *pclk;
	250	struct clk *clk;
	251	void __iomem *base;
	252	int irq;
	253
c7785ea0 RV	254	base = of_iomap(node, 0);
	255	if (!base)
	256	panic("Can't remap registers");
	257
	258	pclk = of_clk_get_by_name(node, "apb_pclk");
	259	if (IS_ERR(pclk))
	260	panic("could not get apb_pclk");
	261
	262	clk = of_clk_get_by_name(node, "timclk");
	263	if (IS_ERR(clk))
	264	panic("could not get timclk");
	265
	266	irq = irq_of_parse_and_map(node, 0);
	267	if (irq <= 0)
	268	panic("Can't parse IRQ");
	269
7172c19a	270	nmdk_timer_init(base, irq, pclk, clk);
c7785ea0 RV	271	}
	272	CLOCKSOURCE_OF_DECLARE(nomadik_mtu, "st,nomadik-mtu",
	273	nmdk_timer_of_init);