[linux-2.6-block.git] / drivers / clocksource / nomadik-mtu.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2008 STMicroelectronics
 * Copyright (C) 2010 Alessandro Rubini
 * Copyright (C) 2010 Linus Walleij for ST-Ericsson
 */
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/clockchips.h>
#include <linux/clocksource.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/clk.h>
#include <linux/jiffies.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/sched_clock.h>
#include <asm/mach/time.h>

/*
 * The MTU device hosts four different counters, with 4 set of
 * registers. These are register names.
 */

#define MTU_IMSC	0x00	/* Interrupt mask set/clear */
#define MTU_RIS		0x04	/* Raw interrupt status */
#define MTU_MIS		0x08	/* Masked interrupt status */
#define MTU_ICR		0x0C	/* Interrupt clear register */

/* per-timer registers take 0..3 as argument */
#define MTU_LR(x)	(0x10 + 0x10 * (x) + 0x00)	/* Load value */
#define MTU_VAL(x)	(0x10 + 0x10 * (x) + 0x04)	/* Current value */
#define MTU_CR(x)	(0x10 + 0x10 * (x) + 0x08)	/* Control reg */
#define MTU_BGLR(x)	(0x10 + 0x10 * (x) + 0x0c)	/* At next overflow */

/* bits for the control register */
#define MTU_CRn_ENA		0x80
#define MTU_CRn_PERIODIC	0x40	/* if 0 = free-running */
#define MTU_CRn_PRESCALE_MASK	0x0c
#define MTU_CRn_PRESCALE_1		0x00
#define MTU_CRn_PRESCALE_16		0x04
#define MTU_CRn_PRESCALE_256		0x08
#define MTU_CRn_32BITS		0x02
#define MTU_CRn_ONESHOT		0x01	/* if 0 = wraps reloading from BGLR*/

/* Other registers are usual amba/primecell registers, currently not used */
#define MTU_ITCR	0xff0
#define MTU_ITOP	0xff4

#define MTU_PERIPH_ID0	0xfe0
#define MTU_PERIPH_ID1	0xfe4
#define MTU_PERIPH_ID2	0xfe8
#define MTU_PERIPH_ID3	0xfeC

#define MTU_PCELL0	0xff0
#define MTU_PCELL1	0xff4
#define MTU_PCELL2	0xff8
#define MTU_PCELL3	0xffC

static void __iomem *mtu_base;
static bool clkevt_periodic;
static u32 clk_prescale;
static u32 nmdk_cycle;		/* write-once */
static struct delay_timer mtu_delay_timer;

/*
 * Override the global weak sched_clock symbol with this
 * local implementation which uses the clocksource to get some
 * better resolution when scheduling the kernel.
 */
static u64 notrace nomadik_read_sched_clock(void)
{
	if (unlikely(!mtu_base))
		return 0;

	return -readl(mtu_base + MTU_VAL(0));
}

static unsigned long nmdk_timer_read_current_timer(void)
{
	return ~readl_relaxed(mtu_base + MTU_VAL(0));
}

/* Clockevent device: use one-shot mode */
static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev)
{
	writel(1 << 1, mtu_base + MTU_IMSC);
	writel(evt, mtu_base + MTU_LR(1));
	/* Load highest value, enable device, enable interrupts */
	writel(MTU_CRn_ONESHOT | clk_prescale |
	       MTU_CRn_32BITS | MTU_CRn_ENA,
	       mtu_base + MTU_CR(1));

	return 0;
}

static void nmdk_clkevt_reset(void)
{
	if (clkevt_periodic) {
		/* Timer: configure load and background-load, and fire it up */
		writel(nmdk_cycle, mtu_base + MTU_LR(1));
		writel(nmdk_cycle, mtu_base + MTU_BGLR(1));

		writel(MTU_CRn_PERIODIC | clk_prescale |
		       MTU_CRn_32BITS | MTU_CRn_ENA,
		       mtu_base + MTU_CR(1));
		writel(1 << 1, mtu_base + MTU_IMSC);
	} else {
		/* Generate an interrupt to start the clockevent again */
		(void) nmdk_clkevt_next(nmdk_cycle, NULL);
	}
}

static int nmdk_clkevt_shutdown(struct clock_event_device *evt)
{
	writel(0, mtu_base + MTU_IMSC);
	/* disable timer */
	writel(0, mtu_base + MTU_CR(1));
	/* load some high default value */
	writel(0xffffffff, mtu_base + MTU_LR(1));
	return 0;
}

static int nmdk_clkevt_set_oneshot(struct clock_event_device *evt)
{
	clkevt_periodic = false;
	return 0;
}

static int nmdk_clkevt_set_periodic(struct clock_event_device *evt)
{
	clkevt_periodic = true;
	nmdk_clkevt_reset();
	return 0;
}

static void nmdk_clksrc_reset(void)
{
	/* Disable */
	writel(0, mtu_base + MTU_CR(0));

	/* ClockSource: configure load and background-load, and fire it up */
	writel(nmdk_cycle, mtu_base + MTU_LR(0));
	writel(nmdk_cycle, mtu_base + MTU_BGLR(0));

	writel(clk_prescale | MTU_CRn_32BITS | MTU_CRn_ENA,
	       mtu_base + MTU_CR(0));
}

static void nmdk_clkevt_resume(struct clock_event_device *cedev)
{
	nmdk_clkevt_reset();
	nmdk_clksrc_reset();
}

static struct clock_event_device nmdk_clkevt = {
	.name			= "mtu_1",
	.features		= CLOCK_EVT_FEAT_ONESHOT |
				  CLOCK_EVT_FEAT_PERIODIC |
				  CLOCK_EVT_FEAT_DYNIRQ,
	.rating			= 200,
	.set_state_shutdown	= nmdk_clkevt_shutdown,
	.set_state_periodic	= nmdk_clkevt_set_periodic,
	.set_state_oneshot	= nmdk_clkevt_set_oneshot,
	.set_next_event		= nmdk_clkevt_next,
	.resume			= nmdk_clkevt_resume,
};

/*
 * IRQ Handler for timer 1 of the MTU block.
 */
static irqreturn_t nmdk_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evdev = dev_id;

	writel(1 << 1, mtu_base + MTU_ICR); /* Interrupt clear reg */
	evdev->event_handler(evdev);
	return IRQ_HANDLED;
}

static struct irqaction nmdk_timer_irq = {
	.name		= "Nomadik Timer Tick",
	.flags		= IRQF_TIMER,
	.handler	= nmdk_timer_interrupt,
	.dev_id		= &nmdk_clkevt,
};

static int __init nmdk_timer_init(void __iomem *base, int irq,
				   struct clk *pclk, struct clk *clk)
{
	unsigned long rate;
	int ret;

	mtu_base = base;

	BUG_ON(clk_prepare_enable(pclk));
	BUG_ON(clk_prepare_enable(clk));

	/*
	 * Tick rate is 2.4MHz for Nomadik and 2.4Mhz, 100MHz or 133 MHz
	 * for ux500.
	 * Use a divide-by-16 counter if the tick rate is more than 32MHz.
	 * At 32 MHz, the timer (with 32 bit counter) can be programmed
	 * to wake-up at a max 127s a head in time. Dividing a 2.4 MHz timer
	 * with 16 gives too low timer resolution.
	 */
	rate = clk_get_rate(clk);
	if (rate > 32000000) {
		rate /= 16;
		clk_prescale = MTU_CRn_PRESCALE_16;
	} else {
		clk_prescale = MTU_CRn_PRESCALE_1;
	}

	/* Cycles for periodic mode */
	nmdk_cycle = DIV_ROUND_CLOSEST(rate, HZ);


	/* Timer 0 is the free running clocksource */
	nmdk_clksrc_reset();

	ret = clocksource_mmio_init(mtu_base + MTU_VAL(0), "mtu_0",
				    rate, 200, 32, clocksource_mmio_readl_down);
	if (ret) {
		pr_err("timer: failed to initialize clock source %s\n", "mtu_0");
		return ret;
	}

	sched_clock_register(nomadik_read_sched_clock, 32, rate);

	/* Timer 1 is used for events, register irq and clockevents */
	setup_irq(irq, &nmdk_timer_irq);
	nmdk_clkevt.cpumask = cpumask_of(0);
	nmdk_clkevt.irq = irq;
	clockevents_config_and_register(&nmdk_clkevt, rate, 2, 0xffffffffU);

	mtu_delay_timer.read_current_timer = &nmdk_timer_read_current_timer;
	mtu_delay_timer.freq = rate;
	register_current_timer_delay(&mtu_delay_timer);

	return 0;
}

static int __init nmdk_timer_of_init(struct device_node *node)
{
	struct clk *pclk;
	struct clk *clk;
	void __iomem *base;
	int irq;

	base = of_iomap(node, 0);
	if (!base) {
		pr_err("Can't remap registers\n");
		return -ENXIO;
	}

	pclk = of_clk_get_by_name(node, "apb_pclk");
	if (IS_ERR(pclk)) {
		pr_err("could not get apb_pclk\n");
		return PTR_ERR(pclk);
	}

	clk = of_clk_get_by_name(node, "timclk");
	if (IS_ERR(clk)) {
		pr_err("could not get timclk\n");
		return PTR_ERR(clk);
	}

	irq = irq_of_parse_and_map(node, 0);
	if (irq <= 0) {
		pr_err("Can't parse IRQ\n");
		return -EINVAL;
	}

	return nmdk_timer_init(base, irq, pclk, clk);
}
TIMER_OF_DECLARE(nomadik_mtu, "st,nomadik-mtu",
		       nmdk_timer_of_init);
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
28ad94ec	2	/*
28ad94ec	3	* Copyright (C) 2008 STMicroelectronics
b102c01f	4	* Copyright (C) 2010 Alessandro Rubini
8fbb97a2	5	* Copyright (C) 2010 Linus Walleij for ST-Ericsson
28ad94ec AR	6	*/
	7	#include <linux/init.h>
	8	#include <linux/interrupt.h>
	9	#include <linux/irq.h>
	10	#include <linux/io.h>
	11	#include <linux/clockchips.h>
694e33a7	12	#include <linux/clocksource.h>
c7785ea0 RV	13	#include <linux/of_address.h>
	14	#include <linux/of_irq.h>
	15	#include <linux/of_platform.h>
ba327b1e	16	#include <linux/clk.h>
28ad94ec	17	#include <linux/jiffies.h>
6f179b72	18	#include <linux/delay.h>
ba327b1e	19	#include <linux/err.h>
38ff87f7	20	#include <linux/sched_clock.h>
28ad94ec	21	#include <asm/mach/time.h>
28ad94ec	22
05387a9f JA	23	/*
	24	* The MTU device hosts four different counters, with 4 set of
	25	* registers. These are register names.
	26	*/
	27
	28	#define MTU_IMSC 0x00 /* Interrupt mask set/clear */
	29	#define MTU_RIS 0x04 /* Raw interrupt status */
	30	#define MTU_MIS 0x08 /* Masked interrupt status */
	31	#define MTU_ICR 0x0C /* Interrupt clear register */
	32
	33	/* per-timer registers take 0..3 as argument */
	34	#define MTU_LR(x) (0x10 + 0x10 * (x) + 0x00) /* Load value */
	35	#define MTU_VAL(x) (0x10 + 0x10 * (x) + 0x04) /* Current value */
	36	#define MTU_CR(x) (0x10 + 0x10 * (x) + 0x08) /* Control reg */
	37	#define MTU_BGLR(x) (0x10 + 0x10 * (x) + 0x0c) /* At next overflow */
	38
	39	/* bits for the control register */
	40	#define MTU_CRn_ENA 0x80
	41	#define MTU_CRn_PERIODIC 0x40 /* if 0 = free-running */
	42	#define MTU_CRn_PRESCALE_MASK 0x0c
	43	#define MTU_CRn_PRESCALE_1 0x00
	44	#define MTU_CRn_PRESCALE_16 0x04
	45	#define MTU_CRn_PRESCALE_256 0x08
	46	#define MTU_CRn_32BITS 0x02
	47	#define MTU_CRn_ONESHOT 0x01 /* if 0 = wraps reloading from BGLR*/
	48
	49	/* Other registers are usual amba/primecell registers, currently not used */
	50	#define MTU_ITCR 0xff0
	51	#define MTU_ITOP 0xff4
	52
	53	#define MTU_PERIPH_ID0 0xfe0
	54	#define MTU_PERIPH_ID1 0xfe4
	55	#define MTU_PERIPH_ID2 0xfe8
	56	#define MTU_PERIPH_ID3 0xfeC
	57
	58	#define MTU_PCELL0 0xff0
	59	#define MTU_PCELL1 0xff4
	60	#define MTU_PCELL2 0xff8
	61	#define MTU_PCELL3 0xffC
28ad94ec	62
b9576623	63	static void __iomem *mtu_base;
2f73a068 JA	64	static bool clkevt_periodic;
	65	static u32 clk_prescale;
	66	static u32 nmdk_cycle; /* write-once */
6f179b72	67	static struct delay_timer mtu_delay_timer;
2f73a068	68
2a847513 LW	69	/*
	70	* Override the global weak sched_clock symbol with this
	71	* local implementation which uses the clocksource to get some
8fbb97a2	72	* better resolution when scheduling the kernel.
2a847513	73	*/
e25bc5f5	74	static u64 notrace nomadik_read_sched_clock(void)
2a847513	75	{
8fbb97a2 LW	76	if (unlikely(!mtu_base))
	77	return 0;
	78
2f0778af	79	return -readl(mtu_base + MTU_VAL(0));
2a847513	80	}
2f73a068	81
6f179b72 FB	82	static unsigned long nmdk_timer_read_current_timer(void)
	83	{
	84	return ~readl_relaxed(mtu_base + MTU_VAL(0));
	85	}
	86
b102c01f	87	/* Clockevent device: use one-shot mode */
2f73a068 JA	88	static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev)
	89	{
	90	writel(1 << 1, mtu_base + MTU_IMSC);
	91	writel(evt, mtu_base + MTU_LR(1));
	92	/* Load highest value, enable device, enable interrupts */
	93	writel(MTU_CRn_ONESHOT \| clk_prescale \|
	94	MTU_CRn_32BITS \| MTU_CRn_ENA,
	95	mtu_base + MTU_CR(1));
	96
	97	return 0;
	98	}
	99
7172c19a	100	static void nmdk_clkevt_reset(void)
2f73a068 JA	101	{
2f73a068 JA	102	if (clkevt_periodic) {
2f73a068 JA	103	/* Timer: configure load and background-load, and fire it up */
	104	writel(nmdk_cycle, mtu_base + MTU_LR(1));
	105	writel(nmdk_cycle, mtu_base + MTU_BGLR(1));
	106
	107	writel(MTU_CRn_PERIODIC \| clk_prescale \|
	108	MTU_CRn_32BITS \| MTU_CRn_ENA,
	109	mtu_base + MTU_CR(1));
	110	writel(1 << 1, mtu_base + MTU_IMSC);
	111	} else {
	112	/* Generate an interrupt to start the clockevent again */
	113	(void) nmdk_clkevt_next(nmdk_cycle, NULL);
	114	}
	115	}
	116
9b0af699	117	static int nmdk_clkevt_shutdown(struct clock_event_device *evt)
28ad94ec	118	{
9b0af699 VK	119	writel(0, mtu_base + MTU_IMSC);
	120	/* disable timer */
	121	writel(0, mtu_base + MTU_CR(1));
	122	/* load some high default value */
	123	writel(0xffffffff, mtu_base + MTU_LR(1));
	124	return 0;
	125	}
	126
	127	static int nmdk_clkevt_set_oneshot(struct clock_event_device *evt)
	128	{
	129	clkevt_periodic = false;
	130	return 0;
	131	}
	132
	133	static int nmdk_clkevt_set_periodic(struct clock_event_device *evt)
	134	{
	135	clkevt_periodic = true;
	136	nmdk_clkevt_reset();
	137	return 0;
28ad94ec AR	138	}
28ad94ec AR	139
7172c19a	140	static void nmdk_clksrc_reset(void)
8726e96f SW	141	{
	142	/* Disable */
	143	writel(0, mtu_base + MTU_CR(0));
	144
	145	/* ClockSource: configure load and background-load, and fire it up */
	146	writel(nmdk_cycle, mtu_base + MTU_LR(0));
	147	writel(nmdk_cycle, mtu_base + MTU_BGLR(0));
	148
	149	writel(clk_prescale \| MTU_CRn_32BITS \| MTU_CRn_ENA,
	150	mtu_base + MTU_CR(0));
	151	}
	152
	153	static void nmdk_clkevt_resume(struct clock_event_device *cedev)
	154	{
	155	nmdk_clkevt_reset();
	156	nmdk_clksrc_reset();
	157	}
	158
28ad94ec	159	static struct clock_event_device nmdk_clkevt = {
9b0af699 VK	160	.name = "mtu_1",
	161	.features = CLOCK_EVT_FEAT_ONESHOT \|
	162	CLOCK_EVT_FEAT_PERIODIC \|
	163	CLOCK_EVT_FEAT_DYNIRQ,
	164	.rating = 200,
	165	.set_state_shutdown = nmdk_clkevt_shutdown,
	166	.set_state_periodic = nmdk_clkevt_set_periodic,
	167	.set_state_oneshot = nmdk_clkevt_set_oneshot,
	168	.set_next_event = nmdk_clkevt_next,
	169	.resume = nmdk_clkevt_resume,
28ad94ec AR	170	};
	171
	172	/*
b102c01f	173	* IRQ Handler for timer 1 of the MTU block.
28ad94ec AR	174	*/
	175	static irqreturn_t nmdk_timer_interrupt(int irq, void *dev_id)
	176	{
b102c01f	177	struct clock_event_device *evdev = dev_id;
28ad94ec	178
b102c01f AR	179	writel(1 << 1, mtu_base + MTU_ICR); /* Interrupt clear reg */
b102c01f AR	180	evdev->event_handler(evdev);
28ad94ec AR	181	return IRQ_HANDLED;
	182	}
	183
28ad94ec AR	184	static struct irqaction nmdk_timer_irq = {
28ad94ec AR	185	.name = "Nomadik Timer Tick",
38c30a84	186	.flags = IRQF_TIMER,
28ad94ec	187	.handler = nmdk_timer_interrupt,
b102c01f	188	.dev_id = &nmdk_clkevt,
28ad94ec AR	189	};
28ad94ec AR	190
e46105af	191	static int __init nmdk_timer_init(void __iomem *base, int irq,
7172c19a	192	struct clk pclk, struct clk clk)
28ad94ec	193	{
28ad94ec	194	unsigned long rate;
e46105af	195	int ret;
ba327b1e	196
b9576623	197	mtu_base = base;
16defa66	198
c7785ea0 RV	199	BUG_ON(clk_prepare_enable(pclk));
c7785ea0 RV	200	BUG_ON(clk_prepare_enable(clk));
b102c01f AR	201
b102c01f AR	202	/*
a0719f52 LW	203	* Tick rate is 2.4MHz for Nomadik and 2.4Mhz, 100MHz or 133 MHz
	204	* for ux500.
	205	* Use a divide-by-16 counter if the tick rate is more than 32MHz.
	206	* At 32 MHz, the timer (with 32 bit counter) can be programmed
	207	* to wake-up at a max 127s a head in time. Dividing a 2.4 MHz timer
	208	* with 16 gives too low timer resolution.
b102c01f	209	*/
c7785ea0	210	rate = clk_get_rate(clk);
a0719f52	211	if (rate > 32000000) {
b102c01f	212	rate /= 16;
2f73a068	213	clk_prescale = MTU_CRn_PRESCALE_16;
b102c01f	214	} else {
2f73a068	215	clk_prescale = MTU_CRn_PRESCALE_1;
b102c01f	216	}
28ad94ec	217
21366831 LW	218	/* Cycles for periodic mode */
21366831 LW	219	nmdk_cycle = DIV_ROUND_CLOSEST(rate, HZ);
2f73a068 JA	220
2f73a068 JA	221
b102c01f	222	/* Timer 0 is the free running clocksource */
2f73a068	223	nmdk_clksrc_reset();
28ad94ec	224
e46105af DL	225	ret = clocksource_mmio_init(mtu_base + MTU_VAL(0), "mtu_0",
	226	rate, 200, 32, clocksource_mmio_readl_down);
	227	if (ret) {
	228	pr_err("timer: failed to initialize clock source %s\n", "mtu_0");
	229	return ret;
	230	}
2f0778af	231
e25bc5f5	232	sched_clock_register(nomadik_read_sched_clock, 32, rate);
2f0778af	233
a3b86a6d	234	/* Timer 1 is used for events, register irq and clockevents */
0813069d	235	setup_irq(irq, &nmdk_timer_irq);
a3b86a6d	236	nmdk_clkevt.cpumask = cpumask_of(0);
00f4e13c	237	nmdk_clkevt.irq = irq;
a3b86a6d	238	clockevents_config_and_register(&nmdk_clkevt, rate, 2, 0xffffffffU);
6f179b72 FB	239
	240	mtu_delay_timer.read_current_timer = &nmdk_timer_read_current_timer;
	241	mtu_delay_timer.freq = rate;
	242	register_current_timer_delay(&mtu_delay_timer);
e46105af DL	243
e46105af DL	244	return 0;
28ad94ec	245	}
c7785ea0	246
e46105af	247	static int __init nmdk_timer_of_init(struct device_node *node)
c7785ea0	248	{
c7785ea0 RV	249	struct clk *pclk;
	250	struct clk *clk;
	251	void __iomem *base;
	252	int irq;
	253
c7785ea0	254	base = of_iomap(node, 0);
e46105af	255	if (!base) {
ac9ce6d1	256	pr_err("Can't remap registers\n");
e46105af DL	257	return -ENXIO;
e46105af DL	258	}
c7785ea0 RV	259
c7785ea0 RV	260	pclk = of_clk_get_by_name(node, "apb_pclk");
e46105af	261	if (IS_ERR(pclk)) {
ac9ce6d1	262	pr_err("could not get apb_pclk\n");
e46105af DL	263	return PTR_ERR(pclk);
e46105af DL	264	}
c7785ea0 RV	265
c7785ea0 RV	266	clk = of_clk_get_by_name(node, "timclk");
e46105af	267	if (IS_ERR(clk)) {
ac9ce6d1	268	pr_err("could not get timclk\n");
e46105af DL	269	return PTR_ERR(clk);
e46105af DL	270	}
c7785ea0 RV	271
c7785ea0 RV	272	irq = irq_of_parse_and_map(node, 0);
e46105af	273	if (irq <= 0) {
ac9ce6d1	274	pr_err("Can't parse IRQ\n");
e46105af DL	275	return -EINVAL;
e46105af DL	276	}
c7785ea0	277
e46105af	278	return nmdk_timer_init(base, irq, pclk, clk);
c7785ea0	279	}
17273395	280	TIMER_OF_DECLARE(nomadik_mtu, "st,nomadik-mtu",
c7785ea0	281	nmdk_timer_of_init);