[linux-2.6-block.git] / drivers / clocksource / mxs_timer.c

// SPDX-License-Identifier: GPL-2.0+
//
//  Copyright (C) 2000-2001 Deep Blue Solutions
//  Copyright (C) 2002 Shane Nay (shane@minirl.com)
//  Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
//  Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
//  Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.

#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/clockchips.h>
#include <linux/clk.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/stmp_device.h>
#include <linux/sched_clock.h>

/*
 * There are 2 versions of the timrot on Freescale MXS-based SoCs.
 * The v1 on MX23 only gets 16 bits counter, while v2 on MX28
 * extends the counter to 32 bits.
 *
 * The implementation uses two timers, one for clock_event and
 * another for clocksource. MX28 uses timrot 0 and 1, while MX23
 * uses 0 and 2.
 */

#define MX23_TIMROT_VERSION_OFFSET	0x0a0
#define MX28_TIMROT_VERSION_OFFSET	0x120
#define BP_TIMROT_MAJOR_VERSION		24
#define BV_TIMROT_VERSION_1		0x01
#define BV_TIMROT_VERSION_2		0x02
#define timrot_is_v1()	(timrot_major_version == BV_TIMROT_VERSION_1)

/*
 * There are 4 registers for each timrotv2 instance, and 2 registers
 * for each timrotv1. So address step 0x40 in macros below strides
 * one instance of timrotv2 while two instances of timrotv1.
 *
 * As the result, HW_TIMROT_XXXn(1) defines the address of timrot1
 * on MX28 while timrot2 on MX23.
 */
/* common between v1 and v2 */
#define HW_TIMROT_ROTCTRL		0x00
#define HW_TIMROT_TIMCTRLn(n)		(0x20 + (n) * 0x40)
/* v1 only */
#define HW_TIMROT_TIMCOUNTn(n)		(0x30 + (n) * 0x40)
/* v2 only */
#define HW_TIMROT_RUNNING_COUNTn(n)	(0x30 + (n) * 0x40)
#define HW_TIMROT_FIXED_COUNTn(n)	(0x40 + (n) * 0x40)

#define BM_TIMROT_TIMCTRLn_RELOAD	(1 << 6)
#define BM_TIMROT_TIMCTRLn_UPDATE	(1 << 7)
#define BM_TIMROT_TIMCTRLn_IRQ_EN	(1 << 14)
#define BM_TIMROT_TIMCTRLn_IRQ		(1 << 15)
#define BP_TIMROT_TIMCTRLn_SELECT	0
#define BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL		0x8
#define BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL		0xb
#define BV_TIMROTv2_TIMCTRLn_SELECT__TICK_ALWAYS	0xf

static struct clock_event_device mxs_clockevent_device;

static void __iomem *mxs_timrot_base;
static u32 timrot_major_version;

static inline void timrot_irq_disable(void)
{
	__raw_writel(BM_TIMROT_TIMCTRLn_IRQ_EN, mxs_timrot_base +
		     HW_TIMROT_TIMCTRLn(0) + STMP_OFFSET_REG_CLR);
}

static inline void timrot_irq_enable(void)
{
	__raw_writel(BM_TIMROT_TIMCTRLn_IRQ_EN, mxs_timrot_base +
		     HW_TIMROT_TIMCTRLn(0) + STMP_OFFSET_REG_SET);
}

static void timrot_irq_acknowledge(void)
{
	__raw_writel(BM_TIMROT_TIMCTRLn_IRQ, mxs_timrot_base +
		     HW_TIMROT_TIMCTRLn(0) + STMP_OFFSET_REG_CLR);
}

static u64 timrotv1_get_cycles(struct clocksource *cs)
{
	return ~((__raw_readl(mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1))
			& 0xffff0000) >> 16);
}

static int timrotv1_set_next_event(unsigned long evt,
					struct clock_event_device *dev)
{
	/* timrot decrements the count */
	__raw_writel(evt, mxs_timrot_base + HW_TIMROT_TIMCOUNTn(0));

	return 0;
}

static int timrotv2_set_next_event(unsigned long evt,
					struct clock_event_device *dev)
{
	/* timrot decrements the count */
	__raw_writel(evt, mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(0));

	return 0;
}

static irqreturn_t mxs_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;

	timrot_irq_acknowledge();
	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static void mxs_irq_clear(char *state)
{
	/* Disable interrupt in timer module */
	timrot_irq_disable();

	/* Set event time into the furthest future */
	if (timrot_is_v1())
		__raw_writel(0xffff, mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1));
	else
		__raw_writel(0xffffffff,
			     mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(1));

	/* Clear pending interrupt */
	timrot_irq_acknowledge();

#ifdef DEBUG
	pr_info("%s: changing mode to %s\n", __func__, state)
#endif /* DEBUG */
}

static int mxs_shutdown(struct clock_event_device *evt)
{
	mxs_irq_clear("shutdown");

	return 0;
}

static int mxs_set_oneshot(struct clock_event_device *evt)
{
	if (clockevent_state_oneshot(evt))
		mxs_irq_clear("oneshot");
	timrot_irq_enable();
	return 0;
}

static struct clock_event_device mxs_clockevent_device = {
	.name			= "mxs_timrot",
	.features		= CLOCK_EVT_FEAT_ONESHOT,
	.set_state_shutdown	= mxs_shutdown,
	.set_state_oneshot	= mxs_set_oneshot,
	.tick_resume		= mxs_shutdown,
	.set_next_event		= timrotv2_set_next_event,
	.rating			= 200,
};

static int __init mxs_clockevent_init(struct clk *timer_clk)
{
	if (timrot_is_v1())
		mxs_clockevent_device.set_next_event = timrotv1_set_next_event;
	mxs_clockevent_device.cpumask = cpumask_of(0);
	clockevents_config_and_register(&mxs_clockevent_device,
					clk_get_rate(timer_clk),
					timrot_is_v1() ? 0xf : 0x2,
					timrot_is_v1() ? 0xfffe : 0xfffffffe);

	return 0;
}

static struct clocksource clocksource_mxs = {
	.name		= "mxs_timer",
	.rating		= 200,
	.read		= timrotv1_get_cycles,
	.mask		= CLOCKSOURCE_MASK(16),
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
};

static u64 notrace mxs_read_sched_clock_v2(void)
{
	return ~readl_relaxed(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1));
}

static int __init mxs_clocksource_init(struct clk *timer_clk)
{
	unsigned int c = clk_get_rate(timer_clk);

	if (timrot_is_v1())
		clocksource_register_hz(&clocksource_mxs, c);
	else {
		clocksource_mmio_init(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1),
			"mxs_timer", c, 200, 32, clocksource_mmio_readl_down);
		sched_clock_register(mxs_read_sched_clock_v2, 32, c);
	}

	return 0;
}

static int __init mxs_timer_init(struct device_node *np)
{
	struct clk *timer_clk;
	int irq, ret;

	mxs_timrot_base = of_iomap(np, 0);
	WARN_ON(!mxs_timrot_base);

	timer_clk = of_clk_get(np, 0);
	if (IS_ERR(timer_clk)) {
		pr_err("%s: failed to get clk\n", __func__);
		return PTR_ERR(timer_clk);
	}

	ret = clk_prepare_enable(timer_clk);
	if (ret)
		return ret;

	/*
	 * Initialize timers to a known state
	 */
	stmp_reset_block(mxs_timrot_base + HW_TIMROT_ROTCTRL);

	/* get timrot version */
	timrot_major_version = __raw_readl(mxs_timrot_base +
			(of_device_is_compatible(np, "fsl,imx23-timrot") ?
						MX23_TIMROT_VERSION_OFFSET :
						MX28_TIMROT_VERSION_OFFSET));
	timrot_major_version >>= BP_TIMROT_MAJOR_VERSION;

	/* one for clock_event */
	__raw_writel((timrot_is_v1() ?
			BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL :
			BV_TIMROTv2_TIMCTRLn_SELECT__TICK_ALWAYS) |
			BM_TIMROT_TIMCTRLn_UPDATE |
			BM_TIMROT_TIMCTRLn_IRQ_EN,
			mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));

	/* another for clocksource */
	__raw_writel((timrot_is_v1() ?
			BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL :
			BV_TIMROTv2_TIMCTRLn_SELECT__TICK_ALWAYS) |
			BM_TIMROT_TIMCTRLn_RELOAD,
			mxs_timrot_base + HW_TIMROT_TIMCTRLn(1));

	/* set clocksource timer fixed count to the maximum */
	if (timrot_is_v1())
		__raw_writel(0xffff,
			mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1));
	else
		__raw_writel(0xffffffff,
			mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(1));

	/* init and register the timer to the framework */
	ret = mxs_clocksource_init(timer_clk);
	if (ret)
		return ret;

	ret = mxs_clockevent_init(timer_clk);
	if (ret)
		return ret;

	/* Make irqs happen */
	irq = irq_of_parse_and_map(np, 0);
	if (irq <= 0)
		return -EINVAL;

	return request_irq(irq, mxs_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL,
			   "MXS Timer Tick", &mxs_clockevent_device);
}
TIMER_OF_DECLARE(mxs, "fsl,timrot", mxs_timer_init);
Commit	Line	Data
e45e778f FE	1	// SPDX-License-Identifier: GPL-2.0+
	2	//
	3	// Copyright (C) 2000-2001 Deep Blue Solutions
	4	// Copyright (C) 2002 Shane Nay (shane@minirl.com)
	5	// Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
	6	// Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
	7	// Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
4e472096	8
39d1367e	9	#include <linux/err.h>
4e472096 SG	10	#include <linux/interrupt.h>
	11	#include <linux/irq.h>
	12	#include <linux/clockchips.h>
	13	#include <linux/clk.h>
eeca6e60	14	#include <linux/of.h>
be35bd2b	15	#include <linux/of_address.h>
eeca6e60	16	#include <linux/of_irq.h>
7a9c39f7	17	#include <linux/stmp_device.h>
38ff87f7	18	#include <linux/sched_clock.h>
4e472096	19
4e472096 SG	20	/*
	21	* There are 2 versions of the timrot on Freescale MXS-based SoCs.
	22	* The v1 on MX23 only gets 16 bits counter, while v2 on MX28
	23	* extends the counter to 32 bits.
	24	*
	25	* The implementation uses two timers, one for clock_event and
	26	* another for clocksource. MX28 uses timrot 0 and 1, while MX23
	27	* uses 0 and 2.
	28	*/
	29
	30	#define MX23_TIMROT_VERSION_OFFSET 0x0a0
	31	#define MX28_TIMROT_VERSION_OFFSET 0x120
	32	#define BP_TIMROT_MAJOR_VERSION 24
	33	#define BV_TIMROT_VERSION_1 0x01
	34	#define BV_TIMROT_VERSION_2 0x02
	35	#define timrot_is_v1() (timrot_major_version == BV_TIMROT_VERSION_1)
	36
	37	/*
	38	* There are 4 registers for each timrotv2 instance, and 2 registers
	39	* for each timrotv1. So address step 0x40 in macros below strides
	40	* one instance of timrotv2 while two instances of timrotv1.
	41	*
	42	* As the result, HW_TIMROT_XXXn(1) defines the address of timrot1
	43	* on MX28 while timrot2 on MX23.
	44	*/
	45	/* common between v1 and v2 */
	46	#define HW_TIMROT_ROTCTRL 0x00
	47	#define HW_TIMROT_TIMCTRLn(n) (0x20 + (n) * 0x40)
	48	/* v1 only */
	49	#define HW_TIMROT_TIMCOUNTn(n) (0x30 + (n) * 0x40)
	50	/* v2 only */
	51	#define HW_TIMROT_RUNNING_COUNTn(n) (0x30 + (n) * 0x40)
	52	#define HW_TIMROT_FIXED_COUNTn(n) (0x40 + (n) * 0x40)
	53
	54	#define BM_TIMROT_TIMCTRLn_RELOAD (1 << 6)
	55	#define BM_TIMROT_TIMCTRLn_UPDATE (1 << 7)
	56	#define BM_TIMROT_TIMCTRLn_IRQ_EN (1 << 14)
	57	#define BM_TIMROT_TIMCTRLn_IRQ (1 << 15)
	58	#define BP_TIMROT_TIMCTRLn_SELECT 0
2fb318ff TH	59	#define BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL 0x8
	60	#define BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL 0xb
	61	#define BV_TIMROTv2_TIMCTRLn_SELECT__TICK_ALWAYS 0xf
4e472096 SG	62
4e472096 SG	63	static struct clock_event_device mxs_clockevent_device;
4e472096	64
be35bd2b	65	static void __iomem *mxs_timrot_base;
4e472096 SG	66	static u32 timrot_major_version;
	67
	68	static inline void timrot_irq_disable(void)
	69	{
7a9c39f7 SG	70	__raw_writel(BM_TIMROT_TIMCTRLn_IRQ_EN, mxs_timrot_base +
7a9c39f7 SG	71	HW_TIMROT_TIMCTRLn(0) + STMP_OFFSET_REG_CLR);
4e472096 SG	72	}
	73
	74	static inline void timrot_irq_enable(void)
	75	{
7a9c39f7 SG	76	__raw_writel(BM_TIMROT_TIMCTRLn_IRQ_EN, mxs_timrot_base +
7a9c39f7 SG	77	HW_TIMROT_TIMCTRLn(0) + STMP_OFFSET_REG_SET);
4e472096 SG	78	}
	79
	80	static void timrot_irq_acknowledge(void)
	81	{
7a9c39f7 SG	82	__raw_writel(BM_TIMROT_TIMCTRLn_IRQ, mxs_timrot_base +
7a9c39f7 SG	83	HW_TIMROT_TIMCTRLn(0) + STMP_OFFSET_REG_CLR);
4e472096 SG	84	}
4e472096 SG	85
a5a1d1c2	86	static u64 timrotv1_get_cycles(struct clocksource *cs)
4e472096 SG	87	{
	88	return ~((__raw_readl(mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1))
	89	& 0xffff0000) >> 16);
	90	}
	91
4e472096 SG	92	static int timrotv1_set_next_event(unsigned long evt,
	93	struct clock_event_device *dev)
	94	{
	95	/* timrot decrements the count */
	96	__raw_writel(evt, mxs_timrot_base + HW_TIMROT_TIMCOUNTn(0));
	97
	98	return 0;
	99	}
	100
	101	static int timrotv2_set_next_event(unsigned long evt,
	102	struct clock_event_device *dev)
	103	{
	104	/* timrot decrements the count */
	105	__raw_writel(evt, mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(0));
	106
	107	return 0;
	108	}
	109
	110	static irqreturn_t mxs_timer_interrupt(int irq, void *dev_id)
	111	{
	112	struct clock_event_device *evt = dev_id;
	113
	114	timrot_irq_acknowledge();
	115	evt->event_handler(evt);
	116
	117	return IRQ_HANDLED;
	118	}
	119
eb8703e2	120	static void mxs_irq_clear(char *state)
4e472096 SG	121	{
	122	/* Disable interrupt in timer module */
	123	timrot_irq_disable();
	124
eb8703e2 VK	125	/* Set event time into the furthest future */
	126	if (timrot_is_v1())
	127	__raw_writel(0xffff, mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1));
	128	else
	129	__raw_writel(0xffffffff,
	130	mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(1));
4e472096	131
eb8703e2 VK	132	/* Clear pending interrupt */
eb8703e2 VK	133	timrot_irq_acknowledge();
4e472096 SG	134
4e472096 SG	135	#ifdef DEBUG
eb8703e2	136	pr_info("%s: changing mode to %s\n", __func__, state)
4e472096	137	#endif /* DEBUG */
eb8703e2	138	}
4e472096	139
eb8703e2 VK	140	static int mxs_shutdown(struct clock_event_device *evt)
	141	{
	142	mxs_irq_clear("shutdown");
	143
	144	return 0;
	145	}
	146
	147	static int mxs_set_oneshot(struct clock_event_device *evt)
	148	{
	149	if (clockevent_state_oneshot(evt))
	150	mxs_irq_clear("oneshot");
	151	timrot_irq_enable();
	152	return 0;
4e472096 SG	153	}
	154
	155	static struct clock_event_device mxs_clockevent_device = {
eb8703e2 VK	156	.name = "mxs_timrot",
	157	.features = CLOCK_EVT_FEAT_ONESHOT,
	158	.set_state_shutdown = mxs_shutdown,
	159	.set_state_oneshot = mxs_set_oneshot,
	160	.tick_resume = mxs_shutdown,
	161	.set_next_event = timrotv2_set_next_event,
	162	.rating = 200,
4e472096 SG	163	};
	164
	165	static int __init mxs_clockevent_init(struct clk *timer_clk)
	166	{
838a2ae8	167	if (timrot_is_v1())
4e472096	168	mxs_clockevent_device.set_next_event = timrotv1_set_next_event;
838a2ae8 SG	169	mxs_clockevent_device.cpumask = cpumask_of(0);
838a2ae8 SG	170	clockevents_config_and_register(&mxs_clockevent_device,
93044fa1 TH	171	clk_get_rate(timer_clk),
93044fa1 TH	172	timrot_is_v1() ? 0xf : 0x2,
838a2ae8	173	timrot_is_v1() ? 0xfffe : 0xfffffffe);
4e472096 SG	174
	175	return 0;
	176	}
	177
	178	static struct clocksource clocksource_mxs = {
	179	.name = "mxs_timer",
	180	.rating = 200,
5c61ddcf RK	181	.read = timrotv1_get_cycles,
5c61ddcf RK	182	.mask = CLOCKSOURCE_MASK(16),
4e472096 SG	183	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	184	};
	185
fcfca6ef	186	static u64 notrace mxs_read_sched_clock_v2(void)
67948ada SM	187	{
	188	return ~readl_relaxed(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1));
	189	}
	190
4e472096 SG	191	static int __init mxs_clocksource_init(struct clk *timer_clk)
	192	{
	193	unsigned int c = clk_get_rate(timer_clk);
	194
5c61ddcf RK	195	if (timrot_is_v1())
5c61ddcf RK	196	clocksource_register_hz(&clocksource_mxs, c);
67948ada	197	else {
5c61ddcf RK	198	clocksource_mmio_init(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1),
5c61ddcf RK	199	"mxs_timer", c, 200, 32, clocksource_mmio_readl_down);
fcfca6ef	200	sched_clock_register(mxs_read_sched_clock_v2, 32, c);
67948ada	201	}
4e472096 SG	202
	203	return 0;
	204	}
	205
e1d2b9f0	206	static int __init mxs_timer_init(struct device_node *np)
4e472096	207	{
50260924	208	struct clk *timer_clk;
e1d2b9f0	209	int irq, ret;
eeca6e60	210
be35bd2b SG	211	mxs_timrot_base = of_iomap(np, 0);
	212	WARN_ON(!mxs_timrot_base);
	213
2efb9504	214	timer_clk = of_clk_get(np, 0);
50260924 SG	215	if (IS_ERR(timer_clk)) {
50260924 SG	216	pr_err("%s: failed to get clk\n", __func__);
e1d2b9f0	217	return PTR_ERR(timer_clk);
39d1367e SG	218	}
39d1367e SG	219
e1d2b9f0 DL	220	ret = clk_prepare_enable(timer_clk);
	221	if (ret)
	222	return ret;
4e472096 SG	223
	224	/*
	225	* Initialize timers to a known state
	226	*/
7a9c39f7	227	stmp_reset_block(mxs_timrot_base + HW_TIMROT_ROTCTRL);
4e472096 SG	228
	229	/* get timrot version */
	230	timrot_major_version = __raw_readl(mxs_timrot_base +
220d2f26 SG	231	(of_device_is_compatible(np, "fsl,imx23-timrot") ?
220d2f26 SG	232	MX23_TIMROT_VERSION_OFFSET :
4e472096 SG	233	MX28_TIMROT_VERSION_OFFSET));
	234	timrot_major_version >>= BP_TIMROT_MAJOR_VERSION;
	235
	236	/* one for clock_event */
	237	__raw_writel((timrot_is_v1() ?
	238	BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL :
2fb318ff	239	BV_TIMROTv2_TIMCTRLn_SELECT__TICK_ALWAYS) \|
4e472096 SG	240	BM_TIMROT_TIMCTRLn_UPDATE \|
	241	BM_TIMROT_TIMCTRLn_IRQ_EN,
	242	mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
	243
	244	/* another for clocksource */
	245	__raw_writel((timrot_is_v1() ?
	246	BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL :
2fb318ff	247	BV_TIMROTv2_TIMCTRLn_SELECT__TICK_ALWAYS) \|
4e472096 SG	248	BM_TIMROT_TIMCTRLn_RELOAD,
	249	mxs_timrot_base + HW_TIMROT_TIMCTRLn(1));
	250
	251	/* set clocksource timer fixed count to the maximum */
	252	if (timrot_is_v1())
	253	__raw_writel(0xffff,
	254	mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1));
	255	else
	256	__raw_writel(0xffffffff,
	257	mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(1));
	258
	259	/* init and register the timer to the framework */
e1d2b9f0 DL	260	ret = mxs_clocksource_init(timer_clk);
	261	if (ret)
	262	return ret;
	263
	264	ret = mxs_clockevent_init(timer_clk);
	265	if (ret)
	266	return ret;
4e472096 SG	267
4e472096 SG	268	/* Make irqs happen */
eeca6e60	269	irq = irq_of_parse_and_map(np, 0);
e1d2b9f0 DL	270	if (irq <= 0)
	271	return -EINVAL;
	272
cc2550b4	273	return request_irq(irq, mxs_timer_interrupt, IRQF_TIMER \| IRQF_IRQPOLL,
cc2550b4	274	"MXS Timer Tick", &mxs_clockevent_device);
4e472096	275	}
17273395	276	TIMER_OF_DECLARE(mxs, "fsl,timrot", mxs_timer_init);