Commit | Line | Data |
---|---|---|
778eeb1b SH |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. | |
7 | */ | |
5b4e8453 | 8 | #include <linux/clk.h> |
a331ce63 | 9 | #include <linux/clockchips.h> |
e4752dbb | 10 | #include <linux/cpu.h> |
778eeb1b | 11 | #include <linux/init.h> |
a331ce63 | 12 | #include <linux/interrupt.h> |
4060bbe9 | 13 | #include <linux/irqchip/mips-gic.h> |
e4752dbb | 14 | #include <linux/notifier.h> |
e12aa828 | 15 | #include <linux/of_irq.h> |
a331ce63 AB |
16 | #include <linux/percpu.h> |
17 | #include <linux/smp.h> | |
dfa762e1 | 18 | #include <linux/time.h> |
778eeb1b | 19 | |
5fee56e0 | 20 | static DEFINE_PER_CPU(struct clock_event_device, gic_clockevent_device); |
e4752dbb | 21 | static int gic_timer_irq; |
b0854514 | 22 | static unsigned int gic_frequency; |
a331ce63 AB |
23 | |
24 | static int gic_next_event(unsigned long delta, struct clock_event_device *evt) | |
25 | { | |
26 | u64 cnt; | |
27 | int res; | |
28 | ||
29 | cnt = gic_read_count(); | |
30 | cnt += (u64)delta; | |
31 | gic_write_cpu_compare(cnt, cpumask_first(evt->cpumask)); | |
32 | res = ((int)(gic_read_count() - cnt) >= 0) ? -ETIME : 0; | |
33 | return res; | |
34 | } | |
35 | ||
5fee56e0 | 36 | static irqreturn_t gic_compare_interrupt(int irq, void *dev_id) |
a331ce63 | 37 | { |
f7ea3060 | 38 | struct clock_event_device *cd = dev_id; |
a331ce63 AB |
39 | |
40 | gic_write_compare(gic_read_compare()); | |
a331ce63 AB |
41 | cd->event_handler(cd); |
42 | return IRQ_HANDLED; | |
43 | } | |
44 | ||
45 | struct irqaction gic_compare_irqaction = { | |
46 | .handler = gic_compare_interrupt, | |
f7ea3060 | 47 | .percpu_dev_id = &gic_clockevent_device, |
a331ce63 AB |
48 | .flags = IRQF_PERCPU | IRQF_TIMER, |
49 | .name = "timer", | |
50 | }; | |
51 | ||
2dab9093 RC |
52 | static void gic_clockevent_cpu_init(unsigned int cpu, |
53 | struct clock_event_device *cd) | |
a331ce63 | 54 | { |
a331ce63 AB |
55 | cd->name = "MIPS GIC"; |
56 | cd->features = CLOCK_EVT_FEAT_ONESHOT | | |
57 | CLOCK_EVT_FEAT_C3STOP; | |
58 | ||
a45da565 | 59 | cd->rating = 350; |
e4752dbb | 60 | cd->irq = gic_timer_irq; |
a331ce63 AB |
61 | cd->cpumask = cpumask_of(cpu); |
62 | cd->set_next_event = gic_next_event; | |
a331ce63 | 63 | |
b695d8e6 | 64 | clockevents_config_and_register(cd, gic_frequency, 0x300, 0x7fffffff); |
a331ce63 | 65 | |
e4752dbb AB |
66 | enable_percpu_irq(gic_timer_irq, IRQ_TYPE_NONE); |
67 | } | |
68 | ||
69 | static void gic_clockevent_cpu_exit(struct clock_event_device *cd) | |
70 | { | |
71 | disable_percpu_irq(gic_timer_irq); | |
72 | } | |
73 | ||
fc6a6772 EG |
74 | static void gic_update_frequency(void *data) |
75 | { | |
76 | unsigned long rate = (unsigned long)data; | |
77 | ||
78 | clockevents_update_freq(this_cpu_ptr(&gic_clockevent_device), rate); | |
79 | } | |
80 | ||
2dab9093 | 81 | static int gic_starting_cpu(unsigned int cpu) |
e4752dbb | 82 | { |
2dab9093 RC |
83 | gic_clockevent_cpu_init(cpu, this_cpu_ptr(&gic_clockevent_device)); |
84 | return 0; | |
e4752dbb AB |
85 | } |
86 | ||
fc6a6772 EG |
87 | static int gic_clk_notifier(struct notifier_block *nb, unsigned long action, |
88 | void *data) | |
89 | { | |
90 | struct clk_notifier_data *cnd = data; | |
91 | ||
92 | if (action == POST_RATE_CHANGE) | |
93 | on_each_cpu(gic_update_frequency, (void *)cnd->new_rate, 1); | |
94 | ||
95 | return NOTIFY_OK; | |
96 | } | |
97 | ||
2dab9093 RC |
98 | static int gic_dying_cpu(unsigned int cpu) |
99 | { | |
100 | gic_clockevent_cpu_exit(this_cpu_ptr(&gic_clockevent_device)); | |
101 | return 0; | |
102 | } | |
e4752dbb | 103 | |
fc6a6772 EG |
104 | static struct notifier_block gic_clk_nb = { |
105 | .notifier_call = gic_clk_notifier, | |
106 | }; | |
107 | ||
e4752dbb AB |
108 | static int gic_clockevent_init(void) |
109 | { | |
f95ac855 EG |
110 | int ret; |
111 | ||
e4752dbb AB |
112 | if (!cpu_has_counter || !gic_frequency) |
113 | return -ENXIO; | |
114 | ||
f95ac855 EG |
115 | ret = setup_percpu_irq(gic_timer_irq, &gic_compare_irqaction); |
116 | if (ret < 0) | |
117 | return ret; | |
e4752dbb | 118 | |
2dab9093 RC |
119 | cpuhp_setup_state(CPUHP_AP_MIPS_GIC_TIMER_STARTING, |
120 | "AP_MIPS_GIC_TIMER_STARTING", gic_starting_cpu, | |
121 | gic_dying_cpu); | |
a331ce63 AB |
122 | return 0; |
123 | } | |
124 | ||
778eeb1b SH |
125 | static cycle_t gic_hpt_read(struct clocksource *cs) |
126 | { | |
dfa762e1 | 127 | return gic_read_count(); |
778eeb1b SH |
128 | } |
129 | ||
130 | static struct clocksource gic_clocksource = { | |
a7f4df4e AS |
131 | .name = "GIC", |
132 | .read = gic_hpt_read, | |
133 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | |
134 | .archdata = { .vdso_clock_mode = VDSO_CLOCK_GIC }, | |
778eeb1b SH |
135 | }; |
136 | ||
d8152bf8 | 137 | static int __init __gic_clocksource_init(void) |
778eeb1b | 138 | { |
f95ac855 EG |
139 | int ret; |
140 | ||
778eeb1b | 141 | /* Set clocksource mask. */ |
387904ff | 142 | gic_clocksource.mask = CLOCKSOURCE_MASK(gic_get_count_width()); |
778eeb1b SH |
143 | |
144 | /* Calculate a somewhat reasonable rating value. */ | |
e12aa828 | 145 | gic_clocksource.rating = 200 + gic_frequency / 10000000; |
778eeb1b | 146 | |
f95ac855 EG |
147 | ret = clocksource_register_hz(&gic_clocksource, gic_frequency); |
148 | if (ret < 0) | |
149 | pr_warn("GIC: Unable to register clocksource\n"); | |
d8152bf8 DL |
150 | |
151 | return ret; | |
778eeb1b | 152 | } |
e12aa828 AB |
153 | |
154 | void __init gic_clocksource_init(unsigned int frequency) | |
155 | { | |
156 | gic_frequency = frequency; | |
157 | gic_timer_irq = MIPS_GIC_IRQ_BASE + | |
158 | GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_COMPARE); | |
159 | ||
160 | __gic_clocksource_init(); | |
67d4e669 EG |
161 | gic_clockevent_init(); |
162 | ||
163 | /* And finally start the counter */ | |
164 | gic_start_count(); | |
e12aa828 AB |
165 | } |
166 | ||
167 | static void __init gic_clocksource_of_init(struct device_node *node) | |
168 | { | |
5b4e8453 | 169 | struct clk *clk; |
fc6a6772 | 170 | int ret; |
5b4e8453 | 171 | |
d8152bf8 DL |
172 | if (!gic_present || !node->parent || |
173 | !of_device_is_compatible(node->parent, "mti,gic")) { | |
174 | pr_warn("No DT definition for the mips gic driver"); | |
175 | return -ENXIO; | |
176 | } | |
e12aa828 | 177 | |
5b4e8453 AB |
178 | clk = of_clk_get(node, 0); |
179 | if (!IS_ERR(clk)) { | |
eb811c73 EG |
180 | if (clk_prepare_enable(clk) < 0) { |
181 | pr_err("GIC failed to enable clock\n"); | |
182 | clk_put(clk); | |
d8152bf8 | 183 | return PTR_ERR(clk); |
eb811c73 EG |
184 | } |
185 | ||
5b4e8453 | 186 | gic_frequency = clk_get_rate(clk); |
5b4e8453 AB |
187 | } else if (of_property_read_u32(node, "clock-frequency", |
188 | &gic_frequency)) { | |
e12aa828 | 189 | pr_err("GIC frequency not specified.\n"); |
d8152bf8 | 190 | return -EINVAL;; |
e12aa828 AB |
191 | } |
192 | gic_timer_irq = irq_of_parse_and_map(node, 0); | |
193 | if (!gic_timer_irq) { | |
194 | pr_err("GIC timer IRQ not specified.\n"); | |
d8152bf8 | 195 | return -EINVAL;; |
e12aa828 AB |
196 | } |
197 | ||
d8152bf8 DL |
198 | ret = __gic_clocksource_init(); |
199 | if (ret) | |
200 | return ret; | |
fc6a6772 EG |
201 | |
202 | ret = gic_clockevent_init(); | |
203 | if (!ret && !IS_ERR(clk)) { | |
204 | if (clk_notifier_register(clk, &gic_clk_nb) < 0) | |
205 | pr_warn("GIC: Unable to register clock notifier\n"); | |
206 | } | |
67d4e669 EG |
207 | |
208 | /* And finally start the counter */ | |
209 | gic_start_count(); | |
d8152bf8 DL |
210 | |
211 | return 0; | |
e12aa828 | 212 | } |
177cf6e5 | 213 | CLOCKSOURCE_OF_DECLARE(mips_gic_timer, "mti,gic-timer", |
e12aa828 | 214 | gic_clocksource_of_init); |