Commit | Line | Data |
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778eeb1b SH |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. | |
7 | */ | |
5b4e8453 | 8 | #include <linux/clk.h> |
a331ce63 | 9 | #include <linux/clockchips.h> |
e4752dbb | 10 | #include <linux/cpu.h> |
778eeb1b | 11 | #include <linux/init.h> |
a331ce63 | 12 | #include <linux/interrupt.h> |
e4752dbb | 13 | #include <linux/notifier.h> |
e12aa828 | 14 | #include <linux/of_irq.h> |
a331ce63 AB |
15 | #include <linux/percpu.h> |
16 | #include <linux/smp.h> | |
dfa762e1 | 17 | #include <linux/time.h> |
e07127a0 | 18 | #include <asm/mips-cps.h> |
778eeb1b | 19 | |
5fee56e0 | 20 | static DEFINE_PER_CPU(struct clock_event_device, gic_clockevent_device); |
e4752dbb | 21 | static int gic_timer_irq; |
b0854514 | 22 | static unsigned int gic_frequency; |
a331ce63 | 23 | |
e07127a0 PB |
24 | static u64 notrace gic_read_count(void) |
25 | { | |
26 | unsigned int hi, hi2, lo; | |
27 | ||
28 | if (mips_cm_is64) | |
29 | return read_gic_counter(); | |
30 | ||
31 | do { | |
32 | hi = read_gic_counter_32h(); | |
33 | lo = read_gic_counter_32l(); | |
34 | hi2 = read_gic_counter_32h(); | |
35 | } while (hi2 != hi); | |
36 | ||
37 | return (((u64) hi) << 32) + lo; | |
38 | } | |
39 | ||
a331ce63 AB |
40 | static int gic_next_event(unsigned long delta, struct clock_event_device *evt) |
41 | { | |
f16ff2bd | 42 | int cpu = cpumask_first(evt->cpumask); |
a331ce63 AB |
43 | u64 cnt; |
44 | int res; | |
45 | ||
46 | cnt = gic_read_count(); | |
47 | cnt += (u64)delta; | |
f16ff2bd MR |
48 | if (cpu == raw_smp_processor_id()) { |
49 | write_gic_vl_compare(cnt); | |
50 | } else { | |
51 | write_gic_vl_other(mips_cm_vp_id(cpu)); | |
52 | write_gic_vo_compare(cnt); | |
53 | } | |
a331ce63 AB |
54 | res = ((int)(gic_read_count() - cnt) >= 0) ? -ETIME : 0; |
55 | return res; | |
56 | } | |
57 | ||
5fee56e0 | 58 | static irqreturn_t gic_compare_interrupt(int irq, void *dev_id) |
a331ce63 | 59 | { |
f7ea3060 | 60 | struct clock_event_device *cd = dev_id; |
a331ce63 | 61 | |
e07127a0 | 62 | write_gic_vl_compare(read_gic_vl_compare()); |
a331ce63 AB |
63 | cd->event_handler(cd); |
64 | return IRQ_HANDLED; | |
65 | } | |
66 | ||
67 | struct irqaction gic_compare_irqaction = { | |
68 | .handler = gic_compare_interrupt, | |
f7ea3060 | 69 | .percpu_dev_id = &gic_clockevent_device, |
a331ce63 AB |
70 | .flags = IRQF_PERCPU | IRQF_TIMER, |
71 | .name = "timer", | |
72 | }; | |
73 | ||
2dab9093 RC |
74 | static void gic_clockevent_cpu_init(unsigned int cpu, |
75 | struct clock_event_device *cd) | |
a331ce63 | 76 | { |
a331ce63 AB |
77 | cd->name = "MIPS GIC"; |
78 | cd->features = CLOCK_EVT_FEAT_ONESHOT | | |
79 | CLOCK_EVT_FEAT_C3STOP; | |
80 | ||
a45da565 | 81 | cd->rating = 350; |
e4752dbb | 82 | cd->irq = gic_timer_irq; |
a331ce63 AB |
83 | cd->cpumask = cpumask_of(cpu); |
84 | cd->set_next_event = gic_next_event; | |
a331ce63 | 85 | |
b695d8e6 | 86 | clockevents_config_and_register(cd, gic_frequency, 0x300, 0x7fffffff); |
a331ce63 | 87 | |
e4752dbb AB |
88 | enable_percpu_irq(gic_timer_irq, IRQ_TYPE_NONE); |
89 | } | |
90 | ||
91 | static void gic_clockevent_cpu_exit(struct clock_event_device *cd) | |
92 | { | |
93 | disable_percpu_irq(gic_timer_irq); | |
94 | } | |
95 | ||
fc6a6772 EG |
96 | static void gic_update_frequency(void *data) |
97 | { | |
98 | unsigned long rate = (unsigned long)data; | |
99 | ||
100 | clockevents_update_freq(this_cpu_ptr(&gic_clockevent_device), rate); | |
101 | } | |
102 | ||
2dab9093 | 103 | static int gic_starting_cpu(unsigned int cpu) |
e4752dbb | 104 | { |
2dab9093 RC |
105 | gic_clockevent_cpu_init(cpu, this_cpu_ptr(&gic_clockevent_device)); |
106 | return 0; | |
e4752dbb AB |
107 | } |
108 | ||
fc6a6772 EG |
109 | static int gic_clk_notifier(struct notifier_block *nb, unsigned long action, |
110 | void *data) | |
111 | { | |
112 | struct clk_notifier_data *cnd = data; | |
113 | ||
114 | if (action == POST_RATE_CHANGE) | |
115 | on_each_cpu(gic_update_frequency, (void *)cnd->new_rate, 1); | |
116 | ||
117 | return NOTIFY_OK; | |
118 | } | |
119 | ||
2dab9093 RC |
120 | static int gic_dying_cpu(unsigned int cpu) |
121 | { | |
122 | gic_clockevent_cpu_exit(this_cpu_ptr(&gic_clockevent_device)); | |
123 | return 0; | |
124 | } | |
e4752dbb | 125 | |
fc6a6772 EG |
126 | static struct notifier_block gic_clk_nb = { |
127 | .notifier_call = gic_clk_notifier, | |
128 | }; | |
129 | ||
e4752dbb AB |
130 | static int gic_clockevent_init(void) |
131 | { | |
f95ac855 EG |
132 | int ret; |
133 | ||
6982530e | 134 | if (!gic_frequency) |
e4752dbb AB |
135 | return -ENXIO; |
136 | ||
f95ac855 | 137 | ret = setup_percpu_irq(gic_timer_irq, &gic_compare_irqaction); |
2fd0c93c PB |
138 | if (ret < 0) { |
139 | pr_err("GIC timer IRQ %d setup failed: %d\n", | |
140 | gic_timer_irq, ret); | |
f95ac855 | 141 | return ret; |
2fd0c93c | 142 | } |
e4752dbb | 143 | |
2dab9093 | 144 | cpuhp_setup_state(CPUHP_AP_MIPS_GIC_TIMER_STARTING, |
73c1b41e TG |
145 | "clockevents/mips/gic/timer:starting", |
146 | gic_starting_cpu, gic_dying_cpu); | |
a331ce63 AB |
147 | return 0; |
148 | } | |
149 | ||
a5a1d1c2 | 150 | static u64 gic_hpt_read(struct clocksource *cs) |
778eeb1b | 151 | { |
dfa762e1 | 152 | return gic_read_count(); |
778eeb1b SH |
153 | } |
154 | ||
155 | static struct clocksource gic_clocksource = { | |
a7f4df4e AS |
156 | .name = "GIC", |
157 | .read = gic_hpt_read, | |
158 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | |
159 | .archdata = { .vdso_clock_mode = VDSO_CLOCK_GIC }, | |
778eeb1b SH |
160 | }; |
161 | ||
d8152bf8 | 162 | static int __init __gic_clocksource_init(void) |
778eeb1b | 163 | { |
e07127a0 | 164 | unsigned int count_width; |
f95ac855 EG |
165 | int ret; |
166 | ||
778eeb1b | 167 | /* Set clocksource mask. */ |
e07127a0 | 168 | count_width = read_gic_config() & GIC_CONFIG_COUNTBITS; |
5753405e | 169 | count_width >>= __ffs(GIC_CONFIG_COUNTBITS); |
e07127a0 PB |
170 | count_width *= 4; |
171 | count_width += 32; | |
172 | gic_clocksource.mask = CLOCKSOURCE_MASK(count_width); | |
778eeb1b SH |
173 | |
174 | /* Calculate a somewhat reasonable rating value. */ | |
e12aa828 | 175 | gic_clocksource.rating = 200 + gic_frequency / 10000000; |
778eeb1b | 176 | |
f95ac855 EG |
177 | ret = clocksource_register_hz(&gic_clocksource, gic_frequency); |
178 | if (ret < 0) | |
179 | pr_warn("GIC: Unable to register clocksource\n"); | |
d8152bf8 DL |
180 | |
181 | return ret; | |
778eeb1b | 182 | } |
e12aa828 | 183 | |
be5769e2 | 184 | static int __init gic_clocksource_of_init(struct device_node *node) |
e12aa828 | 185 | { |
5b4e8453 | 186 | struct clk *clk; |
fc6a6772 | 187 | int ret; |
5b4e8453 | 188 | |
e07127a0 | 189 | if (!mips_gic_present() || !node->parent || |
d8152bf8 | 190 | !of_device_is_compatible(node->parent, "mti,gic")) { |
ac9ce6d1 | 191 | pr_warn("No DT definition for the mips gic driver\n"); |
d8152bf8 DL |
192 | return -ENXIO; |
193 | } | |
e12aa828 | 194 | |
5b4e8453 AB |
195 | clk = of_clk_get(node, 0); |
196 | if (!IS_ERR(clk)) { | |
8c3ecd60 CJ |
197 | ret = clk_prepare_enable(clk); |
198 | if (ret < 0) { | |
eb811c73 EG |
199 | pr_err("GIC failed to enable clock\n"); |
200 | clk_put(clk); | |
8c3ecd60 | 201 | return ret; |
eb811c73 EG |
202 | } |
203 | ||
5b4e8453 | 204 | gic_frequency = clk_get_rate(clk); |
5b4e8453 AB |
205 | } else if (of_property_read_u32(node, "clock-frequency", |
206 | &gic_frequency)) { | |
e12aa828 | 207 | pr_err("GIC frequency not specified.\n"); |
ed7158ba | 208 | return -EINVAL; |
e12aa828 AB |
209 | } |
210 | gic_timer_irq = irq_of_parse_and_map(node, 0); | |
211 | if (!gic_timer_irq) { | |
212 | pr_err("GIC timer IRQ not specified.\n"); | |
ed7158ba | 213 | return -EINVAL; |
e12aa828 AB |
214 | } |
215 | ||
d8152bf8 DL |
216 | ret = __gic_clocksource_init(); |
217 | if (ret) | |
218 | return ret; | |
fc6a6772 EG |
219 | |
220 | ret = gic_clockevent_init(); | |
221 | if (!ret && !IS_ERR(clk)) { | |
222 | if (clk_notifier_register(clk, &gic_clk_nb) < 0) | |
223 | pr_warn("GIC: Unable to register clock notifier\n"); | |
224 | } | |
67d4e669 EG |
225 | |
226 | /* And finally start the counter */ | |
e07127a0 | 227 | clear_gic_config(GIC_CONFIG_COUNTSTOP); |
d8152bf8 DL |
228 | |
229 | return 0; | |
e12aa828 | 230 | } |
17273395 | 231 | TIMER_OF_DECLARE(mips_gic_timer, "mti,gic-timer", |
e12aa828 | 232 | gic_clocksource_of_init); |