Commit | Line | Data |
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778eeb1b SH |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. | |
7 | */ | |
3ca5768d MR |
8 | |
9 | #define pr_fmt(fmt) "mips-gic-timer: " fmt | |
10 | ||
5b4e8453 | 11 | #include <linux/clk.h> |
a331ce63 | 12 | #include <linux/clockchips.h> |
e4752dbb | 13 | #include <linux/cpu.h> |
778eeb1b | 14 | #include <linux/init.h> |
a331ce63 | 15 | #include <linux/interrupt.h> |
e4752dbb | 16 | #include <linux/notifier.h> |
e12aa828 | 17 | #include <linux/of_irq.h> |
a331ce63 AB |
18 | #include <linux/percpu.h> |
19 | #include <linux/smp.h> | |
dfa762e1 | 20 | #include <linux/time.h> |
e07127a0 | 21 | #include <asm/mips-cps.h> |
778eeb1b | 22 | |
5fee56e0 | 23 | static DEFINE_PER_CPU(struct clock_event_device, gic_clockevent_device); |
e4752dbb | 24 | static int gic_timer_irq; |
b0854514 | 25 | static unsigned int gic_frequency; |
a331ce63 | 26 | |
e07127a0 PB |
27 | static u64 notrace gic_read_count(void) |
28 | { | |
29 | unsigned int hi, hi2, lo; | |
30 | ||
31 | if (mips_cm_is64) | |
32 | return read_gic_counter(); | |
33 | ||
34 | do { | |
35 | hi = read_gic_counter_32h(); | |
36 | lo = read_gic_counter_32l(); | |
37 | hi2 = read_gic_counter_32h(); | |
38 | } while (hi2 != hi); | |
39 | ||
40 | return (((u64) hi) << 32) + lo; | |
41 | } | |
42 | ||
a331ce63 AB |
43 | static int gic_next_event(unsigned long delta, struct clock_event_device *evt) |
44 | { | |
f16ff2bd | 45 | int cpu = cpumask_first(evt->cpumask); |
a331ce63 AB |
46 | u64 cnt; |
47 | int res; | |
48 | ||
49 | cnt = gic_read_count(); | |
50 | cnt += (u64)delta; | |
f16ff2bd MR |
51 | if (cpu == raw_smp_processor_id()) { |
52 | write_gic_vl_compare(cnt); | |
53 | } else { | |
54 | write_gic_vl_other(mips_cm_vp_id(cpu)); | |
55 | write_gic_vo_compare(cnt); | |
56 | } | |
a331ce63 AB |
57 | res = ((int)(gic_read_count() - cnt) >= 0) ? -ETIME : 0; |
58 | return res; | |
59 | } | |
60 | ||
5fee56e0 | 61 | static irqreturn_t gic_compare_interrupt(int irq, void *dev_id) |
a331ce63 | 62 | { |
f7ea3060 | 63 | struct clock_event_device *cd = dev_id; |
a331ce63 | 64 | |
e07127a0 | 65 | write_gic_vl_compare(read_gic_vl_compare()); |
a331ce63 AB |
66 | cd->event_handler(cd); |
67 | return IRQ_HANDLED; | |
68 | } | |
69 | ||
9039de40 | 70 | static struct irqaction gic_compare_irqaction = { |
a331ce63 | 71 | .handler = gic_compare_interrupt, |
f7ea3060 | 72 | .percpu_dev_id = &gic_clockevent_device, |
a331ce63 AB |
73 | .flags = IRQF_PERCPU | IRQF_TIMER, |
74 | .name = "timer", | |
75 | }; | |
76 | ||
2dab9093 RC |
77 | static void gic_clockevent_cpu_init(unsigned int cpu, |
78 | struct clock_event_device *cd) | |
a331ce63 | 79 | { |
a331ce63 AB |
80 | cd->name = "MIPS GIC"; |
81 | cd->features = CLOCK_EVT_FEAT_ONESHOT | | |
82 | CLOCK_EVT_FEAT_C3STOP; | |
83 | ||
a45da565 | 84 | cd->rating = 350; |
e4752dbb | 85 | cd->irq = gic_timer_irq; |
a331ce63 AB |
86 | cd->cpumask = cpumask_of(cpu); |
87 | cd->set_next_event = gic_next_event; | |
a331ce63 | 88 | |
b695d8e6 | 89 | clockevents_config_and_register(cd, gic_frequency, 0x300, 0x7fffffff); |
a331ce63 | 90 | |
e4752dbb AB |
91 | enable_percpu_irq(gic_timer_irq, IRQ_TYPE_NONE); |
92 | } | |
93 | ||
94 | static void gic_clockevent_cpu_exit(struct clock_event_device *cd) | |
95 | { | |
96 | disable_percpu_irq(gic_timer_irq); | |
97 | } | |
98 | ||
fc6a6772 EG |
99 | static void gic_update_frequency(void *data) |
100 | { | |
101 | unsigned long rate = (unsigned long)data; | |
102 | ||
103 | clockevents_update_freq(this_cpu_ptr(&gic_clockevent_device), rate); | |
104 | } | |
105 | ||
2dab9093 | 106 | static int gic_starting_cpu(unsigned int cpu) |
e4752dbb | 107 | { |
2dab9093 RC |
108 | gic_clockevent_cpu_init(cpu, this_cpu_ptr(&gic_clockevent_device)); |
109 | return 0; | |
e4752dbb AB |
110 | } |
111 | ||
fc6a6772 EG |
112 | static int gic_clk_notifier(struct notifier_block *nb, unsigned long action, |
113 | void *data) | |
114 | { | |
115 | struct clk_notifier_data *cnd = data; | |
116 | ||
117 | if (action == POST_RATE_CHANGE) | |
118 | on_each_cpu(gic_update_frequency, (void *)cnd->new_rate, 1); | |
119 | ||
120 | return NOTIFY_OK; | |
121 | } | |
122 | ||
2dab9093 RC |
123 | static int gic_dying_cpu(unsigned int cpu) |
124 | { | |
125 | gic_clockevent_cpu_exit(this_cpu_ptr(&gic_clockevent_device)); | |
126 | return 0; | |
127 | } | |
e4752dbb | 128 | |
fc6a6772 EG |
129 | static struct notifier_block gic_clk_nb = { |
130 | .notifier_call = gic_clk_notifier, | |
131 | }; | |
132 | ||
e4752dbb AB |
133 | static int gic_clockevent_init(void) |
134 | { | |
f95ac855 EG |
135 | int ret; |
136 | ||
6982530e | 137 | if (!gic_frequency) |
e4752dbb AB |
138 | return -ENXIO; |
139 | ||
f95ac855 | 140 | ret = setup_percpu_irq(gic_timer_irq, &gic_compare_irqaction); |
2fd0c93c | 141 | if (ret < 0) { |
3ca5768d | 142 | pr_err("IRQ %d setup failed (%d)\n", gic_timer_irq, ret); |
f95ac855 | 143 | return ret; |
2fd0c93c | 144 | } |
e4752dbb | 145 | |
2dab9093 | 146 | cpuhp_setup_state(CPUHP_AP_MIPS_GIC_TIMER_STARTING, |
73c1b41e TG |
147 | "clockevents/mips/gic/timer:starting", |
148 | gic_starting_cpu, gic_dying_cpu); | |
a331ce63 AB |
149 | return 0; |
150 | } | |
151 | ||
a5a1d1c2 | 152 | static u64 gic_hpt_read(struct clocksource *cs) |
778eeb1b | 153 | { |
dfa762e1 | 154 | return gic_read_count(); |
778eeb1b SH |
155 | } |
156 | ||
157 | static struct clocksource gic_clocksource = { | |
a7f4df4e AS |
158 | .name = "GIC", |
159 | .read = gic_hpt_read, | |
160 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | |
161 | .archdata = { .vdso_clock_mode = VDSO_CLOCK_GIC }, | |
778eeb1b SH |
162 | }; |
163 | ||
d8152bf8 | 164 | static int __init __gic_clocksource_init(void) |
778eeb1b | 165 | { |
e07127a0 | 166 | unsigned int count_width; |
f95ac855 EG |
167 | int ret; |
168 | ||
778eeb1b | 169 | /* Set clocksource mask. */ |
e07127a0 | 170 | count_width = read_gic_config() & GIC_CONFIG_COUNTBITS; |
5753405e | 171 | count_width >>= __ffs(GIC_CONFIG_COUNTBITS); |
e07127a0 PB |
172 | count_width *= 4; |
173 | count_width += 32; | |
174 | gic_clocksource.mask = CLOCKSOURCE_MASK(count_width); | |
778eeb1b SH |
175 | |
176 | /* Calculate a somewhat reasonable rating value. */ | |
e12aa828 | 177 | gic_clocksource.rating = 200 + gic_frequency / 10000000; |
778eeb1b | 178 | |
f95ac855 EG |
179 | ret = clocksource_register_hz(&gic_clocksource, gic_frequency); |
180 | if (ret < 0) | |
3ca5768d | 181 | pr_warn("Unable to register clocksource\n"); |
d8152bf8 DL |
182 | |
183 | return ret; | |
778eeb1b | 184 | } |
e12aa828 | 185 | |
be5769e2 | 186 | static int __init gic_clocksource_of_init(struct device_node *node) |
e12aa828 | 187 | { |
5b4e8453 | 188 | struct clk *clk; |
fc6a6772 | 189 | int ret; |
5b4e8453 | 190 | |
e07127a0 | 191 | if (!mips_gic_present() || !node->parent || |
d8152bf8 | 192 | !of_device_is_compatible(node->parent, "mti,gic")) { |
3ca5768d | 193 | pr_warn("No DT definition\n"); |
d8152bf8 DL |
194 | return -ENXIO; |
195 | } | |
e12aa828 | 196 | |
5b4e8453 AB |
197 | clk = of_clk_get(node, 0); |
198 | if (!IS_ERR(clk)) { | |
8c3ecd60 CJ |
199 | ret = clk_prepare_enable(clk); |
200 | if (ret < 0) { | |
3ca5768d | 201 | pr_err("Failed to enable clock\n"); |
eb811c73 | 202 | clk_put(clk); |
8c3ecd60 | 203 | return ret; |
eb811c73 EG |
204 | } |
205 | ||
5b4e8453 | 206 | gic_frequency = clk_get_rate(clk); |
5b4e8453 AB |
207 | } else if (of_property_read_u32(node, "clock-frequency", |
208 | &gic_frequency)) { | |
3ca5768d | 209 | pr_err("Frequency not specified\n"); |
ed7158ba | 210 | return -EINVAL; |
e12aa828 AB |
211 | } |
212 | gic_timer_irq = irq_of_parse_and_map(node, 0); | |
213 | if (!gic_timer_irq) { | |
3ca5768d | 214 | pr_err("IRQ not specified\n"); |
ed7158ba | 215 | return -EINVAL; |
e12aa828 AB |
216 | } |
217 | ||
d8152bf8 DL |
218 | ret = __gic_clocksource_init(); |
219 | if (ret) | |
220 | return ret; | |
fc6a6772 EG |
221 | |
222 | ret = gic_clockevent_init(); | |
223 | if (!ret && !IS_ERR(clk)) { | |
224 | if (clk_notifier_register(clk, &gic_clk_nb) < 0) | |
3ca5768d | 225 | pr_warn("Unable to register clock notifier\n"); |
fc6a6772 | 226 | } |
67d4e669 EG |
227 | |
228 | /* And finally start the counter */ | |
e07127a0 | 229 | clear_gic_config(GIC_CONFIG_COUNTSTOP); |
d8152bf8 DL |
230 | |
231 | return 0; | |
e12aa828 | 232 | } |
17273395 | 233 | TIMER_OF_DECLARE(mips_gic_timer, "mti,gic-timer", |
e12aa828 | 234 | gic_clocksource_of_init); |