[linux-2.6-block.git] / drivers / clocksource / ingenic-timer.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Ingenic SoCs TCU IRQ driver
 * Copyright (C) 2019 Paul Cercueil <paul@crapouillou.net>
 * Copyright (C) 2020 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
 */

#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/clocksource.h>
#include <linux/interrupt.h>
#include <linux/mfd/ingenic-tcu.h>
#include <linux/mfd/syscon.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/overflow.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/sched_clock.h>

#include <dt-bindings/clock/ingenic,tcu.h>

static DEFINE_PER_CPU(call_single_data_t, ingenic_cevt_csd);

struct ingenic_soc_info {
	unsigned int num_channels;
};

struct ingenic_tcu_timer {
	unsigned int cpu;
	unsigned int channel;
	struct clock_event_device cevt;
	struct clk *clk;
	char name[8];
};

struct ingenic_tcu {
	struct regmap *map;
	struct device_node *np;
	struct clk *cs_clk;
	unsigned int cs_channel;
	struct clocksource cs;
	unsigned long pwm_channels_mask;
	struct ingenic_tcu_timer timers[];
};

static struct ingenic_tcu *ingenic_tcu;

static u64 notrace ingenic_tcu_timer_read(void)
{
	struct ingenic_tcu *tcu = ingenic_tcu;
	unsigned int count;

	regmap_read(tcu->map, TCU_REG_TCNTc(tcu->cs_channel), &count);

	return count;
}

static u64 notrace ingenic_tcu_timer_cs_read(struct clocksource *cs)
{
	return ingenic_tcu_timer_read();
}

static inline struct ingenic_tcu *
to_ingenic_tcu(struct ingenic_tcu_timer *timer)
{
	return container_of(timer, struct ingenic_tcu, timers[timer->cpu]);
}

static inline struct ingenic_tcu_timer *
to_ingenic_tcu_timer(struct clock_event_device *evt)
{
	return container_of(evt, struct ingenic_tcu_timer, cevt);
}

static int ingenic_tcu_cevt_set_state_shutdown(struct clock_event_device *evt)
{
	struct ingenic_tcu_timer *timer = to_ingenic_tcu_timer(evt);
	struct ingenic_tcu *tcu = to_ingenic_tcu(timer);

	regmap_write(tcu->map, TCU_REG_TECR, BIT(timer->channel));

	return 0;
}

static int ingenic_tcu_cevt_set_next(unsigned long next,
				     struct clock_event_device *evt)
{
	struct ingenic_tcu_timer *timer = to_ingenic_tcu_timer(evt);
	struct ingenic_tcu *tcu = to_ingenic_tcu(timer);

	if (next > 0xffff)
		return -EINVAL;

	regmap_write(tcu->map, TCU_REG_TDFRc(timer->channel), next);
	regmap_write(tcu->map, TCU_REG_TCNTc(timer->channel), 0);
	regmap_write(tcu->map, TCU_REG_TESR, BIT(timer->channel));

	return 0;
}

static void ingenic_per_cpu_event_handler(void *info)
{
	struct clock_event_device *cevt = (struct clock_event_device *) info;

	cevt->event_handler(cevt);
}

static irqreturn_t ingenic_tcu_cevt_cb(int irq, void *dev_id)
{
	struct ingenic_tcu_timer *timer = dev_id;
	struct ingenic_tcu *tcu = to_ingenic_tcu(timer);
	call_single_data_t *csd;

	regmap_write(tcu->map, TCU_REG_TECR, BIT(timer->channel));

	if (timer->cevt.event_handler) {
		csd = &per_cpu(ingenic_cevt_csd, timer->cpu);
		csd->info = (void *) &timer->cevt;
		csd->func = ingenic_per_cpu_event_handler;
		smp_call_function_single_async(timer->cpu, csd);
	}

	return IRQ_HANDLED;
}

static struct clk *ingenic_tcu_get_clock(struct device_node *np, int id)
{
	struct of_phandle_args args;

	args.np = np;
	args.args_count = 1;
	args.args[0] = id;

	return of_clk_get_from_provider(&args);
}

static int ingenic_tcu_setup_cevt(unsigned int cpu)
{
	struct ingenic_tcu *tcu = ingenic_tcu;
	struct ingenic_tcu_timer *timer = &tcu->timers[cpu];
	unsigned int timer_virq;
	struct irq_domain *domain;
	unsigned long rate;
	int err;

	timer->clk = ingenic_tcu_get_clock(tcu->np, timer->channel);
	if (IS_ERR(timer->clk))
		return PTR_ERR(timer->clk);

	err = clk_prepare_enable(timer->clk);
	if (err)
		goto err_clk_put;

	rate = clk_get_rate(timer->clk);
	if (!rate) {
		err = -EINVAL;
		goto err_clk_disable;
	}

	domain = irq_find_host(tcu->np);
	if (!domain) {
		err = -ENODEV;
		goto err_clk_disable;
	}

	timer_virq = irq_create_mapping(domain, timer->channel);
	if (!timer_virq) {
		err = -EINVAL;
		goto err_clk_disable;
	}

	snprintf(timer->name, sizeof(timer->name), "TCU%u", timer->channel);

	err = request_irq(timer_virq, ingenic_tcu_cevt_cb, IRQF_TIMER,
			  timer->name, timer);
	if (err)
		goto err_irq_dispose_mapping;

	timer->cpu = smp_processor_id();
	timer->cevt.cpumask = cpumask_of(smp_processor_id());
	timer->cevt.features = CLOCK_EVT_FEAT_ONESHOT;
	timer->cevt.name = timer->name;
	timer->cevt.rating = 200;
	timer->cevt.set_state_shutdown = ingenic_tcu_cevt_set_state_shutdown;
	timer->cevt.set_next_event = ingenic_tcu_cevt_set_next;

	clockevents_config_and_register(&timer->cevt, rate, 10, 0xffff);

	return 0;

err_irq_dispose_mapping:
	irq_dispose_mapping(timer_virq);
err_clk_disable:
	clk_disable_unprepare(timer->clk);
err_clk_put:
	clk_put(timer->clk);
	return err;
}

static int __init ingenic_tcu_clocksource_init(struct device_node *np,
					       struct ingenic_tcu *tcu)
{
	unsigned int channel = tcu->cs_channel;
	struct clocksource *cs = &tcu->cs;
	unsigned long rate;
	int err;

	tcu->cs_clk = ingenic_tcu_get_clock(np, channel);
	if (IS_ERR(tcu->cs_clk))
		return PTR_ERR(tcu->cs_clk);

	err = clk_prepare_enable(tcu->cs_clk);
	if (err)
		goto err_clk_put;

	rate = clk_get_rate(tcu->cs_clk);
	if (!rate) {
		err = -EINVAL;
		goto err_clk_disable;
	}

	/* Reset channel */
	regmap_update_bits(tcu->map, TCU_REG_TCSRc(channel),
			   0xffff & ~TCU_TCSR_RESERVED_BITS, 0);

	/* Reset counter */
	regmap_write(tcu->map, TCU_REG_TDFRc(channel), 0xffff);
	regmap_write(tcu->map, TCU_REG_TCNTc(channel), 0);

	/* Enable channel */
	regmap_write(tcu->map, TCU_REG_TESR, BIT(channel));

	cs->name = "ingenic-timer";
	cs->rating = 200;
	cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
	cs->mask = CLOCKSOURCE_MASK(16);
	cs->read = ingenic_tcu_timer_cs_read;

	err = clocksource_register_hz(cs, rate);
	if (err)
		goto err_clk_disable;

	return 0;

err_clk_disable:
	clk_disable_unprepare(tcu->cs_clk);
err_clk_put:
	clk_put(tcu->cs_clk);
	return err;
}

static const struct ingenic_soc_info jz4740_soc_info = {
	.num_channels = 8,
};

static const struct ingenic_soc_info jz4725b_soc_info = {
	.num_channels = 6,
};

static const struct of_device_id ingenic_tcu_of_match[] = {
	{ .compatible = "ingenic,jz4740-tcu", .data = &jz4740_soc_info, },
	{ .compatible = "ingenic,jz4725b-tcu", .data = &jz4725b_soc_info, },
	{ .compatible = "ingenic,jz4760-tcu", .data = &jz4740_soc_info, },
	{ .compatible = "ingenic,jz4770-tcu", .data = &jz4740_soc_info, },
	{ .compatible = "ingenic,x1000-tcu", .data = &jz4740_soc_info, },
	{ /* sentinel */ }
};

static int __init ingenic_tcu_init(struct device_node *np)
{
	const struct of_device_id *id = of_match_node(ingenic_tcu_of_match, np);
	const struct ingenic_soc_info *soc_info = id->data;
	struct ingenic_tcu_timer *timer;
	struct ingenic_tcu *tcu;
	struct regmap *map;
	unsigned int cpu;
	int ret, last_bit = -1;
	long rate;

	of_node_clear_flag(np, OF_POPULATED);

	map = device_node_to_regmap(np);
	if (IS_ERR(map))
		return PTR_ERR(map);

	tcu = kzalloc(struct_size(tcu, timers, num_possible_cpus()),
		      GFP_KERNEL);
	if (!tcu)
		return -ENOMEM;

	/*
	 * Enable all TCU channels for PWM use by default except channels 0/1,
	 * and channel 2 if target CPU is JZ4780/X2000 and SMP is selected.
	 */
	tcu->pwm_channels_mask = GENMASK(soc_info->num_channels - 1,
					 num_possible_cpus() + 1);
	of_property_read_u32(np, "ingenic,pwm-channels-mask",
			     (u32 *)&tcu->pwm_channels_mask);

	/* Verify that we have at least num_possible_cpus() + 1 free channels */
	if (hweight8(tcu->pwm_channels_mask) >
			soc_info->num_channels - num_possible_cpus() + 1) {
		pr_crit("%s: Invalid PWM channel mask: 0x%02lx\n", __func__,
			tcu->pwm_channels_mask);
		ret = -EINVAL;
		goto err_free_ingenic_tcu;
	}

	tcu->map = map;
	tcu->np = np;
	ingenic_tcu = tcu;

	for (cpu = 0; cpu < num_possible_cpus(); cpu++) {
		timer = &tcu->timers[cpu];

		timer->cpu = cpu;
		timer->channel = find_next_zero_bit(&tcu->pwm_channels_mask,
						  soc_info->num_channels,
						  last_bit + 1);
		last_bit = timer->channel;
	}

	tcu->cs_channel = find_next_zero_bit(&tcu->pwm_channels_mask,
					     soc_info->num_channels,
					     last_bit + 1);

	ret = ingenic_tcu_clocksource_init(np, tcu);
	if (ret) {
		pr_crit("%s: Unable to init clocksource: %d\n", __func__, ret);
		goto err_free_ingenic_tcu;
	}

	/* Setup clock events on each CPU core */
	ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "Ingenic XBurst: online",
				ingenic_tcu_setup_cevt, NULL);
	if (ret < 0) {
		pr_crit("%s: Unable to start CPU timers: %d\n", __func__, ret);
		goto err_tcu_clocksource_cleanup;
	}

	/* Register the sched_clock at the end as there's no way to undo it */
	rate = clk_get_rate(tcu->cs_clk);
	sched_clock_register(ingenic_tcu_timer_read, 16, rate);

	return 0;

err_tcu_clocksource_cleanup:
	clocksource_unregister(&tcu->cs);
	clk_disable_unprepare(tcu->cs_clk);
	clk_put(tcu->cs_clk);
err_free_ingenic_tcu:
	kfree(tcu);
	return ret;
}

TIMER_OF_DECLARE(jz4740_tcu_intc,  "ingenic,jz4740-tcu",  ingenic_tcu_init);
TIMER_OF_DECLARE(jz4725b_tcu_intc, "ingenic,jz4725b-tcu", ingenic_tcu_init);
TIMER_OF_DECLARE(jz4760_tcu_intc,  "ingenic,jz4760-tcu",  ingenic_tcu_init);
TIMER_OF_DECLARE(jz4770_tcu_intc,  "ingenic,jz4770-tcu",  ingenic_tcu_init);
TIMER_OF_DECLARE(x1000_tcu_intc,  "ingenic,x1000-tcu",  ingenic_tcu_init);

static int __init ingenic_tcu_probe(struct platform_device *pdev)
{
	platform_set_drvdata(pdev, ingenic_tcu);

	return 0;
}

static int __maybe_unused ingenic_tcu_suspend(struct device *dev)
{
	struct ingenic_tcu *tcu = dev_get_drvdata(dev);
	unsigned int cpu;

	clk_disable(tcu->cs_clk);

	for (cpu = 0; cpu < num_online_cpus(); cpu++)
		clk_disable(tcu->timers[cpu].clk);

	return 0;
}

static int __maybe_unused ingenic_tcu_resume(struct device *dev)
{
	struct ingenic_tcu *tcu = dev_get_drvdata(dev);
	unsigned int cpu;
	int ret;

	for (cpu = 0; cpu < num_online_cpus(); cpu++) {
		ret = clk_enable(tcu->timers[cpu].clk);
		if (ret)
			goto err_timer_clk_disable;
	}

	ret = clk_enable(tcu->cs_clk);
	if (ret)
		goto err_timer_clk_disable;

	return 0;

err_timer_clk_disable:
	for (; cpu > 0; cpu--)
		clk_disable(tcu->timers[cpu - 1].clk);
	return ret;
}

static const struct dev_pm_ops __maybe_unused ingenic_tcu_pm_ops = {
	/* _noirq: We want the TCU clocks to be gated last / ungated first */
	.suspend_noirq = ingenic_tcu_suspend,
	.resume_noirq  = ingenic_tcu_resume,
};

static struct platform_driver ingenic_tcu_driver = {
	.driver = {
		.name	= "ingenic-tcu-timer",
#ifdef CONFIG_PM_SLEEP
		.pm	= &ingenic_tcu_pm_ops,
#endif
		.of_match_table = ingenic_tcu_of_match,
	},
};
builtin_platform_driver_probe(ingenic_tcu_driver, ingenic_tcu_probe);
Commit	Line	Data
34e93683 PC	1	// SPDX-License-Identifier: GPL-2.0
34e93683 PC	2	/*
f19d838d	3	* Ingenic SoCs TCU IRQ driver
34e93683	4	* Copyright (C) 2019 Paul Cercueil <paul@crapouillou.net>
f19d838d	5	* Copyright (C) 2020 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
34e93683 PC	6	*/
	7
	8	#include <linux/bitops.h>
	9	#include <linux/clk.h>
	10	#include <linux/clockchips.h>
	11	#include <linux/clocksource.h>
	12	#include <linux/interrupt.h>
	13	#include <linux/mfd/ingenic-tcu.h>
	14	#include <linux/mfd/syscon.h>
	15	#include <linux/of.h>
	16	#include <linux/of_address.h>
	17	#include <linux/of_irq.h>
	18	#include <linux/of_platform.h>
f19d838d	19	#include <linux/overflow.h>
34e93683 PC	20	#include <linux/platform_device.h>
	21	#include <linux/regmap.h>
	22	#include <linux/sched_clock.h>
	23
	24	#include <dt-bindings/clock/ingenic,tcu.h>
	25
f19d838d ZY	26	static DEFINE_PER_CPU(call_single_data_t, ingenic_cevt_csd);
f19d838d ZY	27
34e93683 PC	28	struct ingenic_soc_info {
	29	unsigned int num_channels;
	30	};
	31
f19d838d ZY	32	struct ingenic_tcu_timer {
	33	unsigned int cpu;
	34	unsigned int channel;
	35	struct clock_event_device cevt;
	36	struct clk *clk;
	37	char name[8];
	38	};
	39
34e93683 PC	40	struct ingenic_tcu {
34e93683 PC	41	struct regmap *map;
f19d838d ZY	42	struct device_node *np;
	43	struct clk *cs_clk;
	44	unsigned int cs_channel;
34e93683	45	struct clocksource cs;
34e93683	46	unsigned long pwm_channels_mask;
f19d838d	47	struct ingenic_tcu_timer timers[];
34e93683 PC	48	};
	49
	50	static struct ingenic_tcu *ingenic_tcu;
	51
	52	static u64 notrace ingenic_tcu_timer_read(void)
	53	{
	54	struct ingenic_tcu *tcu = ingenic_tcu;
	55	unsigned int count;
	56
	57	regmap_read(tcu->map, TCU_REG_TCNTc(tcu->cs_channel), &count);
	58
	59	return count;
	60	}
	61
	62	static u64 notrace ingenic_tcu_timer_cs_read(struct clocksource *cs)
	63	{
	64	return ingenic_tcu_timer_read();
	65	}
	66
f19d838d ZY	67	static inline struct ingenic_tcu *
	68	to_ingenic_tcu(struct ingenic_tcu_timer *timer)
	69	{
	70	return container_of(timer, struct ingenic_tcu, timers[timer->cpu]);
	71	}
	72
	73	static inline struct ingenic_tcu_timer *
	74	to_ingenic_tcu_timer(struct clock_event_device *evt)
34e93683	75	{
f19d838d	76	return container_of(evt, struct ingenic_tcu_timer, cevt);
34e93683 PC	77	}
	78
	79	static int ingenic_tcu_cevt_set_state_shutdown(struct clock_event_device *evt)
	80	{
f19d838d ZY	81	struct ingenic_tcu_timer *timer = to_ingenic_tcu_timer(evt);
f19d838d ZY	82	struct ingenic_tcu *tcu = to_ingenic_tcu(timer);
34e93683	83
f19d838d	84	regmap_write(tcu->map, TCU_REG_TECR, BIT(timer->channel));
34e93683 PC	85
	86	return 0;
	87	}
	88
	89	static int ingenic_tcu_cevt_set_next(unsigned long next,
	90	struct clock_event_device *evt)
	91	{
f19d838d ZY	92	struct ingenic_tcu_timer *timer = to_ingenic_tcu_timer(evt);
f19d838d ZY	93	struct ingenic_tcu *tcu = to_ingenic_tcu(timer);
34e93683 PC	94
	95	if (next > 0xffff)
	96	return -EINVAL;
	97
f19d838d ZY	98	regmap_write(tcu->map, TCU_REG_TDFRc(timer->channel), next);
	99	regmap_write(tcu->map, TCU_REG_TCNTc(timer->channel), 0);
	100	regmap_write(tcu->map, TCU_REG_TESR, BIT(timer->channel));
34e93683 PC	101
	102	return 0;
	103	}
	104
f19d838d ZY	105	static void ingenic_per_cpu_event_handler(void *info)
	106	{
	107	struct clock_event_device cevt = (struct clock_event_device ) info;
	108
	109	cevt->event_handler(cevt);
	110	}
	111
34e93683 PC	112	static irqreturn_t ingenic_tcu_cevt_cb(int irq, void *dev_id)
34e93683 PC	113	{
f19d838d ZY	114	struct ingenic_tcu_timer *timer = dev_id;
	115	struct ingenic_tcu *tcu = to_ingenic_tcu(timer);
	116	call_single_data_t *csd;
34e93683	117
f19d838d	118	regmap_write(tcu->map, TCU_REG_TECR, BIT(timer->channel));
34e93683	119
f19d838d ZY	120	if (timer->cevt.event_handler) {
	121	csd = &per_cpu(ingenic_cevt_csd, timer->cpu);
	122	csd->info = (void *) &timer->cevt;
	123	csd->func = ingenic_per_cpu_event_handler;
	124	smp_call_function_single_async(timer->cpu, csd);
	125	}
34e93683 PC	126
	127	return IRQ_HANDLED;
	128	}
	129
5bd7cb29	130	static struct clk ingenic_tcu_get_clock(struct device_node np, int id)
34e93683 PC	131	{
	132	struct of_phandle_args args;
	133
	134	args.np = np;
	135	args.args_count = 1;
	136	args.args[0] = id;
	137
	138	return of_clk_get_from_provider(&args);
	139	}
	140
f19d838d	141	static int ingenic_tcu_setup_cevt(unsigned int cpu)
34e93683	142	{
f19d838d ZY	143	struct ingenic_tcu *tcu = ingenic_tcu;
	144	struct ingenic_tcu_timer *timer = &tcu->timers[cpu];
	145	unsigned int timer_virq;
34e93683 PC	146	struct irq_domain *domain;
	147	unsigned long rate;
	148	int err;
	149
f19d838d ZY	150	timer->clk = ingenic_tcu_get_clock(tcu->np, timer->channel);
	151	if (IS_ERR(timer->clk))
	152	return PTR_ERR(timer->clk);
34e93683	153
f19d838d	154	err = clk_prepare_enable(timer->clk);
34e93683 PC	155	if (err)
	156	goto err_clk_put;
	157
f19d838d	158	rate = clk_get_rate(timer->clk);
34e93683 PC	159	if (!rate) {
	160	err = -EINVAL;
	161	goto err_clk_disable;
	162	}
	163
f19d838d	164	domain = irq_find_host(tcu->np);
34e93683 PC	165	if (!domain) {
	166	err = -ENODEV;
	167	goto err_clk_disable;
	168	}
	169
f19d838d	170	timer_virq = irq_create_mapping(domain, timer->channel);
34e93683 PC	171	if (!timer_virq) {
	172	err = -EINVAL;
	173	goto err_clk_disable;
	174	}
	175
f19d838d	176	snprintf(timer->name, sizeof(timer->name), "TCU%u", timer->channel);
34e93683 PC	177
34e93683 PC	178	err = request_irq(timer_virq, ingenic_tcu_cevt_cb, IRQF_TIMER,
f19d838d	179	timer->name, timer);
34e93683 PC	180	if (err)
	181	goto err_irq_dispose_mapping;
	182
f19d838d ZY	183	timer->cpu = smp_processor_id();
	184	timer->cevt.cpumask = cpumask_of(smp_processor_id());
	185	timer->cevt.features = CLOCK_EVT_FEAT_ONESHOT;
	186	timer->cevt.name = timer->name;
	187	timer->cevt.rating = 200;
	188	timer->cevt.set_state_shutdown = ingenic_tcu_cevt_set_state_shutdown;
	189	timer->cevt.set_next_event = ingenic_tcu_cevt_set_next;
34e93683	190
f19d838d	191	clockevents_config_and_register(&timer->cevt, rate, 10, 0xffff);
34e93683 PC	192
	193	return 0;
	194
	195	err_irq_dispose_mapping:
	196	irq_dispose_mapping(timer_virq);
	197	err_clk_disable:
f19d838d	198	clk_disable_unprepare(timer->clk);
34e93683	199	err_clk_put:
f19d838d	200	clk_put(timer->clk);
34e93683 PC	201	return err;
	202	}
	203
	204	static int __init ingenic_tcu_clocksource_init(struct device_node *np,
	205	struct ingenic_tcu *tcu)
	206	{
	207	unsigned int channel = tcu->cs_channel;
	208	struct clocksource *cs = &tcu->cs;
	209	unsigned long rate;
	210	int err;
	211
	212	tcu->cs_clk = ingenic_tcu_get_clock(np, channel);
	213	if (IS_ERR(tcu->cs_clk))
	214	return PTR_ERR(tcu->cs_clk);
	215
	216	err = clk_prepare_enable(tcu->cs_clk);
	217	if (err)
	218	goto err_clk_put;
	219
	220	rate = clk_get_rate(tcu->cs_clk);
	221	if (!rate) {
	222	err = -EINVAL;
	223	goto err_clk_disable;
	224	}
	225
	226	/* Reset channel */
	227	regmap_update_bits(tcu->map, TCU_REG_TCSRc(channel),
	228	0xffff & ~TCU_TCSR_RESERVED_BITS, 0);
	229
	230	/* Reset counter */
	231	regmap_write(tcu->map, TCU_REG_TDFRc(channel), 0xffff);
	232	regmap_write(tcu->map, TCU_REG_TCNTc(channel), 0);
	233
	234	/* Enable channel */
	235	regmap_write(tcu->map, TCU_REG_TESR, BIT(channel));
	236
	237	cs->name = "ingenic-timer";
	238	cs->rating = 200;
	239	cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
	240	cs->mask = CLOCKSOURCE_MASK(16);
	241	cs->read = ingenic_tcu_timer_cs_read;
	242
	243	err = clocksource_register_hz(cs, rate);
	244	if (err)
	245	goto err_clk_disable;
	246
	247	return 0;
	248
	249	err_clk_disable:
	250	clk_disable_unprepare(tcu->cs_clk);
	251	err_clk_put:
	252	clk_put(tcu->cs_clk);
	253	return err;
	254	}
	255
	256	static const struct ingenic_soc_info jz4740_soc_info = {
	257	.num_channels = 8,
	258	};
	259
	260	static const struct ingenic_soc_info jz4725b_soc_info = {
	261	.num_channels = 6,
	262	};
	263
	264	static const struct of_device_id ingenic_tcu_of_match[] = {
265	{ .compatible = "ingenic,jz4740-tcu", .data = &jz4740_soc_info, },
266	{ .compatible = "ingenic,jz4725b-tcu", .data = &jz4725b_soc_info, },
8a3f717f	267	{ .compatible = "ingenic,jz4760-tcu", .data = &jz4740_soc_info, },
34e93683	268	{ .compatible = "ingenic,jz4770-tcu", .data = &jz4740_soc_info, },
a7cd3955	269	{ .compatible = "ingenic,x1000-tcu", .data = &jz4740_soc_info, },
34e93683 PC	270	{ /* sentinel */ }
	271	};
	272
	273	static int __init ingenic_tcu_init(struct device_node *np)
	274	{
	275	const struct of_device_id *id = of_match_node(ingenic_tcu_of_match, np);
	276	const struct ingenic_soc_info *soc_info = id->data;
f19d838d	277	struct ingenic_tcu_timer *timer;
34e93683 PC	278	struct ingenic_tcu *tcu;
34e93683 PC	279	struct regmap *map;
f19d838d ZY	280	unsigned int cpu;
f19d838d ZY	281	int ret, last_bit = -1;
34e93683	282	long rate;
34e93683 PC	283
	284	of_node_clear_flag(np, OF_POPULATED);
	285
	286	map = device_node_to_regmap(np);
	287	if (IS_ERR(map))
	288	return PTR_ERR(map);
	289
f19d838d ZY	290	tcu = kzalloc(struct_size(tcu, timers, num_possible_cpus()),
f19d838d ZY	291	GFP_KERNEL);
34e93683 PC	292	if (!tcu)
	293	return -ENOMEM;
	294
f19d838d ZY	295	/*
	296	* Enable all TCU channels for PWM use by default except channels 0/1,
	297	* and channel 2 if target CPU is JZ4780/X2000 and SMP is selected.
	298	*/
	299	tcu->pwm_channels_mask = GENMASK(soc_info->num_channels - 1,
	300	num_possible_cpus() + 1);
34e93683 PC	301	of_property_read_u32(np, "ingenic,pwm-channels-mask",
	302	(u32 *)&tcu->pwm_channels_mask);
	303
f19d838d ZY	304	/* Verify that we have at least num_possible_cpus() + 1 free channels */
	305	if (hweight8(tcu->pwm_channels_mask) >
	306	soc_info->num_channels - num_possible_cpus() + 1) {
34e93683 PC	307	pr_crit("%s: Invalid PWM channel mask: 0x%02lx\n", __func__,
	308	tcu->pwm_channels_mask);
	309	ret = -EINVAL;
	310	goto err_free_ingenic_tcu;
	311	}
	312
	313	tcu->map = map;
f19d838d	314	tcu->np = np;
34e93683 PC	315	ingenic_tcu = tcu;
34e93683 PC	316
f19d838d ZY	317	for (cpu = 0; cpu < num_possible_cpus(); cpu++) {
	318	timer = &tcu->timers[cpu];
	319
	320	timer->cpu = cpu;
	321	timer->channel = find_next_zero_bit(&tcu->pwm_channels_mask,
	322	soc_info->num_channels,
	323	last_bit + 1);
	324	last_bit = timer->channel;
	325	}
	326
34e93683 PC	327	tcu->cs_channel = find_next_zero_bit(&tcu->pwm_channels_mask,
34e93683 PC	328	soc_info->num_channels,
f19d838d	329	last_bit + 1);
34e93683 PC	330
	331	ret = ingenic_tcu_clocksource_init(np, tcu);
	332	if (ret) {
	333	pr_crit("%s: Unable to init clocksource: %d\n", __func__, ret);
	334	goto err_free_ingenic_tcu;
	335	}
	336
f19d838d ZY	337	/* Setup clock events on each CPU core */
	338	ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "Ingenic XBurst: online",
	339	ingenic_tcu_setup_cevt, NULL);
	340	if (ret < 0) {
	341	pr_crit("%s: Unable to start CPU timers: %d\n", __func__, ret);
34e93683	342	goto err_tcu_clocksource_cleanup;
f19d838d	343	}
34e93683 PC	344
	345	/* Register the sched_clock at the end as there's no way to undo it */
	346	rate = clk_get_rate(tcu->cs_clk);
	347	sched_clock_register(ingenic_tcu_timer_read, 16, rate);
	348
	349	return 0;
	350
	351	err_tcu_clocksource_cleanup:
	352	clocksource_unregister(&tcu->cs);
	353	clk_disable_unprepare(tcu->cs_clk);
	354	clk_put(tcu->cs_clk);
	355	err_free_ingenic_tcu:
	356	kfree(tcu);
	357	return ret;
	358	}
	359
	360	TIMER_OF_DECLARE(jz4740_tcu_intc, "ingenic,jz4740-tcu", ingenic_tcu_init);
	361	TIMER_OF_DECLARE(jz4725b_tcu_intc, "ingenic,jz4725b-tcu", ingenic_tcu_init);
8a3f717f	362	TIMER_OF_DECLARE(jz4760_tcu_intc, "ingenic,jz4760-tcu", ingenic_tcu_init);
34e93683	363	TIMER_OF_DECLARE(jz4770_tcu_intc, "ingenic,jz4770-tcu", ingenic_tcu_init);
a7cd3955	364	TIMER_OF_DECLARE(x1000_tcu_intc, "ingenic,x1000-tcu", ingenic_tcu_init);
34e93683 PC	365
	366	static int __init ingenic_tcu_probe(struct platform_device *pdev)
	367	{
	368	platform_set_drvdata(pdev, ingenic_tcu);
	369
	370	return 0;
	371	}
	372
	373	static int __maybe_unused ingenic_tcu_suspend(struct device *dev)
	374	{
	375	struct ingenic_tcu *tcu = dev_get_drvdata(dev);
f19d838d	376	unsigned int cpu;
34e93683 PC	377
34e93683 PC	378	clk_disable(tcu->cs_clk);
f19d838d ZY	379
	380	for (cpu = 0; cpu < num_online_cpus(); cpu++)
	381	clk_disable(tcu->timers[cpu].clk);
	382
34e93683 PC	383	return 0;
	384	}
	385
	386	static int __maybe_unused ingenic_tcu_resume(struct device *dev)
	387	{
	388	struct ingenic_tcu *tcu = dev_get_drvdata(dev);
f19d838d	389	unsigned int cpu;
34e93683 PC	390	int ret;
34e93683 PC	391
f19d838d ZY	392	for (cpu = 0; cpu < num_online_cpus(); cpu++) {
	393	ret = clk_enable(tcu->timers[cpu].clk);
	394	if (ret)
	395	goto err_timer_clk_disable;
	396	}
34e93683 PC	397
34e93683 PC	398	ret = clk_enable(tcu->cs_clk);
f19d838d ZY	399	if (ret)
f19d838d ZY	400	goto err_timer_clk_disable;
34e93683 PC	401
34e93683 PC	402	return 0;
f19d838d ZY	403
	404	err_timer_clk_disable:
	405	for (; cpu > 0; cpu--)
	406	clk_disable(tcu->timers[cpu - 1].clk);
	407	return ret;
34e93683 PC	408	}
	409
	410	static const struct dev_pm_ops __maybe_unused ingenic_tcu_pm_ops = {
	411	/* _noirq: We want the TCU clocks to be gated last / ungated first */
	412	.suspend_noirq = ingenic_tcu_suspend,
	413	.resume_noirq = ingenic_tcu_resume,
	414	};
	415
	416	static struct platform_driver ingenic_tcu_driver = {
	417	.driver = {
	418	.name = "ingenic-tcu-timer",
	419	#ifdef CONFIG_PM_SLEEP
	420	.pm = &ingenic_tcu_pm_ops,
	421	#endif
	422	.of_match_table = ingenic_tcu_of_match,
	423	},
	424	};
	425	builtin_platform_driver_probe(ingenic_tcu_driver, ingenic_tcu_probe);