Commit | Line | Data |
---|---|---|
b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
89c0b8e2 RK |
2 | /* |
3 | * i8253 PIT clocksource | |
4 | */ | |
e6220bdc | 5 | #include <linux/clockchips.h> |
89c0b8e2 RK |
6 | #include <linux/init.h> |
7 | #include <linux/io.h> | |
8 | #include <linux/spinlock.h> | |
9 | #include <linux/timex.h> | |
15f304b6 | 10 | #include <linux/module.h> |
334955ef | 11 | #include <linux/i8253.h> |
e6220bdc | 12 | #include <linux/smp.h> |
89c0b8e2 | 13 | |
15f304b6 RB |
14 | /* |
15 | * Protects access to I/O ports | |
16 | * | |
17 | * 0040-0043 : timer0, i8253 / i8254 | |
18 | * 0061-0061 : NMI Control Register which contains two speaker control bits. | |
19 | */ | |
20 | DEFINE_RAW_SPINLOCK(i8253_lock); | |
21 | EXPORT_SYMBOL(i8253_lock); | |
22 | ||
35b69a42 MK |
23 | /* |
24 | * Handle PIT quirk in pit_shutdown() where zeroing the counter register | |
25 | * restarts the PIT, negating the shutdown. On platforms with the quirk, | |
26 | * platform specific code can set this to false. | |
27 | */ | |
28 | bool i8253_clear_counter_on_shutdown __ro_after_init = true; | |
29 | ||
15f304b6 | 30 | #ifdef CONFIG_CLKSRC_I8253 |
89c0b8e2 RK |
31 | /* |
32 | * Since the PIT overflows every tick, its not very useful | |
33 | * to just read by itself. So use jiffies to emulate a free | |
34 | * running counter: | |
35 | */ | |
a5a1d1c2 | 36 | static u64 i8253_read(struct clocksource *cs) |
89c0b8e2 RK |
37 | { |
38 | static int old_count; | |
39 | static u32 old_jifs; | |
40 | unsigned long flags; | |
41 | int count; | |
42 | u32 jifs; | |
43 | ||
44 | raw_spin_lock_irqsave(&i8253_lock, flags); | |
45 | /* | |
d6ad4187 | 46 | * Although our caller may have the read side of jiffies_lock, |
89c0b8e2 RK |
47 | * this is now a seqlock, and we are cheating in this routine |
48 | * by having side effects on state that we cannot undo if | |
49 | * there is a collision on the seqlock and our caller has to | |
50 | * retry. (Namely, old_jifs and old_count.) So we must treat | |
51 | * jiffies as volatile despite the lock. We read jiffies | |
52 | * before latching the timer count to guarantee that although | |
53 | * the jiffies value might be older than the count (that is, | |
54 | * the counter may underflow between the last point where | |
55 | * jiffies was incremented and the point where we latch the | |
56 | * count), it cannot be newer. | |
57 | */ | |
58 | jifs = jiffies; | |
e6220bdc TG |
59 | outb_p(0x00, PIT_MODE); /* latch the count ASAP */ |
60 | count = inb_p(PIT_CH0); /* read the latched count */ | |
61 | count |= inb_p(PIT_CH0) << 8; | |
89c0b8e2 RK |
62 | |
63 | /* VIA686a test code... reset the latch if count > max + 1 */ | |
5f724e84 | 64 | if (count > PIT_LATCH) { |
e6220bdc TG |
65 | outb_p(0x34, PIT_MODE); |
66 | outb_p(PIT_LATCH & 0xff, PIT_CH0); | |
67 | outb_p(PIT_LATCH >> 8, PIT_CH0); | |
89c0b8e2 RK |
68 | count = PIT_LATCH - 1; |
69 | } | |
70 | ||
71 | /* | |
72 | * It's possible for count to appear to go the wrong way for a | |
73 | * couple of reasons: | |
74 | * | |
75 | * 1. The timer counter underflows, but we haven't handled the | |
76 | * resulting interrupt and incremented jiffies yet. | |
77 | * 2. Hardware problem with the timer, not giving us continuous time, | |
78 | * the counter does small "jumps" upwards on some Pentium systems, | |
79 | * (see c't 95/10 page 335 for Neptun bug.) | |
80 | * | |
81 | * Previous attempts to handle these cases intelligently were | |
82 | * buggy, so we just do the simple thing now. | |
83 | */ | |
84 | if (count > old_count && jifs == old_jifs) | |
85 | count = old_count; | |
86 | ||
87 | old_count = count; | |
88 | old_jifs = jifs; | |
89 | ||
90 | raw_spin_unlock_irqrestore(&i8253_lock, flags); | |
91 | ||
92 | count = (PIT_LATCH - 1) - count; | |
93 | ||
a5a1d1c2 | 94 | return (u64)(jifs * PIT_LATCH) + count; |
89c0b8e2 RK |
95 | } |
96 | ||
97 | static struct clocksource i8253_cs = { | |
98 | .name = "pit", | |
99 | .rating = 110, | |
100 | .read = i8253_read, | |
101 | .mask = CLOCKSOURCE_MASK(32), | |
102 | }; | |
103 | ||
104 | int __init clocksource_i8253_init(void) | |
105 | { | |
106 | return clocksource_register_hz(&i8253_cs, PIT_TICK_RATE); | |
107 | } | |
15f304b6 | 108 | #endif |
e6220bdc TG |
109 | |
110 | #ifdef CONFIG_CLKEVT_I8253 | |
8eda41b0 | 111 | static int pit_shutdown(struct clock_event_device *evt) |
e6220bdc | 112 | { |
8eda41b0 VK |
113 | if (!clockevent_state_oneshot(evt) && !clockevent_state_periodic(evt)) |
114 | return 0; | |
115 | ||
e6220bdc TG |
116 | raw_spin_lock(&i8253_lock); |
117 | ||
8eda41b0 | 118 | outb_p(0x30, PIT_MODE); |
35b69a42 MK |
119 | |
120 | if (i8253_clear_counter_on_shutdown) { | |
121 | outb_p(0, PIT_CH0); | |
122 | outb_p(0, PIT_CH0); | |
123 | } | |
8eda41b0 VK |
124 | |
125 | raw_spin_unlock(&i8253_lock); | |
126 | return 0; | |
127 | } | |
128 | ||
129 | static int pit_set_oneshot(struct clock_event_device *evt) | |
130 | { | |
131 | raw_spin_lock(&i8253_lock); | |
132 | outb_p(0x38, PIT_MODE); | |
133 | raw_spin_unlock(&i8253_lock); | |
134 | return 0; | |
135 | } | |
136 | ||
137 | static int pit_set_periodic(struct clock_event_device *evt) | |
138 | { | |
139 | raw_spin_lock(&i8253_lock); | |
140 | ||
141 | /* binary, mode 2, LSB/MSB, ch 0 */ | |
142 | outb_p(0x34, PIT_MODE); | |
143 | outb_p(PIT_LATCH & 0xff, PIT_CH0); /* LSB */ | |
144 | outb_p(PIT_LATCH >> 8, PIT_CH0); /* MSB */ | |
145 | ||
e6220bdc | 146 | raw_spin_unlock(&i8253_lock); |
8eda41b0 | 147 | return 0; |
e6220bdc TG |
148 | } |
149 | ||
150 | /* | |
151 | * Program the next event in oneshot mode | |
152 | * | |
153 | * Delta is given in PIT ticks | |
154 | */ | |
155 | static int pit_next_event(unsigned long delta, struct clock_event_device *evt) | |
156 | { | |
157 | raw_spin_lock(&i8253_lock); | |
158 | outb_p(delta & 0xff , PIT_CH0); /* LSB */ | |
159 | outb_p(delta >> 8 , PIT_CH0); /* MSB */ | |
160 | raw_spin_unlock(&i8253_lock); | |
161 | ||
162 | return 0; | |
163 | } | |
164 | ||
165 | /* | |
166 | * On UP the PIT can serve all of the possible timer functions. On SMP systems | |
167 | * it can be solely used for the global tick. | |
168 | */ | |
169 | struct clock_event_device i8253_clockevent = { | |
8eda41b0 VK |
170 | .name = "pit", |
171 | .features = CLOCK_EVT_FEAT_PERIODIC, | |
172 | .set_state_shutdown = pit_shutdown, | |
173 | .set_state_periodic = pit_set_periodic, | |
174 | .set_next_event = pit_next_event, | |
e6220bdc TG |
175 | }; |
176 | ||
177 | /* | |
178 | * Initialize the conversion factor and the min/max deltas of the clock event | |
179 | * structure and register the clock event source with the framework. | |
180 | */ | |
181 | void __init clockevent_i8253_init(bool oneshot) | |
182 | { | |
8eda41b0 | 183 | if (oneshot) { |
e6220bdc | 184 | i8253_clockevent.features |= CLOCK_EVT_FEAT_ONESHOT; |
8eda41b0 VK |
185 | i8253_clockevent.set_state_oneshot = pit_set_oneshot; |
186 | } | |
e6220bdc TG |
187 | /* |
188 | * Start pit with the boot cpu mask. x86 might make it global | |
189 | * when it is used as broadcast device later. | |
190 | */ | |
191 | i8253_clockevent.cpumask = cpumask_of(smp_processor_id()); | |
192 | ||
193 | clockevents_config_and_register(&i8253_clockevent, PIT_TICK_RATE, | |
194 | 0xF, 0x7FFF); | |
195 | } | |
196 | #endif |