Commit | Line | Data |
---|---|---|
b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
618b902d | 2 | /* |
4633f4ca | 3 | * H8S TPU Driver |
618b902d YS |
4 | * |
5 | * Copyright 2015 Yoshinori Sato <ysato@users.sourcefoge.jp> | |
6 | * | |
7 | */ | |
8 | ||
9 | #include <linux/errno.h> | |
618b902d | 10 | #include <linux/kernel.h> |
618b902d | 11 | #include <linux/init.h> |
618b902d | 12 | #include <linux/clocksource.h> |
618b902d YS |
13 | #include <linux/clk.h> |
14 | #include <linux/io.h> | |
15 | #include <linux/of.h> | |
4633f4ca YS |
16 | #include <linux/of_address.h> |
17 | #include <linux/of_irq.h> | |
618b902d | 18 | |
9471f1d9 DL |
19 | #define TCR 0x0 |
20 | #define TSR 0x5 | |
21 | #define TCNT 0x6 | |
618b902d | 22 | |
d33f250a YS |
23 | #define TCFV 0x10 |
24 | ||
618b902d | 25 | struct tpu_priv { |
618b902d | 26 | struct clocksource cs; |
75160515 DL |
27 | void __iomem *mapbase1; |
28 | void __iomem *mapbase2; | |
618b902d YS |
29 | raw_spinlock_t lock; |
30 | unsigned int cs_enabled; | |
31 | }; | |
32 | ||
33 | static inline unsigned long read_tcnt32(struct tpu_priv *p) | |
34 | { | |
35 | unsigned long tcnt; | |
36 | ||
d33f250a YS |
37 | tcnt = ioread16be(p->mapbase1 + TCNT) << 16; |
38 | tcnt |= ioread16be(p->mapbase2 + TCNT); | |
618b902d YS |
39 | return tcnt; |
40 | } | |
41 | ||
42 | static int tpu_get_counter(struct tpu_priv *p, unsigned long long *val) | |
43 | { | |
44 | unsigned long v1, v2, v3; | |
45 | int o1, o2; | |
46 | ||
d33f250a | 47 | o1 = ioread8(p->mapbase1 + TSR) & TCFV; |
618b902d YS |
48 | |
49 | /* Make sure the timer value is stable. Stolen from acpi_pm.c */ | |
50 | do { | |
51 | o2 = o1; | |
52 | v1 = read_tcnt32(p); | |
53 | v2 = read_tcnt32(p); | |
54 | v3 = read_tcnt32(p); | |
d33f250a | 55 | o1 = ioread8(p->mapbase1 + TSR) & TCFV; |
618b902d YS |
56 | } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3) |
57 | || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2))); | |
58 | ||
59 | *val = v2; | |
60 | return o1; | |
61 | } | |
62 | ||
63 | static inline struct tpu_priv *cs_to_priv(struct clocksource *cs) | |
64 | { | |
65 | return container_of(cs, struct tpu_priv, cs); | |
66 | } | |
67 | ||
a5a1d1c2 | 68 | static u64 tpu_clocksource_read(struct clocksource *cs) |
618b902d YS |
69 | { |
70 | struct tpu_priv *p = cs_to_priv(cs); | |
71 | unsigned long flags; | |
72 | unsigned long long value; | |
73 | ||
74 | raw_spin_lock_irqsave(&p->lock, flags); | |
75 | if (tpu_get_counter(p, &value)) | |
76 | value += 0x100000000; | |
77 | raw_spin_unlock_irqrestore(&p->lock, flags); | |
78 | ||
79 | return value; | |
80 | } | |
81 | ||
82 | static int tpu_clocksource_enable(struct clocksource *cs) | |
83 | { | |
84 | struct tpu_priv *p = cs_to_priv(cs); | |
85 | ||
86 | WARN_ON(p->cs_enabled); | |
87 | ||
d33f250a YS |
88 | iowrite16be(0, p->mapbase1 + TCNT); |
89 | iowrite16be(0, p->mapbase2 + TCNT); | |
90 | iowrite8(0x0f, p->mapbase1 + TCR); | |
91 | iowrite8(0x03, p->mapbase2 + TCR); | |
618b902d YS |
92 | |
93 | p->cs_enabled = true; | |
94 | return 0; | |
95 | } | |
96 | ||
97 | static void tpu_clocksource_disable(struct clocksource *cs) | |
98 | { | |
99 | struct tpu_priv *p = cs_to_priv(cs); | |
100 | ||
101 | WARN_ON(!p->cs_enabled); | |
102 | ||
d33f250a YS |
103 | iowrite8(0, p->mapbase1 + TCR); |
104 | iowrite8(0, p->mapbase2 + TCR); | |
618b902d YS |
105 | p->cs_enabled = false; |
106 | } | |
107 | ||
4633f4ca YS |
108 | static struct tpu_priv tpu_priv = { |
109 | .cs = { | |
110 | .name = "H8S_TPU", | |
111 | .rating = 200, | |
112 | .read = tpu_clocksource_read, | |
113 | .enable = tpu_clocksource_enable, | |
114 | .disable = tpu_clocksource_disable, | |
115 | .mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8), | |
116 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | |
117 | }, | |
118 | }; | |
119 | ||
618b902d YS |
120 | #define CH_L 0 |
121 | #define CH_H 1 | |
122 | ||
f2f9900c | 123 | static int __init h8300_tpu_init(struct device_node *node) |
618b902d | 124 | { |
4633f4ca YS |
125 | void __iomem *base[2]; |
126 | struct clk *clk; | |
f2f9900c | 127 | int ret = -ENXIO; |
618b902d | 128 | |
4633f4ca YS |
129 | clk = of_clk_get(node, 0); |
130 | if (IS_ERR(clk)) { | |
131 | pr_err("failed to get clock for clocksource\n"); | |
f2f9900c | 132 | return PTR_ERR(clk); |
618b902d YS |
133 | } |
134 | ||
4633f4ca YS |
135 | base[CH_L] = of_iomap(node, CH_L); |
136 | if (!base[CH_L]) { | |
137 | pr_err("failed to map registers for clocksource\n"); | |
138 | goto free_clk; | |
618b902d | 139 | } |
4633f4ca YS |
140 | base[CH_H] = of_iomap(node, CH_H); |
141 | if (!base[CH_H]) { | |
142 | pr_err("failed to map registers for clocksource\n"); | |
143 | goto unmap_L; | |
618b902d YS |
144 | } |
145 | ||
75160515 DL |
146 | tpu_priv.mapbase1 = base[CH_L]; |
147 | tpu_priv.mapbase2 = base[CH_H]; | |
618b902d | 148 | |
f2f9900c | 149 | return clocksource_register_hz(&tpu_priv.cs, clk_get_rate(clk) / 64); |
618b902d | 150 | |
4633f4ca YS |
151 | unmap_L: |
152 | iounmap(base[CH_H]); | |
153 | free_clk: | |
154 | clk_put(clk); | |
f2f9900c | 155 | return ret; |
618b902d YS |
156 | } |
157 | ||
17273395 | 158 | TIMER_OF_DECLARE(h8300_tpu, "renesas,tpu", h8300_tpu_init); |