Commit | Line | Data |
---|---|---|
618b902d YS |
1 | /* |
2 | * linux/arch/h8300/kernel/cpu/timer/timer8.c | |
3 | * | |
4 | * Yoshinori Sato <ysato@users.sourcefoge.jp> | |
5 | * | |
6 | * 8bit Timer driver | |
7 | * | |
8 | */ | |
9 | ||
10 | #include <linux/errno.h> | |
618b902d YS |
11 | #include <linux/kernel.h> |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/init.h> | |
618b902d | 14 | #include <linux/clockchips.h> |
618b902d YS |
15 | #include <linux/clk.h> |
16 | #include <linux/io.h> | |
17 | #include <linux/of.h> | |
4633f4ca YS |
18 | #include <linux/of_address.h> |
19 | #include <linux/of_irq.h> | |
618b902d | 20 | |
618b902d YS |
21 | #define _8TCR 0 |
22 | #define _8TCSR 2 | |
23 | #define TCORA 4 | |
24 | #define TCORB 6 | |
25 | #define _8TCNT 8 | |
26 | ||
d33f250a YS |
27 | #define CMIEA 6 |
28 | #define CMFA 6 | |
29 | ||
618b902d YS |
30 | #define FLAG_STARTED (1 << 3) |
31 | ||
4633f4ca YS |
32 | #define SCALE 64 |
33 | ||
d33f250a YS |
34 | #define bset(b, a) iowrite8(ioread8(a) | (1 << (b)), (a)) |
35 | #define bclr(b, a) iowrite8(ioread8(a) & ~(1 << (b)), (a)) | |
36 | ||
618b902d | 37 | struct timer8_priv { |
618b902d | 38 | struct clock_event_device ced; |
75160515 | 39 | void __iomem *mapbase; |
618b902d YS |
40 | unsigned long flags; |
41 | unsigned int rate; | |
618b902d YS |
42 | }; |
43 | ||
618b902d YS |
44 | static irqreturn_t timer8_interrupt(int irq, void *dev_id) |
45 | { | |
46 | struct timer8_priv *p = dev_id; | |
47 | ||
7053fdac | 48 | if (clockevent_state_oneshot(&p->ced)) |
d33f250a | 49 | iowrite16be(0x0000, p->mapbase + _8TCR); |
7053fdac DL |
50 | |
51 | p->ced.event_handler(&p->ced); | |
618b902d | 52 | |
d33f250a | 53 | bclr(CMFA, p->mapbase + _8TCSR); |
f37632d1 | 54 | |
618b902d YS |
55 | return IRQ_HANDLED; |
56 | } | |
57 | ||
58 | static void timer8_set_next(struct timer8_priv *p, unsigned long delta) | |
59 | { | |
618b902d | 60 | if (delta >= 0x10000) |
8c09b7d6 | 61 | pr_warn("delta out of range\n"); |
d33f250a YS |
62 | bclr(CMIEA, p->mapbase + _8TCR); |
63 | iowrite16be(delta, p->mapbase + TCORA); | |
64 | iowrite16be(0x0000, p->mapbase + _8TCNT); | |
65 | bclr(CMFA, p->mapbase + _8TCSR); | |
66 | bset(CMIEA, p->mapbase + _8TCR); | |
618b902d YS |
67 | } |
68 | ||
69 | static int timer8_enable(struct timer8_priv *p) | |
70 | { | |
d33f250a YS |
71 | iowrite16be(0xffff, p->mapbase + TCORA); |
72 | iowrite16be(0x0000, p->mapbase + _8TCNT); | |
73 | iowrite16be(0x0c02, p->mapbase + _8TCR); | |
618b902d YS |
74 | |
75 | return 0; | |
76 | } | |
77 | ||
78 | static int timer8_start(struct timer8_priv *p) | |
79 | { | |
cce483e0 | 80 | int ret; |
618b902d | 81 | |
cce483e0 DL |
82 | if ((p->flags & FLAG_STARTED)) |
83 | return 0; | |
618b902d | 84 | |
cce483e0 DL |
85 | ret = timer8_enable(p); |
86 | if (!ret) | |
87 | p->flags |= FLAG_STARTED; | |
618b902d | 88 | |
618b902d YS |
89 | return ret; |
90 | } | |
91 | ||
92 | static void timer8_stop(struct timer8_priv *p) | |
93 | { | |
d33f250a | 94 | iowrite16be(0x0000, p->mapbase + _8TCR); |
618b902d YS |
95 | } |
96 | ||
97 | static inline struct timer8_priv *ced_to_priv(struct clock_event_device *ced) | |
98 | { | |
99 | return container_of(ced, struct timer8_priv, ced); | |
100 | } | |
101 | ||
1f058d52 | 102 | static void timer8_clock_event_start(struct timer8_priv *p, unsigned long delta) |
618b902d | 103 | { |
618b902d | 104 | timer8_start(p); |
1f058d52 | 105 | timer8_set_next(p, delta); |
618b902d YS |
106 | } |
107 | ||
fc2b2f5d VK |
108 | static int timer8_clock_event_shutdown(struct clock_event_device *ced) |
109 | { | |
110 | timer8_stop(ced_to_priv(ced)); | |
111 | return 0; | |
112 | } | |
113 | ||
114 | static int timer8_clock_event_periodic(struct clock_event_device *ced) | |
618b902d YS |
115 | { |
116 | struct timer8_priv *p = ced_to_priv(ced); | |
117 | ||
4633f4ca | 118 | pr_info("%s: used for periodic clock events\n", ced->name); |
fc2b2f5d | 119 | timer8_stop(p); |
1f058d52 | 120 | timer8_clock_event_start(p, (p->rate + HZ/2) / HZ); |
fc2b2f5d VK |
121 | |
122 | return 0; | |
123 | } | |
124 | ||
125 | static int timer8_clock_event_oneshot(struct clock_event_device *ced) | |
126 | { | |
127 | struct timer8_priv *p = ced_to_priv(ced); | |
128 | ||
4633f4ca | 129 | pr_info("%s: used for oneshot clock events\n", ced->name); |
fc2b2f5d | 130 | timer8_stop(p); |
1f058d52 | 131 | timer8_clock_event_start(p, 0x10000); |
fc2b2f5d VK |
132 | |
133 | return 0; | |
618b902d YS |
134 | } |
135 | ||
136 | static int timer8_clock_event_next(unsigned long delta, | |
137 | struct clock_event_device *ced) | |
138 | { | |
139 | struct timer8_priv *p = ced_to_priv(ced); | |
140 | ||
fc2b2f5d | 141 | BUG_ON(!clockevent_state_oneshot(ced)); |
618b902d YS |
142 | timer8_set_next(p, delta - 1); |
143 | ||
144 | return 0; | |
145 | } | |
146 | ||
4633f4ca YS |
147 | static struct timer8_priv timer8_priv = { |
148 | .ced = { | |
149 | .name = "h8300_8timer", | |
150 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | |
151 | .rating = 200, | |
152 | .set_next_event = timer8_clock_event_next, | |
153 | .set_state_shutdown = timer8_clock_event_shutdown, | |
154 | .set_state_periodic = timer8_clock_event_periodic, | |
155 | .set_state_oneshot = timer8_clock_event_oneshot, | |
156 | }, | |
157 | }; | |
158 | ||
691f8f87 | 159 | static int __init h8300_8timer_init(struct device_node *node) |
618b902d | 160 | { |
4633f4ca | 161 | void __iomem *base; |
691f8f87 | 162 | int irq, ret; |
4633f4ca | 163 | struct clk *clk; |
618b902d | 164 | |
4633f4ca YS |
165 | clk = of_clk_get(node, 0); |
166 | if (IS_ERR(clk)) { | |
167 | pr_err("failed to get clock for clockevent\n"); | |
691f8f87 | 168 | return PTR_ERR(clk); |
4633f4ca | 169 | } |
618b902d | 170 | |
691f8f87 | 171 | ret = ENXIO; |
4633f4ca YS |
172 | base = of_iomap(node, 0); |
173 | if (!base) { | |
174 | pr_err("failed to map registers for clockevent\n"); | |
175 | goto free_clk; | |
618b902d YS |
176 | } |
177 | ||
691f8f87 | 178 | ret = -EINVAL; |
4633f4ca | 179 | irq = irq_of_parse_and_map(node, 0); |
54a0cd5a | 180 | if (!irq) { |
4633f4ca YS |
181 | pr_err("failed to get irq for clockevent\n"); |
182 | goto unmap_reg; | |
618b902d YS |
183 | } |
184 | ||
75160515 | 185 | timer8_priv.mapbase = base; |
cce483e0 | 186 | |
6f2b611d YS |
187 | timer8_priv.rate = clk_get_rate(clk) / SCALE; |
188 | if (!timer8_priv.rate) { | |
cce483e0 DL |
189 | pr_err("Failed to get rate for the clocksource\n"); |
190 | goto unmap_reg; | |
191 | } | |
618b902d | 192 | |
6f2b611d YS |
193 | if (request_irq(irq, timer8_interrupt, IRQF_TIMER, |
194 | timer8_priv.ced.name, &timer8_priv) < 0) { | |
4633f4ca YS |
195 | pr_err("failed to request irq %d for clockevent\n", irq); |
196 | goto unmap_reg; | |
618b902d | 197 | } |
cce483e0 | 198 | |
6f2b611d YS |
199 | clockevents_config_and_register(&timer8_priv.ced, |
200 | timer8_priv.rate, 1, 0x0000ffff); | |
4633f4ca | 201 | |
691f8f87 | 202 | return 0; |
4633f4ca YS |
203 | unmap_reg: |
204 | iounmap(base); | |
205 | free_clk: | |
206 | clk_put(clk); | |
691f8f87 | 207 | return ret; |
618b902d YS |
208 | } |
209 | ||
17273395 | 210 | TIMER_OF_DECLARE(h8300_8bit, "renesas,8bit-timer", h8300_8timer_init); |