[linux-2.6-block.git] / drivers / clocksource / h8300_timer16.c

// SPDX-License-Identifier: GPL-2.0
/*
 *  H8/300 16bit Timer driver
 *
 *  Copyright 2015 Yoshinori Sato <ysato@users.sourcefoge.jp>
 */

#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/clocksource.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>

#define TSTR	0
#define TISRC	6

#define TCR	0
#define TCNT	2

#define bset(b, a) iowrite8(ioread8(a) | (1 << (b)), (a))
#define bclr(b, a) iowrite8(ioread8(a) & ~(1 << (b)), (a))

struct timer16_priv {
	struct clocksource cs;
	unsigned long total_cycles;
	void __iomem *mapbase;
	void __iomem *mapcommon;
	unsigned short cs_enabled;
	unsigned char enb;
	unsigned char ovf;
	unsigned char ovie;
};

static unsigned long timer16_get_counter(struct timer16_priv *p)
{
	unsigned short v1, v2, v3;
	unsigned char  o1, o2;

	o1 = ioread8(p->mapcommon + TISRC) & p->ovf;

	/* Make sure the timer value is stable. Stolen from acpi_pm.c */
	do {
		o2 = o1;
		v1 = ioread16be(p->mapbase + TCNT);
		v2 = ioread16be(p->mapbase + TCNT);
		v3 = ioread16be(p->mapbase + TCNT);
		o1 = ioread8(p->mapcommon + TISRC) & p->ovf;
	} while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3)
			  || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2)));

	if (likely(!o1))
		return v2;
	else
		return v2 + 0x10000;
}


static irqreturn_t timer16_interrupt(int irq, void *dev_id)
{
	struct timer16_priv *p = (struct timer16_priv *)dev_id;

	bclr(p->ovf, p->mapcommon + TISRC);
	p->total_cycles += 0x10000;

	return IRQ_HANDLED;
}

static inline struct timer16_priv *cs_to_priv(struct clocksource *cs)
{
	return container_of(cs, struct timer16_priv, cs);
}

static u64 timer16_clocksource_read(struct clocksource *cs)
{
	struct timer16_priv *p = cs_to_priv(cs);
	unsigned long raw, value;

	value = p->total_cycles;
	raw = timer16_get_counter(p);

	return value + raw;
}

static int timer16_enable(struct clocksource *cs)
{
	struct timer16_priv *p = cs_to_priv(cs);

	WARN_ON(p->cs_enabled);

	p->total_cycles = 0;
	iowrite16be(0x0000, p->mapbase + TCNT);
	iowrite8(0x83, p->mapbase + TCR);
	bset(p->ovie, p->mapcommon + TISRC);
	bset(p->enb, p->mapcommon + TSTR);

	p->cs_enabled = true;
	return 0;
}

static void timer16_disable(struct clocksource *cs)
{
	struct timer16_priv *p = cs_to_priv(cs);

	WARN_ON(!p->cs_enabled);

	bclr(p->ovie, p->mapcommon + TISRC);
	bclr(p->enb, p->mapcommon + TSTR);

	p->cs_enabled = false;
}

static struct timer16_priv timer16_priv = {
	.cs = {
		.name = "h8300_16timer",
		.rating = 200,
		.read = timer16_clocksource_read,
		.enable = timer16_enable,
		.disable = timer16_disable,
		.mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8),
		.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	},
};

#define REG_CH   0
#define REG_COMM 1

static int __init h8300_16timer_init(struct device_node *node)
{
	void __iomem *base[2];
	int ret, irq;
	unsigned int ch;
	struct clk *clk;

	clk = of_clk_get(node, 0);
	if (IS_ERR(clk)) {
		pr_err("failed to get clock for clocksource\n");
		return PTR_ERR(clk);
	}

	ret = -ENXIO;
	base[REG_CH] = of_iomap(node, 0);
	if (!base[REG_CH]) {
		pr_err("failed to map registers for clocksource\n");
		goto free_clk;
	}

	base[REG_COMM] = of_iomap(node, 1);
	if (!base[REG_COMM]) {
		pr_err("failed to map registers for clocksource\n");
		goto unmap_ch;
	}

	ret = -EINVAL;
	irq = irq_of_parse_and_map(node, 0);
	if (!irq) {
		pr_err("failed to get irq for clockevent\n");
		goto unmap_comm;
	}

	of_property_read_u32(node, "renesas,channel", &ch);

	timer16_priv.mapbase = base[REG_CH];
	timer16_priv.mapcommon = base[REG_COMM];
	timer16_priv.enb = ch;
	timer16_priv.ovf = ch;
	timer16_priv.ovie = 4 + ch;

	ret = request_irq(irq, timer16_interrupt,
			  IRQF_TIMER, timer16_priv.cs.name, &timer16_priv);
	if (ret < 0) {
		pr_err("failed to request irq %d of clocksource\n", irq);
		goto unmap_comm;
	}

	clocksource_register_hz(&timer16_priv.cs,
				clk_get_rate(clk) / 8);
	return 0;

unmap_comm:
	iounmap(base[REG_COMM]);
unmap_ch:
	iounmap(base[REG_CH]);
free_clk:
	clk_put(clk);
	return ret;
}

TIMER_OF_DECLARE(h8300_16bit, "renesas,16bit-timer",
			   h8300_16timer_init);
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
618b902d YS	2	/*
	3	* H8/300 16bit Timer driver
	4	*
	5	* Copyright 2015 Yoshinori Sato <ysato@users.sourcefoge.jp>
	6	*/
	7
618b902d YS	8	#include <linux/interrupt.h>
618b902d YS	9	#include <linux/init.h>
618b902d	10	#include <linux/clocksource.h>
618b902d YS	11	#include <linux/clk.h>
	12	#include <linux/io.h>
	13	#include <linux/of.h>
4633f4ca YS	14	#include <linux/of_address.h>
4633f4ca YS	15	#include <linux/of_irq.h>
618b902d	16
618b902d	17	#define TSTR 0
618b902d YS	18	#define TISRC 6
	19
	20	#define TCR 0
618b902d	21	#define TCNT 2
618b902d	22
d33f250a YS	23	#define bset(b, a) iowrite8(ioread8(a) \| (1 << (b)), (a))
	24	#define bclr(b, a) iowrite8(ioread8(a) & ~(1 << (b)), (a))
	25
618b902d	26	struct timer16_priv {
618b902d	27	struct clocksource cs;
618b902d	28	unsigned long total_cycles;
75160515 DL	29	void __iomem *mapbase;
75160515 DL	30	void __iomem *mapcommon;
618b902d YS	31	unsigned short cs_enabled;
618b902d YS	32	unsigned char enb;
618b902d	33	unsigned char ovf;
2a0ff877	34	unsigned char ovie;
618b902d YS	35	};
	36
	37	static unsigned long timer16_get_counter(struct timer16_priv *p)
	38	{
d33f250a YS	39	unsigned short v1, v2, v3;
d33f250a YS	40	unsigned char o1, o2;
618b902d	41
d33f250a	42	o1 = ioread8(p->mapcommon + TISRC) & p->ovf;
618b902d YS	43
	44	/* Make sure the timer value is stable. Stolen from acpi_pm.c */
	45	do {
	46	o2 = o1;
d33f250a YS	47	v1 = ioread16be(p->mapbase + TCNT);
	48	v2 = ioread16be(p->mapbase + TCNT);
	49	v3 = ioread16be(p->mapbase + TCNT);
	50	o1 = ioread8(p->mapcommon + TISRC) & p->ovf;
618b902d YS	51	} while (unlikely((o1 != o2) \|\| (v1 > v2 && v1 < v3)
	52	\|\| (v2 > v3 && v2 < v1) \|\| (v3 > v1 && v3 < v2)));
	53
2f445e0a YS	54	if (likely(!o1))
	55	return v2;
	56	else
	57	return v2 + 0x10000;
618b902d YS	58	}
	59
	60
	61	static irqreturn_t timer16_interrupt(int irq, void *dev_id)
	62	{
	63	struct timer16_priv p = (struct timer16_priv )dev_id;
	64
d33f250a	65	bclr(p->ovf, p->mapcommon + TISRC);
618b902d YS	66	p->total_cycles += 0x10000;
	67
	68	return IRQ_HANDLED;
	69	}
	70
	71	static inline struct timer16_priv cs_to_priv(struct clocksource cs)
	72	{
	73	return container_of(cs, struct timer16_priv, cs);
	74	}
	75
a5a1d1c2	76	static u64 timer16_clocksource_read(struct clocksource *cs)
618b902d YS	77	{
618b902d YS	78	struct timer16_priv *p = cs_to_priv(cs);
05de7ed6	79	unsigned long raw, value;
618b902d	80
618b902d YS	81	value = p->total_cycles;
618b902d YS	82	raw = timer16_get_counter(p);
618b902d YS	83
	84	return value + raw;
	85	}
	86
	87	static int timer16_enable(struct clocksource *cs)
	88	{
	89	struct timer16_priv *p = cs_to_priv(cs);
	90
	91	WARN_ON(p->cs_enabled);
	92
	93	p->total_cycles = 0;
d33f250a YS	94	iowrite16be(0x0000, p->mapbase + TCNT);
	95	iowrite8(0x83, p->mapbase + TCR);
	96	bset(p->ovie, p->mapcommon + TISRC);
	97	bset(p->enb, p->mapcommon + TSTR);
618b902d YS	98
	99	p->cs_enabled = true;
	100	return 0;
	101	}
	102
	103	static void timer16_disable(struct clocksource *cs)
	104	{
	105	struct timer16_priv *p = cs_to_priv(cs);
	106
	107	WARN_ON(!p->cs_enabled);
	108
d33f250a YS	109	bclr(p->ovie, p->mapcommon + TISRC);
d33f250a YS	110	bclr(p->enb, p->mapcommon + TSTR);
618b902d YS	111
	112	p->cs_enabled = false;
	113	}
	114
4633f4ca YS	115	static struct timer16_priv timer16_priv = {
	116	.cs = {
	117	.name = "h8300_16timer",
	118	.rating = 200,
	119	.read = timer16_clocksource_read,
	120	.enable = timer16_enable,
	121	.disable = timer16_disable,
	122	.mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8),
	123	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	124	},
	125	};
	126
618b902d YS	127	#define REG_CH 0
	128	#define REG_COMM 1
	129
eacf2091	130	static int __init h8300_16timer_init(struct device_node *node)
618b902d	131	{
4633f4ca	132	void __iomem *base[2];
618b902d YS	133	int ret, irq;
618b902d YS	134	unsigned int ch;
4633f4ca	135	struct clk *clk;
618b902d	136
4633f4ca YS	137	clk = of_clk_get(node, 0);
	138	if (IS_ERR(clk)) {
	139	pr_err("failed to get clock for clocksource\n");
eacf2091	140	return PTR_ERR(clk);
618b902d YS	141	}
618b902d YS	142
eacf2091	143	ret = -ENXIO;
4633f4ca YS	144	base[REG_CH] = of_iomap(node, 0);
	145	if (!base[REG_CH]) {
	146	pr_err("failed to map registers for clocksource\n");
	147	goto free_clk;
618b902d	148	}
618b902d	149
4633f4ca YS	150	base[REG_COMM] = of_iomap(node, 1);
	151	if (!base[REG_COMM]) {
	152	pr_err("failed to map registers for clocksource\n");
	153	goto unmap_ch;
618b902d YS	154	}
618b902d YS	155
eacf2091	156	ret = -EINVAL;
4633f4ca	157	irq = irq_of_parse_and_map(node, 0);
5019c902	158	if (!irq) {
4633f4ca YS	159	pr_err("failed to get irq for clockevent\n");
4633f4ca YS	160	goto unmap_comm;
618b902d YS	161	}
618b902d YS	162
4633f4ca	163	of_property_read_u32(node, "renesas,channel", &ch);
618b902d	164
75160515 DL	165	timer16_priv.mapbase = base[REG_CH];
75160515 DL	166	timer16_priv.mapcommon = base[REG_COMM];
d33f250a YS	167	timer16_priv.enb = ch;
	168	timer16_priv.ovf = ch;
	169	timer16_priv.ovie = 4 + ch;
618b902d	170
4633f4ca YS	171	ret = request_irq(irq, timer16_interrupt,
	172	IRQF_TIMER, timer16_priv.cs.name, &timer16_priv);
	173	if (ret < 0) {
	174	pr_err("failed to request irq %d of clocksource\n", irq);
	175	goto unmap_comm;
618b902d	176	}
618b902d	177
4633f4ca	178	clocksource_register_hz(&timer16_priv.cs,
d33f250a	179	clk_get_rate(clk) / 8);
eacf2091	180	return 0;
618b902d	181
4633f4ca YS	182	unmap_comm:
	183	iounmap(base[REG_COMM]);
	184	unmap_ch:
	185	iounmap(base[REG_CH]);
	186	free_clk:
	187	clk_put(clk);
eacf2091	188	return ret;
618b902d YS	189	}
618b902d YS	190
17273395	191	TIMER_OF_DECLARE(h8300_16bit, "renesas,16bit-timer",
eacf2091	192	h8300_16timer_init);