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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
30d8bead CY |
2 | /* linux/arch/arm/mach-exynos4/mct.c |
3 | * | |
4 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | |
5 | * http://www.samsung.com | |
6 | * | |
4ad35346 | 7 | * Exynos4 MCT(Multi-Core Timer) support |
30d8bead CY |
8 | */ |
9 | ||
30d8bead CY |
10 | #include <linux/interrupt.h> |
11 | #include <linux/irq.h> | |
12 | #include <linux/err.h> | |
13 | #include <linux/clk.h> | |
14 | #include <linux/clockchips.h> | |
ee98d27d | 15 | #include <linux/cpu.h> |
30d8bead CY |
16 | #include <linux/delay.h> |
17 | #include <linux/percpu.h> | |
2edb36c4 | 18 | #include <linux/of.h> |
36ba5d52 TA |
19 | #include <linux/of_irq.h> |
20 | #include <linux/of_address.h> | |
9fbf0c85 | 21 | #include <linux/clocksource.h> |
93bfb769 | 22 | #include <linux/sched_clock.h> |
30d8bead | 23 | |
a1ba7a7a TA |
24 | #define EXYNOS4_MCTREG(x) (x) |
25 | #define EXYNOS4_MCT_G_CNT_L EXYNOS4_MCTREG(0x100) | |
26 | #define EXYNOS4_MCT_G_CNT_U EXYNOS4_MCTREG(0x104) | |
27 | #define EXYNOS4_MCT_G_CNT_WSTAT EXYNOS4_MCTREG(0x110) | |
28 | #define EXYNOS4_MCT_G_COMP0_L EXYNOS4_MCTREG(0x200) | |
29 | #define EXYNOS4_MCT_G_COMP0_U EXYNOS4_MCTREG(0x204) | |
30 | #define EXYNOS4_MCT_G_COMP0_ADD_INCR EXYNOS4_MCTREG(0x208) | |
31 | #define EXYNOS4_MCT_G_TCON EXYNOS4_MCTREG(0x240) | |
32 | #define EXYNOS4_MCT_G_INT_CSTAT EXYNOS4_MCTREG(0x244) | |
33 | #define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248) | |
34 | #define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C) | |
35 | #define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300) | |
36 | #define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x)) | |
37 | #define EXYNOS4_MCT_L_MASK (0xffffff00) | |
38 | ||
39 | #define MCT_L_TCNTB_OFFSET (0x00) | |
40 | #define MCT_L_ICNTB_OFFSET (0x08) | |
41 | #define MCT_L_TCON_OFFSET (0x20) | |
42 | #define MCT_L_INT_CSTAT_OFFSET (0x30) | |
43 | #define MCT_L_INT_ENB_OFFSET (0x34) | |
44 | #define MCT_L_WSTAT_OFFSET (0x40) | |
45 | #define MCT_G_TCON_START (1 << 8) | |
46 | #define MCT_G_TCON_COMP0_AUTO_INC (1 << 1) | |
47 | #define MCT_G_TCON_COMP0_ENABLE (1 << 0) | |
48 | #define MCT_L_TCON_INTERVAL_MODE (1 << 2) | |
49 | #define MCT_L_TCON_INT_START (1 << 1) | |
50 | #define MCT_L_TCON_TIMER_START (1 << 0) | |
51 | ||
4d2e4d7f CY |
52 | #define TICK_BASE_CNT 1 |
53 | ||
3a062281 CY |
54 | enum { |
55 | MCT_INT_SPI, | |
56 | MCT_INT_PPI | |
57 | }; | |
58 | ||
c371dc60 TA |
59 | enum { |
60 | MCT_G0_IRQ, | |
61 | MCT_G1_IRQ, | |
62 | MCT_G2_IRQ, | |
63 | MCT_G3_IRQ, | |
64 | MCT_L0_IRQ, | |
65 | MCT_L1_IRQ, | |
66 | MCT_L2_IRQ, | |
67 | MCT_L3_IRQ, | |
6c16dedf CK |
68 | MCT_L4_IRQ, |
69 | MCT_L5_IRQ, | |
70 | MCT_L6_IRQ, | |
71 | MCT_L7_IRQ, | |
c371dc60 TA |
72 | MCT_NR_IRQS, |
73 | }; | |
74 | ||
a1ba7a7a | 75 | static void __iomem *reg_base; |
30d8bead | 76 | static unsigned long clk_rate; |
3a062281 | 77 | static unsigned int mct_int_type; |
c371dc60 | 78 | static int mct_irqs[MCT_NR_IRQS]; |
30d8bead CY |
79 | |
80 | struct mct_clock_event_device { | |
ee98d27d | 81 | struct clock_event_device evt; |
a1ba7a7a | 82 | unsigned long base; |
c8987470 | 83 | char name[10]; |
30d8bead CY |
84 | }; |
85 | ||
a1ba7a7a | 86 | static void exynos4_mct_write(unsigned int value, unsigned long offset) |
30d8bead | 87 | { |
a1ba7a7a | 88 | unsigned long stat_addr; |
30d8bead CY |
89 | u32 mask; |
90 | u32 i; | |
91 | ||
fdb06f66 | 92 | writel_relaxed(value, reg_base + offset); |
30d8bead | 93 | |
a1ba7a7a | 94 | if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) { |
8c38d28b TJ |
95 | stat_addr = (offset & EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET; |
96 | switch (offset & ~EXYNOS4_MCT_L_MASK) { | |
a1ba7a7a | 97 | case MCT_L_TCON_OFFSET: |
c8987470 CY |
98 | mask = 1 << 3; /* L_TCON write status */ |
99 | break; | |
a1ba7a7a | 100 | case MCT_L_ICNTB_OFFSET: |
c8987470 CY |
101 | mask = 1 << 1; /* L_ICNTB write status */ |
102 | break; | |
a1ba7a7a | 103 | case MCT_L_TCNTB_OFFSET: |
c8987470 CY |
104 | mask = 1 << 0; /* L_TCNTB write status */ |
105 | break; | |
106 | default: | |
107 | return; | |
108 | } | |
109 | } else { | |
a1ba7a7a TA |
110 | switch (offset) { |
111 | case EXYNOS4_MCT_G_TCON: | |
c8987470 CY |
112 | stat_addr = EXYNOS4_MCT_G_WSTAT; |
113 | mask = 1 << 16; /* G_TCON write status */ | |
114 | break; | |
a1ba7a7a | 115 | case EXYNOS4_MCT_G_COMP0_L: |
c8987470 CY |
116 | stat_addr = EXYNOS4_MCT_G_WSTAT; |
117 | mask = 1 << 0; /* G_COMP0_L write status */ | |
118 | break; | |
a1ba7a7a | 119 | case EXYNOS4_MCT_G_COMP0_U: |
c8987470 CY |
120 | stat_addr = EXYNOS4_MCT_G_WSTAT; |
121 | mask = 1 << 1; /* G_COMP0_U write status */ | |
122 | break; | |
a1ba7a7a | 123 | case EXYNOS4_MCT_G_COMP0_ADD_INCR: |
c8987470 CY |
124 | stat_addr = EXYNOS4_MCT_G_WSTAT; |
125 | mask = 1 << 2; /* G_COMP0_ADD_INCR w status */ | |
126 | break; | |
a1ba7a7a | 127 | case EXYNOS4_MCT_G_CNT_L: |
c8987470 CY |
128 | stat_addr = EXYNOS4_MCT_G_CNT_WSTAT; |
129 | mask = 1 << 0; /* G_CNT_L write status */ | |
130 | break; | |
a1ba7a7a | 131 | case EXYNOS4_MCT_G_CNT_U: |
c8987470 CY |
132 | stat_addr = EXYNOS4_MCT_G_CNT_WSTAT; |
133 | mask = 1 << 1; /* G_CNT_U write status */ | |
134 | break; | |
135 | default: | |
136 | return; | |
137 | } | |
30d8bead CY |
138 | } |
139 | ||
140 | /* Wait maximum 1 ms until written values are applied */ | |
141 | for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++) | |
fdb06f66 DA |
142 | if (readl_relaxed(reg_base + stat_addr) & mask) { |
143 | writel_relaxed(mask, reg_base + stat_addr); | |
30d8bead CY |
144 | return; |
145 | } | |
146 | ||
a1ba7a7a | 147 | panic("MCT hangs after writing %d (offset:0x%lx)\n", value, offset); |
30d8bead CY |
148 | } |
149 | ||
150 | /* Clocksource handling */ | |
1d80415d | 151 | static void exynos4_mct_frc_start(void) |
30d8bead CY |
152 | { |
153 | u32 reg; | |
154 | ||
fdb06f66 | 155 | reg = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON); |
30d8bead CY |
156 | reg |= MCT_G_TCON_START; |
157 | exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON); | |
158 | } | |
159 | ||
3252a646 DA |
160 | /** |
161 | * exynos4_read_count_64 - Read all 64-bits of the global counter | |
162 | * | |
163 | * This will read all 64-bits of the global counter taking care to make sure | |
164 | * that the upper and lower half match. Note that reading the MCT can be quite | |
165 | * slow (hundreds of nanoseconds) so you should use the 32-bit (lower half | |
166 | * only) version when possible. | |
167 | * | |
168 | * Returns the number of cycles in the global counter. | |
169 | */ | |
170 | static u64 exynos4_read_count_64(void) | |
30d8bead CY |
171 | { |
172 | unsigned int lo, hi; | |
fdb06f66 | 173 | u32 hi2 = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_U); |
30d8bead CY |
174 | |
175 | do { | |
176 | hi = hi2; | |
fdb06f66 DA |
177 | lo = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_L); |
178 | hi2 = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_U); | |
30d8bead CY |
179 | } while (hi != hi2); |
180 | ||
a5a1d1c2 | 181 | return ((u64)hi << 32) | lo; |
30d8bead CY |
182 | } |
183 | ||
3252a646 DA |
184 | /** |
185 | * exynos4_read_count_32 - Read the lower 32-bits of the global counter | |
186 | * | |
187 | * This will read just the lower 32-bits of the global counter. This is marked | |
188 | * as notrace so it can be used by the scheduler clock. | |
189 | * | |
190 | * Returns the number of cycles in the global counter (lower 32 bits). | |
191 | */ | |
192 | static u32 notrace exynos4_read_count_32(void) | |
193 | { | |
194 | return readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_L); | |
195 | } | |
196 | ||
a5a1d1c2 | 197 | static u64 exynos4_frc_read(struct clocksource *cs) |
89e6a13b | 198 | { |
3252a646 | 199 | return exynos4_read_count_32(); |
89e6a13b DA |
200 | } |
201 | ||
aa421c13 CY |
202 | static void exynos4_frc_resume(struct clocksource *cs) |
203 | { | |
1d80415d | 204 | exynos4_mct_frc_start(); |
aa421c13 CY |
205 | } |
206 | ||
6c10bf63 | 207 | static struct clocksource mct_frc = { |
30d8bead | 208 | .name = "mct-frc", |
6282edb7 | 209 | .rating = 450, /* use value higher than ARM arch timer */ |
30d8bead | 210 | .read = exynos4_frc_read, |
3252a646 | 211 | .mask = CLOCKSOURCE_MASK(32), |
30d8bead | 212 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
aa421c13 | 213 | .resume = exynos4_frc_resume, |
30d8bead CY |
214 | }; |
215 | ||
93bfb769 VG |
216 | static u64 notrace exynos4_read_sched_clock(void) |
217 | { | |
3252a646 | 218 | return exynos4_read_count_32(); |
93bfb769 VG |
219 | } |
220 | ||
f1a4c1f3 | 221 | #if defined(CONFIG_ARM) |
8bf13a43 ADK |
222 | static struct delay_timer exynos4_delay_timer; |
223 | ||
224 | static cycles_t exynos4_read_current_timer(void) | |
225 | { | |
3252a646 DA |
226 | BUILD_BUG_ON_MSG(sizeof(cycles_t) != sizeof(u32), |
227 | "cycles_t needs to move to 32-bit for ARM64 usage"); | |
228 | return exynos4_read_count_32(); | |
8bf13a43 | 229 | } |
f1a4c1f3 | 230 | #endif |
8bf13a43 | 231 | |
5e558ebd | 232 | static int __init exynos4_clocksource_init(void) |
30d8bead | 233 | { |
1d80415d | 234 | exynos4_mct_frc_start(); |
30d8bead | 235 | |
f1a4c1f3 | 236 | #if defined(CONFIG_ARM) |
8bf13a43 ADK |
237 | exynos4_delay_timer.read_current_timer = &exynos4_read_current_timer; |
238 | exynos4_delay_timer.freq = clk_rate; | |
239 | register_current_timer_delay(&exynos4_delay_timer); | |
f1a4c1f3 | 240 | #endif |
8bf13a43 | 241 | |
30d8bead CY |
242 | if (clocksource_register_hz(&mct_frc, clk_rate)) |
243 | panic("%s: can't register clocksource\n", mct_frc.name); | |
93bfb769 | 244 | |
3252a646 | 245 | sched_clock_register(exynos4_read_sched_clock, 32, clk_rate); |
5e558ebd DL |
246 | |
247 | return 0; | |
30d8bead CY |
248 | } |
249 | ||
250 | static void exynos4_mct_comp0_stop(void) | |
251 | { | |
252 | unsigned int tcon; | |
253 | ||
fdb06f66 | 254 | tcon = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON); |
30d8bead CY |
255 | tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC); |
256 | ||
257 | exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON); | |
258 | exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB); | |
259 | } | |
260 | ||
79e436d3 | 261 | static void exynos4_mct_comp0_start(bool periodic, unsigned long cycles) |
30d8bead CY |
262 | { |
263 | unsigned int tcon; | |
a5a1d1c2 | 264 | u64 comp_cycle; |
30d8bead | 265 | |
fdb06f66 | 266 | tcon = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON); |
30d8bead | 267 | |
79e436d3 | 268 | if (periodic) { |
30d8bead CY |
269 | tcon |= MCT_G_TCON_COMP0_AUTO_INC; |
270 | exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR); | |
271 | } | |
272 | ||
3252a646 | 273 | comp_cycle = exynos4_read_count_64() + cycles; |
30d8bead CY |
274 | exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L); |
275 | exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U); | |
276 | ||
277 | exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB); | |
278 | ||
279 | tcon |= MCT_G_TCON_COMP0_ENABLE; | |
280 | exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON); | |
281 | } | |
282 | ||
283 | static int exynos4_comp_set_next_event(unsigned long cycles, | |
284 | struct clock_event_device *evt) | |
285 | { | |
79e436d3 | 286 | exynos4_mct_comp0_start(false, cycles); |
30d8bead CY |
287 | |
288 | return 0; | |
289 | } | |
290 | ||
79e436d3 | 291 | static int mct_set_state_shutdown(struct clock_event_device *evt) |
30d8bead CY |
292 | { |
293 | exynos4_mct_comp0_stop(); | |
79e436d3 VK |
294 | return 0; |
295 | } | |
30d8bead | 296 | |
79e436d3 VK |
297 | static int mct_set_state_periodic(struct clock_event_device *evt) |
298 | { | |
299 | unsigned long cycles_per_jiffy; | |
300 | ||
301 | cycles_per_jiffy = (((unsigned long long)NSEC_PER_SEC / HZ * evt->mult) | |
302 | >> evt->shift); | |
303 | exynos4_mct_comp0_stop(); | |
304 | exynos4_mct_comp0_start(true, cycles_per_jiffy); | |
305 | return 0; | |
30d8bead CY |
306 | } |
307 | ||
308 | static struct clock_event_device mct_comp_device = { | |
79e436d3 VK |
309 | .name = "mct-comp", |
310 | .features = CLOCK_EVT_FEAT_PERIODIC | | |
311 | CLOCK_EVT_FEAT_ONESHOT, | |
312 | .rating = 250, | |
313 | .set_next_event = exynos4_comp_set_next_event, | |
314 | .set_state_periodic = mct_set_state_periodic, | |
315 | .set_state_shutdown = mct_set_state_shutdown, | |
316 | .set_state_oneshot = mct_set_state_shutdown, | |
07f101d3 | 317 | .set_state_oneshot_stopped = mct_set_state_shutdown, |
79e436d3 | 318 | .tick_resume = mct_set_state_shutdown, |
30d8bead CY |
319 | }; |
320 | ||
321 | static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id) | |
322 | { | |
323 | struct clock_event_device *evt = dev_id; | |
324 | ||
325 | exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT); | |
326 | ||
327 | evt->event_handler(evt); | |
328 | ||
329 | return IRQ_HANDLED; | |
330 | } | |
331 | ||
5e558ebd | 332 | static int exynos4_clockevent_init(void) |
30d8bead | 333 | { |
30d8bead | 334 | mct_comp_device.cpumask = cpumask_of(0); |
838a2ae8 SG |
335 | clockevents_config_and_register(&mct_comp_device, clk_rate, |
336 | 0xf, 0xffffffff); | |
cc2550b4 | 337 | if (request_irq(mct_irqs[MCT_G0_IRQ], exynos4_mct_comp_isr, |
338 | IRQF_TIMER | IRQF_IRQPOLL, "mct_comp_irq", | |
339 | &mct_comp_device)) | |
340 | pr_err("%s: request_irq() failed\n", "mct_comp_irq"); | |
5e558ebd DL |
341 | |
342 | return 0; | |
30d8bead CY |
343 | } |
344 | ||
991a6c7d KK |
345 | static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick); |
346 | ||
30d8bead CY |
347 | /* Clock event handling */ |
348 | static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt) | |
349 | { | |
350 | unsigned long tmp; | |
351 | unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START; | |
a1ba7a7a | 352 | unsigned long offset = mevt->base + MCT_L_TCON_OFFSET; |
30d8bead | 353 | |
fdb06f66 | 354 | tmp = readl_relaxed(reg_base + offset); |
30d8bead CY |
355 | if (tmp & mask) { |
356 | tmp &= ~mask; | |
a1ba7a7a | 357 | exynos4_mct_write(tmp, offset); |
30d8bead CY |
358 | } |
359 | } | |
360 | ||
361 | static void exynos4_mct_tick_start(unsigned long cycles, | |
362 | struct mct_clock_event_device *mevt) | |
363 | { | |
364 | unsigned long tmp; | |
365 | ||
366 | exynos4_mct_tick_stop(mevt); | |
367 | ||
368 | tmp = (1 << 31) | cycles; /* MCT_L_UPDATE_ICNTB */ | |
369 | ||
370 | /* update interrupt count buffer */ | |
371 | exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET); | |
372 | ||
25985edc | 373 | /* enable MCT tick interrupt */ |
30d8bead CY |
374 | exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET); |
375 | ||
fdb06f66 | 376 | tmp = readl_relaxed(reg_base + mevt->base + MCT_L_TCON_OFFSET); |
30d8bead CY |
377 | tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START | |
378 | MCT_L_TCON_INTERVAL_MODE; | |
379 | exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET); | |
380 | } | |
381 | ||
a5719a40 SM |
382 | static void exynos4_mct_tick_clear(struct mct_clock_event_device *mevt) |
383 | { | |
384 | /* Clear the MCT tick interrupt */ | |
385 | if (readl_relaxed(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) | |
386 | exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET); | |
387 | } | |
388 | ||
30d8bead CY |
389 | static int exynos4_tick_set_next_event(unsigned long cycles, |
390 | struct clock_event_device *evt) | |
391 | { | |
31f79874 | 392 | struct mct_clock_event_device *mevt; |
30d8bead | 393 | |
31f79874 | 394 | mevt = container_of(evt, struct mct_clock_event_device, evt); |
30d8bead | 395 | exynos4_mct_tick_start(cycles, mevt); |
30d8bead CY |
396 | return 0; |
397 | } | |
398 | ||
79e436d3 VK |
399 | static int set_state_shutdown(struct clock_event_device *evt) |
400 | { | |
31f79874 AK |
401 | struct mct_clock_event_device *mevt; |
402 | ||
403 | mevt = container_of(evt, struct mct_clock_event_device, evt); | |
404 | exynos4_mct_tick_stop(mevt); | |
d2f276c8 | 405 | exynos4_mct_tick_clear(mevt); |
79e436d3 VK |
406 | return 0; |
407 | } | |
408 | ||
409 | static int set_state_periodic(struct clock_event_device *evt) | |
30d8bead | 410 | { |
31f79874 | 411 | struct mct_clock_event_device *mevt; |
4d2e4d7f | 412 | unsigned long cycles_per_jiffy; |
30d8bead | 413 | |
31f79874 | 414 | mevt = container_of(evt, struct mct_clock_event_device, evt); |
79e436d3 VK |
415 | cycles_per_jiffy = (((unsigned long long)NSEC_PER_SEC / HZ * evt->mult) |
416 | >> evt->shift); | |
30d8bead | 417 | exynos4_mct_tick_stop(mevt); |
79e436d3 VK |
418 | exynos4_mct_tick_start(cycles_per_jiffy, mevt); |
419 | return 0; | |
30d8bead CY |
420 | } |
421 | ||
a5719a40 | 422 | static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id) |
30d8bead | 423 | { |
a5719a40 SM |
424 | struct mct_clock_event_device *mevt = dev_id; |
425 | struct clock_event_device *evt = &mevt->evt; | |
426 | ||
30d8bead CY |
427 | /* |
428 | * This is for supporting oneshot mode. | |
429 | * Mct would generate interrupt periodically | |
430 | * without explicit stopping. | |
431 | */ | |
79e436d3 | 432 | if (!clockevent_state_periodic(&mevt->evt)) |
30d8bead CY |
433 | exynos4_mct_tick_stop(mevt); |
434 | ||
3a062281 | 435 | exynos4_mct_tick_clear(mevt); |
30d8bead CY |
436 | |
437 | evt->event_handler(evt); | |
438 | ||
439 | return IRQ_HANDLED; | |
440 | } | |
441 | ||
d11b3a60 | 442 | static int exynos4_mct_starting_cpu(unsigned int cpu) |
30d8bead | 443 | { |
d11b3a60 RC |
444 | struct mct_clock_event_device *mevt = |
445 | per_cpu_ptr(&percpu_mct_tick, cpu); | |
479a9329 | 446 | struct clock_event_device *evt = &mevt->evt; |
30d8bead | 447 | |
e700e41d | 448 | mevt->base = EXYNOS4_MCT_L_BASE(cpu); |
09e15176 | 449 | snprintf(mevt->name, sizeof(mevt->name), "mct_tick%d", cpu); |
30d8bead | 450 | |
e700e41d | 451 | evt->name = mevt->name; |
30d8bead CY |
452 | evt->cpumask = cpumask_of(cpu); |
453 | evt->set_next_event = exynos4_tick_set_next_event; | |
79e436d3 VK |
454 | evt->set_state_periodic = set_state_periodic; |
455 | evt->set_state_shutdown = set_state_shutdown; | |
456 | evt->set_state_oneshot = set_state_shutdown; | |
07f101d3 | 457 | evt->set_state_oneshot_stopped = set_state_shutdown; |
79e436d3 | 458 | evt->tick_resume = set_state_shutdown; |
30d8bead | 459 | evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; |
6282edb7 | 460 | evt->rating = 500; /* use value higher than ARM arch timer */ |
30d8bead | 461 | |
4d2e4d7f | 462 | exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET); |
30d8bead | 463 | |
3a062281 | 464 | if (mct_int_type == MCT_INT_SPI) { |
56a94f13 DE |
465 | |
466 | if (evt->irq == -1) | |
7114cd74 | 467 | return -EIO; |
56a94f13 DE |
468 | |
469 | irq_force_affinity(evt->irq, cpumask_of(cpu)); | |
470 | enable_irq(evt->irq); | |
30d8bead | 471 | } else { |
c371dc60 | 472 | enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0); |
30d8bead | 473 | } |
8db6e510 KK |
474 | clockevents_config_and_register(evt, clk_rate / (TICK_BASE_CNT + 1), |
475 | 0xf, 0x7fffffff); | |
4d487d7e KK |
476 | |
477 | return 0; | |
30d8bead CY |
478 | } |
479 | ||
d11b3a60 | 480 | static int exynos4_mct_dying_cpu(unsigned int cpu) |
30d8bead | 481 | { |
d11b3a60 RC |
482 | struct mct_clock_event_device *mevt = |
483 | per_cpu_ptr(&percpu_mct_tick, cpu); | |
479a9329 AK |
484 | struct clock_event_device *evt = &mevt->evt; |
485 | ||
79e436d3 | 486 | evt->set_state_shutdown(evt); |
56a94f13 DE |
487 | if (mct_int_type == MCT_INT_SPI) { |
488 | if (evt->irq != -1) | |
489 | disable_irq_nosync(evt->irq); | |
bc7c36ee | 490 | exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET); |
56a94f13 | 491 | } else { |
c371dc60 | 492 | disable_percpu_irq(mct_irqs[MCT_L0_IRQ]); |
56a94f13 | 493 | } |
d11b3a60 | 494 | return 0; |
30d8bead | 495 | } |
a8cb6041 | 496 | |
5e558ebd | 497 | static int __init exynos4_timer_resources(struct device_node *np, void __iomem *base) |
30d8bead | 498 | { |
56a94f13 | 499 | int err, cpu; |
ca9048ec | 500 | struct clk *mct_clk, *tick_clk; |
30d8bead | 501 | |
9fd464fe | 502 | tick_clk = of_clk_get_by_name(np, "fin_pll"); |
415ac2e2 TA |
503 | if (IS_ERR(tick_clk)) |
504 | panic("%s: unable to determine tick clock rate\n", __func__); | |
505 | clk_rate = clk_get_rate(tick_clk); | |
e700e41d | 506 | |
9fd464fe | 507 | mct_clk = of_clk_get_by_name(np, "mct"); |
ca9048ec TA |
508 | if (IS_ERR(mct_clk)) |
509 | panic("%s: unable to retrieve mct clock instance\n", __func__); | |
510 | clk_prepare_enable(mct_clk); | |
e700e41d | 511 | |
228e3023 | 512 | reg_base = base; |
36ba5d52 TA |
513 | if (!reg_base) |
514 | panic("%s: unable to ioremap mct address space\n", __func__); | |
a1ba7a7a | 515 | |
e700e41d | 516 | if (mct_int_type == MCT_INT_PPI) { |
e700e41d | 517 | |
c371dc60 | 518 | err = request_percpu_irq(mct_irqs[MCT_L0_IRQ], |
e700e41d MZ |
519 | exynos4_mct_tick_isr, "MCT", |
520 | &percpu_mct_tick); | |
521 | WARN(err, "MCT: can't request IRQ %d (%d)\n", | |
c371dc60 | 522 | mct_irqs[MCT_L0_IRQ], err); |
5df718d8 | 523 | } else { |
56a94f13 DE |
524 | for_each_possible_cpu(cpu) { |
525 | int mct_irq = mct_irqs[MCT_L0_IRQ + cpu]; | |
526 | struct mct_clock_event_device *pcpu_mevt = | |
527 | per_cpu_ptr(&percpu_mct_tick, cpu); | |
528 | ||
529 | pcpu_mevt->evt.irq = -1; | |
530 | ||
531 | irq_set_status_flags(mct_irq, IRQ_NOAUTOEN); | |
532 | if (request_irq(mct_irq, | |
533 | exynos4_mct_tick_isr, | |
534 | IRQF_TIMER | IRQF_NOBALANCING, | |
535 | pcpu_mevt->name, pcpu_mevt)) { | |
536 | pr_err("exynos-mct: cannot register IRQ (cpu%d)\n", | |
537 | cpu); | |
538 | ||
539 | continue; | |
540 | } | |
541 | pcpu_mevt->evt.irq = mct_irq; | |
542 | } | |
e700e41d | 543 | } |
a8cb6041 | 544 | |
d11b3a60 RC |
545 | /* Install hotplug callbacks which configure the timer on this CPU */ |
546 | err = cpuhp_setup_state(CPUHP_AP_EXYNOS4_MCT_TIMER_STARTING, | |
73c1b41e | 547 | "clockevents/exynos4/mct_timer:starting", |
d11b3a60 RC |
548 | exynos4_mct_starting_cpu, |
549 | exynos4_mct_dying_cpu); | |
ee98d27d SB |
550 | if (err) |
551 | goto out_irq; | |
552 | ||
5e558ebd | 553 | return 0; |
ee98d27d SB |
554 | |
555 | out_irq: | |
b9307420 MS |
556 | if (mct_int_type == MCT_INT_PPI) { |
557 | free_percpu_irq(mct_irqs[MCT_L0_IRQ], &percpu_mct_tick); | |
558 | } else { | |
559 | for_each_possible_cpu(cpu) { | |
560 | struct mct_clock_event_device *pcpu_mevt = | |
561 | per_cpu_ptr(&percpu_mct_tick, cpu); | |
562 | ||
563 | if (pcpu_mevt->evt.irq != -1) { | |
564 | free_irq(pcpu_mevt->evt.irq, pcpu_mevt); | |
565 | pcpu_mevt->evt.irq = -1; | |
566 | } | |
567 | } | |
568 | } | |
5e558ebd | 569 | return err; |
30d8bead CY |
570 | } |
571 | ||
5e558ebd | 572 | static int __init mct_init_dt(struct device_node *np, unsigned int int_type) |
228e3023 AB |
573 | { |
574 | u32 nr_irqs, i; | |
5e558ebd | 575 | int ret; |
228e3023 AB |
576 | |
577 | mct_int_type = int_type; | |
578 | ||
579 | /* This driver uses only one global timer interrupt */ | |
580 | mct_irqs[MCT_G0_IRQ] = irq_of_parse_and_map(np, MCT_G0_IRQ); | |
581 | ||
582 | /* | |
583 | * Find out the number of local irqs specified. The local | |
584 | * timer irqs are specified after the four global timer | |
585 | * irqs are specified. | |
586 | */ | |
587 | nr_irqs = of_irq_count(np); | |
588 | for (i = MCT_L0_IRQ; i < nr_irqs; i++) | |
589 | mct_irqs[i] = irq_of_parse_and_map(np, i); | |
590 | ||
5e558ebd DL |
591 | ret = exynos4_timer_resources(np, of_iomap(np, 0)); |
592 | if (ret) | |
593 | return ret; | |
594 | ||
595 | ret = exynos4_clocksource_init(); | |
596 | if (ret) | |
597 | return ret; | |
598 | ||
599 | return exynos4_clockevent_init(); | |
30d8bead | 600 | } |
228e3023 AB |
601 | |
602 | ||
5e558ebd | 603 | static int __init mct_init_spi(struct device_node *np) |
228e3023 AB |
604 | { |
605 | return mct_init_dt(np, MCT_INT_SPI); | |
606 | } | |
607 | ||
5e558ebd | 608 | static int __init mct_init_ppi(struct device_node *np) |
228e3023 AB |
609 | { |
610 | return mct_init_dt(np, MCT_INT_PPI); | |
611 | } | |
17273395 DL |
612 | TIMER_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init_spi); |
613 | TIMER_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init_ppi); |