[linux-2.6-block.git] / drivers / clocksource / exynos_mct.c

/* linux/arch/arm/mach-exynos4/mct.c
 *
 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * EXYNOS4 MCT(Multi-Core Timer) support
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/cpu.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/percpu.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/clocksource.h>

#include <asm/mach/time.h>

#define EXYNOS4_MCTREG(x)		(x)
#define EXYNOS4_MCT_G_CNT_L		EXYNOS4_MCTREG(0x100)
#define EXYNOS4_MCT_G_CNT_U		EXYNOS4_MCTREG(0x104)
#define EXYNOS4_MCT_G_CNT_WSTAT		EXYNOS4_MCTREG(0x110)
#define EXYNOS4_MCT_G_COMP0_L		EXYNOS4_MCTREG(0x200)
#define EXYNOS4_MCT_G_COMP0_U		EXYNOS4_MCTREG(0x204)
#define EXYNOS4_MCT_G_COMP0_ADD_INCR	EXYNOS4_MCTREG(0x208)
#define EXYNOS4_MCT_G_TCON		EXYNOS4_MCTREG(0x240)
#define EXYNOS4_MCT_G_INT_CSTAT		EXYNOS4_MCTREG(0x244)
#define EXYNOS4_MCT_G_INT_ENB		EXYNOS4_MCTREG(0x248)
#define EXYNOS4_MCT_G_WSTAT		EXYNOS4_MCTREG(0x24C)
#define _EXYNOS4_MCT_L_BASE		EXYNOS4_MCTREG(0x300)
#define EXYNOS4_MCT_L_BASE(x)		(_EXYNOS4_MCT_L_BASE + (0x100 * x))
#define EXYNOS4_MCT_L_MASK		(0xffffff00)

#define MCT_L_TCNTB_OFFSET		(0x00)
#define MCT_L_ICNTB_OFFSET		(0x08)
#define MCT_L_TCON_OFFSET		(0x20)
#define MCT_L_INT_CSTAT_OFFSET		(0x30)
#define MCT_L_INT_ENB_OFFSET		(0x34)
#define MCT_L_WSTAT_OFFSET		(0x40)
#define MCT_G_TCON_START		(1 << 8)
#define MCT_G_TCON_COMP0_AUTO_INC	(1 << 1)
#define MCT_G_TCON_COMP0_ENABLE		(1 << 0)
#define MCT_L_TCON_INTERVAL_MODE	(1 << 2)
#define MCT_L_TCON_INT_START		(1 << 1)
#define MCT_L_TCON_TIMER_START		(1 << 0)

#define TICK_BASE_CNT	1

enum {
	MCT_INT_SPI,
	MCT_INT_PPI
};

enum {
	MCT_G0_IRQ,
	MCT_G1_IRQ,
	MCT_G2_IRQ,
	MCT_G3_IRQ,
	MCT_L0_IRQ,
	MCT_L1_IRQ,
	MCT_L2_IRQ,
	MCT_L3_IRQ,
	MCT_L4_IRQ,
	MCT_L5_IRQ,
	MCT_L6_IRQ,
	MCT_L7_IRQ,
	MCT_NR_IRQS,
};

static void __iomem *reg_base;
static unsigned long clk_rate;
static unsigned int mct_int_type;
static int mct_irqs[MCT_NR_IRQS];

struct mct_clock_event_device {
	struct clock_event_device evt;
	unsigned long base;
	char name[10];
};

static void exynos4_mct_write(unsigned int value, unsigned long offset)
{
	unsigned long stat_addr;
	u32 mask;
	u32 i;

	__raw_writel(value, reg_base + offset);

	if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) {
		stat_addr = (offset & ~EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET;
		switch (offset & EXYNOS4_MCT_L_MASK) {
		case MCT_L_TCON_OFFSET:
			mask = 1 << 3;		/* L_TCON write status */
			break;
		case MCT_L_ICNTB_OFFSET:
			mask = 1 << 1;		/* L_ICNTB write status */
			break;
		case MCT_L_TCNTB_OFFSET:
			mask = 1 << 0;		/* L_TCNTB write status */
			break;
		default:
			return;
		}
	} else {
		switch (offset) {
		case EXYNOS4_MCT_G_TCON:
			stat_addr = EXYNOS4_MCT_G_WSTAT;
			mask = 1 << 16;		/* G_TCON write status */
			break;
		case EXYNOS4_MCT_G_COMP0_L:
			stat_addr = EXYNOS4_MCT_G_WSTAT;
			mask = 1 << 0;		/* G_COMP0_L write status */
			break;
		case EXYNOS4_MCT_G_COMP0_U:
			stat_addr = EXYNOS4_MCT_G_WSTAT;
			mask = 1 << 1;		/* G_COMP0_U write status */
			break;
		case EXYNOS4_MCT_G_COMP0_ADD_INCR:
			stat_addr = EXYNOS4_MCT_G_WSTAT;
			mask = 1 << 2;		/* G_COMP0_ADD_INCR w status */
			break;
		case EXYNOS4_MCT_G_CNT_L:
			stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
			mask = 1 << 0;		/* G_CNT_L write status */
			break;
		case EXYNOS4_MCT_G_CNT_U:
			stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
			mask = 1 << 1;		/* G_CNT_U write status */
			break;
		default:
			return;
		}
	}

	/* Wait maximum 1 ms until written values are applied */
	for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
		if (__raw_readl(reg_base + stat_addr) & mask) {
			__raw_writel(mask, reg_base + stat_addr);
			return;
		}

	panic("MCT hangs after writing %d (offset:0x%lx)\n", value, offset);
}

/* Clocksource handling */
static void exynos4_mct_frc_start(u32 hi, u32 lo)
{
	u32 reg;

	exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L);
	exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U);

	reg = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
	reg |= MCT_G_TCON_START;
	exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
}

static cycle_t exynos4_frc_read(struct clocksource *cs)
{
	unsigned int lo, hi;
	u32 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);

	do {
		hi = hi2;
		lo = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_L);
		hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
	} while (hi != hi2);

	return ((cycle_t)hi << 32) | lo;
}

static void exynos4_frc_resume(struct clocksource *cs)
{
	exynos4_mct_frc_start(0, 0);
}

struct clocksource mct_frc = {
	.name		= "mct-frc",
	.rating		= 400,
	.read		= exynos4_frc_read,
	.mask		= CLOCKSOURCE_MASK(64),
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
	.resume		= exynos4_frc_resume,
};

static void __init exynos4_clocksource_init(void)
{
	exynos4_mct_frc_start(0, 0);

	if (clocksource_register_hz(&mct_frc, clk_rate))
		panic("%s: can't register clocksource\n", mct_frc.name);
}

static void exynos4_mct_comp0_stop(void)
{
	unsigned int tcon;

	tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
	tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC);

	exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
	exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB);
}

static void exynos4_mct_comp0_start(enum clock_event_mode mode,
				    unsigned long cycles)
{
	unsigned int tcon;
	cycle_t comp_cycle;

	tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);

	if (mode == CLOCK_EVT_MODE_PERIODIC) {
		tcon |= MCT_G_TCON_COMP0_AUTO_INC;
		exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR);
	}

	comp_cycle = exynos4_frc_read(&mct_frc) + cycles;
	exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L);
	exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U);

	exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB);

	tcon |= MCT_G_TCON_COMP0_ENABLE;
	exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON);
}

static int exynos4_comp_set_next_event(unsigned long cycles,
				       struct clock_event_device *evt)
{
	exynos4_mct_comp0_start(evt->mode, cycles);

	return 0;
}

static void exynos4_comp_set_mode(enum clock_event_mode mode,
				  struct clock_event_device *evt)
{
	unsigned long cycles_per_jiffy;
	exynos4_mct_comp0_stop();

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		cycles_per_jiffy =
			(((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
		exynos4_mct_comp0_start(mode, cycles_per_jiffy);
		break;

	case CLOCK_EVT_MODE_ONESHOT:
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
	case CLOCK_EVT_MODE_RESUME:
		break;
	}
}

static struct clock_event_device mct_comp_device = {
	.name		= "mct-comp",
	.features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
	.rating		= 250,
	.set_next_event	= exynos4_comp_set_next_event,
	.set_mode	= exynos4_comp_set_mode,
};

static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;

	exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT);

	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static struct irqaction mct_comp_event_irq = {
	.name		= "mct_comp_irq",
	.flags		= IRQF_TIMER | IRQF_IRQPOLL,
	.handler	= exynos4_mct_comp_isr,
	.dev_id		= &mct_comp_device,
};

static void exynos4_clockevent_init(void)
{
	mct_comp_device.cpumask = cpumask_of(0);
	clockevents_config_and_register(&mct_comp_device, clk_rate,
					0xf, 0xffffffff);
	setup_irq(mct_irqs[MCT_G0_IRQ], &mct_comp_event_irq);
}

static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick);

/* Clock event handling */
static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
{
	unsigned long tmp;
	unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START;
	unsigned long offset = mevt->base + MCT_L_TCON_OFFSET;

	tmp = __raw_readl(reg_base + offset);
	if (tmp & mask) {
		tmp &= ~mask;
		exynos4_mct_write(tmp, offset);
	}
}

static void exynos4_mct_tick_start(unsigned long cycles,
				   struct mct_clock_event_device *mevt)
{
	unsigned long tmp;

	exynos4_mct_tick_stop(mevt);

	tmp = (1 << 31) | cycles;	/* MCT_L_UPDATE_ICNTB */

	/* update interrupt count buffer */
	exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET);

	/* enable MCT tick interrupt */
	exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);

	tmp = __raw_readl(reg_base + mevt->base + MCT_L_TCON_OFFSET);
	tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START |
	       MCT_L_TCON_INTERVAL_MODE;
	exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
}

static int exynos4_tick_set_next_event(unsigned long cycles,
				       struct clock_event_device *evt)
{
	struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);

	exynos4_mct_tick_start(cycles, mevt);

	return 0;
}

static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
					 struct clock_event_device *evt)
{
	struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
	unsigned long cycles_per_jiffy;

	exynos4_mct_tick_stop(mevt);

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		cycles_per_jiffy =
			(((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
		exynos4_mct_tick_start(cycles_per_jiffy, mevt);
		break;

	case CLOCK_EVT_MODE_ONESHOT:
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
	case CLOCK_EVT_MODE_RESUME:
		break;
	}
}

static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
{
	struct clock_event_device *evt = &mevt->evt;

	/*
	 * This is for supporting oneshot mode.
	 * Mct would generate interrupt periodically
	 * without explicit stopping.
	 */
	if (evt->mode != CLOCK_EVT_MODE_PERIODIC)
		exynos4_mct_tick_stop(mevt);

	/* Clear the MCT tick interrupt */
	if (__raw_readl(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
		exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
		return 1;
	} else {
		return 0;
	}
}

static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
{
	struct mct_clock_event_device *mevt = dev_id;
	struct clock_event_device *evt = &mevt->evt;

	exynos4_mct_tick_clear(mevt);

	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static int exynos4_local_timer_setup(struct clock_event_device *evt)
{
	struct mct_clock_event_device *mevt;
	unsigned int cpu = smp_processor_id();

	mevt = container_of(evt, struct mct_clock_event_device, evt);

	mevt->base = EXYNOS4_MCT_L_BASE(cpu);
	sprintf(mevt->name, "mct_tick%d", cpu);

	evt->name = mevt->name;
	evt->cpumask = cpumask_of(cpu);
	evt->set_next_event = exynos4_tick_set_next_event;
	evt->set_mode = exynos4_tick_set_mode;
	evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
	evt->rating = 450;
	clockevents_config_and_register(evt, clk_rate / (TICK_BASE_CNT + 1),
					0xf, 0x7fffffff);

	exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET);

	if (mct_int_type == MCT_INT_SPI) {
		evt->irq = mct_irqs[MCT_L0_IRQ + cpu];
		if (request_irq(evt->irq, exynos4_mct_tick_isr,
				IRQF_TIMER | IRQF_NOBALANCING,
				evt->name, mevt)) {
			pr_err("exynos-mct: cannot register IRQ %d\n",
				evt->irq);
			return -EIO;
		}
	} else {
		enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0);
	}

	return 0;
}

static void exynos4_local_timer_stop(struct clock_event_device *evt)
{
	evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
	if (mct_int_type == MCT_INT_SPI)
		free_irq(evt->irq, this_cpu_ptr(&percpu_mct_tick));
	else
		disable_percpu_irq(mct_irqs[MCT_L0_IRQ]);
}

static int exynos4_mct_cpu_notify(struct notifier_block *self,
					   unsigned long action, void *hcpu)
{
	struct mct_clock_event_device *mevt;
	unsigned int cpu;

	/*
	 * Grab cpu pointer in each case to avoid spurious
	 * preemptible warnings
	 */
	switch (action & ~CPU_TASKS_FROZEN) {
	case CPU_STARTING:
		mevt = this_cpu_ptr(&percpu_mct_tick);
		exynos4_local_timer_setup(&mevt->evt);
		break;
	case CPU_ONLINE:
		cpu = (unsigned long)hcpu;
		if (mct_int_type == MCT_INT_SPI)
			irq_set_affinity(mct_irqs[MCT_L0_IRQ + cpu],
						cpumask_of(cpu));
		break;
	case CPU_DYING:
		mevt = this_cpu_ptr(&percpu_mct_tick);
		exynos4_local_timer_stop(&mevt->evt);
		break;
	}

	return NOTIFY_OK;
}

static struct notifier_block exynos4_mct_cpu_nb = {
	.notifier_call = exynos4_mct_cpu_notify,
};

static void __init exynos4_timer_resources(struct device_node *np, void __iomem *base)
{
	int err;
	struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
	struct clk *mct_clk, *tick_clk;

	tick_clk = np ? of_clk_get_by_name(np, "fin_pll") :
				clk_get(NULL, "fin_pll");
	if (IS_ERR(tick_clk))
		panic("%s: unable to determine tick clock rate\n", __func__);
	clk_rate = clk_get_rate(tick_clk);

	mct_clk = np ? of_clk_get_by_name(np, "mct") : clk_get(NULL, "mct");
	if (IS_ERR(mct_clk))
		panic("%s: unable to retrieve mct clock instance\n", __func__);
	clk_prepare_enable(mct_clk);

	reg_base = base;
	if (!reg_base)
		panic("%s: unable to ioremap mct address space\n", __func__);

	if (mct_int_type == MCT_INT_PPI) {

		err = request_percpu_irq(mct_irqs[MCT_L0_IRQ],
					 exynos4_mct_tick_isr, "MCT",
					 &percpu_mct_tick);
		WARN(err, "MCT: can't request IRQ %d (%d)\n",
		     mct_irqs[MCT_L0_IRQ], err);
	} else {
		irq_set_affinity(mct_irqs[MCT_L0_IRQ], cpumask_of(0));
	}

	err = register_cpu_notifier(&exynos4_mct_cpu_nb);
	if (err)
		goto out_irq;

	/* Immediately configure the timer on the boot CPU */
	exynos4_local_timer_setup(&mevt->evt);
	return;

out_irq:
	free_percpu_irq(mct_irqs[MCT_L0_IRQ], &percpu_mct_tick);
}

void __init mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1)
{
	mct_irqs[MCT_G0_IRQ] = irq_g0;
	mct_irqs[MCT_L0_IRQ] = irq_l0;
	mct_irqs[MCT_L1_IRQ] = irq_l1;
	mct_int_type = MCT_INT_SPI;

	exynos4_timer_resources(NULL, base);
	exynos4_clocksource_init();
	exynos4_clockevent_init();
}

static void __init mct_init_dt(struct device_node *np, unsigned int int_type)
{
	u32 nr_irqs, i;

	mct_int_type = int_type;

	/* This driver uses only one global timer interrupt */
	mct_irqs[MCT_G0_IRQ] = irq_of_parse_and_map(np, MCT_G0_IRQ);

	/*
	 * Find out the number of local irqs specified. The local
	 * timer irqs are specified after the four global timer
	 * irqs are specified.
	 */
#ifdef CONFIG_OF
	nr_irqs = of_irq_count(np);
#else
	nr_irqs = 0;
#endif
	for (i = MCT_L0_IRQ; i < nr_irqs; i++)
		mct_irqs[i] = irq_of_parse_and_map(np, i);

	exynos4_timer_resources(np, of_iomap(np, 0));
	exynos4_clocksource_init();
	exynos4_clockevent_init();
}


static void __init mct_init_spi(struct device_node *np)
{
	return mct_init_dt(np, MCT_INT_SPI);
}

static void __init mct_init_ppi(struct device_node *np)
{
	return mct_init_dt(np, MCT_INT_PPI);
}
CLOCKSOURCE_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init_spi);
CLOCKSOURCE_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init_ppi);
Commit	Line	Data
30d8bead CY	1	/* linux/arch/arm/mach-exynos4/mct.c
	2	*
	3	* Copyright (c) 2011 Samsung Electronics Co., Ltd.
	4	* http://www.samsung.com
	5	*
	6	* EXYNOS4 MCT(Multi-Core Timer) support
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	#include <linux/sched.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/irq.h>
	16	#include <linux/err.h>
	17	#include <linux/clk.h>
	18	#include <linux/clockchips.h>
ee98d27d	19	#include <linux/cpu.h>
30d8bead CY	20	#include <linux/platform_device.h>
	21	#include <linux/delay.h>
	22	#include <linux/percpu.h>
2edb36c4	23	#include <linux/of.h>
36ba5d52 TA	24	#include <linux/of_irq.h>
36ba5d52 TA	25	#include <linux/of_address.h>
9fbf0c85	26	#include <linux/clocksource.h>
30d8bead	27
30d8bead CY	28	#include <asm/mach/time.h>
30d8bead CY	29
a1ba7a7a TA	30	#define EXYNOS4_MCTREG(x) (x)
	31	#define EXYNOS4_MCT_G_CNT_L EXYNOS4_MCTREG(0x100)
	32	#define EXYNOS4_MCT_G_CNT_U EXYNOS4_MCTREG(0x104)
	33	#define EXYNOS4_MCT_G_CNT_WSTAT EXYNOS4_MCTREG(0x110)
	34	#define EXYNOS4_MCT_G_COMP0_L EXYNOS4_MCTREG(0x200)
	35	#define EXYNOS4_MCT_G_COMP0_U EXYNOS4_MCTREG(0x204)
	36	#define EXYNOS4_MCT_G_COMP0_ADD_INCR EXYNOS4_MCTREG(0x208)
	37	#define EXYNOS4_MCT_G_TCON EXYNOS4_MCTREG(0x240)
	38	#define EXYNOS4_MCT_G_INT_CSTAT EXYNOS4_MCTREG(0x244)
	39	#define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248)
	40	#define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C)
	41	#define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300)
	42	#define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x))
	43	#define EXYNOS4_MCT_L_MASK (0xffffff00)
	44
	45	#define MCT_L_TCNTB_OFFSET (0x00)
	46	#define MCT_L_ICNTB_OFFSET (0x08)
	47	#define MCT_L_TCON_OFFSET (0x20)
	48	#define MCT_L_INT_CSTAT_OFFSET (0x30)
	49	#define MCT_L_INT_ENB_OFFSET (0x34)
	50	#define MCT_L_WSTAT_OFFSET (0x40)
	51	#define MCT_G_TCON_START (1 << 8)
	52	#define MCT_G_TCON_COMP0_AUTO_INC (1 << 1)
	53	#define MCT_G_TCON_COMP0_ENABLE (1 << 0)
	54	#define MCT_L_TCON_INTERVAL_MODE (1 << 2)
	55	#define MCT_L_TCON_INT_START (1 << 1)
	56	#define MCT_L_TCON_TIMER_START (1 << 0)
	57
4d2e4d7f CY	58	#define TICK_BASE_CNT 1
4d2e4d7f CY	59
3a062281 CY	60	enum {
	61	MCT_INT_SPI,
	62	MCT_INT_PPI
	63	};
	64
c371dc60 TA	65	enum {
	66	MCT_G0_IRQ,
	67	MCT_G1_IRQ,
	68	MCT_G2_IRQ,
	69	MCT_G3_IRQ,
	70	MCT_L0_IRQ,
	71	MCT_L1_IRQ,
	72	MCT_L2_IRQ,
	73	MCT_L3_IRQ,
6c16dedf CK	74	MCT_L4_IRQ,
	75	MCT_L5_IRQ,
	76	MCT_L6_IRQ,
	77	MCT_L7_IRQ,
c371dc60 TA	78	MCT_NR_IRQS,
	79	};
	80
a1ba7a7a	81	static void __iomem *reg_base;
30d8bead	82	static unsigned long clk_rate;
3a062281	83	static unsigned int mct_int_type;
c371dc60	84	static int mct_irqs[MCT_NR_IRQS];
30d8bead CY	85
30d8bead CY	86	struct mct_clock_event_device {
ee98d27d	87	struct clock_event_device evt;
a1ba7a7a	88	unsigned long base;
c8987470	89	char name[10];
30d8bead CY	90	};
30d8bead CY	91
a1ba7a7a	92	static void exynos4_mct_write(unsigned int value, unsigned long offset)
30d8bead	93	{
a1ba7a7a	94	unsigned long stat_addr;
30d8bead CY	95	u32 mask;
	96	u32 i;
	97
a1ba7a7a	98	__raw_writel(value, reg_base + offset);
30d8bead	99
a1ba7a7a TA	100	if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) {
	101	stat_addr = (offset & ~EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET;
	102	switch (offset & EXYNOS4_MCT_L_MASK) {
	103	case MCT_L_TCON_OFFSET:
c8987470 CY	104	mask = 1 << 3; /* L_TCON write status */
c8987470 CY	105	break;
a1ba7a7a	106	case MCT_L_ICNTB_OFFSET:
c8987470 CY	107	mask = 1 << 1; /* L_ICNTB write status */
c8987470 CY	108	break;
a1ba7a7a	109	case MCT_L_TCNTB_OFFSET:
c8987470 CY	110	mask = 1 << 0; /* L_TCNTB write status */
	111	break;
	112	default:
	113	return;
	114	}
	115	} else {
a1ba7a7a TA	116	switch (offset) {
a1ba7a7a TA	117	case EXYNOS4_MCT_G_TCON:
c8987470 CY	118	stat_addr = EXYNOS4_MCT_G_WSTAT;
	119	mask = 1 << 16; /* G_TCON write status */
	120	break;
a1ba7a7a	121	case EXYNOS4_MCT_G_COMP0_L:
c8987470 CY	122	stat_addr = EXYNOS4_MCT_G_WSTAT;
	123	mask = 1 << 0; /* G_COMP0_L write status */
	124	break;
a1ba7a7a	125	case EXYNOS4_MCT_G_COMP0_U:
c8987470 CY	126	stat_addr = EXYNOS4_MCT_G_WSTAT;
	127	mask = 1 << 1; /* G_COMP0_U write status */
	128	break;
a1ba7a7a	129	case EXYNOS4_MCT_G_COMP0_ADD_INCR:
c8987470 CY	130	stat_addr = EXYNOS4_MCT_G_WSTAT;
	131	mask = 1 << 2; /* G_COMP0_ADD_INCR w status */
	132	break;
a1ba7a7a	133	case EXYNOS4_MCT_G_CNT_L:
c8987470 CY	134	stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
	135	mask = 1 << 0; /* G_CNT_L write status */
	136	break;
a1ba7a7a	137	case EXYNOS4_MCT_G_CNT_U:
c8987470 CY	138	stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
	139	mask = 1 << 1; /* G_CNT_U write status */
	140	break;
	141	default:
	142	return;
	143	}
30d8bead CY	144	}
	145
	146	/* Wait maximum 1 ms until written values are applied */
	147	for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
a1ba7a7a TA	148	if (__raw_readl(reg_base + stat_addr) & mask) {
a1ba7a7a TA	149	__raw_writel(mask, reg_base + stat_addr);
30d8bead CY	150	return;
	151	}
	152
a1ba7a7a	153	panic("MCT hangs after writing %d (offset:0x%lx)\n", value, offset);
30d8bead CY	154	}
	155
	156	/* Clocksource handling */
	157	static void exynos4_mct_frc_start(u32 hi, u32 lo)
	158	{
	159	u32 reg;
	160
	161	exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L);
	162	exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U);
	163
a1ba7a7a	164	reg = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
30d8bead CY	165	reg \|= MCT_G_TCON_START;
	166	exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
	167	}
	168
	169	static cycle_t exynos4_frc_read(struct clocksource *cs)
	170	{
	171	unsigned int lo, hi;
a1ba7a7a	172	u32 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
30d8bead CY	173
	174	do {
	175	hi = hi2;
a1ba7a7a TA	176	lo = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_L);
a1ba7a7a TA	177	hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
30d8bead CY	178	} while (hi != hi2);
	179
	180	return ((cycle_t)hi << 32) \| lo;
	181	}
	182
aa421c13 CY	183	static void exynos4_frc_resume(struct clocksource *cs)
	184	{
	185	exynos4_mct_frc_start(0, 0);
	186	}
	187
30d8bead CY	188	struct clocksource mct_frc = {
	189	.name = "mct-frc",
	190	.rating = 400,
	191	.read = exynos4_frc_read,
	192	.mask = CLOCKSOURCE_MASK(64),
	193	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
aa421c13	194	.resume = exynos4_frc_resume,
30d8bead CY	195	};
	196
	197	static void __init exynos4_clocksource_init(void)
	198	{
	199	exynos4_mct_frc_start(0, 0);
	200
	201	if (clocksource_register_hz(&mct_frc, clk_rate))
	202	panic("%s: can't register clocksource\n", mct_frc.name);
	203	}
	204
	205	static void exynos4_mct_comp0_stop(void)
	206	{
	207	unsigned int tcon;
	208
a1ba7a7a	209	tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
30d8bead CY	210	tcon &= ~(MCT_G_TCON_COMP0_ENABLE \| MCT_G_TCON_COMP0_AUTO_INC);
	211
	212	exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
	213	exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB);
	214	}
	215
	216	static void exynos4_mct_comp0_start(enum clock_event_mode mode,
	217	unsigned long cycles)
	218	{
	219	unsigned int tcon;
	220	cycle_t comp_cycle;
	221
a1ba7a7a	222	tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
30d8bead CY	223
	224	if (mode == CLOCK_EVT_MODE_PERIODIC) {
	225	tcon \|= MCT_G_TCON_COMP0_AUTO_INC;
	226	exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR);
	227	}
	228
	229	comp_cycle = exynos4_frc_read(&mct_frc) + cycles;
	230	exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L);
	231	exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U);
	232
	233	exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB);
	234
	235	tcon \|= MCT_G_TCON_COMP0_ENABLE;
	236	exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON);
	237	}
	238
	239	static int exynos4_comp_set_next_event(unsigned long cycles,
	240	struct clock_event_device *evt)
	241	{
	242	exynos4_mct_comp0_start(evt->mode, cycles);
	243
	244	return 0;
	245	}
	246
	247	static void exynos4_comp_set_mode(enum clock_event_mode mode,
	248	struct clock_event_device *evt)
	249	{
4d2e4d7f	250	unsigned long cycles_per_jiffy;
30d8bead CY	251	exynos4_mct_comp0_stop();
	252
	253	switch (mode) {
	254	case CLOCK_EVT_MODE_PERIODIC:
4d2e4d7f CY	255	cycles_per_jiffy =
	256	(((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
	257	exynos4_mct_comp0_start(mode, cycles_per_jiffy);
30d8bead CY	258	break;
	259
	260	case CLOCK_EVT_MODE_ONESHOT:
	261	case CLOCK_EVT_MODE_UNUSED:
	262	case CLOCK_EVT_MODE_SHUTDOWN:
	263	case CLOCK_EVT_MODE_RESUME:
	264	break;
	265	}
	266	}
	267
	268	static struct clock_event_device mct_comp_device = {
	269	.name = "mct-comp",
	270	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
	271	.rating = 250,
	272	.set_next_event = exynos4_comp_set_next_event,
	273	.set_mode = exynos4_comp_set_mode,
	274	};
	275
	276	static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id)
	277	{
	278	struct clock_event_device *evt = dev_id;
	279
	280	exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT);
	281
	282	evt->event_handler(evt);
	283
	284	return IRQ_HANDLED;
	285	}
	286
	287	static struct irqaction mct_comp_event_irq = {
	288	.name = "mct_comp_irq",
	289	.flags = IRQF_TIMER \| IRQF_IRQPOLL,
	290	.handler = exynos4_mct_comp_isr,
	291	.dev_id = &mct_comp_device,
	292	};
	293
	294	static void exynos4_clockevent_init(void)
	295	{
30d8bead	296	mct_comp_device.cpumask = cpumask_of(0);
838a2ae8 SG	297	clockevents_config_and_register(&mct_comp_device, clk_rate,
838a2ae8 SG	298	0xf, 0xffffffff);
c371dc60	299	setup_irq(mct_irqs[MCT_G0_IRQ], &mct_comp_event_irq);
30d8bead CY	300	}
30d8bead CY	301
991a6c7d KK	302	static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick);
991a6c7d KK	303
30d8bead CY	304	/* Clock event handling */
	305	static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
	306	{
	307	unsigned long tmp;
	308	unsigned long mask = MCT_L_TCON_INT_START \| MCT_L_TCON_TIMER_START;
a1ba7a7a	309	unsigned long offset = mevt->base + MCT_L_TCON_OFFSET;
30d8bead	310
a1ba7a7a	311	tmp = __raw_readl(reg_base + offset);
30d8bead CY	312	if (tmp & mask) {
30d8bead CY	313	tmp &= ~mask;
a1ba7a7a	314	exynos4_mct_write(tmp, offset);
30d8bead CY	315	}
	316	}
	317
	318	static void exynos4_mct_tick_start(unsigned long cycles,
	319	struct mct_clock_event_device *mevt)
	320	{
	321	unsigned long tmp;
	322
	323	exynos4_mct_tick_stop(mevt);
	324
	325	tmp = (1 << 31) \| cycles; /* MCT_L_UPDATE_ICNTB */
	326
	327	/* update interrupt count buffer */
	328	exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET);
	329
25985edc	330	/* enable MCT tick interrupt */
30d8bead CY	331	exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
30d8bead CY	332
a1ba7a7a	333	tmp = __raw_readl(reg_base + mevt->base + MCT_L_TCON_OFFSET);
30d8bead CY	334	tmp \|= MCT_L_TCON_INT_START \| MCT_L_TCON_TIMER_START \|
	335	MCT_L_TCON_INTERVAL_MODE;
	336	exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
	337	}
	338
	339	static int exynos4_tick_set_next_event(unsigned long cycles,
	340	struct clock_event_device *evt)
	341	{
e700e41d	342	struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
30d8bead CY	343
	344	exynos4_mct_tick_start(cycles, mevt);
	345
	346	return 0;
	347	}
	348
	349	static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
	350	struct clock_event_device *evt)
	351	{
e700e41d	352	struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
4d2e4d7f	353	unsigned long cycles_per_jiffy;
30d8bead CY	354
	355	exynos4_mct_tick_stop(mevt);
	356
	357	switch (mode) {
	358	case CLOCK_EVT_MODE_PERIODIC:
4d2e4d7f CY	359	cycles_per_jiffy =
	360	(((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
	361	exynos4_mct_tick_start(cycles_per_jiffy, mevt);
30d8bead CY	362	break;
	363
	364	case CLOCK_EVT_MODE_ONESHOT:
	365	case CLOCK_EVT_MODE_UNUSED:
	366	case CLOCK_EVT_MODE_SHUTDOWN:
	367	case CLOCK_EVT_MODE_RESUME:
	368	break;
	369	}
	370	}
	371
c8987470	372	static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
30d8bead	373	{
ee98d27d	374	struct clock_event_device *evt = &mevt->evt;
30d8bead CY	375
	376	/*
	377	* This is for supporting oneshot mode.
	378	* Mct would generate interrupt periodically
	379	* without explicit stopping.
	380	*/
	381	if (evt->mode != CLOCK_EVT_MODE_PERIODIC)
	382	exynos4_mct_tick_stop(mevt);
	383
	384	/* Clear the MCT tick interrupt */
a1ba7a7a	385	if (__raw_readl(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
3a062281 CY	386	exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
	387	return 1;
	388	} else {
	389	return 0;
	390	}
	391	}
	392
	393	static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
	394	{
	395	struct mct_clock_event_device *mevt = dev_id;
ee98d27d	396	struct clock_event_device *evt = &mevt->evt;
3a062281 CY	397
3a062281 CY	398	exynos4_mct_tick_clear(mevt);
30d8bead CY	399
	400	evt->event_handler(evt);
	401
	402	return IRQ_HANDLED;
	403	}
	404
8c37bb3a	405	static int exynos4_local_timer_setup(struct clock_event_device *evt)
30d8bead	406	{
e700e41d	407	struct mct_clock_event_device *mevt;
30d8bead CY	408	unsigned int cpu = smp_processor_id();
30d8bead CY	409
ee98d27d	410	mevt = container_of(evt, struct mct_clock_event_device, evt);
30d8bead	411
e700e41d MZ	412	mevt->base = EXYNOS4_MCT_L_BASE(cpu);
e700e41d MZ	413	sprintf(mevt->name, "mct_tick%d", cpu);
30d8bead	414
e700e41d	415	evt->name = mevt->name;
30d8bead CY	416	evt->cpumask = cpumask_of(cpu);
	417	evt->set_next_event = exynos4_tick_set_next_event;
	418	evt->set_mode = exynos4_tick_set_mode;
	419	evt->features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT;
	420	evt->rating = 450;
838a2ae8 SG	421	clockevents_config_and_register(evt, clk_rate / (TICK_BASE_CNT + 1),
838a2ae8 SG	422	0xf, 0x7fffffff);
30d8bead	423
4d2e4d7f	424	exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET);
30d8bead	425
3a062281	426	if (mct_int_type == MCT_INT_SPI) {
7114cd74 CK	427	evt->irq = mct_irqs[MCT_L0_IRQ + cpu];
	428	if (request_irq(evt->irq, exynos4_mct_tick_isr,
	429	IRQF_TIMER \| IRQF_NOBALANCING,
	430	evt->name, mevt)) {
	431	pr_err("exynos-mct: cannot register IRQ %d\n",
	432	evt->irq);
	433	return -EIO;
3a062281	434	}
30d8bead	435	} else {
c371dc60	436	enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0);
30d8bead	437	}
4d487d7e KK	438
4d487d7e KK	439	return 0;
30d8bead CY	440	}
30d8bead CY	441
a8cb6041	442	static void exynos4_local_timer_stop(struct clock_event_device *evt)
30d8bead	443	{
28af690a	444	evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
e700e41d	445	if (mct_int_type == MCT_INT_SPI)
7114cd74	446	free_irq(evt->irq, this_cpu_ptr(&percpu_mct_tick));
e700e41d	447	else
c371dc60	448	disable_percpu_irq(mct_irqs[MCT_L0_IRQ]);
30d8bead	449	}
a8cb6041	450
47dcd356	451	static int exynos4_mct_cpu_notify(struct notifier_block *self,
ee98d27d SB	452	unsigned long action, void *hcpu)
	453	{
	454	struct mct_clock_event_device *mevt;
5df718d8	455	unsigned int cpu;
ee98d27d SB	456
	457	/*
	458	* Grab cpu pointer in each case to avoid spurious
	459	* preemptible warnings
	460	*/
	461	switch (action & ~CPU_TASKS_FROZEN) {
	462	case CPU_STARTING:
	463	mevt = this_cpu_ptr(&percpu_mct_tick);
	464	exynos4_local_timer_setup(&mevt->evt);
	465	break;
5df718d8 TF	466	case CPU_ONLINE:
	467	cpu = (unsigned long)hcpu;
	468	if (mct_int_type == MCT_INT_SPI)
	469	irq_set_affinity(mct_irqs[MCT_L0_IRQ + cpu],
	470	cpumask_of(cpu));
	471	break;
ee98d27d SB	472	case CPU_DYING:
	473	mevt = this_cpu_ptr(&percpu_mct_tick);
	474	exynos4_local_timer_stop(&mevt->evt);
	475	break;
	476	}
	477
	478	return NOTIFY_OK;
	479	}
	480
47dcd356	481	static struct notifier_block exynos4_mct_cpu_nb = {
ee98d27d	482	.notifier_call = exynos4_mct_cpu_notify,
a8cb6041	483	};
30d8bead	484
19ce4f4a	485	static void __init exynos4_timer_resources(struct device_node np, void __iomem base)
30d8bead	486	{
ee98d27d SB	487	int err;
ee98d27d SB	488	struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
ca9048ec	489	struct clk mct_clk, tick_clk;
30d8bead	490
415ac2e2 TA	491	tick_clk = np ? of_clk_get_by_name(np, "fin_pll") :
	492	clk_get(NULL, "fin_pll");
	493	if (IS_ERR(tick_clk))
	494	panic("%s: unable to determine tick clock rate\n", __func__);
	495	clk_rate = clk_get_rate(tick_clk);
e700e41d	496
ca9048ec TA	497	mct_clk = np ? of_clk_get_by_name(np, "mct") : clk_get(NULL, "mct");
	498	if (IS_ERR(mct_clk))
	499	panic("%s: unable to retrieve mct clock instance\n", __func__);
	500	clk_prepare_enable(mct_clk);
e700e41d	501
228e3023	502	reg_base = base;
36ba5d52 TA	503	if (!reg_base)
36ba5d52 TA	504	panic("%s: unable to ioremap mct address space\n", __func__);
a1ba7a7a	505
e700e41d	506	if (mct_int_type == MCT_INT_PPI) {
e700e41d	507
c371dc60	508	err = request_percpu_irq(mct_irqs[MCT_L0_IRQ],
e700e41d MZ	509	exynos4_mct_tick_isr, "MCT",
	510	&percpu_mct_tick);
	511	WARN(err, "MCT: can't request IRQ %d (%d)\n",
c371dc60	512	mct_irqs[MCT_L0_IRQ], err);
5df718d8 TF	513	} else {
5df718d8 TF	514	irq_set_affinity(mct_irqs[MCT_L0_IRQ], cpumask_of(0));
e700e41d	515	}
a8cb6041	516
ee98d27d SB	517	err = register_cpu_notifier(&exynos4_mct_cpu_nb);
	518	if (err)
	519	goto out_irq;
	520
	521	/* Immediately configure the timer on the boot CPU */
	522	exynos4_local_timer_setup(&mevt->evt);
	523	return;
	524
	525	out_irq:
	526	free_percpu_irq(mct_irqs[MCT_L0_IRQ], &percpu_mct_tick);
30d8bead CY	527	}
30d8bead CY	528
034c097c	529	void __init mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1)
30d8bead	530	{
034c097c AB	531	mct_irqs[MCT_G0_IRQ] = irq_g0;
	532	mct_irqs[MCT_L0_IRQ] = irq_l0;
	533	mct_irqs[MCT_L1_IRQ] = irq_l1;
	534	mct_int_type = MCT_INT_SPI;
2edb36c4	535
034c097c	536	exynos4_timer_resources(NULL, base);
30d8bead CY	537	exynos4_clocksource_init();
	538	exynos4_clockevent_init();
	539	}
3a062281	540
228e3023 AB	541	static void __init mct_init_dt(struct device_node *np, unsigned int int_type)
	542	{
	543	u32 nr_irqs, i;
	544
	545	mct_int_type = int_type;
	546
	547	/* This driver uses only one global timer interrupt */
	548	mct_irqs[MCT_G0_IRQ] = irq_of_parse_and_map(np, MCT_G0_IRQ);
	549
	550	/*
	551	* Find out the number of local irqs specified. The local
	552	* timer irqs are specified after the four global timer
	553	* irqs are specified.
	554	*/
f4636d0a	555	#ifdef CONFIG_OF
228e3023	556	nr_irqs = of_irq_count(np);
f4636d0a AB	557	#else
	558	nr_irqs = 0;
	559	#endif
228e3023 AB	560	for (i = MCT_L0_IRQ; i < nr_irqs; i++)
	561	mct_irqs[i] = irq_of_parse_and_map(np, i);
	562
19ce4f4a	563	exynos4_timer_resources(np, of_iomap(np, 0));
30d8bead CY	564	exynos4_clocksource_init();
	565	exynos4_clockevent_init();
	566	}
228e3023 AB	567
	568
	569	static void __init mct_init_spi(struct device_node *np)
	570	{
	571	return mct_init_dt(np, MCT_INT_SPI);
	572	}
	573
	574	static void __init mct_init_ppi(struct device_node *np)
	575	{
	576	return mct_init_dt(np, MCT_INT_PPI);
	577	}
	578	CLOCKSOURCE_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init_spi);
	579	CLOCKSOURCE_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init_ppi);