Commit | Line | Data |
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caab277b | 1 | // SPDX-License-Identifier: GPL-2.0-only |
af75655c | 2 | /* |
cfda5901 | 3 | * Copyright (C) 2012 Altera Corporation |
af75655c JI |
4 | * Copyright (c) 2011 Picochip Ltd., Jamie Iles |
5 | * | |
cfda5901 | 6 | * Modified from mach-picoxcell/time.c |
af75655c | 7 | */ |
9115df89 | 8 | #include <linux/delay.h> |
af75655c JI |
9 | #include <linux/dw_apb_timer.h> |
10 | #include <linux/of.h> | |
11 | #include <linux/of_address.h> | |
12 | #include <linux/of_irq.h> | |
a8b447f2 | 13 | #include <linux/clk.h> |
1f174a1a | 14 | #include <linux/reset.h> |
38ff87f7 | 15 | #include <linux/sched_clock.h> |
af75655c | 16 | |
1cf0203a | 17 | static void __init timer_get_base_and_rate(struct device_node *np, |
af75655c JI |
18 | void __iomem **base, u32 *rate) |
19 | { | |
a8b447f2 HS |
20 | struct clk *timer_clk; |
21 | struct clk *pclk; | |
1f174a1a | 22 | struct reset_control *rstc; |
a8b447f2 | 23 | |
af75655c JI |
24 | *base = of_iomap(np, 0); |
25 | ||
26 | if (!*base) | |
2a4849d2 | 27 | panic("Unable to map regs for %pOFn", np); |
af75655c | 28 | |
1f174a1a DN |
29 | /* |
30 | * Reset the timer if the reset control is available, wiping | |
31 | * out the state the firmware may have left it | |
32 | */ | |
33 | rstc = of_reset_control_get(np, NULL); | |
34 | if (!IS_ERR(rstc)) { | |
35 | reset_control_assert(rstc); | |
36 | reset_control_deassert(rstc); | |
37 | } | |
38 | ||
a8b447f2 HS |
39 | /* |
40 | * Not all implementations use a periphal clock, so don't panic | |
41 | * if it's not present | |
42 | */ | |
43 | pclk = of_clk_get_by_name(np, "pclk"); | |
44 | if (!IS_ERR(pclk)) | |
45 | if (clk_prepare_enable(pclk)) | |
2a4849d2 RH |
46 | pr_warn("pclk for %pOFn is present, but could not be activated\n", |
47 | np); | |
a8b447f2 HS |
48 | |
49 | timer_clk = of_clk_get_by_name(np, "timer"); | |
50 | if (IS_ERR(timer_clk)) | |
51 | goto try_clock_freq; | |
52 | ||
53 | if (!clk_prepare_enable(timer_clk)) { | |
54 | *rate = clk_get_rate(timer_clk); | |
55 | return; | |
56 | } | |
57 | ||
58 | try_clock_freq: | |
cfda5901 | 59 | if (of_property_read_u32(np, "clock-freq", rate) && |
1cf0203a | 60 | of_property_read_u32(np, "clock-frequency", rate)) |
2a4849d2 | 61 | panic("No clock nor clock-frequency property for %pOFn", np); |
af75655c JI |
62 | } |
63 | ||
1cf0203a | 64 | static void __init add_clockevent(struct device_node *event_timer) |
af75655c JI |
65 | { |
66 | void __iomem *iobase; | |
67 | struct dw_apb_clock_event_device *ced; | |
68 | u32 irq, rate; | |
69 | ||
70 | irq = irq_of_parse_and_map(event_timer, 0); | |
1a33bd2b | 71 | if (irq == 0) |
af75655c JI |
72 | panic("No IRQ for clock event timer"); |
73 | ||
74 | timer_get_base_and_rate(event_timer, &iobase, &rate); | |
75 | ||
76 | ced = dw_apb_clockevent_init(0, event_timer->name, 300, iobase, irq, | |
77 | rate); | |
78 | if (!ced) | |
79 | panic("Unable to initialise clockevent device"); | |
80 | ||
81 | dw_apb_clockevent_register(ced); | |
82 | } | |
83 | ||
a1198f83 HS |
84 | static void __iomem *sched_io_base; |
85 | static u32 sched_rate; | |
86 | ||
1cf0203a | 87 | static void __init add_clocksource(struct device_node *source_timer) |
af75655c JI |
88 | { |
89 | void __iomem *iobase; | |
90 | struct dw_apb_clocksource *cs; | |
91 | u32 rate; | |
92 | ||
93 | timer_get_base_and_rate(source_timer, &iobase, &rate); | |
94 | ||
95 | cs = dw_apb_clocksource_init(300, source_timer->name, iobase, rate); | |
96 | if (!cs) | |
97 | panic("Unable to initialise clocksource device"); | |
98 | ||
99 | dw_apb_clocksource_start(cs); | |
100 | dw_apb_clocksource_register(cs); | |
af75655c | 101 | |
a1198f83 HS |
102 | /* |
103 | * Fallback to use the clocksource as sched_clock if no separate | |
104 | * timer is found. sched_io_base then points to the current_value | |
105 | * register of the clocksource timer. | |
106 | */ | |
107 | sched_io_base = iobase + 0x04; | |
108 | sched_rate = rate; | |
109 | } | |
af75655c | 110 | |
0d24d1f2 | 111 | static u64 notrace read_sched_clock(void) |
af75655c | 112 | { |
3a10013b | 113 | return ~readl_relaxed(sched_io_base); |
af75655c JI |
114 | } |
115 | ||
cfda5901 | 116 | static const struct of_device_id sptimer_ids[] __initconst = { |
af75655c JI |
117 | { .compatible = "picochip,pc3x2-rtc" }, |
118 | { /* Sentinel */ }, | |
119 | }; | |
120 | ||
1cf0203a | 121 | static void __init init_sched_clock(void) |
af75655c JI |
122 | { |
123 | struct device_node *sched_timer; | |
af75655c | 124 | |
cfda5901 | 125 | sched_timer = of_find_matching_node(NULL, sptimer_ids); |
a1198f83 HS |
126 | if (sched_timer) { |
127 | timer_get_base_and_rate(sched_timer, &sched_io_base, | |
128 | &sched_rate); | |
129 | of_node_put(sched_timer); | |
130 | } | |
af75655c | 131 | |
fa8296ae | 132 | sched_clock_register(read_sched_clock, 32, sched_rate); |
af75655c JI |
133 | } |
134 | ||
9115df89 JZ |
135 | #ifdef CONFIG_ARM |
136 | static unsigned long dw_apb_delay_timer_read(void) | |
137 | { | |
138 | return ~readl_relaxed(sched_io_base); | |
139 | } | |
140 | ||
141 | static struct delay_timer dw_apb_delay_timer = { | |
142 | .read_current_timer = dw_apb_delay_timer_read, | |
143 | }; | |
144 | #endif | |
145 | ||
10021488 | 146 | static int num_called; |
2e1773f8 | 147 | static int __init dw_apb_timer_init(struct device_node *timer) |
af75655c | 148 | { |
10021488 HS |
149 | switch (num_called) { |
150 | case 0: | |
151 | pr_debug("%s: found clockevent timer\n", __func__); | |
152 | add_clockevent(timer); | |
10021488 HS |
153 | break; |
154 | case 1: | |
155 | pr_debug("%s: found clocksource timer\n", __func__); | |
156 | add_clocksource(timer); | |
10021488 | 157 | init_sched_clock(); |
9115df89 JZ |
158 | #ifdef CONFIG_ARM |
159 | dw_apb_delay_timer.freq = sched_rate; | |
160 | register_current_timer_delay(&dw_apb_delay_timer); | |
161 | #endif | |
10021488 HS |
162 | break; |
163 | default: | |
164 | break; | |
165 | } | |
af75655c | 166 | |
10021488 | 167 | num_called++; |
2e1773f8 DL |
168 | |
169 | return 0; | |
af75655c | 170 | } |
17273395 DL |
171 | TIMER_OF_DECLARE(pc3x2_timer, "picochip,pc3x2-timer", dw_apb_timer_init); |
172 | TIMER_OF_DECLARE(apb_timer_osc, "snps,dw-apb-timer-osc", dw_apb_timer_init); | |
173 | TIMER_OF_DECLARE(apb_timer_sp, "snps,dw-apb-timer-sp", dw_apb_timer_init); | |
174 | TIMER_OF_DECLARE(apb_timer, "snps,dw-apb-timer", dw_apb_timer_init); |