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489bccea MW |
1 | /* |
2 | * Copyright (C) ST-Ericsson SA 2011 | |
3 | * | |
4 | * License Terms: GNU General Public License v2 | |
5 | * Author: Mattias Wallin <mattias.wallin@stericsson.com> for ST-Ericsson | |
6 | * Author: Sundar Iyer for ST-Ericsson | |
7 | * sched_clock implementation is based on: | |
8 | * plat-nomadik/timer.c Linus Walleij <linus.walleij@stericsson.com> | |
9 | * | |
10 | * DBx500-PRCMU Timer | |
11 | * The PRCMU has 5 timers which are available in a always-on | |
12 | * power domain. We use the Timer 4 for our always-on clock | |
807eba55 | 13 | * source on DB8500. |
489bccea | 14 | */ |
9d2aa8c7 LW |
15 | #include <linux/of.h> |
16 | #include <linux/of_address.h> | |
489bccea | 17 | #include <linux/clockchips.h> |
38ff87f7 | 18 | #include <linux/sched_clock.h> |
489bccea | 19 | |
489bccea MW |
20 | #define RATE_32K 32768 |
21 | ||
22 | #define TIMER_MODE_CONTINOUS 0x1 | |
23 | #define TIMER_DOWNCOUNT_VAL 0xffffffff | |
24 | ||
25 | #define PRCMU_TIMER_REF 0 | |
26 | #define PRCMU_TIMER_DOWNCOUNT 0x4 | |
27 | #define PRCMU_TIMER_MODE 0x8 | |
28 | ||
29 | #define SCHED_CLOCK_MIN_WRAP 131072 /* 2^32 / 32768 */ | |
30 | ||
b1e3be06 | 31 | static void __iomem *clksrc_dbx500_timer_base; |
489bccea | 32 | |
53028227 | 33 | static cycle_t notrace clksrc_dbx500_prcmu_read(struct clocksource *cs) |
489bccea | 34 | { |
53028227 | 35 | void __iomem *base = clksrc_dbx500_timer_base; |
489bccea MW |
36 | u32 count, count2; |
37 | ||
38 | do { | |
53028227 RV |
39 | count = readl_relaxed(base + PRCMU_TIMER_DOWNCOUNT); |
40 | count2 = readl_relaxed(base + PRCMU_TIMER_DOWNCOUNT); | |
489bccea MW |
41 | } while (count2 != count); |
42 | ||
43 | /* Negate because the timer is a decrementing counter */ | |
44 | return ~count; | |
45 | } | |
46 | ||
47 | static struct clocksource clocksource_dbx500_prcmu = { | |
48 | .name = "dbx500-prcmu-timer", | |
49 | .rating = 300, | |
50 | .read = clksrc_dbx500_prcmu_read, | |
489bccea MW |
51 | .mask = CLOCKSOURCE_MASK(32), |
52 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | |
53 | }; | |
54 | ||
55 | #ifdef CONFIG_CLKSRC_DBX500_PRCMU_SCHED_CLOCK | |
489bccea | 56 | |
5602d7c8 | 57 | static u64 notrace dbx500_prcmu_sched_clock_read(void) |
489bccea | 58 | { |
489bccea MW |
59 | if (unlikely(!clksrc_dbx500_timer_base)) |
60 | return 0; | |
61 | ||
cfef0320 | 62 | return clksrc_dbx500_prcmu_read(&clocksource_dbx500_prcmu); |
489bccea MW |
63 | } |
64 | ||
489bccea MW |
65 | #endif |
66 | ||
108a4ed9 | 67 | static int __init clksrc_dbx500_prcmu_init(struct device_node *node) |
489bccea | 68 | { |
9d2aa8c7 | 69 | clksrc_dbx500_timer_base = of_iomap(node, 0); |
b1e3be06 | 70 | |
489bccea MW |
71 | /* |
72 | * The A9 sub system expects the timer to be configured as | |
73 | * a continous looping timer. | |
74 | * The PRCMU should configure it but if it for some reason | |
75 | * don't we do it here. | |
76 | */ | |
77 | if (readl(clksrc_dbx500_timer_base + PRCMU_TIMER_MODE) != | |
78 | TIMER_MODE_CONTINOUS) { | |
79 | writel(TIMER_MODE_CONTINOUS, | |
80 | clksrc_dbx500_timer_base + PRCMU_TIMER_MODE); | |
81 | writel(TIMER_DOWNCOUNT_VAL, | |
82 | clksrc_dbx500_timer_base + PRCMU_TIMER_REF); | |
83 | } | |
84 | #ifdef CONFIG_CLKSRC_DBX500_PRCMU_SCHED_CLOCK | |
5602d7c8 | 85 | sched_clock_register(dbx500_prcmu_sched_clock_read, 32, RATE_32K); |
489bccea | 86 | #endif |
108a4ed9 | 87 | return clocksource_register_hz(&clocksource_dbx500_prcmu, RATE_32K); |
489bccea | 88 | } |
177cf6e5 | 89 | CLOCKSOURCE_OF_DECLARE(dbx500_prcmu, "stericsson,db8500-prcmu-timer-4", |
9d2aa8c7 | 90 | clksrc_dbx500_prcmu_init); |