Commit | Line | Data |
---|---|---|
0376148f | 1 | // SPDX-License-Identifier: GPL-2.0-only |
489bccea MW |
2 | /* |
3 | * Copyright (C) ST-Ericsson SA 2011 | |
4 | * | |
489bccea MW |
5 | * Author: Mattias Wallin <mattias.wallin@stericsson.com> for ST-Ericsson |
6 | * Author: Sundar Iyer for ST-Ericsson | |
7 | * sched_clock implementation is based on: | |
8 | * plat-nomadik/timer.c Linus Walleij <linus.walleij@stericsson.com> | |
9 | * | |
10 | * DBx500-PRCMU Timer | |
11 | * The PRCMU has 5 timers which are available in a always-on | |
12 | * power domain. We use the Timer 4 for our always-on clock | |
807eba55 | 13 | * source on DB8500. |
489bccea | 14 | */ |
9d2aa8c7 LW |
15 | #include <linux/of.h> |
16 | #include <linux/of_address.h> | |
489bccea | 17 | #include <linux/clockchips.h> |
489bccea | 18 | |
489bccea MW |
19 | #define RATE_32K 32768 |
20 | ||
4bf07f65 | 21 | #define TIMER_MODE_CONTINUOUS 0x1 |
489bccea MW |
22 | #define TIMER_DOWNCOUNT_VAL 0xffffffff |
23 | ||
24 | #define PRCMU_TIMER_REF 0 | |
25 | #define PRCMU_TIMER_DOWNCOUNT 0x4 | |
26 | #define PRCMU_TIMER_MODE 0x8 | |
27 | ||
b1e3be06 | 28 | static void __iomem *clksrc_dbx500_timer_base; |
489bccea | 29 | |
a5a1d1c2 | 30 | static u64 notrace clksrc_dbx500_prcmu_read(struct clocksource *cs) |
489bccea | 31 | { |
53028227 | 32 | void __iomem *base = clksrc_dbx500_timer_base; |
489bccea MW |
33 | u32 count, count2; |
34 | ||
35 | do { | |
53028227 RV |
36 | count = readl_relaxed(base + PRCMU_TIMER_DOWNCOUNT); |
37 | count2 = readl_relaxed(base + PRCMU_TIMER_DOWNCOUNT); | |
489bccea MW |
38 | } while (count2 != count); |
39 | ||
40 | /* Negate because the timer is a decrementing counter */ | |
41 | return ~count; | |
42 | } | |
43 | ||
44 | static struct clocksource clocksource_dbx500_prcmu = { | |
45 | .name = "dbx500-prcmu-timer", | |
bc0750e4 | 46 | .rating = 100, |
489bccea | 47 | .read = clksrc_dbx500_prcmu_read, |
489bccea | 48 | .mask = CLOCKSOURCE_MASK(32), |
bc0750e4 | 49 | .flags = CLOCK_SOURCE_IS_CONTINUOUS | CLOCK_SOURCE_SUSPEND_NONSTOP, |
489bccea MW |
50 | }; |
51 | ||
108a4ed9 | 52 | static int __init clksrc_dbx500_prcmu_init(struct device_node *node) |
489bccea | 53 | { |
9d2aa8c7 | 54 | clksrc_dbx500_timer_base = of_iomap(node, 0); |
b1e3be06 | 55 | |
489bccea MW |
56 | /* |
57 | * The A9 sub system expects the timer to be configured as | |
4bf07f65 | 58 | * a continuous looping timer. |
489bccea MW |
59 | * The PRCMU should configure it but if it for some reason |
60 | * don't we do it here. | |
61 | */ | |
62 | if (readl(clksrc_dbx500_timer_base + PRCMU_TIMER_MODE) != | |
4bf07f65 IM |
63 | TIMER_MODE_CONTINUOUS) { |
64 | writel(TIMER_MODE_CONTINUOUS, | |
489bccea MW |
65 | clksrc_dbx500_timer_base + PRCMU_TIMER_MODE); |
66 | writel(TIMER_DOWNCOUNT_VAL, | |
67 | clksrc_dbx500_timer_base + PRCMU_TIMER_REF); | |
68 | } | |
108a4ed9 | 69 | return clocksource_register_hz(&clocksource_dbx500_prcmu, RATE_32K); |
489bccea | 70 | } |
17273395 | 71 | TIMER_OF_DECLARE(dbx500_prcmu, "stericsson,db8500-prcmu-timer-4", |
9d2aa8c7 | 72 | clksrc_dbx500_prcmu_init); |