Commit | Line | Data |
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b85a3ef4 | 1 | /* |
9e09dc5f | 2 | * This file contains driver for the Cadence Triple Timer Counter Rev 06 |
b85a3ef4 | 3 | * |
e932900a | 4 | * Copyright (C) 2011-2013 Xilinx |
b85a3ef4 JL |
5 | * |
6 | * based on arch/mips/kernel/time.c timer driver | |
7 | * | |
8 | * This software is licensed under the terms of the GNU General Public | |
9 | * License version 2, as published by the Free Software Foundation, and | |
10 | * may be copied, distributed, and modified under those terms. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | */ | |
17 | ||
e932900a | 18 | #include <linux/clk.h> |
b85a3ef4 | 19 | #include <linux/interrupt.h> |
b85a3ef4 | 20 | #include <linux/clockchips.h> |
91dc985c JC |
21 | #include <linux/of_address.h> |
22 | #include <linux/of_irq.h> | |
23 | #include <linux/slab.h> | |
b85a3ef4 | 24 | |
e932900a MS |
25 | /* |
26 | * This driver configures the 2 16-bit count-up timers as follows: | |
27 | * | |
28 | * T1: Timer 1, clocksource for generic timekeeping | |
29 | * T2: Timer 2, clockevent source for hrtimers | |
30 | * T3: Timer 3, <unused> | |
31 | * | |
32 | * The input frequency to the timer module for emulation is 2.5MHz which is | |
33 | * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32, | |
34 | * the timers are clocked at 78.125KHz (12.8 us resolution). | |
35 | ||
36 | * The input frequency to the timer module in silicon is configurable and | |
37 | * obtained from device tree. The pre-scaler of 32 is used. | |
38 | */ | |
39 | ||
b85a3ef4 JL |
40 | /* |
41 | * Timer Register Offset Definitions of Timer 1, Increment base address by 4 | |
42 | * and use same offsets for Timer 2 | |
43 | */ | |
9e09dc5f MS |
44 | #define TTC_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */ |
45 | #define TTC_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */ | |
46 | #define TTC_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */ | |
47 | #define TTC_INTR_VAL_OFFSET 0x24 /* Interval Count Reg, RW */ | |
48 | #define TTC_ISR_OFFSET 0x54 /* Interrupt Status Reg, RO */ | |
49 | #define TTC_IER_OFFSET 0x60 /* Interrupt Enable Reg, RW */ | |
f184c5ca | 50 | |
9e09dc5f | 51 | #define TTC_CNT_CNTRL_DISABLE_MASK 0x1 |
b85a3ef4 | 52 | |
30e1e285 SB |
53 | #define TTC_CLK_CNTRL_CSRC_MASK (1 << 5) /* clock source */ |
54 | ||
03377e58 SB |
55 | /* |
56 | * Setup the timers to use pre-scaling, using a fixed value for now that will | |
91dc985c JC |
57 | * work across most input frequency, but it may need to be more dynamic |
58 | */ | |
59 | #define PRESCALE_EXPONENT 11 /* 2 ^ PRESCALE_EXPONENT = PRESCALE */ | |
60 | #define PRESCALE 2048 /* The exponent must match this */ | |
61 | #define CLK_CNTRL_PRESCALE ((PRESCALE_EXPONENT - 1) << 1) | |
62 | #define CLK_CNTRL_PRESCALE_EN 1 | |
e932900a | 63 | #define CNT_CNTRL_RESET (1 << 4) |
b85a3ef4 JL |
64 | |
65 | /** | |
9e09dc5f | 66 | * struct ttc_timer - This definition defines local timer structure |
b85a3ef4 JL |
67 | * |
68 | * @base_addr: Base address of timer | |
e932900a MS |
69 | * @clk: Associated clock source |
70 | * @clk_rate_change_nb Notifier block for clock rate changes | |
71 | */ | |
9e09dc5f | 72 | struct ttc_timer { |
e932900a MS |
73 | void __iomem *base_addr; |
74 | struct clk *clk; | |
75 | struct notifier_block clk_rate_change_nb; | |
91dc985c JC |
76 | }; |
77 | ||
9e09dc5f MS |
78 | #define to_ttc_timer(x) \ |
79 | container_of(x, struct ttc_timer, clk_rate_change_nb) | |
e932900a | 80 | |
9e09dc5f MS |
81 | struct ttc_timer_clocksource { |
82 | struct ttc_timer ttc; | |
91dc985c | 83 | struct clocksource cs; |
b85a3ef4 JL |
84 | }; |
85 | ||
9e09dc5f MS |
86 | #define to_ttc_timer_clksrc(x) \ |
87 | container_of(x, struct ttc_timer_clocksource, cs) | |
91dc985c | 88 | |
9e09dc5f MS |
89 | struct ttc_timer_clockevent { |
90 | struct ttc_timer ttc; | |
91dc985c | 91 | struct clock_event_device ce; |
91dc985c JC |
92 | }; |
93 | ||
9e09dc5f MS |
94 | #define to_ttc_timer_clkevent(x) \ |
95 | container_of(x, struct ttc_timer_clockevent, ce) | |
b85a3ef4 JL |
96 | |
97 | /** | |
9e09dc5f | 98 | * ttc_set_interval - Set the timer interval value |
b85a3ef4 JL |
99 | * |
100 | * @timer: Pointer to the timer instance | |
101 | * @cycles: Timer interval ticks | |
102 | **/ | |
9e09dc5f | 103 | static void ttc_set_interval(struct ttc_timer *timer, |
b85a3ef4 JL |
104 | unsigned long cycles) |
105 | { | |
106 | u32 ctrl_reg; | |
107 | ||
108 | /* Disable the counter, set the counter value and re-enable counter */ | |
9e09dc5f MS |
109 | ctrl_reg = __raw_readl(timer->base_addr + TTC_CNT_CNTRL_OFFSET); |
110 | ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK; | |
111 | __raw_writel(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); | |
b85a3ef4 | 112 | |
9e09dc5f | 113 | __raw_writel(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET); |
b85a3ef4 | 114 | |
03377e58 SB |
115 | /* |
116 | * Reset the counter (0x10) so that it starts from 0, one-shot | |
117 | * mode makes this needed for timing to be right. | |
118 | */ | |
91dc985c | 119 | ctrl_reg |= CNT_CNTRL_RESET; |
9e09dc5f MS |
120 | ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK; |
121 | __raw_writel(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); | |
b85a3ef4 JL |
122 | } |
123 | ||
124 | /** | |
9e09dc5f | 125 | * ttc_clock_event_interrupt - Clock event timer interrupt handler |
b85a3ef4 JL |
126 | * |
127 | * @irq: IRQ number of the Timer | |
9e09dc5f | 128 | * @dev_id: void pointer to the ttc_timer instance |
b85a3ef4 JL |
129 | * |
130 | * returns: Always IRQ_HANDLED - success | |
131 | **/ | |
9e09dc5f | 132 | static irqreturn_t ttc_clock_event_interrupt(int irq, void *dev_id) |
b85a3ef4 | 133 | { |
9e09dc5f MS |
134 | struct ttc_timer_clockevent *ttce = dev_id; |
135 | struct ttc_timer *timer = &ttce->ttc; | |
b85a3ef4 JL |
136 | |
137 | /* Acknowledge the interrupt and call event handler */ | |
9e09dc5f | 138 | __raw_readl(timer->base_addr + TTC_ISR_OFFSET); |
b85a3ef4 | 139 | |
9e09dc5f | 140 | ttce->ce.event_handler(&ttce->ce); |
b85a3ef4 JL |
141 | |
142 | return IRQ_HANDLED; | |
143 | } | |
144 | ||
b85a3ef4 | 145 | /** |
9e09dc5f | 146 | * __ttc_clocksource_read - Reads the timer counter register |
b85a3ef4 JL |
147 | * |
148 | * returns: Current timer counter register value | |
149 | **/ | |
9e09dc5f | 150 | static cycle_t __ttc_clocksource_read(struct clocksource *cs) |
b85a3ef4 | 151 | { |
9e09dc5f | 152 | struct ttc_timer *timer = &to_ttc_timer_clksrc(cs)->ttc; |
b85a3ef4 JL |
153 | |
154 | return (cycle_t)__raw_readl(timer->base_addr + | |
9e09dc5f | 155 | TTC_COUNT_VAL_OFFSET); |
b85a3ef4 JL |
156 | } |
157 | ||
b85a3ef4 | 158 | /** |
9e09dc5f | 159 | * ttc_set_next_event - Sets the time interval for next event |
b85a3ef4 JL |
160 | * |
161 | * @cycles: Timer interval ticks | |
162 | * @evt: Address of clock event instance | |
163 | * | |
164 | * returns: Always 0 - success | |
165 | **/ | |
9e09dc5f | 166 | static int ttc_set_next_event(unsigned long cycles, |
b85a3ef4 JL |
167 | struct clock_event_device *evt) |
168 | { | |
9e09dc5f MS |
169 | struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt); |
170 | struct ttc_timer *timer = &ttce->ttc; | |
b85a3ef4 | 171 | |
9e09dc5f | 172 | ttc_set_interval(timer, cycles); |
b85a3ef4 JL |
173 | return 0; |
174 | } | |
175 | ||
176 | /** | |
9e09dc5f | 177 | * ttc_set_mode - Sets the mode of timer |
b85a3ef4 JL |
178 | * |
179 | * @mode: Mode to be set | |
180 | * @evt: Address of clock event instance | |
181 | **/ | |
9e09dc5f | 182 | static void ttc_set_mode(enum clock_event_mode mode, |
b85a3ef4 JL |
183 | struct clock_event_device *evt) |
184 | { | |
9e09dc5f MS |
185 | struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt); |
186 | struct ttc_timer *timer = &ttce->ttc; | |
b85a3ef4 JL |
187 | u32 ctrl_reg; |
188 | ||
189 | switch (mode) { | |
190 | case CLOCK_EVT_MODE_PERIODIC: | |
9e09dc5f MS |
191 | ttc_set_interval(timer, |
192 | DIV_ROUND_CLOSEST(clk_get_rate(ttce->ttc.clk), | |
e932900a | 193 | PRESCALE * HZ)); |
b85a3ef4 JL |
194 | break; |
195 | case CLOCK_EVT_MODE_ONESHOT: | |
196 | case CLOCK_EVT_MODE_UNUSED: | |
197 | case CLOCK_EVT_MODE_SHUTDOWN: | |
198 | ctrl_reg = __raw_readl(timer->base_addr + | |
9e09dc5f MS |
199 | TTC_CNT_CNTRL_OFFSET); |
200 | ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK; | |
b85a3ef4 | 201 | __raw_writel(ctrl_reg, |
9e09dc5f | 202 | timer->base_addr + TTC_CNT_CNTRL_OFFSET); |
b85a3ef4 JL |
203 | break; |
204 | case CLOCK_EVT_MODE_RESUME: | |
205 | ctrl_reg = __raw_readl(timer->base_addr + | |
9e09dc5f MS |
206 | TTC_CNT_CNTRL_OFFSET); |
207 | ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK; | |
b85a3ef4 | 208 | __raw_writel(ctrl_reg, |
9e09dc5f | 209 | timer->base_addr + TTC_CNT_CNTRL_OFFSET); |
b85a3ef4 JL |
210 | break; |
211 | } | |
212 | } | |
213 | ||
9e09dc5f | 214 | static int ttc_rate_change_clocksource_cb(struct notifier_block *nb, |
e932900a MS |
215 | unsigned long event, void *data) |
216 | { | |
217 | struct clk_notifier_data *ndata = data; | |
9e09dc5f MS |
218 | struct ttc_timer *ttc = to_ttc_timer(nb); |
219 | struct ttc_timer_clocksource *ttccs = container_of(ttc, | |
220 | struct ttc_timer_clocksource, ttc); | |
e932900a MS |
221 | |
222 | switch (event) { | |
223 | case POST_RATE_CHANGE: | |
224 | /* | |
225 | * Do whatever is necessary to maintain a proper time base | |
226 | * | |
227 | * I cannot find a way to adjust the currently used clocksource | |
228 | * to the new frequency. __clocksource_updatefreq_hz() sounds | |
229 | * good, but does not work. Not sure what's that missing. | |
230 | * | |
231 | * This approach works, but triggers two clocksource switches. | |
232 | * The first after unregister to clocksource jiffies. And | |
233 | * another one after the register to the newly registered timer. | |
234 | * | |
235 | * Alternatively we could 'waste' another HW timer to ping pong | |
236 | * between clock sources. That would also use one register and | |
237 | * one unregister call, but only trigger one clocksource switch | |
238 | * for the cost of another HW timer used by the OS. | |
239 | */ | |
9e09dc5f MS |
240 | clocksource_unregister(&ttccs->cs); |
241 | clocksource_register_hz(&ttccs->cs, | |
e932900a MS |
242 | ndata->new_rate / PRESCALE); |
243 | /* fall through */ | |
244 | case PRE_RATE_CHANGE: | |
245 | case ABORT_RATE_CHANGE: | |
246 | default: | |
247 | return NOTIFY_DONE; | |
248 | } | |
249 | } | |
250 | ||
9e09dc5f | 251 | static void __init ttc_setup_clocksource(struct clk *clk, void __iomem *base) |
91dc985c | 252 | { |
9e09dc5f | 253 | struct ttc_timer_clocksource *ttccs; |
91dc985c | 254 | int err; |
91dc985c JC |
255 | |
256 | ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL); | |
257 | if (WARN_ON(!ttccs)) | |
258 | return; | |
259 | ||
9e09dc5f | 260 | ttccs->ttc.clk = clk; |
91dc985c | 261 | |
9e09dc5f | 262 | err = clk_prepare_enable(ttccs->ttc.clk); |
c5263bb8 MS |
263 | if (WARN_ON(err)) { |
264 | kfree(ttccs); | |
91dc985c | 265 | return; |
c5263bb8 | 266 | } |
91dc985c | 267 | |
9e09dc5f MS |
268 | ttccs->ttc.clk_rate_change_nb.notifier_call = |
269 | ttc_rate_change_clocksource_cb; | |
270 | ttccs->ttc.clk_rate_change_nb.next = NULL; | |
271 | if (clk_notifier_register(ttccs->ttc.clk, | |
272 | &ttccs->ttc.clk_rate_change_nb)) | |
e932900a | 273 | pr_warn("Unable to register clock notifier.\n"); |
91dc985c | 274 | |
9e09dc5f MS |
275 | ttccs->ttc.base_addr = base; |
276 | ttccs->cs.name = "ttc_clocksource"; | |
91dc985c | 277 | ttccs->cs.rating = 200; |
9e09dc5f | 278 | ttccs->cs.read = __ttc_clocksource_read; |
91dc985c JC |
279 | ttccs->cs.mask = CLOCKSOURCE_MASK(16); |
280 | ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS; | |
281 | ||
e932900a MS |
282 | /* |
283 | * Setup the clock source counter to be an incrementing counter | |
284 | * with no interrupt and it rolls over at 0xFFFF. Pre-scale | |
285 | * it by 32 also. Let it start running now. | |
286 | */ | |
9e09dc5f | 287 | __raw_writel(0x0, ttccs->ttc.base_addr + TTC_IER_OFFSET); |
91dc985c | 288 | __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN, |
9e09dc5f | 289 | ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET); |
91dc985c | 290 | __raw_writel(CNT_CNTRL_RESET, |
9e09dc5f | 291 | ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET); |
91dc985c | 292 | |
e932900a | 293 | err = clocksource_register_hz(&ttccs->cs, |
9e09dc5f | 294 | clk_get_rate(ttccs->ttc.clk) / PRESCALE); |
c5263bb8 MS |
295 | if (WARN_ON(err)) { |
296 | kfree(ttccs); | |
91dc985c | 297 | return; |
c5263bb8 | 298 | } |
91dc985c JC |
299 | } |
300 | ||
9e09dc5f | 301 | static int ttc_rate_change_clockevent_cb(struct notifier_block *nb, |
e932900a MS |
302 | unsigned long event, void *data) |
303 | { | |
304 | struct clk_notifier_data *ndata = data; | |
9e09dc5f MS |
305 | struct ttc_timer *ttc = to_ttc_timer(nb); |
306 | struct ttc_timer_clockevent *ttcce = container_of(ttc, | |
307 | struct ttc_timer_clockevent, ttc); | |
e932900a MS |
308 | |
309 | switch (event) { | |
310 | case POST_RATE_CHANGE: | |
311 | { | |
312 | unsigned long flags; | |
313 | ||
314 | /* | |
315 | * clockevents_update_freq should be called with IRQ disabled on | |
316 | * the CPU the timer provides events for. The timer we use is | |
317 | * common to both CPUs, not sure if we need to run on both | |
318 | * cores. | |
319 | */ | |
320 | local_irq_save(flags); | |
9e09dc5f | 321 | clockevents_update_freq(&ttcce->ce, |
e932900a MS |
322 | ndata->new_rate / PRESCALE); |
323 | local_irq_restore(flags); | |
324 | ||
325 | /* fall through */ | |
326 | } | |
327 | case PRE_RATE_CHANGE: | |
328 | case ABORT_RATE_CHANGE: | |
329 | default: | |
330 | return NOTIFY_DONE; | |
331 | } | |
332 | } | |
333 | ||
9e09dc5f | 334 | static void __init ttc_setup_clockevent(struct clk *clk, |
e932900a | 335 | void __iomem *base, u32 irq) |
91dc985c | 336 | { |
9e09dc5f | 337 | struct ttc_timer_clockevent *ttcce; |
e932900a | 338 | int err; |
91dc985c JC |
339 | |
340 | ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL); | |
341 | if (WARN_ON(!ttcce)) | |
342 | return; | |
343 | ||
9e09dc5f | 344 | ttcce->ttc.clk = clk; |
91dc985c | 345 | |
9e09dc5f | 346 | err = clk_prepare_enable(ttcce->ttc.clk); |
c5263bb8 MS |
347 | if (WARN_ON(err)) { |
348 | kfree(ttcce); | |
91dc985c | 349 | return; |
c5263bb8 | 350 | } |
91dc985c | 351 | |
9e09dc5f MS |
352 | ttcce->ttc.clk_rate_change_nb.notifier_call = |
353 | ttc_rate_change_clockevent_cb; | |
354 | ttcce->ttc.clk_rate_change_nb.next = NULL; | |
355 | if (clk_notifier_register(ttcce->ttc.clk, | |
356 | &ttcce->ttc.clk_rate_change_nb)) | |
e932900a | 357 | pr_warn("Unable to register clock notifier.\n"); |
91dc985c | 358 | |
9e09dc5f MS |
359 | ttcce->ttc.base_addr = base; |
360 | ttcce->ce.name = "ttc_clockevent"; | |
91dc985c | 361 | ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; |
9e09dc5f MS |
362 | ttcce->ce.set_next_event = ttc_set_next_event; |
363 | ttcce->ce.set_mode = ttc_set_mode; | |
91dc985c JC |
364 | ttcce->ce.rating = 200; |
365 | ttcce->ce.irq = irq; | |
87e4ee75 | 366 | ttcce->ce.cpumask = cpu_possible_mask; |
91dc985c | 367 | |
e932900a MS |
368 | /* |
369 | * Setup the clock event timer to be an interval timer which | |
370 | * is prescaled by 32 using the interval interrupt. Leave it | |
371 | * disabled for now. | |
372 | */ | |
9e09dc5f | 373 | __raw_writel(0x23, ttcce->ttc.base_addr + TTC_CNT_CNTRL_OFFSET); |
91dc985c | 374 | __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN, |
9e09dc5f MS |
375 | ttcce->ttc.base_addr + TTC_CLK_CNTRL_OFFSET); |
376 | __raw_writel(0x1, ttcce->ttc.base_addr + TTC_IER_OFFSET); | |
91dc985c | 377 | |
9e09dc5f | 378 | err = request_irq(irq, ttc_clock_event_interrupt, |
e932900a MS |
379 | IRQF_DISABLED | IRQF_TIMER, |
380 | ttcce->ce.name, ttcce); | |
c5263bb8 MS |
381 | if (WARN_ON(err)) { |
382 | kfree(ttcce); | |
91dc985c | 383 | return; |
c5263bb8 | 384 | } |
91dc985c JC |
385 | |
386 | clockevents_config_and_register(&ttcce->ce, | |
9e09dc5f | 387 | clk_get_rate(ttcce->ttc.clk) / PRESCALE, 1, 0xfffe); |
91dc985c JC |
388 | } |
389 | ||
b85a3ef4 | 390 | /** |
9e09dc5f | 391 | * ttc_timer_init - Initialize the timer |
b85a3ef4 JL |
392 | * |
393 | * Initializes the timer hardware and register the clock source and clock event | |
394 | * timers with Linux kernal timer framework | |
e932900a | 395 | */ |
9e09dc5f | 396 | static void __init ttc_timer_init(struct device_node *timer) |
e932900a MS |
397 | { |
398 | unsigned int irq; | |
399 | void __iomem *timer_baseaddr; | |
30e1e285 | 400 | struct clk *clk_cs, *clk_ce; |
c5263bb8 | 401 | static int initialized; |
30e1e285 | 402 | int clksel; |
c5263bb8 MS |
403 | |
404 | if (initialized) | |
405 | return; | |
406 | ||
407 | initialized = 1; | |
e932900a MS |
408 | |
409 | /* | |
410 | * Get the 1st Triple Timer Counter (TTC) block from the device tree | |
411 | * and use it. Note that the event timer uses the interrupt and it's the | |
412 | * 2nd TTC hence the irq_of_parse_and_map(,1) | |
413 | */ | |
414 | timer_baseaddr = of_iomap(timer, 0); | |
415 | if (!timer_baseaddr) { | |
416 | pr_err("ERROR: invalid timer base address\n"); | |
417 | BUG(); | |
418 | } | |
419 | ||
420 | irq = irq_of_parse_and_map(timer, 1); | |
421 | if (irq <= 0) { | |
422 | pr_err("ERROR: invalid interrupt number\n"); | |
423 | BUG(); | |
424 | } | |
425 | ||
30e1e285 SB |
426 | clksel = __raw_readl(timer_baseaddr + TTC_CLK_CNTRL_OFFSET); |
427 | clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK); | |
428 | clk_cs = of_clk_get(timer, clksel); | |
429 | if (IS_ERR(clk_cs)) { | |
430 | pr_err("ERROR: timer input clock not found\n"); | |
431 | BUG(); | |
432 | } | |
433 | ||
434 | clksel = __raw_readl(timer_baseaddr + 4 + TTC_CLK_CNTRL_OFFSET); | |
435 | clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK); | |
436 | clk_ce = of_clk_get(timer, clksel); | |
437 | if (IS_ERR(clk_ce)) { | |
e932900a MS |
438 | pr_err("ERROR: timer input clock not found\n"); |
439 | BUG(); | |
440 | } | |
441 | ||
30e1e285 SB |
442 | ttc_setup_clocksource(clk_cs, timer_baseaddr); |
443 | ttc_setup_clockevent(clk_ce, timer_baseaddr + 4, irq); | |
e932900a MS |
444 | |
445 | pr_info("%s #0 at %p, irq=%d\n", timer->name, timer_baseaddr, irq); | |
446 | } | |
447 | ||
9e09dc5f | 448 | CLOCKSOURCE_OF_DECLARE(ttc, "cdns,ttc", ttc_timer_init); |