Commit | Line | Data |
---|---|---|
b85a3ef4 | 1 | /* |
9e09dc5f | 2 | * This file contains driver for the Cadence Triple Timer Counter Rev 06 |
b85a3ef4 | 3 | * |
e932900a | 4 | * Copyright (C) 2011-2013 Xilinx |
b85a3ef4 JL |
5 | * |
6 | * based on arch/mips/kernel/time.c timer driver | |
7 | * | |
8 | * This software is licensed under the terms of the GNU General Public | |
9 | * License version 2, as published by the Free Software Foundation, and | |
10 | * may be copied, distributed, and modified under those terms. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | */ | |
17 | ||
e932900a | 18 | #include <linux/clk.h> |
b85a3ef4 | 19 | #include <linux/interrupt.h> |
b85a3ef4 | 20 | #include <linux/clockchips.h> |
459fa246 | 21 | #include <linux/clocksource.h> |
91dc985c JC |
22 | #include <linux/of_address.h> |
23 | #include <linux/of_irq.h> | |
24 | #include <linux/slab.h> | |
3d77b30e | 25 | #include <linux/sched_clock.h> |
b85a3ef4 | 26 | |
e932900a | 27 | /* |
4e2bec0c | 28 | * This driver configures the 2 16/32-bit count-up timers as follows: |
e932900a MS |
29 | * |
30 | * T1: Timer 1, clocksource for generic timekeeping | |
31 | * T2: Timer 2, clockevent source for hrtimers | |
32 | * T3: Timer 3, <unused> | |
33 | * | |
34 | * The input frequency to the timer module for emulation is 2.5MHz which is | |
35 | * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32, | |
36 | * the timers are clocked at 78.125KHz (12.8 us resolution). | |
37 | ||
38 | * The input frequency to the timer module in silicon is configurable and | |
39 | * obtained from device tree. The pre-scaler of 32 is used. | |
40 | */ | |
41 | ||
b85a3ef4 JL |
42 | /* |
43 | * Timer Register Offset Definitions of Timer 1, Increment base address by 4 | |
44 | * and use same offsets for Timer 2 | |
45 | */ | |
9e09dc5f MS |
46 | #define TTC_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */ |
47 | #define TTC_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */ | |
48 | #define TTC_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */ | |
49 | #define TTC_INTR_VAL_OFFSET 0x24 /* Interval Count Reg, RW */ | |
50 | #define TTC_ISR_OFFSET 0x54 /* Interrupt Status Reg, RO */ | |
51 | #define TTC_IER_OFFSET 0x60 /* Interrupt Enable Reg, RW */ | |
f184c5ca | 52 | |
9e09dc5f | 53 | #define TTC_CNT_CNTRL_DISABLE_MASK 0x1 |
b85a3ef4 | 54 | |
30e1e285 | 55 | #define TTC_CLK_CNTRL_CSRC_MASK (1 << 5) /* clock source */ |
b3e90722 SB |
56 | #define TTC_CLK_CNTRL_PSV_MASK 0x1e |
57 | #define TTC_CLK_CNTRL_PSV_SHIFT 1 | |
30e1e285 | 58 | |
03377e58 SB |
59 | /* |
60 | * Setup the timers to use pre-scaling, using a fixed value for now that will | |
91dc985c JC |
61 | * work across most input frequency, but it may need to be more dynamic |
62 | */ | |
63 | #define PRESCALE_EXPONENT 11 /* 2 ^ PRESCALE_EXPONENT = PRESCALE */ | |
64 | #define PRESCALE 2048 /* The exponent must match this */ | |
65 | #define CLK_CNTRL_PRESCALE ((PRESCALE_EXPONENT - 1) << 1) | |
66 | #define CLK_CNTRL_PRESCALE_EN 1 | |
e932900a | 67 | #define CNT_CNTRL_RESET (1 << 4) |
b85a3ef4 | 68 | |
b3e90722 SB |
69 | #define MAX_F_ERR 50 |
70 | ||
b85a3ef4 | 71 | /** |
9e09dc5f | 72 | * struct ttc_timer - This definition defines local timer structure |
b85a3ef4 JL |
73 | * |
74 | * @base_addr: Base address of timer | |
c1dcc927 | 75 | * @freq: Timer input clock frequency |
e932900a MS |
76 | * @clk: Associated clock source |
77 | * @clk_rate_change_nb Notifier block for clock rate changes | |
78 | */ | |
9e09dc5f | 79 | struct ttc_timer { |
e932900a | 80 | void __iomem *base_addr; |
c1dcc927 | 81 | unsigned long freq; |
e932900a MS |
82 | struct clk *clk; |
83 | struct notifier_block clk_rate_change_nb; | |
91dc985c JC |
84 | }; |
85 | ||
9e09dc5f MS |
86 | #define to_ttc_timer(x) \ |
87 | container_of(x, struct ttc_timer, clk_rate_change_nb) | |
e932900a | 88 | |
9e09dc5f | 89 | struct ttc_timer_clocksource { |
b3e90722 SB |
90 | u32 scale_clk_ctrl_reg_old; |
91 | u32 scale_clk_ctrl_reg_new; | |
9e09dc5f | 92 | struct ttc_timer ttc; |
91dc985c | 93 | struct clocksource cs; |
b85a3ef4 JL |
94 | }; |
95 | ||
9e09dc5f MS |
96 | #define to_ttc_timer_clksrc(x) \ |
97 | container_of(x, struct ttc_timer_clocksource, cs) | |
91dc985c | 98 | |
9e09dc5f MS |
99 | struct ttc_timer_clockevent { |
100 | struct ttc_timer ttc; | |
91dc985c | 101 | struct clock_event_device ce; |
91dc985c JC |
102 | }; |
103 | ||
9e09dc5f MS |
104 | #define to_ttc_timer_clkevent(x) \ |
105 | container_of(x, struct ttc_timer_clockevent, ce) | |
b85a3ef4 | 106 | |
3d77b30e SB |
107 | static void __iomem *ttc_sched_clock_val_reg; |
108 | ||
b85a3ef4 | 109 | /** |
9e09dc5f | 110 | * ttc_set_interval - Set the timer interval value |
b85a3ef4 JL |
111 | * |
112 | * @timer: Pointer to the timer instance | |
113 | * @cycles: Timer interval ticks | |
114 | **/ | |
9e09dc5f | 115 | static void ttc_set_interval(struct ttc_timer *timer, |
b85a3ef4 JL |
116 | unsigned long cycles) |
117 | { | |
118 | u32 ctrl_reg; | |
119 | ||
120 | /* Disable the counter, set the counter value and re-enable counter */ | |
87ab4361 | 121 | ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET); |
9e09dc5f | 122 | ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK; |
87ab4361 | 123 | writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); |
b85a3ef4 | 124 | |
87ab4361 | 125 | writel_relaxed(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET); |
b85a3ef4 | 126 | |
03377e58 SB |
127 | /* |
128 | * Reset the counter (0x10) so that it starts from 0, one-shot | |
129 | * mode makes this needed for timing to be right. | |
130 | */ | |
91dc985c | 131 | ctrl_reg |= CNT_CNTRL_RESET; |
9e09dc5f | 132 | ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK; |
87ab4361 | 133 | writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); |
b85a3ef4 JL |
134 | } |
135 | ||
136 | /** | |
9e09dc5f | 137 | * ttc_clock_event_interrupt - Clock event timer interrupt handler |
b85a3ef4 JL |
138 | * |
139 | * @irq: IRQ number of the Timer | |
9e09dc5f | 140 | * @dev_id: void pointer to the ttc_timer instance |
b85a3ef4 JL |
141 | * |
142 | * returns: Always IRQ_HANDLED - success | |
143 | **/ | |
9e09dc5f | 144 | static irqreturn_t ttc_clock_event_interrupt(int irq, void *dev_id) |
b85a3ef4 | 145 | { |
9e09dc5f MS |
146 | struct ttc_timer_clockevent *ttce = dev_id; |
147 | struct ttc_timer *timer = &ttce->ttc; | |
b85a3ef4 JL |
148 | |
149 | /* Acknowledge the interrupt and call event handler */ | |
87ab4361 | 150 | readl_relaxed(timer->base_addr + TTC_ISR_OFFSET); |
b85a3ef4 | 151 | |
9e09dc5f | 152 | ttce->ce.event_handler(&ttce->ce); |
b85a3ef4 JL |
153 | |
154 | return IRQ_HANDLED; | |
155 | } | |
156 | ||
b85a3ef4 | 157 | /** |
9e09dc5f | 158 | * __ttc_clocksource_read - Reads the timer counter register |
b85a3ef4 JL |
159 | * |
160 | * returns: Current timer counter register value | |
161 | **/ | |
a5a1d1c2 | 162 | static u64 __ttc_clocksource_read(struct clocksource *cs) |
b85a3ef4 | 163 | { |
9e09dc5f | 164 | struct ttc_timer *timer = &to_ttc_timer_clksrc(cs)->ttc; |
b85a3ef4 | 165 | |
a5a1d1c2 | 166 | return (u64)readl_relaxed(timer->base_addr + |
9e09dc5f | 167 | TTC_COUNT_VAL_OFFSET); |
b85a3ef4 JL |
168 | } |
169 | ||
dfded009 | 170 | static u64 notrace ttc_sched_clock_read(void) |
3d77b30e | 171 | { |
87ab4361 | 172 | return readl_relaxed(ttc_sched_clock_val_reg); |
3d77b30e SB |
173 | } |
174 | ||
b85a3ef4 | 175 | /** |
9e09dc5f | 176 | * ttc_set_next_event - Sets the time interval for next event |
b85a3ef4 JL |
177 | * |
178 | * @cycles: Timer interval ticks | |
179 | * @evt: Address of clock event instance | |
180 | * | |
181 | * returns: Always 0 - success | |
182 | **/ | |
9e09dc5f | 183 | static int ttc_set_next_event(unsigned long cycles, |
b85a3ef4 JL |
184 | struct clock_event_device *evt) |
185 | { | |
9e09dc5f MS |
186 | struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt); |
187 | struct ttc_timer *timer = &ttce->ttc; | |
b85a3ef4 | 188 | |
9e09dc5f | 189 | ttc_set_interval(timer, cycles); |
b85a3ef4 JL |
190 | return 0; |
191 | } | |
192 | ||
193 | /** | |
5c0a4bbe | 194 | * ttc_set_{shutdown|oneshot|periodic} - Sets the state of timer |
b85a3ef4 | 195 | * |
b85a3ef4 JL |
196 | * @evt: Address of clock event instance |
197 | **/ | |
5c0a4bbe | 198 | static int ttc_shutdown(struct clock_event_device *evt) |
b85a3ef4 | 199 | { |
9e09dc5f MS |
200 | struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt); |
201 | struct ttc_timer *timer = &ttce->ttc; | |
b85a3ef4 JL |
202 | u32 ctrl_reg; |
203 | ||
5c0a4bbe VK |
204 | ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET); |
205 | ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK; | |
206 | writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); | |
207 | return 0; | |
208 | } | |
209 | ||
210 | static int ttc_set_periodic(struct clock_event_device *evt) | |
211 | { | |
212 | struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt); | |
213 | struct ttc_timer *timer = &ttce->ttc; | |
214 | ||
215 | ttc_set_interval(timer, | |
216 | DIV_ROUND_CLOSEST(ttce->ttc.freq, PRESCALE * HZ)); | |
217 | return 0; | |
218 | } | |
219 | ||
220 | static int ttc_resume(struct clock_event_device *evt) | |
221 | { | |
222 | struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt); | |
223 | struct ttc_timer *timer = &ttce->ttc; | |
224 | u32 ctrl_reg; | |
225 | ||
226 | ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET); | |
227 | ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK; | |
228 | writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); | |
229 | return 0; | |
b85a3ef4 JL |
230 | } |
231 | ||
9e09dc5f | 232 | static int ttc_rate_change_clocksource_cb(struct notifier_block *nb, |
e932900a MS |
233 | unsigned long event, void *data) |
234 | { | |
235 | struct clk_notifier_data *ndata = data; | |
9e09dc5f MS |
236 | struct ttc_timer *ttc = to_ttc_timer(nb); |
237 | struct ttc_timer_clocksource *ttccs = container_of(ttc, | |
238 | struct ttc_timer_clocksource, ttc); | |
e932900a MS |
239 | |
240 | switch (event) { | |
b3e90722 SB |
241 | case PRE_RATE_CHANGE: |
242 | { | |
243 | u32 psv; | |
244 | unsigned long factor, rate_low, rate_high; | |
245 | ||
246 | if (ndata->new_rate > ndata->old_rate) { | |
247 | factor = DIV_ROUND_CLOSEST(ndata->new_rate, | |
248 | ndata->old_rate); | |
249 | rate_low = ndata->old_rate; | |
250 | rate_high = ndata->new_rate; | |
251 | } else { | |
252 | factor = DIV_ROUND_CLOSEST(ndata->old_rate, | |
253 | ndata->new_rate); | |
254 | rate_low = ndata->new_rate; | |
255 | rate_high = ndata->old_rate; | |
256 | } | |
257 | ||
258 | if (!is_power_of_2(factor)) | |
259 | return NOTIFY_BAD; | |
260 | ||
261 | if (abs(rate_high - (factor * rate_low)) > MAX_F_ERR) | |
262 | return NOTIFY_BAD; | |
263 | ||
264 | factor = __ilog2_u32(factor); | |
265 | ||
e932900a | 266 | /* |
b3e90722 SB |
267 | * store timer clock ctrl register so we can restore it in case |
268 | * of an abort. | |
e932900a | 269 | */ |
b3e90722 | 270 | ttccs->scale_clk_ctrl_reg_old = |
87ab4361 MS |
271 | readl_relaxed(ttccs->ttc.base_addr + |
272 | TTC_CLK_CNTRL_OFFSET); | |
b3e90722 SB |
273 | |
274 | psv = (ttccs->scale_clk_ctrl_reg_old & | |
275 | TTC_CLK_CNTRL_PSV_MASK) >> | |
276 | TTC_CLK_CNTRL_PSV_SHIFT; | |
277 | if (ndata->new_rate < ndata->old_rate) | |
278 | psv -= factor; | |
279 | else | |
280 | psv += factor; | |
281 | ||
282 | /* prescaler within legal range? */ | |
283 | if (psv & ~(TTC_CLK_CNTRL_PSV_MASK >> TTC_CLK_CNTRL_PSV_SHIFT)) | |
284 | return NOTIFY_BAD; | |
285 | ||
286 | ttccs->scale_clk_ctrl_reg_new = ttccs->scale_clk_ctrl_reg_old & | |
287 | ~TTC_CLK_CNTRL_PSV_MASK; | |
288 | ttccs->scale_clk_ctrl_reg_new |= psv << TTC_CLK_CNTRL_PSV_SHIFT; | |
289 | ||
290 | ||
291 | /* scale down: adjust divider in post-change notification */ | |
292 | if (ndata->new_rate < ndata->old_rate) | |
293 | return NOTIFY_DONE; | |
294 | ||
295 | /* scale up: adjust divider now - before frequency change */ | |
87ab4361 MS |
296 | writel_relaxed(ttccs->scale_clk_ctrl_reg_new, |
297 | ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET); | |
b3e90722 SB |
298 | break; |
299 | } | |
300 | case POST_RATE_CHANGE: | |
301 | /* scale up: pre-change notification did the adjustment */ | |
302 | if (ndata->new_rate > ndata->old_rate) | |
303 | return NOTIFY_OK; | |
304 | ||
305 | /* scale down: adjust divider now - after frequency change */ | |
87ab4361 MS |
306 | writel_relaxed(ttccs->scale_clk_ctrl_reg_new, |
307 | ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET); | |
b3e90722 SB |
308 | break; |
309 | ||
e932900a | 310 | case ABORT_RATE_CHANGE: |
b3e90722 SB |
311 | /* we have to undo the adjustment in case we scale up */ |
312 | if (ndata->new_rate < ndata->old_rate) | |
313 | return NOTIFY_OK; | |
314 | ||
315 | /* restore original register value */ | |
87ab4361 MS |
316 | writel_relaxed(ttccs->scale_clk_ctrl_reg_old, |
317 | ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET); | |
b3e90722 | 318 | /* fall through */ |
e932900a MS |
319 | default: |
320 | return NOTIFY_DONE; | |
321 | } | |
b3e90722 SB |
322 | |
323 | return NOTIFY_DONE; | |
e932900a MS |
324 | } |
325 | ||
70504f31 | 326 | static int __init ttc_setup_clocksource(struct clk *clk, void __iomem *base, |
4e2bec0c | 327 | u32 timer_width) |
91dc985c | 328 | { |
9e09dc5f | 329 | struct ttc_timer_clocksource *ttccs; |
91dc985c | 330 | int err; |
91dc985c JC |
331 | |
332 | ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL); | |
70504f31 DL |
333 | if (!ttccs) |
334 | return -ENOMEM; | |
91dc985c | 335 | |
9e09dc5f | 336 | ttccs->ttc.clk = clk; |
91dc985c | 337 | |
9e09dc5f | 338 | err = clk_prepare_enable(ttccs->ttc.clk); |
70504f31 | 339 | if (err) { |
c5263bb8 | 340 | kfree(ttccs); |
70504f31 | 341 | return err; |
c5263bb8 | 342 | } |
91dc985c | 343 | |
c1dcc927 SB |
344 | ttccs->ttc.freq = clk_get_rate(ttccs->ttc.clk); |
345 | ||
9e09dc5f MS |
346 | ttccs->ttc.clk_rate_change_nb.notifier_call = |
347 | ttc_rate_change_clocksource_cb; | |
348 | ttccs->ttc.clk_rate_change_nb.next = NULL; | |
70504f31 DL |
349 | |
350 | err = clk_notifier_register(ttccs->ttc.clk, | |
351 | &ttccs->ttc.clk_rate_change_nb); | |
352 | if (err) | |
e932900a | 353 | pr_warn("Unable to register clock notifier.\n"); |
91dc985c | 354 | |
9e09dc5f MS |
355 | ttccs->ttc.base_addr = base; |
356 | ttccs->cs.name = "ttc_clocksource"; | |
91dc985c | 357 | ttccs->cs.rating = 200; |
9e09dc5f | 358 | ttccs->cs.read = __ttc_clocksource_read; |
4e2bec0c | 359 | ttccs->cs.mask = CLOCKSOURCE_MASK(timer_width); |
91dc985c JC |
360 | ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS; |
361 | ||
e932900a MS |
362 | /* |
363 | * Setup the clock source counter to be an incrementing counter | |
364 | * with no interrupt and it rolls over at 0xFFFF. Pre-scale | |
365 | * it by 32 also. Let it start running now. | |
366 | */ | |
87ab4361 MS |
367 | writel_relaxed(0x0, ttccs->ttc.base_addr + TTC_IER_OFFSET); |
368 | writel_relaxed(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN, | |
9e09dc5f | 369 | ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET); |
87ab4361 | 370 | writel_relaxed(CNT_CNTRL_RESET, |
9e09dc5f | 371 | ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET); |
91dc985c | 372 | |
c1dcc927 | 373 | err = clocksource_register_hz(&ttccs->cs, ttccs->ttc.freq / PRESCALE); |
70504f31 | 374 | if (err) { |
c5263bb8 | 375 | kfree(ttccs); |
70504f31 | 376 | return err; |
c5263bb8 | 377 | } |
3d77b30e SB |
378 | |
379 | ttc_sched_clock_val_reg = base + TTC_COUNT_VAL_OFFSET; | |
4e2bec0c MS |
380 | sched_clock_register(ttc_sched_clock_read, timer_width, |
381 | ttccs->ttc.freq / PRESCALE); | |
70504f31 DL |
382 | |
383 | return 0; | |
91dc985c JC |
384 | } |
385 | ||
9e09dc5f | 386 | static int ttc_rate_change_clockevent_cb(struct notifier_block *nb, |
e932900a MS |
387 | unsigned long event, void *data) |
388 | { | |
389 | struct clk_notifier_data *ndata = data; | |
9e09dc5f MS |
390 | struct ttc_timer *ttc = to_ttc_timer(nb); |
391 | struct ttc_timer_clockevent *ttcce = container_of(ttc, | |
392 | struct ttc_timer_clockevent, ttc); | |
e932900a MS |
393 | |
394 | switch (event) { | |
395 | case POST_RATE_CHANGE: | |
c1dcc927 SB |
396 | /* update cached frequency */ |
397 | ttc->freq = ndata->new_rate; | |
398 | ||
5f0ba3b4 SB |
399 | clockevents_update_freq(&ttcce->ce, ndata->new_rate / PRESCALE); |
400 | ||
e932900a | 401 | /* fall through */ |
e932900a MS |
402 | case PRE_RATE_CHANGE: |
403 | case ABORT_RATE_CHANGE: | |
404 | default: | |
405 | return NOTIFY_DONE; | |
406 | } | |
407 | } | |
408 | ||
70504f31 DL |
409 | static int __init ttc_setup_clockevent(struct clk *clk, |
410 | void __iomem *base, u32 irq) | |
91dc985c | 411 | { |
9e09dc5f | 412 | struct ttc_timer_clockevent *ttcce; |
e932900a | 413 | int err; |
91dc985c JC |
414 | |
415 | ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL); | |
70504f31 DL |
416 | if (!ttcce) |
417 | return -ENOMEM; | |
91dc985c | 418 | |
9e09dc5f | 419 | ttcce->ttc.clk = clk; |
91dc985c | 420 | |
9e09dc5f | 421 | err = clk_prepare_enable(ttcce->ttc.clk); |
70504f31 | 422 | if (err) { |
c5263bb8 | 423 | kfree(ttcce); |
70504f31 | 424 | return err; |
c5263bb8 | 425 | } |
91dc985c | 426 | |
9e09dc5f MS |
427 | ttcce->ttc.clk_rate_change_nb.notifier_call = |
428 | ttc_rate_change_clockevent_cb; | |
429 | ttcce->ttc.clk_rate_change_nb.next = NULL; | |
70504f31 DL |
430 | |
431 | err = clk_notifier_register(ttcce->ttc.clk, | |
432 | &ttcce->ttc.clk_rate_change_nb); | |
433 | if (err) { | |
e932900a | 434 | pr_warn("Unable to register clock notifier.\n"); |
70504f31 DL |
435 | return err; |
436 | } | |
437 | ||
c1dcc927 | 438 | ttcce->ttc.freq = clk_get_rate(ttcce->ttc.clk); |
91dc985c | 439 | |
9e09dc5f MS |
440 | ttcce->ttc.base_addr = base; |
441 | ttcce->ce.name = "ttc_clockevent"; | |
91dc985c | 442 | ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; |
9e09dc5f | 443 | ttcce->ce.set_next_event = ttc_set_next_event; |
5c0a4bbe VK |
444 | ttcce->ce.set_state_shutdown = ttc_shutdown; |
445 | ttcce->ce.set_state_periodic = ttc_set_periodic; | |
446 | ttcce->ce.set_state_oneshot = ttc_shutdown; | |
447 | ttcce->ce.tick_resume = ttc_resume; | |
91dc985c JC |
448 | ttcce->ce.rating = 200; |
449 | ttcce->ce.irq = irq; | |
87e4ee75 | 450 | ttcce->ce.cpumask = cpu_possible_mask; |
91dc985c | 451 | |
e932900a MS |
452 | /* |
453 | * Setup the clock event timer to be an interval timer which | |
454 | * is prescaled by 32 using the interval interrupt. Leave it | |
455 | * disabled for now. | |
456 | */ | |
87ab4361 MS |
457 | writel_relaxed(0x23, ttcce->ttc.base_addr + TTC_CNT_CNTRL_OFFSET); |
458 | writel_relaxed(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN, | |
9e09dc5f | 459 | ttcce->ttc.base_addr + TTC_CLK_CNTRL_OFFSET); |
87ab4361 | 460 | writel_relaxed(0x1, ttcce->ttc.base_addr + TTC_IER_OFFSET); |
91dc985c | 461 | |
9e09dc5f | 462 | err = request_irq(irq, ttc_clock_event_interrupt, |
38c30a84 | 463 | IRQF_TIMER, ttcce->ce.name, ttcce); |
70504f31 | 464 | if (err) { |
c5263bb8 | 465 | kfree(ttcce); |
70504f31 | 466 | return err; |
c5263bb8 | 467 | } |
91dc985c JC |
468 | |
469 | clockevents_config_and_register(&ttcce->ce, | |
c1dcc927 | 470 | ttcce->ttc.freq / PRESCALE, 1, 0xfffe); |
70504f31 DL |
471 | |
472 | return 0; | |
91dc985c JC |
473 | } |
474 | ||
b85a3ef4 | 475 | /** |
9e09dc5f | 476 | * ttc_timer_init - Initialize the timer |
b85a3ef4 JL |
477 | * |
478 | * Initializes the timer hardware and register the clock source and clock event | |
479 | * timers with Linux kernal timer framework | |
e932900a | 480 | */ |
70504f31 | 481 | static int __init ttc_timer_init(struct device_node *timer) |
e932900a MS |
482 | { |
483 | unsigned int irq; | |
484 | void __iomem *timer_baseaddr; | |
30e1e285 | 485 | struct clk *clk_cs, *clk_ce; |
c5263bb8 | 486 | static int initialized; |
70504f31 | 487 | int clksel, ret; |
4e2bec0c | 488 | u32 timer_width = 16; |
c5263bb8 MS |
489 | |
490 | if (initialized) | |
70504f31 | 491 | return 0; |
c5263bb8 MS |
492 | |
493 | initialized = 1; | |
e932900a MS |
494 | |
495 | /* | |
496 | * Get the 1st Triple Timer Counter (TTC) block from the device tree | |
497 | * and use it. Note that the event timer uses the interrupt and it's the | |
498 | * 2nd TTC hence the irq_of_parse_and_map(,1) | |
499 | */ | |
500 | timer_baseaddr = of_iomap(timer, 0); | |
501 | if (!timer_baseaddr) { | |
502 | pr_err("ERROR: invalid timer base address\n"); | |
70504f31 | 503 | return -ENXIO; |
e932900a MS |
504 | } |
505 | ||
506 | irq = irq_of_parse_and_map(timer, 1); | |
507 | if (irq <= 0) { | |
508 | pr_err("ERROR: invalid interrupt number\n"); | |
70504f31 | 509 | return -EINVAL; |
e932900a MS |
510 | } |
511 | ||
4e2bec0c MS |
512 | of_property_read_u32(timer, "timer-width", &timer_width); |
513 | ||
87ab4361 | 514 | clksel = readl_relaxed(timer_baseaddr + TTC_CLK_CNTRL_OFFSET); |
30e1e285 SB |
515 | clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK); |
516 | clk_cs = of_clk_get(timer, clksel); | |
517 | if (IS_ERR(clk_cs)) { | |
518 | pr_err("ERROR: timer input clock not found\n"); | |
70504f31 | 519 | return PTR_ERR(clk_cs); |
30e1e285 SB |
520 | } |
521 | ||
87ab4361 | 522 | clksel = readl_relaxed(timer_baseaddr + 4 + TTC_CLK_CNTRL_OFFSET); |
30e1e285 SB |
523 | clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK); |
524 | clk_ce = of_clk_get(timer, clksel); | |
525 | if (IS_ERR(clk_ce)) { | |
e932900a | 526 | pr_err("ERROR: timer input clock not found\n"); |
34c720a9 | 527 | return PTR_ERR(clk_ce); |
e932900a MS |
528 | } |
529 | ||
70504f31 DL |
530 | ret = ttc_setup_clocksource(clk_cs, timer_baseaddr, timer_width); |
531 | if (ret) | |
532 | return ret; | |
533 | ||
534 | ret = ttc_setup_clockevent(clk_ce, timer_baseaddr + 4, irq); | |
535 | if (ret) | |
536 | return ret; | |
e932900a MS |
537 | |
538 | pr_info("%s #0 at %p, irq=%d\n", timer->name, timer_baseaddr, irq); | |
70504f31 DL |
539 | |
540 | return 0; | |
e932900a MS |
541 | } |
542 | ||
17273395 | 543 | TIMER_OF_DECLARE(ttc, "cdns,ttc", ttc_timer_init); |