[linux-2.6-block.git] / drivers / clocksource / bcm2835_timer.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2012 Simon Arlott
 */

#include <linux/bitops.h>
#include <linux/clockchips.h>
#include <linux/clocksource.h>
#include <linux/interrupt.h>
#include <linux/irqreturn.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/sched_clock.h>

#include <asm/irq.h>

#define REG_CONTROL	0x00
#define REG_COUNTER_LO	0x04
#define REG_COUNTER_HI	0x08
#define REG_COMPARE(n)	(0x0c + (n) * 4)
#define MAX_TIMER	3
#define DEFAULT_TIMER	3

struct bcm2835_timer {
	void __iomem *control;
	void __iomem *compare;
	int match_mask;
	struct clock_event_device evt;
};

static void __iomem *system_clock __read_mostly;

static u64 notrace bcm2835_sched_read(void)
{
	return readl_relaxed(system_clock);
}

static int bcm2835_time_set_next_event(unsigned long event,
	struct clock_event_device *evt_dev)
{
	struct bcm2835_timer *timer = container_of(evt_dev,
		struct bcm2835_timer, evt);
	writel_relaxed(readl_relaxed(system_clock) + event,
		timer->compare);
	return 0;
}

static irqreturn_t bcm2835_time_interrupt(int irq, void *dev_id)
{
	struct bcm2835_timer *timer = dev_id;
	void (*event_handler)(struct clock_event_device *);
	if (readl_relaxed(timer->control) & timer->match_mask) {
		writel_relaxed(timer->match_mask, timer->control);

		event_handler = READ_ONCE(timer->evt.event_handler);
		if (event_handler)
			event_handler(&timer->evt);
		return IRQ_HANDLED;
	} else {
		return IRQ_NONE;
	}
}

static int __init bcm2835_timer_init(struct device_node *node)
{
	void __iomem *base;
	u32 freq;
	int irq, ret;
	struct bcm2835_timer *timer;

	base = of_iomap(node, 0);
	if (!base) {
		pr_err("Can't remap registers\n");
		return -ENXIO;
	}

	ret = of_property_read_u32(node, "clock-frequency", &freq);
	if (ret) {
		pr_err("Can't read clock-frequency\n");
		goto err_iounmap;
	}

	system_clock = base + REG_COUNTER_LO;
	sched_clock_register(bcm2835_sched_read, 32, freq);

	clocksource_mmio_init(base + REG_COUNTER_LO, node->name,
		freq, 300, 32, clocksource_mmio_readl_up);

	irq = irq_of_parse_and_map(node, DEFAULT_TIMER);
	if (irq <= 0) {
		pr_err("Can't parse IRQ\n");
		ret = -EINVAL;
		goto err_iounmap;
	}

	timer = kzalloc(sizeof(*timer), GFP_KERNEL);
	if (!timer) {
		ret = -ENOMEM;
		goto err_iounmap;
	}

	timer->control = base + REG_CONTROL;
	timer->compare = base + REG_COMPARE(DEFAULT_TIMER);
	timer->match_mask = BIT(DEFAULT_TIMER);
	timer->evt.name = node->name;
	timer->evt.rating = 300;
	timer->evt.features = CLOCK_EVT_FEAT_ONESHOT;
	timer->evt.set_next_event = bcm2835_time_set_next_event;
	timer->evt.cpumask = cpumask_of(0);

	ret = request_irq(irq, bcm2835_time_interrupt, IRQF_TIMER | IRQF_SHARED,
			  node->name, timer);
	if (ret) {
		pr_err("Can't set up timer IRQ\n");
		goto err_timer_free;
	}

	clockevents_config_and_register(&timer->evt, freq, 0xf, 0xffffffff);

	pr_info("bcm2835: system timer (irq = %d)\n", irq);

	return 0;

err_timer_free:
	kfree(timer);

err_iounmap:
	iounmap(base);
	return ret;
}
TIMER_OF_DECLARE(bcm2835, "brcm,bcm2835-system-timer",
			bcm2835_timer_init);
Commit	Line	Data
64db8bb1	1	// SPDX-License-Identifier: GPL-2.0+
ee4af569 SA	2	/*
ee4af569 SA	3	* Copyright 2012 Simon Arlott
ee4af569 SA	4	*/
ee4af569 SA	5
ee4af569 SA	6	#include <linux/bitops.h>
	7	#include <linux/clockchips.h>
	8	#include <linux/clocksource.h>
	9	#include <linux/interrupt.h>
	10	#include <linux/irqreturn.h>
	11	#include <linux/kernel.h>
	12	#include <linux/module.h>
6303d069	13	#include <linux/of.h>
ee4af569 SA	14	#include <linux/of_address.h>
ee4af569 SA	15	#include <linux/of_irq.h>
ee4af569 SA	16	#include <linux/slab.h>
ee4af569 SA	17	#include <linux/string.h>
38ff87f7	18	#include <linux/sched_clock.h>
ee4af569	19
ee4af569 SA	20	#include <asm/irq.h>
	21
	22	#define REG_CONTROL 0x00
	23	#define REG_COUNTER_LO 0x04
	24	#define REG_COUNTER_HI 0x08
	25	#define REG_COMPARE(n) (0x0c + (n) * 4)
	26	#define MAX_TIMER 3
	27	#define DEFAULT_TIMER 3
	28
	29	struct bcm2835_timer {
	30	void __iomem *control;
	31	void __iomem *compare;
	32	int match_mask;
	33	struct clock_event_device evt;
ee4af569 SA	34	};
	35
	36	static void __iomem *system_clock __read_mostly;
	37
18952f20	38	static u64 notrace bcm2835_sched_read(void)
ee4af569 SA	39	{
	40	return readl_relaxed(system_clock);
	41	}
	42
ee4af569 SA	43	static int bcm2835_time_set_next_event(unsigned long event,
	44	struct clock_event_device *evt_dev)
	45	{
	46	struct bcm2835_timer *timer = container_of(evt_dev,
	47	struct bcm2835_timer, evt);
	48	writel_relaxed(readl_relaxed(system_clock) + event,
	49	timer->compare);
	50	return 0;
	51	}
	52
	53	static irqreturn_t bcm2835_time_interrupt(int irq, void *dev_id)
	54	{
	55	struct bcm2835_timer *timer = dev_id;
	56	void (event_handler)(struct clock_event_device );
	57	if (readl_relaxed(timer->control) & timer->match_mask) {
	58	writel_relaxed(timer->match_mask, timer->control);
	59
6aa7de05	60	event_handler = READ_ONCE(timer->evt.event_handler);
ee4af569 SA	61	if (event_handler)
	62	event_handler(&timer->evt);
	63	return IRQ_HANDLED;
	64	} else {
	65	return IRQ_NONE;
	66	}
	67	}
	68
524a7f08	69	static int __init bcm2835_timer_init(struct device_node *node)
ee4af569	70	{
ee4af569 SA	71	void __iomem *base;
ee4af569 SA	72	u32 freq;
524a7f08	73	int irq, ret;
ee4af569 SA	74	struct bcm2835_timer *timer;
ee4af569 SA	75
ee4af569	76	base = of_iomap(node, 0);
524a7f08	77	if (!base) {
ac9ce6d1	78	pr_err("Can't remap registers\n");
524a7f08 DL	79	return -ENXIO;
524a7f08 DL	80	}
ee4af569	81
524a7f08 DL	82	ret = of_property_read_u32(node, "clock-frequency", &freq);
524a7f08 DL	83	if (ret) {
ac9ce6d1	84	pr_err("Can't read clock-frequency\n");
84c39b8b	85	goto err_iounmap;
524a7f08	86	}
ee4af569 SA	87
ee4af569 SA	88	system_clock = base + REG_COUNTER_LO;
18952f20	89	sched_clock_register(bcm2835_sched_read, 32, freq);
ee4af569 SA	90
	91	clocksource_mmio_init(base + REG_COUNTER_LO, node->name,
	92	freq, 300, 32, clocksource_mmio_readl_up);
	93
	94	irq = irq_of_parse_and_map(node, DEFAULT_TIMER);
524a7f08	95	if (irq <= 0) {
ac9ce6d1	96	pr_err("Can't parse IRQ\n");
84c39b8b AY	97	ret = -EINVAL;
84c39b8b AY	98	goto err_iounmap;
524a7f08	99	}
ee4af569 SA	100
ee4af569 SA	101	timer = kzalloc(sizeof(*timer), GFP_KERNEL);
524a7f08	102	if (!timer) {
84c39b8b AY	103	ret = -ENOMEM;
84c39b8b AY	104	goto err_iounmap;
524a7f08	105	}
ee4af569 SA	106
	107	timer->control = base + REG_CONTROL;
	108	timer->compare = base + REG_COMPARE(DEFAULT_TIMER);
	109	timer->match_mask = BIT(DEFAULT_TIMER);
	110	timer->evt.name = node->name;
	111	timer->evt.rating = 300;
	112	timer->evt.features = CLOCK_EVT_FEAT_ONESHOT;
ee4af569 SA	113	timer->evt.set_next_event = bcm2835_time_set_next_event;
ee4af569 SA	114	timer->evt.cpumask = cpumask_of(0);
ee4af569	115
cc2550b4	116	ret = request_irq(irq, bcm2835_time_interrupt, IRQF_TIMER \| IRQF_SHARED,
cc2550b4	117	node->name, timer);
524a7f08 DL	118	if (ret) {
524a7f08 DL	119	pr_err("Can't set up timer IRQ\n");
2052d032	120	goto err_timer_free;
524a7f08	121	}
ee4af569 SA	122
	123	clockevents_config_and_register(&timer->evt, freq, 0xf, 0xffffffff);
	124
	125	pr_info("bcm2835: system timer (irq = %d)\n", irq);
524a7f08 DL	126
524a7f08 DL	127	return 0;
84c39b8b	128
2052d032 CIK	129	err_timer_free:
	130	kfree(timer);
	131
84c39b8b AY	132	err_iounmap:
	133	iounmap(base);
	134	return ret;
ee4af569	135	}
17273395	136	TIMER_OF_DECLARE(bcm2835, "brcm,bcm2835-system-timer",
c1b724f6	137	bcm2835_timer_init);