[linux-2.6-block.git] / drivers / clocksource / arm_arch_timer.c

/*
 *  linux/drivers/clocksource/arm_arch_timer.c
 *
 *  Copyright (C) 2011 ARM Ltd.
 *  All Rights Reserved
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/smp.h>
#include <linux/cpu.h>
#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/of_irq.h>
#include <linux/io.h>

#include <asm/arch_timer.h>
#include <asm/virt.h>

#include <clocksource/arm_arch_timer.h>

static u32 arch_timer_rate;

enum ppi_nr {
	PHYS_SECURE_PPI,
	PHYS_NONSECURE_PPI,
	VIRT_PPI,
	HYP_PPI,
	MAX_TIMER_PPI
};

static int arch_timer_ppi[MAX_TIMER_PPI];

static struct clock_event_device __percpu *arch_timer_evt;

static bool arch_timer_use_virtual = true;

/*
 * Architected system timer support.
 */

static __always_inline
void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val,
		struct clock_event_device *clk)
{
	arch_timer_reg_write_cp15(access, reg, val);
}

static __always_inline
u32 arch_timer_reg_read(int access, enum arch_timer_reg reg,
		struct clock_event_device *clk)
{
	return arch_timer_reg_read_cp15(access, reg);
}

static __always_inline irqreturn_t timer_handler(const int access,
					struct clock_event_device *evt)
{
	unsigned long ctrl;
	ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, evt);
	if (ctrl & ARCH_TIMER_CTRL_IT_STAT) {
		ctrl |= ARCH_TIMER_CTRL_IT_MASK;
		arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, evt);
		evt->event_handler(evt);
		return IRQ_HANDLED;
	}

	return IRQ_NONE;
}

static irqreturn_t arch_timer_handler_virt(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;

	return timer_handler(ARCH_TIMER_VIRT_ACCESS, evt);
}

static irqreturn_t arch_timer_handler_phys(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;

	return timer_handler(ARCH_TIMER_PHYS_ACCESS, evt);
}

static __always_inline void timer_set_mode(const int access, int mode,
				  struct clock_event_device *clk)
{
	unsigned long ctrl;
	switch (mode) {
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
		ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
		ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
		arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
		break;
	default:
		break;
	}
}

static void arch_timer_set_mode_virt(enum clock_event_mode mode,
				     struct clock_event_device *clk)
{
	timer_set_mode(ARCH_TIMER_VIRT_ACCESS, mode, clk);
}

static void arch_timer_set_mode_phys(enum clock_event_mode mode,
				     struct clock_event_device *clk)
{
	timer_set_mode(ARCH_TIMER_PHYS_ACCESS, mode, clk);
}

static __always_inline void set_next_event(const int access, unsigned long evt,
				  struct clock_event_device *clk)
{
	unsigned long ctrl;
	ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
	ctrl |= ARCH_TIMER_CTRL_ENABLE;
	ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
	arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, evt, clk);
	arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
}

static int arch_timer_set_next_event_virt(unsigned long evt,
					  struct clock_event_device *clk)
{
	set_next_event(ARCH_TIMER_VIRT_ACCESS, evt, clk);
	return 0;
}

static int arch_timer_set_next_event_phys(unsigned long evt,
					  struct clock_event_device *clk)
{
	set_next_event(ARCH_TIMER_PHYS_ACCESS, evt, clk);
	return 0;
}

static int __cpuinit arch_timer_setup(struct clock_event_device *clk)
{
	clk->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP;
	clk->name = "arch_sys_timer";
	clk->rating = 450;
	if (arch_timer_use_virtual) {
		clk->irq = arch_timer_ppi[VIRT_PPI];
		clk->set_mode = arch_timer_set_mode_virt;
		clk->set_next_event = arch_timer_set_next_event_virt;
	} else {
		clk->irq = arch_timer_ppi[PHYS_SECURE_PPI];
		clk->set_mode = arch_timer_set_mode_phys;
		clk->set_next_event = arch_timer_set_next_event_phys;
	}

	clk->cpumask = cpumask_of(smp_processor_id());

	clk->set_mode(CLOCK_EVT_MODE_SHUTDOWN, clk);

	clockevents_config_and_register(clk, arch_timer_rate,
					0xf, 0x7fffffff);

	if (arch_timer_use_virtual)
		enable_percpu_irq(arch_timer_ppi[VIRT_PPI], 0);
	else {
		enable_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI], 0);
		if (arch_timer_ppi[PHYS_NONSECURE_PPI])
			enable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI], 0);
	}

	arch_counter_set_user_access();

	return 0;
}

static int arch_timer_available(void)
{
	u32 freq;

	if (arch_timer_rate == 0) {
		freq = arch_timer_get_cntfrq();

		/* Check the timer frequency. */
		if (freq == 0) {
			pr_warn("Architected timer frequency not available\n");
			return -EINVAL;
		}

		arch_timer_rate = freq;
	}

	pr_info_once("Architected local timer running at %lu.%02luMHz (%s).\n",
		     (unsigned long)arch_timer_rate / 1000000,
		     (unsigned long)(arch_timer_rate / 10000) % 100,
		     arch_timer_use_virtual ? "virt" : "phys");
	return 0;
}

u32 arch_timer_get_rate(void)
{
	return arch_timer_rate;
}

u64 arch_timer_read_counter(void)
{
	return arch_counter_get_cntvct();
}

static cycle_t arch_counter_read(struct clocksource *cs)
{
	return arch_counter_get_cntvct();
}

static cycle_t arch_counter_read_cc(const struct cyclecounter *cc)
{
	return arch_counter_get_cntvct();
}

static struct clocksource clocksource_counter = {
	.name	= "arch_sys_counter",
	.rating	= 400,
	.read	= arch_counter_read,
	.mask	= CLOCKSOURCE_MASK(56),
	.flags	= CLOCK_SOURCE_IS_CONTINUOUS,
};

static struct cyclecounter cyclecounter = {
	.read	= arch_counter_read_cc,
	.mask	= CLOCKSOURCE_MASK(56),
};

static struct timecounter timecounter;

struct timecounter *arch_timer_get_timecounter(void)
{
	return &timecounter;
}

static void __cpuinit arch_timer_stop(struct clock_event_device *clk)
{
	pr_debug("arch_timer_teardown disable IRQ%d cpu #%d\n",
		 clk->irq, smp_processor_id());

	if (arch_timer_use_virtual)
		disable_percpu_irq(arch_timer_ppi[VIRT_PPI]);
	else {
		disable_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI]);
		if (arch_timer_ppi[PHYS_NONSECURE_PPI])
			disable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI]);
	}

	clk->set_mode(CLOCK_EVT_MODE_UNUSED, clk);
}

static int __cpuinit arch_timer_cpu_notify(struct notifier_block *self,
					   unsigned long action, void *hcpu)
{
	/*
	 * Grab cpu pointer in each case to avoid spurious
	 * preemptible warnings
	 */
	switch (action & ~CPU_TASKS_FROZEN) {
	case CPU_STARTING:
		arch_timer_setup(this_cpu_ptr(arch_timer_evt));
		break;
	case CPU_DYING:
		arch_timer_stop(this_cpu_ptr(arch_timer_evt));
		break;
	}

	return NOTIFY_OK;
}

static struct notifier_block arch_timer_cpu_nb __cpuinitdata = {
	.notifier_call = arch_timer_cpu_notify,
};

static int __init arch_timer_register(void)
{
	int err;
	int ppi;

	err = arch_timer_available();
	if (err)
		goto out;

	arch_timer_evt = alloc_percpu(struct clock_event_device);
	if (!arch_timer_evt) {
		err = -ENOMEM;
		goto out;
	}

	clocksource_register_hz(&clocksource_counter, arch_timer_rate);
	cyclecounter.mult = clocksource_counter.mult;
	cyclecounter.shift = clocksource_counter.shift;
	timecounter_init(&timecounter, &cyclecounter,
			 arch_counter_get_cntvct());

	if (arch_timer_use_virtual) {
		ppi = arch_timer_ppi[VIRT_PPI];
		err = request_percpu_irq(ppi, arch_timer_handler_virt,
					 "arch_timer", arch_timer_evt);
	} else {
		ppi = arch_timer_ppi[PHYS_SECURE_PPI];
		err = request_percpu_irq(ppi, arch_timer_handler_phys,
					 "arch_timer", arch_timer_evt);
		if (!err && arch_timer_ppi[PHYS_NONSECURE_PPI]) {
			ppi = arch_timer_ppi[PHYS_NONSECURE_PPI];
			err = request_percpu_irq(ppi, arch_timer_handler_phys,
						 "arch_timer", arch_timer_evt);
			if (err)
				free_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI],
						arch_timer_evt);
		}
	}

	if (err) {
		pr_err("arch_timer: can't register interrupt %d (%d)\n",
		       ppi, err);
		goto out_free;
	}

	err = register_cpu_notifier(&arch_timer_cpu_nb);
	if (err)
		goto out_free_irq;

	/* Immediately configure the timer on the boot CPU */
	arch_timer_setup(this_cpu_ptr(arch_timer_evt));

	return 0;

out_free_irq:
	if (arch_timer_use_virtual)
		free_percpu_irq(arch_timer_ppi[VIRT_PPI], arch_timer_evt);
	else {
		free_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI],
				arch_timer_evt);
		if (arch_timer_ppi[PHYS_NONSECURE_PPI])
			free_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI],
					arch_timer_evt);
	}

out_free:
	free_percpu(arch_timer_evt);
out:
	return err;
}

static void __init arch_timer_init(struct device_node *np)
{
	u32 freq;
	int i;

	if (arch_timer_get_rate()) {
		pr_warn("arch_timer: multiple nodes in dt, skipping\n");
		return;
	}

	/* Try to determine the frequency from the device tree or CNTFRQ */
	if (!of_property_read_u32(np, "clock-frequency", &freq))
		arch_timer_rate = freq;

	for (i = PHYS_SECURE_PPI; i < MAX_TIMER_PPI; i++)
		arch_timer_ppi[i] = irq_of_parse_and_map(np, i);

	of_node_put(np);

	/*
	 * If HYP mode is available, we know that the physical timer
	 * has been configured to be accessible from PL1. Use it, so
	 * that a guest can use the virtual timer instead.
	 *
	 * If no interrupt provided for virtual timer, we'll have to
	 * stick to the physical timer. It'd better be accessible...
	 */
	if (is_hyp_mode_available() || !arch_timer_ppi[VIRT_PPI]) {
		arch_timer_use_virtual = false;

		if (!arch_timer_ppi[PHYS_SECURE_PPI] ||
		    !arch_timer_ppi[PHYS_NONSECURE_PPI]) {
			pr_warn("arch_timer: No interrupt available, giving up\n");
			return;
		}
	}

	arch_timer_register();
	arch_timer_arch_init();
}
CLOCKSOURCE_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_init);
CLOCKSOURCE_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", arch_timer_init);
Commit	Line	Data
8a4da6e3 MR	1	/*
	2	* linux/drivers/clocksource/arm_arch_timer.c
	3	*
	4	* Copyright (C) 2011 ARM Ltd.
	5	* All Rights Reserved
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11	#include <linux/init.h>
	12	#include <linux/kernel.h>
	13	#include <linux/device.h>
	14	#include <linux/smp.h>
	15	#include <linux/cpu.h>
	16	#include <linux/clockchips.h>
	17	#include <linux/interrupt.h>
	18	#include <linux/of_irq.h>
	19	#include <linux/io.h>
	20
	21	#include <asm/arch_timer.h>
8266891e	22	#include <asm/virt.h>
8a4da6e3 MR	23
	24	#include <clocksource/arm_arch_timer.h>
	25
	26	static u32 arch_timer_rate;
	27
	28	enum ppi_nr {
	29	PHYS_SECURE_PPI,
	30	PHYS_NONSECURE_PPI,
	31	VIRT_PPI,
	32	HYP_PPI,
	33	MAX_TIMER_PPI
	34	};
	35
	36	static int arch_timer_ppi[MAX_TIMER_PPI];
	37
	38	static struct clock_event_device __percpu *arch_timer_evt;
	39
	40	static bool arch_timer_use_virtual = true;
	41
	42	/*
	43	* Architected system timer support.
	44	*/
	45
60faddf6 SB	46	static __always_inline
	47	void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val,
	48	struct clock_event_device *clk)
	49	{
	50	arch_timer_reg_write_cp15(access, reg, val);
	51	}
	52
	53	static __always_inline
	54	u32 arch_timer_reg_read(int access, enum arch_timer_reg reg,
	55	struct clock_event_device *clk)
	56	{
	57	return arch_timer_reg_read_cp15(access, reg);
	58	}
	59
e09f3cc0	60	static __always_inline irqreturn_t timer_handler(const int access,
8a4da6e3 MR	61	struct clock_event_device *evt)
	62	{
	63	unsigned long ctrl;
60faddf6	64	ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, evt);
8a4da6e3 MR	65	if (ctrl & ARCH_TIMER_CTRL_IT_STAT) {
8a4da6e3 MR	66	ctrl \|= ARCH_TIMER_CTRL_IT_MASK;
60faddf6	67	arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, evt);
8a4da6e3 MR	68	evt->event_handler(evt);
	69	return IRQ_HANDLED;
	70	}
	71
	72	return IRQ_NONE;
	73	}
	74
	75	static irqreturn_t arch_timer_handler_virt(int irq, void *dev_id)
	76	{
	77	struct clock_event_device *evt = dev_id;
	78
	79	return timer_handler(ARCH_TIMER_VIRT_ACCESS, evt);
	80	}
	81
	82	static irqreturn_t arch_timer_handler_phys(int irq, void *dev_id)
	83	{
	84	struct clock_event_device *evt = dev_id;
	85
	86	return timer_handler(ARCH_TIMER_PHYS_ACCESS, evt);
	87	}
	88
60faddf6 SB	89	static __always_inline void timer_set_mode(const int access, int mode,
60faddf6 SB	90	struct clock_event_device *clk)
8a4da6e3 MR	91	{
	92	unsigned long ctrl;
	93	switch (mode) {
	94	case CLOCK_EVT_MODE_UNUSED:
	95	case CLOCK_EVT_MODE_SHUTDOWN:
60faddf6	96	ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
8a4da6e3	97	ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
60faddf6	98	arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
8a4da6e3 MR	99	break;
	100	default:
	101	break;
	102	}
	103	}
	104
	105	static void arch_timer_set_mode_virt(enum clock_event_mode mode,
	106	struct clock_event_device *clk)
	107	{
60faddf6	108	timer_set_mode(ARCH_TIMER_VIRT_ACCESS, mode, clk);
8a4da6e3 MR	109	}
	110
	111	static void arch_timer_set_mode_phys(enum clock_event_mode mode,
	112	struct clock_event_device *clk)
	113	{
60faddf6	114	timer_set_mode(ARCH_TIMER_PHYS_ACCESS, mode, clk);
8a4da6e3 MR	115	}
8a4da6e3 MR	116
60faddf6 SB	117	static __always_inline void set_next_event(const int access, unsigned long evt,
60faddf6 SB	118	struct clock_event_device *clk)
8a4da6e3 MR	119	{
8a4da6e3 MR	120	unsigned long ctrl;
60faddf6	121	ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
8a4da6e3 MR	122	ctrl \|= ARCH_TIMER_CTRL_ENABLE;
8a4da6e3 MR	123	ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
60faddf6 SB	124	arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, evt, clk);
60faddf6 SB	125	arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
8a4da6e3 MR	126	}
	127
	128	static int arch_timer_set_next_event_virt(unsigned long evt,
60faddf6	129	struct clock_event_device *clk)
8a4da6e3	130	{
60faddf6	131	set_next_event(ARCH_TIMER_VIRT_ACCESS, evt, clk);
8a4da6e3 MR	132	return 0;
	133	}
	134
	135	static int arch_timer_set_next_event_phys(unsigned long evt,
60faddf6	136	struct clock_event_device *clk)
8a4da6e3	137	{
60faddf6	138	set_next_event(ARCH_TIMER_PHYS_ACCESS, evt, clk);
8a4da6e3 MR	139	return 0;
	140	}
	141
	142	static int __cpuinit arch_timer_setup(struct clock_event_device *clk)
	143	{
	144	clk->features = CLOCK_EVT_FEAT_ONESHOT \| CLOCK_EVT_FEAT_C3STOP;
	145	clk->name = "arch_sys_timer";
	146	clk->rating = 450;
	147	if (arch_timer_use_virtual) {
	148	clk->irq = arch_timer_ppi[VIRT_PPI];
	149	clk->set_mode = arch_timer_set_mode_virt;
	150	clk->set_next_event = arch_timer_set_next_event_virt;
	151	} else {
	152	clk->irq = arch_timer_ppi[PHYS_SECURE_PPI];
	153	clk->set_mode = arch_timer_set_mode_phys;
	154	clk->set_next_event = arch_timer_set_next_event_phys;
	155	}
	156
	157	clk->cpumask = cpumask_of(smp_processor_id());
	158
1ff99ea6	159	clk->set_mode(CLOCK_EVT_MODE_SHUTDOWN, clk);
8a4da6e3 MR	160
	161	clockevents_config_and_register(clk, arch_timer_rate,
	162	0xf, 0x7fffffff);
	163
	164	if (arch_timer_use_virtual)
	165	enable_percpu_irq(arch_timer_ppi[VIRT_PPI], 0);
	166	else {
	167	enable_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI], 0);
	168	if (arch_timer_ppi[PHYS_NONSECURE_PPI])
	169	enable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI], 0);
	170	}
	171
	172	arch_counter_set_user_access();
	173
	174	return 0;
	175	}
	176
	177	static int arch_timer_available(void)
	178	{
	179	u32 freq;
	180
	181	if (arch_timer_rate == 0) {
	182	freq = arch_timer_get_cntfrq();
	183
	184	/* Check the timer frequency. */
	185	if (freq == 0) {
	186	pr_warn("Architected timer frequency not available\n");
	187	return -EINVAL;
	188	}
	189
	190	arch_timer_rate = freq;
	191	}
	192
	193	pr_info_once("Architected local timer running at %lu.%02luMHz (%s).\n",
	194	(unsigned long)arch_timer_rate / 1000000,
	195	(unsigned long)(arch_timer_rate / 10000) % 100,
	196	arch_timer_use_virtual ? "virt" : "phys");
	197	return 0;
	198	}
	199
	200	u32 arch_timer_get_rate(void)
	201	{
	202	return arch_timer_rate;
	203	}
	204
0d651e4e	205	u64 arch_timer_read_counter(void)
8a4da6e3	206	{
0d651e4e	207	return arch_counter_get_cntvct();
8a4da6e3 MR	208	}
8a4da6e3 MR	209
8a4da6e3 MR	210	static cycle_t arch_counter_read(struct clocksource *cs)
8a4da6e3 MR	211	{
0d651e4e	212	return arch_counter_get_cntvct();
8a4da6e3 MR	213	}
	214
	215	static cycle_t arch_counter_read_cc(const struct cyclecounter *cc)
	216	{
0d651e4e	217	return arch_counter_get_cntvct();
8a4da6e3 MR	218	}
	219
	220	static struct clocksource clocksource_counter = {
	221	.name = "arch_sys_counter",
	222	.rating = 400,
	223	.read = arch_counter_read,
	224	.mask = CLOCKSOURCE_MASK(56),
	225	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	226	};
	227
	228	static struct cyclecounter cyclecounter = {
	229	.read = arch_counter_read_cc,
	230	.mask = CLOCKSOURCE_MASK(56),
	231	};
	232
	233	static struct timecounter timecounter;
	234
	235	struct timecounter *arch_timer_get_timecounter(void)
	236	{
	237	return &timecounter;
	238	}
	239
	240	static void __cpuinit arch_timer_stop(struct clock_event_device *clk)
	241	{
	242	pr_debug("arch_timer_teardown disable IRQ%d cpu #%d\n",
	243	clk->irq, smp_processor_id());
	244
	245	if (arch_timer_use_virtual)
	246	disable_percpu_irq(arch_timer_ppi[VIRT_PPI]);
	247	else {
	248	disable_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI]);
	249	if (arch_timer_ppi[PHYS_NONSECURE_PPI])
	250	disable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI]);
	251	}
	252
	253	clk->set_mode(CLOCK_EVT_MODE_UNUSED, clk);
	254	}
	255
	256	static int __cpuinit arch_timer_cpu_notify(struct notifier_block *self,
	257	unsigned long action, void *hcpu)
	258	{
f31c2f1c SB	259	/*
	260	* Grab cpu pointer in each case to avoid spurious
	261	* preemptible warnings
	262	*/
8a4da6e3 MR	263	switch (action & ~CPU_TASKS_FROZEN) {
8a4da6e3 MR	264	case CPU_STARTING:
f31c2f1c	265	arch_timer_setup(this_cpu_ptr(arch_timer_evt));
8a4da6e3 MR	266	break;
8a4da6e3 MR	267	case CPU_DYING:
f31c2f1c	268	arch_timer_stop(this_cpu_ptr(arch_timer_evt));
8a4da6e3 MR	269	break;
	270	}
	271
	272	return NOTIFY_OK;
	273	}
	274
	275	static struct notifier_block arch_timer_cpu_nb __cpuinitdata = {
	276	.notifier_call = arch_timer_cpu_notify,
	277	};
	278
	279	static int __init arch_timer_register(void)
	280	{
	281	int err;
	282	int ppi;
	283
	284	err = arch_timer_available();
	285	if (err)
	286	goto out;
	287
	288	arch_timer_evt = alloc_percpu(struct clock_event_device);
	289	if (!arch_timer_evt) {
	290	err = -ENOMEM;
	291	goto out;
	292	}
	293
	294	clocksource_register_hz(&clocksource_counter, arch_timer_rate);
	295	cyclecounter.mult = clocksource_counter.mult;
	296	cyclecounter.shift = clocksource_counter.shift;
	297	timecounter_init(&timecounter, &cyclecounter,
0d651e4e	298	arch_counter_get_cntvct());
8a4da6e3 MR	299
	300	if (arch_timer_use_virtual) {
	301	ppi = arch_timer_ppi[VIRT_PPI];
	302	err = request_percpu_irq(ppi, arch_timer_handler_virt,
	303	"arch_timer", arch_timer_evt);
	304	} else {
	305	ppi = arch_timer_ppi[PHYS_SECURE_PPI];
	306	err = request_percpu_irq(ppi, arch_timer_handler_phys,
	307	"arch_timer", arch_timer_evt);
	308	if (!err && arch_timer_ppi[PHYS_NONSECURE_PPI]) {
	309	ppi = arch_timer_ppi[PHYS_NONSECURE_PPI];
	310	err = request_percpu_irq(ppi, arch_timer_handler_phys,
	311	"arch_timer", arch_timer_evt);
	312	if (err)
	313	free_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI],
	314	arch_timer_evt);
	315	}
	316	}
	317
	318	if (err) {
	319	pr_err("arch_timer: can't register interrupt %d (%d)\n",
	320	ppi, err);
	321	goto out_free;
	322	}
	323
	324	err = register_cpu_notifier(&arch_timer_cpu_nb);
	325	if (err)
	326	goto out_free_irq;
	327
	328	/* Immediately configure the timer on the boot CPU */
	329	arch_timer_setup(this_cpu_ptr(arch_timer_evt));
	330
	331	return 0;
	332
	333	out_free_irq:
	334	if (arch_timer_use_virtual)
	335	free_percpu_irq(arch_timer_ppi[VIRT_PPI], arch_timer_evt);
	336	else {
	337	free_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI],
	338	arch_timer_evt);
	339	if (arch_timer_ppi[PHYS_NONSECURE_PPI])
	340	free_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI],
	341	arch_timer_evt);
	342	}
	343
	344	out_free:
	345	free_percpu(arch_timer_evt);
	346	out:
	347	return err;
	348	}
	349
0583fe47	350	static void __init arch_timer_init(struct device_node *np)
8a4da6e3	351	{
8a4da6e3 MR	352	u32 freq;
	353	int i;
	354
0583fe47 RH	355	if (arch_timer_get_rate()) {
	356	pr_warn("arch_timer: multiple nodes in dt, skipping\n");
	357	return;
8a4da6e3 MR	358	}
	359
	360	/* Try to determine the frequency from the device tree or CNTFRQ */
	361	if (!of_property_read_u32(np, "clock-frequency", &freq))
	362	arch_timer_rate = freq;
	363
	364	for (i = PHYS_SECURE_PPI; i < MAX_TIMER_PPI; i++)
	365	arch_timer_ppi[i] = irq_of_parse_and_map(np, i);
	366
	367	of_node_put(np);
	368
	369	/*
8266891e MZ	370	* If HYP mode is available, we know that the physical timer
	371	* has been configured to be accessible from PL1. Use it, so
	372	* that a guest can use the virtual timer instead.
	373	*
8a4da6e3 MR	374	* If no interrupt provided for virtual timer, we'll have to
	375	* stick to the physical timer. It'd better be accessible...
	376	*/
8266891e	377	if (is_hyp_mode_available() \|\| !arch_timer_ppi[VIRT_PPI]) {
8a4da6e3 MR	378	arch_timer_use_virtual = false;
	379
	380	if (!arch_timer_ppi[PHYS_SECURE_PPI] \|\|
	381	!arch_timer_ppi[PHYS_NONSECURE_PPI]) {
	382	pr_warn("arch_timer: No interrupt available, giving up\n");
0583fe47	383	return;
8a4da6e3 MR	384	}
	385	}
	386
0583fe47 RH	387	arch_timer_register();
0583fe47 RH	388	arch_timer_arch_init();
8a4da6e3	389	}
0583fe47 RH	390	CLOCKSOURCE_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_init);
0583fe47 RH	391	CLOCKSOURCE_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", arch_timer_init);