Commit | Line | Data |
---|---|---|
d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
d8005e6b | 2 | /* |
c4c9a040 | 3 | * Copyright (C) 2016-17 Synopsys, Inc. (www.synopsys.com) |
d8005e6b | 4 | * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) |
d8005e6b VG |
5 | */ |
6 | ||
c4c9a040 VG |
7 | /* ARC700 has two 32bit independent prog Timers: TIMER0 and TIMER1, Each can be |
8 | * programmed to go from @count to @limit and optionally interrupt. | |
9 | * We've designated TIMER0 for clockevents and TIMER1 for clocksource | |
d8005e6b | 10 | * |
c4c9a040 VG |
11 | * ARCv2 based HS38 cores have RTC (in-core) and GFRC (inside ARConnect/MCIP) |
12 | * which are suitable for UP and SMP based clocksources respectively | |
d8005e6b VG |
13 | */ |
14 | ||
d8005e6b | 15 | #include <linux/interrupt.h> |
93665ab0 | 16 | #include <linux/bits.h> |
69fbd098 NC |
17 | #include <linux/clk.h> |
18 | #include <linux/clk-provider.h> | |
d8005e6b VG |
19 | #include <linux/clocksource.h> |
20 | #include <linux/clockchips.h> | |
eec3c58e | 21 | #include <linux/cpu.h> |
77c8d0d6 VG |
22 | #include <linux/of.h> |
23 | #include <linux/of_irq.h> | |
bf287607 | 24 | #include <linux/sched_clock.h> |
d8005e6b | 25 | |
b26c2e38 | 26 | #include <soc/arc/timers.h> |
2d7f5c48 | 27 | #include <soc/arc/mcip.h> |
72d72880 | 28 | |
d8005e6b | 29 | |
77c8d0d6 VG |
30 | static unsigned long arc_timer_freq; |
31 | ||
32 | static int noinline arc_get_timer_clk(struct device_node *node) | |
33 | { | |
34 | struct clk *clk; | |
35 | int ret; | |
36 | ||
37 | clk = of_clk_get(node, 0); | |
38 | if (IS_ERR(clk)) { | |
ac9ce6d1 | 39 | pr_err("timer missing clk\n"); |
77c8d0d6 VG |
40 | return PTR_ERR(clk); |
41 | } | |
42 | ||
43 | ret = clk_prepare_enable(clk); | |
44 | if (ret) { | |
45 | pr_err("Couldn't enable parent clk\n"); | |
46 | return ret; | |
47 | } | |
48 | ||
49 | arc_timer_freq = clk_get_rate(clk); | |
50 | ||
51 | return 0; | |
52 | } | |
53 | ||
d8005e6b VG |
54 | /********** Clock Source Device *********/ |
55 | ||
04421420 | 56 | #ifdef CONFIG_ARC_TIMERS_64BIT |
72d72880 | 57 | |
a5a1d1c2 | 58 | static u64 arc_read_gfrc(struct clocksource *cs) |
72d72880 VG |
59 | { |
60 | unsigned long flags; | |
2cd690ea | 61 | u32 l, h; |
72d72880 | 62 | |
6bd9549d EP |
63 | /* |
64 | * From a programming model pov, there seems to be just one instance of | |
65 | * MCIP_CMD/MCIP_READBACK however micro-architecturally there's | |
66 | * an instance PER ARC CORE (not per cluster), and there are dedicated | |
67 | * hardware decode logic (per core) inside ARConnect to handle | |
68 | * simultaneous read/write accesses from cores via those two registers. | |
69 | * So several concurrent commands to ARConnect are OK if they are | |
70 | * trying to access two different sub-components (like GFRC, | |
71 | * inter-core interrupt, etc...). HW also supports simultaneously | |
72 | * accessing GFRC by multiple cores. | |
73 | * That's why it is safe to disable hard interrupts on the local CPU | |
74 | * before access to GFRC instead of taking global MCIP spinlock | |
75 | * defined in arch/arc/kernel/mcip.c | |
76 | */ | |
72d72880 VG |
77 | local_irq_save(flags); |
78 | ||
d584f0fb | 79 | __mcip_cmd(CMD_GFRC_READ_LO, 0); |
2cd690ea | 80 | l = read_aux_reg(ARC_REG_MCIP_READBACK); |
72d72880 | 81 | |
d584f0fb | 82 | __mcip_cmd(CMD_GFRC_READ_HI, 0); |
2cd690ea | 83 | h = read_aux_reg(ARC_REG_MCIP_READBACK); |
72d72880 VG |
84 | |
85 | local_irq_restore(flags); | |
86 | ||
a5a1d1c2 | 87 | return (((u64)h) << 32) | l; |
72d72880 VG |
88 | } |
89 | ||
bf287607 AB |
90 | static notrace u64 arc_gfrc_clock_read(void) |
91 | { | |
92 | return arc_read_gfrc(NULL); | |
93 | } | |
94 | ||
e608b53e | 95 | static struct clocksource arc_counter_gfrc = { |
d584f0fb | 96 | .name = "ARConnect GFRC", |
72d72880 | 97 | .rating = 400, |
e608b53e | 98 | .read = arc_read_gfrc, |
72d72880 VG |
99 | .mask = CLOCKSOURCE_MASK(64), |
100 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | |
101 | }; | |
102 | ||
43d75604 | 103 | static int __init arc_cs_setup_gfrc(struct device_node *node) |
e608b53e | 104 | { |
ec7cb87b | 105 | struct mcip_bcr mp; |
e608b53e VG |
106 | int ret; |
107 | ||
ec7cb87b VG |
108 | READ_BCR(ARC_REG_MCIP_BCR, mp); |
109 | if (!mp.gfrc) { | |
ac9ce6d1 | 110 | pr_warn("Global-64-bit-Ctr clocksource not detected\n"); |
43d75604 | 111 | return -ENXIO; |
ec7cb87b | 112 | } |
e608b53e VG |
113 | |
114 | ret = arc_get_timer_clk(node); | |
115 | if (ret) | |
43d75604 | 116 | return ret; |
e608b53e | 117 | |
bf287607 AB |
118 | sched_clock_register(arc_gfrc_clock_read, 64, arc_timer_freq); |
119 | ||
43d75604 | 120 | return clocksource_register_hz(&arc_counter_gfrc, arc_timer_freq); |
e608b53e | 121 | } |
17273395 | 122 | TIMER_OF_DECLARE(arc_gfrc, "snps,archs-timer-gfrc", arc_cs_setup_gfrc); |
e608b53e | 123 | |
aa93e8ef VG |
124 | #define AUX_RTC_CTRL 0x103 |
125 | #define AUX_RTC_LOW 0x104 | |
126 | #define AUX_RTC_HIGH 0x105 | |
127 | ||
a5a1d1c2 | 128 | static u64 arc_read_rtc(struct clocksource *cs) |
aa93e8ef VG |
129 | { |
130 | unsigned long status; | |
2cd690ea | 131 | u32 l, h; |
aa93e8ef | 132 | |
922cc171 VG |
133 | /* |
134 | * hardware has an internal state machine which tracks readout of | |
135 | * low/high and updates the CTRL.status if | |
136 | * - interrupt/exception taken between the two reads | |
137 | * - high increments after low has been read | |
138 | */ | |
139 | do { | |
2cd690ea VG |
140 | l = read_aux_reg(AUX_RTC_LOW); |
141 | h = read_aux_reg(AUX_RTC_HIGH); | |
922cc171 | 142 | status = read_aux_reg(AUX_RTC_CTRL); |
93665ab0 | 143 | } while (!(status & BIT(31))); |
aa93e8ef | 144 | |
a5a1d1c2 | 145 | return (((u64)h) << 32) | l; |
aa93e8ef VG |
146 | } |
147 | ||
bf287607 AB |
148 | static notrace u64 arc_rtc_clock_read(void) |
149 | { | |
150 | return arc_read_rtc(NULL); | |
151 | } | |
152 | ||
e608b53e | 153 | static struct clocksource arc_counter_rtc = { |
aa93e8ef VG |
154 | .name = "ARCv2 RTC", |
155 | .rating = 350, | |
e608b53e | 156 | .read = arc_read_rtc, |
aa93e8ef VG |
157 | .mask = CLOCKSOURCE_MASK(64), |
158 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | |
159 | }; | |
160 | ||
43d75604 | 161 | static int __init arc_cs_setup_rtc(struct device_node *node) |
d8005e6b | 162 | { |
ec7cb87b | 163 | struct bcr_timer timer; |
e608b53e VG |
164 | int ret; |
165 | ||
ec7cb87b VG |
166 | READ_BCR(ARC_REG_TIMERS_BCR, timer); |
167 | if (!timer.rtc) { | |
ac9ce6d1 | 168 | pr_warn("Local-64-bit-Ctr clocksource not detected\n"); |
43d75604 | 169 | return -ENXIO; |
ec7cb87b | 170 | } |
e608b53e VG |
171 | |
172 | /* Local to CPU hence not usable in SMP */ | |
ec7cb87b | 173 | if (IS_ENABLED(CONFIG_SMP)) { |
ac9ce6d1 | 174 | pr_warn("Local-64-bit-Ctr not usable in SMP\n"); |
43d75604 | 175 | return -EINVAL; |
ec7cb87b | 176 | } |
e608b53e VG |
177 | |
178 | ret = arc_get_timer_clk(node); | |
179 | if (ret) | |
43d75604 | 180 | return ret; |
d8005e6b | 181 | |
e608b53e VG |
182 | write_aux_reg(AUX_RTC_CTRL, 1); |
183 | ||
bf287607 AB |
184 | sched_clock_register(arc_rtc_clock_read, 64, arc_timer_freq); |
185 | ||
43d75604 | 186 | return clocksource_register_hz(&arc_counter_rtc, arc_timer_freq); |
d8005e6b | 187 | } |
17273395 | 188 | TIMER_OF_DECLARE(arc_rtc, "snps,archs-timer-rtc", arc_cs_setup_rtc); |
e608b53e VG |
189 | |
190 | #endif | |
d8005e6b | 191 | |
e608b53e VG |
192 | /* |
193 | * 32bit TIMER1 to keep counting monotonically and wraparound | |
194 | */ | |
195 | ||
a5a1d1c2 | 196 | static u64 arc_read_timer1(struct clocksource *cs) |
d8005e6b | 197 | { |
a5a1d1c2 | 198 | return (u64) read_aux_reg(ARC_REG_TIMER1_CNT); |
d8005e6b VG |
199 | } |
200 | ||
bf287607 AB |
201 | static notrace u64 arc_timer1_clock_read(void) |
202 | { | |
203 | return arc_read_timer1(NULL); | |
204 | } | |
205 | ||
e608b53e | 206 | static struct clocksource arc_counter_timer1 = { |
d8005e6b VG |
207 | .name = "ARC Timer1", |
208 | .rating = 300, | |
e608b53e | 209 | .read = arc_read_timer1, |
d8005e6b VG |
210 | .mask = CLOCKSOURCE_MASK(32), |
211 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | |
212 | }; | |
213 | ||
43d75604 | 214 | static int __init arc_cs_setup_timer1(struct device_node *node) |
e608b53e VG |
215 | { |
216 | int ret; | |
217 | ||
218 | /* Local to CPU hence not usable in SMP */ | |
219 | if (IS_ENABLED(CONFIG_SMP)) | |
43d75604 | 220 | return -EINVAL; |
e608b53e VG |
221 | |
222 | ret = arc_get_timer_clk(node); | |
223 | if (ret) | |
43d75604 | 224 | return ret; |
e608b53e | 225 | |
b26c2e38 | 226 | write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMERN_MAX); |
e608b53e VG |
227 | write_aux_reg(ARC_REG_TIMER1_CNT, 0); |
228 | write_aux_reg(ARC_REG_TIMER1_CTRL, TIMER_CTRL_NH); | |
229 | ||
bf287607 AB |
230 | sched_clock_register(arc_timer1_clock_read, 32, arc_timer_freq); |
231 | ||
43d75604 | 232 | return clocksource_register_hz(&arc_counter_timer1, arc_timer_freq); |
e608b53e | 233 | } |
aa93e8ef | 234 | |
d8005e6b VG |
235 | /********** Clock Event Device *********/ |
236 | ||
77c8d0d6 | 237 | static int arc_timer_irq; |
eec3c58e | 238 | |
d8005e6b | 239 | /* |
c9a98e18 | 240 | * Arm the timer to interrupt after @cycles |
d8005e6b VG |
241 | * The distinction for oneshot/periodic is done in arc_event_timer_ack() below |
242 | */ | |
c9a98e18 | 243 | static void arc_timer_event_setup(unsigned int cycles) |
d8005e6b | 244 | { |
c9a98e18 | 245 | write_aux_reg(ARC_REG_TIMER0_LIMIT, cycles); |
d8005e6b VG |
246 | write_aux_reg(ARC_REG_TIMER0_CNT, 0); /* start from 0 */ |
247 | ||
248 | write_aux_reg(ARC_REG_TIMER0_CTRL, TIMER_CTRL_IE | TIMER_CTRL_NH); | |
249 | } | |
250 | ||
d8005e6b VG |
251 | |
252 | static int arc_clkevent_set_next_event(unsigned long delta, | |
253 | struct clock_event_device *dev) | |
254 | { | |
255 | arc_timer_event_setup(delta); | |
256 | return 0; | |
257 | } | |
258 | ||
aeec6cda | 259 | static int arc_clkevent_set_periodic(struct clock_event_device *dev) |
d8005e6b | 260 | { |
aeec6cda VK |
261 | /* |
262 | * At X Hz, 1 sec = 1000ms -> X cycles; | |
263 | * 10ms -> X / 100 cycles | |
264 | */ | |
77c8d0d6 | 265 | arc_timer_event_setup(arc_timer_freq / HZ); |
aeec6cda | 266 | return 0; |
d8005e6b VG |
267 | } |
268 | ||
269 | static DEFINE_PER_CPU(struct clock_event_device, arc_clockevent_device) = { | |
aeec6cda VK |
270 | .name = "ARC Timer0", |
271 | .features = CLOCK_EVT_FEAT_ONESHOT | | |
272 | CLOCK_EVT_FEAT_PERIODIC, | |
273 | .rating = 300, | |
aeec6cda VK |
274 | .set_next_event = arc_clkevent_set_next_event, |
275 | .set_state_periodic = arc_clkevent_set_periodic, | |
d8005e6b VG |
276 | }; |
277 | ||
278 | static irqreturn_t timer_irq_handler(int irq, void *dev_id) | |
279 | { | |
f8b34c3f VG |
280 | /* |
281 | * Note that generic IRQ core could have passed @evt for @dev_id if | |
282 | * irq_set_chip_and_handler() asked for handle_percpu_devid_irq() | |
283 | */ | |
284 | struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device); | |
aeec6cda | 285 | int irq_reenable = clockevent_state_periodic(evt); |
f8b34c3f VG |
286 | |
287 | /* | |
a4f53857 VG |
288 | * 1. ACK the interrupt |
289 | * - For ARC700, any write to CTRL reg ACKs it, so just rewrite | |
290 | * Count when [N]ot [H]alted bit. | |
291 | * - For HS3x, it is a bit subtle. On taken count-down interrupt, | |
292 | * IP bit [3] is set, which needs to be cleared for ACK'ing. | |
293 | * The write below can only update the other two bits, hence | |
294 | * explicitly clears IP bit | |
295 | * 2. Re-arm interrupt if periodic by writing to IE bit [0] | |
f8b34c3f VG |
296 | */ |
297 | write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | TIMER_CTRL_NH); | |
298 | ||
299 | evt->event_handler(evt); | |
d8005e6b | 300 | |
d8005e6b VG |
301 | return IRQ_HANDLED; |
302 | } | |
303 | ||
ecd8081f AMG |
304 | |
305 | static int arc_timer_starting_cpu(unsigned int cpu) | |
eec3c58e NC |
306 | { |
307 | struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device); | |
308 | ||
309 | evt->cpumask = cpumask_of(smp_processor_id()); | |
310 | ||
b26c2e38 | 311 | clockevents_config_and_register(evt, arc_timer_freq, 0, ARC_TIMERN_MAX); |
ecd8081f AMG |
312 | enable_percpu_irq(arc_timer_irq, 0); |
313 | return 0; | |
eec3c58e NC |
314 | } |
315 | ||
ecd8081f AMG |
316 | static int arc_timer_dying_cpu(unsigned int cpu) |
317 | { | |
318 | disable_percpu_irq(arc_timer_irq); | |
319 | return 0; | |
320 | } | |
eec3c58e | 321 | |
d8005e6b | 322 | /* |
eec3c58e | 323 | * clockevent setup for boot CPU |
d8005e6b | 324 | */ |
43d75604 | 325 | static int __init arc_clockevent_setup(struct device_node *node) |
d8005e6b | 326 | { |
2d4899f6 | 327 | struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device); |
eec3c58e | 328 | int ret; |
d8005e6b | 329 | |
77c8d0d6 | 330 | arc_timer_irq = irq_of_parse_and_map(node, 0); |
43d75604 | 331 | if (arc_timer_irq <= 0) { |
ac9ce6d1 | 332 | pr_err("clockevent: missing irq\n"); |
43d75604 DL |
333 | return -EINVAL; |
334 | } | |
77c8d0d6 VG |
335 | |
336 | ret = arc_get_timer_clk(node); | |
311fb70a | 337 | if (ret) |
43d75604 | 338 | return ret; |
77c8d0d6 | 339 | |
eec3c58e NC |
340 | /* Needs apriori irq_set_percpu_devid() done in intc map function */ |
341 | ret = request_percpu_irq(arc_timer_irq, timer_irq_handler, | |
342 | "Timer0 (per-cpu-tick)", evt); | |
43d75604 DL |
343 | if (ret) { |
344 | pr_err("clockevent: unable to request irq\n"); | |
345 | return ret; | |
346 | } | |
56957940 | 347 | |
ecd8081f | 348 | ret = cpuhp_setup_state(CPUHP_AP_ARC_TIMER_STARTING, |
73c1b41e | 349 | "clockevents/arc/timer:starting", |
ecd8081f AMG |
350 | arc_timer_starting_cpu, |
351 | arc_timer_dying_cpu); | |
352 | if (ret) { | |
ac9ce6d1 | 353 | pr_err("Failed to setup hotplug state\n"); |
ecd8081f AMG |
354 | return ret; |
355 | } | |
43d75604 | 356 | return 0; |
d8005e6b | 357 | } |
e608b53e | 358 | |
43d75604 | 359 | static int __init arc_of_timer_init(struct device_node *np) |
e608b53e VG |
360 | { |
361 | static int init_count = 0; | |
43d75604 | 362 | int ret; |
e608b53e VG |
363 | |
364 | if (!init_count) { | |
365 | init_count = 1; | |
43d75604 | 366 | ret = arc_clockevent_setup(np); |
e608b53e | 367 | } else { |
43d75604 | 368 | ret = arc_cs_setup_timer1(np); |
e608b53e | 369 | } |
43d75604 DL |
370 | |
371 | return ret; | |
e608b53e | 372 | } |
17273395 | 373 | TIMER_OF_DECLARE(arc_clkevt, "snps,arc-timer", arc_of_timer_init); |