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0ee52b15 SB |
1 | /* |
2 | * Zynq clock controller | |
3 | * | |
4 | * Copyright (C) 2012 - 2013 Xilinx | |
5 | * | |
6 | * Sören Brinkmann <soren.brinkmann@xilinx.com> | |
7 | * | |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License v2 as published by | |
10 | * the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
21 | #include <linux/clk/zynq.h> | |
22 | #include <linux/clk-provider.h> | |
23 | #include <linux/of.h> | |
b0504e39 | 24 | #include <linux/of_address.h> |
0ee52b15 SB |
25 | #include <linux/slab.h> |
26 | #include <linux/string.h> | |
27 | #include <linux/io.h> | |
28 | ||
b0504e39 MS |
29 | static void __iomem *zynq_clkc_base; |
30 | ||
31 | #define SLCR_ARMPLL_CTRL (zynq_clkc_base + 0x00) | |
32 | #define SLCR_DDRPLL_CTRL (zynq_clkc_base + 0x04) | |
33 | #define SLCR_IOPLL_CTRL (zynq_clkc_base + 0x08) | |
34 | #define SLCR_PLL_STATUS (zynq_clkc_base + 0x0c) | |
35 | #define SLCR_ARM_CLK_CTRL (zynq_clkc_base + 0x20) | |
36 | #define SLCR_DDR_CLK_CTRL (zynq_clkc_base + 0x24) | |
37 | #define SLCR_DCI_CLK_CTRL (zynq_clkc_base + 0x28) | |
38 | #define SLCR_APER_CLK_CTRL (zynq_clkc_base + 0x2c) | |
39 | #define SLCR_GEM0_CLK_CTRL (zynq_clkc_base + 0x40) | |
40 | #define SLCR_GEM1_CLK_CTRL (zynq_clkc_base + 0x44) | |
41 | #define SLCR_SMC_CLK_CTRL (zynq_clkc_base + 0x48) | |
42 | #define SLCR_LQSPI_CLK_CTRL (zynq_clkc_base + 0x4c) | |
43 | #define SLCR_SDIO_CLK_CTRL (zynq_clkc_base + 0x50) | |
44 | #define SLCR_UART_CLK_CTRL (zynq_clkc_base + 0x54) | |
45 | #define SLCR_SPI_CLK_CTRL (zynq_clkc_base + 0x58) | |
46 | #define SLCR_CAN_CLK_CTRL (zynq_clkc_base + 0x5c) | |
47 | #define SLCR_CAN_MIOCLK_CTRL (zynq_clkc_base + 0x60) | |
48 | #define SLCR_DBG_CLK_CTRL (zynq_clkc_base + 0x64) | |
49 | #define SLCR_PCAP_CLK_CTRL (zynq_clkc_base + 0x68) | |
50 | #define SLCR_FPGA0_CLK_CTRL (zynq_clkc_base + 0x70) | |
51 | #define SLCR_621_TRUE (zynq_clkc_base + 0xc4) | |
52 | #define SLCR_SWDT_CLK_SEL (zynq_clkc_base + 0x204) | |
0ee52b15 SB |
53 | |
54 | #define NUM_MIO_PINS 54 | |
55 | ||
56 | enum zynq_clk { | |
57 | armpll, ddrpll, iopll, | |
58 | cpu_6or4x, cpu_3or2x, cpu_2x, cpu_1x, | |
59 | ddr2x, ddr3x, dci, | |
60 | lqspi, smc, pcap, gem0, gem1, fclk0, fclk1, fclk2, fclk3, can0, can1, | |
61 | sdio0, sdio1, uart0, uart1, spi0, spi1, dma, | |
62 | usb0_aper, usb1_aper, gem0_aper, gem1_aper, | |
63 | sdio0_aper, sdio1_aper, spi0_aper, spi1_aper, can0_aper, can1_aper, | |
64 | i2c0_aper, i2c1_aper, uart0_aper, uart1_aper, gpio_aper, lqspi_aper, | |
65 | smc_aper, swdt, dbg_trc, dbg_apb, clk_max}; | |
66 | ||
67 | static struct clk *ps_clk; | |
68 | static struct clk *clks[clk_max]; | |
69 | static struct clk_onecell_data clk_data; | |
70 | ||
71 | static DEFINE_SPINLOCK(armpll_lock); | |
72 | static DEFINE_SPINLOCK(ddrpll_lock); | |
73 | static DEFINE_SPINLOCK(iopll_lock); | |
74 | static DEFINE_SPINLOCK(armclk_lock); | |
252957cc | 75 | static DEFINE_SPINLOCK(swdtclk_lock); |
0ee52b15 SB |
76 | static DEFINE_SPINLOCK(ddrclk_lock); |
77 | static DEFINE_SPINLOCK(dciclk_lock); | |
78 | static DEFINE_SPINLOCK(gem0clk_lock); | |
79 | static DEFINE_SPINLOCK(gem1clk_lock); | |
80 | static DEFINE_SPINLOCK(canclk_lock); | |
81 | static DEFINE_SPINLOCK(canmioclk_lock); | |
82 | static DEFINE_SPINLOCK(dbgclk_lock); | |
83 | static DEFINE_SPINLOCK(aperclk_lock); | |
84 | ||
85 | static const char dummy_nm[] __initconst = "dummy_name"; | |
86 | ||
87 | static const char *armpll_parents[] __initdata = {"armpll_int", "ps_clk"}; | |
88 | static const char *ddrpll_parents[] __initdata = {"ddrpll_int", "ps_clk"}; | |
89 | static const char *iopll_parents[] __initdata = {"iopll_int", "ps_clk"}; | |
90 | static const char *gem0_mux_parents[] __initdata = {"gem0_div1", dummy_nm}; | |
91 | static const char *gem1_mux_parents[] __initdata = {"gem1_div1", dummy_nm}; | |
92 | static const char *can0_mio_mux2_parents[] __initdata = {"can0_gate", | |
93 | "can0_mio_mux"}; | |
94 | static const char *can1_mio_mux2_parents[] __initdata = {"can1_gate", | |
95 | "can1_mio_mux"}; | |
96 | static const char *dbg_emio_mux_parents[] __initdata = {"dbg_div", | |
97 | dummy_nm}; | |
98 | ||
99 | static const char *dbgtrc_emio_input_names[] __initdata = {"trace_emio_clk"}; | |
100 | static const char *gem0_emio_input_names[] __initdata = {"gem0_emio_clk"}; | |
101 | static const char *gem1_emio_input_names[] __initdata = {"gem1_emio_clk"}; | |
102 | static const char *swdt_ext_clk_input_names[] __initdata = {"swdt_ext_clk"}; | |
103 | ||
104 | static void __init zynq_clk_register_fclk(enum zynq_clk fclk, | |
105 | const char *clk_name, void __iomem *fclk_ctrl_reg, | |
ba52f8a9 | 106 | const char **parents, int enable) |
0ee52b15 SB |
107 | { |
108 | struct clk *clk; | |
ba52f8a9 | 109 | u32 enable_reg; |
0ee52b15 SB |
110 | char *mux_name; |
111 | char *div0_name; | |
112 | char *div1_name; | |
113 | spinlock_t *fclk_lock; | |
114 | spinlock_t *fclk_gate_lock; | |
115 | void __iomem *fclk_gate_reg = fclk_ctrl_reg + 8; | |
116 | ||
117 | fclk_lock = kmalloc(sizeof(*fclk_lock), GFP_KERNEL); | |
118 | if (!fclk_lock) | |
119 | goto err; | |
120 | fclk_gate_lock = kmalloc(sizeof(*fclk_gate_lock), GFP_KERNEL); | |
121 | if (!fclk_gate_lock) | |
f8fe36f6 | 122 | goto err_fclk_gate_lock; |
0ee52b15 SB |
123 | spin_lock_init(fclk_lock); |
124 | spin_lock_init(fclk_gate_lock); | |
125 | ||
126 | mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name); | |
f8fe36f6 FP |
127 | if (!mux_name) |
128 | goto err_mux_name; | |
0ee52b15 | 129 | div0_name = kasprintf(GFP_KERNEL, "%s_div0", clk_name); |
f8fe36f6 FP |
130 | if (!div0_name) |
131 | goto err_div0_name; | |
0ee52b15 | 132 | div1_name = kasprintf(GFP_KERNEL, "%s_div1", clk_name); |
f8fe36f6 FP |
133 | if (!div1_name) |
134 | goto err_div1_name; | |
0ee52b15 | 135 | |
819c1de3 JH |
136 | clk = clk_register_mux(NULL, mux_name, parents, 4, |
137 | CLK_SET_RATE_NO_REPARENT, fclk_ctrl_reg, 4, 2, 0, | |
138 | fclk_lock); | |
0ee52b15 SB |
139 | |
140 | clk = clk_register_divider(NULL, div0_name, mux_name, | |
141 | 0, fclk_ctrl_reg, 8, 6, CLK_DIVIDER_ONE_BASED | | |
142 | CLK_DIVIDER_ALLOW_ZERO, fclk_lock); | |
143 | ||
144 | clk = clk_register_divider(NULL, div1_name, div0_name, | |
145 | CLK_SET_RATE_PARENT, fclk_ctrl_reg, 20, 6, | |
146 | CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, | |
147 | fclk_lock); | |
148 | ||
149 | clks[fclk] = clk_register_gate(NULL, clk_name, | |
150 | div1_name, CLK_SET_RATE_PARENT, fclk_gate_reg, | |
151 | 0, CLK_GATE_SET_TO_DISABLE, fclk_gate_lock); | |
2c97ec58 | 152 | enable_reg = clk_readl(fclk_gate_reg) & 1; |
ba52f8a9 SB |
153 | if (enable && !enable_reg) { |
154 | if (clk_prepare_enable(clks[fclk])) | |
155 | pr_warn("%s: FCLK%u enable failed\n", __func__, | |
156 | fclk - fclk0); | |
157 | } | |
0ee52b15 SB |
158 | kfree(mux_name); |
159 | kfree(div0_name); | |
160 | kfree(div1_name); | |
161 | ||
162 | return; | |
163 | ||
f8fe36f6 FP |
164 | err_div1_name: |
165 | kfree(div0_name); | |
166 | err_div0_name: | |
167 | kfree(mux_name); | |
168 | err_mux_name: | |
169 | kfree(fclk_gate_lock); | |
170 | err_fclk_gate_lock: | |
171 | kfree(fclk_lock); | |
0ee52b15 SB |
172 | err: |
173 | clks[fclk] = ERR_PTR(-ENOMEM); | |
174 | } | |
175 | ||
176 | static void __init zynq_clk_register_periph_clk(enum zynq_clk clk0, | |
177 | enum zynq_clk clk1, const char *clk_name0, | |
178 | const char *clk_name1, void __iomem *clk_ctrl, | |
179 | const char **parents, unsigned int two_gates) | |
180 | { | |
181 | struct clk *clk; | |
182 | char *mux_name; | |
183 | char *div_name; | |
184 | spinlock_t *lock; | |
185 | ||
186 | lock = kmalloc(sizeof(*lock), GFP_KERNEL); | |
187 | if (!lock) | |
188 | goto err; | |
189 | spin_lock_init(lock); | |
190 | ||
191 | mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name0); | |
192 | div_name = kasprintf(GFP_KERNEL, "%s_div", clk_name0); | |
193 | ||
819c1de3 JH |
194 | clk = clk_register_mux(NULL, mux_name, parents, 4, |
195 | CLK_SET_RATE_NO_REPARENT, clk_ctrl, 4, 2, 0, lock); | |
0ee52b15 SB |
196 | |
197 | clk = clk_register_divider(NULL, div_name, mux_name, 0, clk_ctrl, 8, 6, | |
198 | CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, lock); | |
199 | ||
200 | clks[clk0] = clk_register_gate(NULL, clk_name0, div_name, | |
201 | CLK_SET_RATE_PARENT, clk_ctrl, 0, 0, lock); | |
202 | if (two_gates) | |
203 | clks[clk1] = clk_register_gate(NULL, clk_name1, div_name, | |
204 | CLK_SET_RATE_PARENT, clk_ctrl, 1, 0, lock); | |
205 | ||
206 | kfree(mux_name); | |
207 | kfree(div_name); | |
208 | ||
209 | return; | |
210 | ||
211 | err: | |
212 | clks[clk0] = ERR_PTR(-ENOMEM); | |
213 | if (two_gates) | |
214 | clks[clk1] = ERR_PTR(-ENOMEM); | |
215 | } | |
216 | ||
217 | static void __init zynq_clk_setup(struct device_node *np) | |
218 | { | |
219 | int i; | |
220 | u32 tmp; | |
221 | int ret; | |
222 | struct clk *clk; | |
223 | char *clk_name; | |
ba52f8a9 | 224 | unsigned int fclk_enable = 0; |
0ee52b15 SB |
225 | const char *clk_output_name[clk_max]; |
226 | const char *cpu_parents[4]; | |
227 | const char *periph_parents[4]; | |
228 | const char *swdt_ext_clk_mux_parents[2]; | |
229 | const char *can_mio_mux_parents[NUM_MIO_PINS]; | |
230 | ||
231 | pr_info("Zynq clock init\n"); | |
232 | ||
233 | /* get clock output names from DT */ | |
234 | for (i = 0; i < clk_max; i++) { | |
235 | if (of_property_read_string_index(np, "clock-output-names", | |
236 | i, &clk_output_name[i])) { | |
237 | pr_err("%s: clock output name not in DT\n", __func__); | |
238 | BUG(); | |
239 | } | |
240 | } | |
241 | cpu_parents[0] = clk_output_name[armpll]; | |
242 | cpu_parents[1] = clk_output_name[armpll]; | |
243 | cpu_parents[2] = clk_output_name[ddrpll]; | |
244 | cpu_parents[3] = clk_output_name[iopll]; | |
245 | periph_parents[0] = clk_output_name[iopll]; | |
246 | periph_parents[1] = clk_output_name[iopll]; | |
247 | periph_parents[2] = clk_output_name[armpll]; | |
248 | periph_parents[3] = clk_output_name[ddrpll]; | |
249 | ||
ba52f8a9 SB |
250 | of_property_read_u32(np, "fclk-enable", &fclk_enable); |
251 | ||
0ee52b15 SB |
252 | /* ps_clk */ |
253 | ret = of_property_read_u32(np, "ps-clk-frequency", &tmp); | |
254 | if (ret) { | |
255 | pr_warn("ps_clk frequency not specified, using 33 MHz.\n"); | |
256 | tmp = 33333333; | |
257 | } | |
258 | ps_clk = clk_register_fixed_rate(NULL, "ps_clk", NULL, CLK_IS_ROOT, | |
259 | tmp); | |
260 | ||
261 | /* PLLs */ | |
262 | clk = clk_register_zynq_pll("armpll_int", "ps_clk", SLCR_ARMPLL_CTRL, | |
263 | SLCR_PLL_STATUS, 0, &armpll_lock); | |
264 | clks[armpll] = clk_register_mux(NULL, clk_output_name[armpll], | |
819c1de3 JH |
265 | armpll_parents, 2, CLK_SET_RATE_NO_REPARENT, |
266 | SLCR_ARMPLL_CTRL, 4, 1, 0, &armpll_lock); | |
0ee52b15 SB |
267 | |
268 | clk = clk_register_zynq_pll("ddrpll_int", "ps_clk", SLCR_DDRPLL_CTRL, | |
269 | SLCR_PLL_STATUS, 1, &ddrpll_lock); | |
270 | clks[ddrpll] = clk_register_mux(NULL, clk_output_name[ddrpll], | |
819c1de3 JH |
271 | ddrpll_parents, 2, CLK_SET_RATE_NO_REPARENT, |
272 | SLCR_DDRPLL_CTRL, 4, 1, 0, &ddrpll_lock); | |
0ee52b15 SB |
273 | |
274 | clk = clk_register_zynq_pll("iopll_int", "ps_clk", SLCR_IOPLL_CTRL, | |
275 | SLCR_PLL_STATUS, 2, &iopll_lock); | |
276 | clks[iopll] = clk_register_mux(NULL, clk_output_name[iopll], | |
819c1de3 JH |
277 | iopll_parents, 2, CLK_SET_RATE_NO_REPARENT, |
278 | SLCR_IOPLL_CTRL, 4, 1, 0, &iopll_lock); | |
0ee52b15 SB |
279 | |
280 | /* CPU clocks */ | |
2c97ec58 | 281 | tmp = clk_readl(SLCR_621_TRUE) & 1; |
819c1de3 JH |
282 | clk = clk_register_mux(NULL, "cpu_mux", cpu_parents, 4, |
283 | CLK_SET_RATE_NO_REPARENT, SLCR_ARM_CLK_CTRL, 4, 2, 0, | |
284 | &armclk_lock); | |
0ee52b15 SB |
285 | clk = clk_register_divider(NULL, "cpu_div", "cpu_mux", 0, |
286 | SLCR_ARM_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | | |
287 | CLK_DIVIDER_ALLOW_ZERO, &armclk_lock); | |
288 | ||
289 | clks[cpu_6or4x] = clk_register_gate(NULL, clk_output_name[cpu_6or4x], | |
290 | "cpu_div", CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, | |
291 | SLCR_ARM_CLK_CTRL, 24, 0, &armclk_lock); | |
292 | ||
293 | clk = clk_register_fixed_factor(NULL, "cpu_3or2x_div", "cpu_div", 0, | |
294 | 1, 2); | |
295 | clks[cpu_3or2x] = clk_register_gate(NULL, clk_output_name[cpu_3or2x], | |
296 | "cpu_3or2x_div", CLK_IGNORE_UNUSED, | |
297 | SLCR_ARM_CLK_CTRL, 25, 0, &armclk_lock); | |
298 | ||
299 | clk = clk_register_fixed_factor(NULL, "cpu_2x_div", "cpu_div", 0, 1, | |
300 | 2 + tmp); | |
301 | clks[cpu_2x] = clk_register_gate(NULL, clk_output_name[cpu_2x], | |
302 | "cpu_2x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL, | |
303 | 26, 0, &armclk_lock); | |
304 | ||
305 | clk = clk_register_fixed_factor(NULL, "cpu_1x_div", "cpu_div", 0, 1, | |
306 | 4 + 2 * tmp); | |
307 | clks[cpu_1x] = clk_register_gate(NULL, clk_output_name[cpu_1x], | |
308 | "cpu_1x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL, 27, | |
309 | 0, &armclk_lock); | |
310 | ||
311 | /* Timers */ | |
312 | swdt_ext_clk_mux_parents[0] = clk_output_name[cpu_1x]; | |
313 | for (i = 0; i < ARRAY_SIZE(swdt_ext_clk_input_names); i++) { | |
314 | int idx = of_property_match_string(np, "clock-names", | |
315 | swdt_ext_clk_input_names[i]); | |
316 | if (idx >= 0) | |
317 | swdt_ext_clk_mux_parents[i + 1] = | |
318 | of_clk_get_parent_name(np, idx); | |
319 | else | |
320 | swdt_ext_clk_mux_parents[i + 1] = dummy_nm; | |
321 | } | |
322 | clks[swdt] = clk_register_mux(NULL, clk_output_name[swdt], | |
819c1de3 JH |
323 | swdt_ext_clk_mux_parents, 2, CLK_SET_RATE_PARENT | |
324 | CLK_SET_RATE_NO_REPARENT, SLCR_SWDT_CLK_SEL, 0, 1, 0, | |
bef4a0ab | 325 | &swdtclk_lock); |
0ee52b15 SB |
326 | |
327 | /* DDR clocks */ | |
328 | clk = clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0, | |
329 | SLCR_DDR_CLK_CTRL, 26, 6, CLK_DIVIDER_ONE_BASED | | |
330 | CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock); | |
331 | clks[ddr2x] = clk_register_gate(NULL, clk_output_name[ddr2x], | |
332 | "ddr2x_div", 0, SLCR_DDR_CLK_CTRL, 1, 0, &ddrclk_lock); | |
333 | clk_prepare_enable(clks[ddr2x]); | |
334 | clk = clk_register_divider(NULL, "ddr3x_div", "ddrpll", 0, | |
335 | SLCR_DDR_CLK_CTRL, 20, 6, CLK_DIVIDER_ONE_BASED | | |
336 | CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock); | |
337 | clks[ddr3x] = clk_register_gate(NULL, clk_output_name[ddr3x], | |
338 | "ddr3x_div", 0, SLCR_DDR_CLK_CTRL, 0, 0, &ddrclk_lock); | |
339 | clk_prepare_enable(clks[ddr3x]); | |
340 | ||
341 | clk = clk_register_divider(NULL, "dci_div0", "ddrpll", 0, | |
342 | SLCR_DCI_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | | |
343 | CLK_DIVIDER_ALLOW_ZERO, &dciclk_lock); | |
344 | clk = clk_register_divider(NULL, "dci_div1", "dci_div0", | |
345 | CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 20, 6, | |
346 | CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, | |
347 | &dciclk_lock); | |
348 | clks[dci] = clk_register_gate(NULL, clk_output_name[dci], "dci_div1", | |
349 | CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 0, 0, | |
350 | &dciclk_lock); | |
351 | clk_prepare_enable(clks[dci]); | |
352 | ||
353 | /* Peripheral clocks */ | |
ba52f8a9 SB |
354 | for (i = fclk0; i <= fclk3; i++) { |
355 | int enable = !!(fclk_enable & BIT(i - fclk0)); | |
0ee52b15 SB |
356 | zynq_clk_register_fclk(i, clk_output_name[i], |
357 | SLCR_FPGA0_CLK_CTRL + 0x10 * (i - fclk0), | |
ba52f8a9 SB |
358 | periph_parents, enable); |
359 | } | |
0ee52b15 SB |
360 | |
361 | zynq_clk_register_periph_clk(lqspi, 0, clk_output_name[lqspi], NULL, | |
362 | SLCR_LQSPI_CLK_CTRL, periph_parents, 0); | |
363 | ||
364 | zynq_clk_register_periph_clk(smc, 0, clk_output_name[smc], NULL, | |
365 | SLCR_SMC_CLK_CTRL, periph_parents, 0); | |
366 | ||
367 | zynq_clk_register_periph_clk(pcap, 0, clk_output_name[pcap], NULL, | |
368 | SLCR_PCAP_CLK_CTRL, periph_parents, 0); | |
369 | ||
370 | zynq_clk_register_periph_clk(sdio0, sdio1, clk_output_name[sdio0], | |
371 | clk_output_name[sdio1], SLCR_SDIO_CLK_CTRL, | |
372 | periph_parents, 1); | |
373 | ||
374 | zynq_clk_register_periph_clk(uart0, uart1, clk_output_name[uart0], | |
375 | clk_output_name[uart1], SLCR_UART_CLK_CTRL, | |
376 | periph_parents, 1); | |
377 | ||
378 | zynq_clk_register_periph_clk(spi0, spi1, clk_output_name[spi0], | |
379 | clk_output_name[spi1], SLCR_SPI_CLK_CTRL, | |
380 | periph_parents, 1); | |
381 | ||
382 | for (i = 0; i < ARRAY_SIZE(gem0_emio_input_names); i++) { | |
383 | int idx = of_property_match_string(np, "clock-names", | |
384 | gem0_emio_input_names[i]); | |
385 | if (idx >= 0) | |
386 | gem0_mux_parents[i + 1] = of_clk_get_parent_name(np, | |
387 | idx); | |
388 | } | |
819c1de3 JH |
389 | clk = clk_register_mux(NULL, "gem0_mux", periph_parents, 4, |
390 | CLK_SET_RATE_NO_REPARENT, SLCR_GEM0_CLK_CTRL, 4, 2, 0, | |
391 | &gem0clk_lock); | |
0ee52b15 SB |
392 | clk = clk_register_divider(NULL, "gem0_div0", "gem0_mux", 0, |
393 | SLCR_GEM0_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | | |
394 | CLK_DIVIDER_ALLOW_ZERO, &gem0clk_lock); | |
395 | clk = clk_register_divider(NULL, "gem0_div1", "gem0_div0", | |
396 | CLK_SET_RATE_PARENT, SLCR_GEM0_CLK_CTRL, 20, 6, | |
397 | CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, | |
398 | &gem0clk_lock); | |
765b7d4c | 399 | clk = clk_register_mux(NULL, "gem0_emio_mux", gem0_mux_parents, 2, |
bef4a0ab LT |
400 | CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, |
401 | SLCR_GEM0_CLK_CTRL, 6, 1, 0, | |
765b7d4c | 402 | &gem0clk_lock); |
0ee52b15 SB |
403 | clks[gem0] = clk_register_gate(NULL, clk_output_name[gem0], |
404 | "gem0_emio_mux", CLK_SET_RATE_PARENT, | |
405 | SLCR_GEM0_CLK_CTRL, 0, 0, &gem0clk_lock); | |
406 | ||
407 | for (i = 0; i < ARRAY_SIZE(gem1_emio_input_names); i++) { | |
408 | int idx = of_property_match_string(np, "clock-names", | |
409 | gem1_emio_input_names[i]); | |
410 | if (idx >= 0) | |
411 | gem1_mux_parents[i + 1] = of_clk_get_parent_name(np, | |
412 | idx); | |
413 | } | |
819c1de3 JH |
414 | clk = clk_register_mux(NULL, "gem1_mux", periph_parents, 4, |
415 | CLK_SET_RATE_NO_REPARENT, SLCR_GEM1_CLK_CTRL, 4, 2, 0, | |
416 | &gem1clk_lock); | |
0ee52b15 SB |
417 | clk = clk_register_divider(NULL, "gem1_div0", "gem1_mux", 0, |
418 | SLCR_GEM1_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | | |
419 | CLK_DIVIDER_ALLOW_ZERO, &gem1clk_lock); | |
420 | clk = clk_register_divider(NULL, "gem1_div1", "gem1_div0", | |
421 | CLK_SET_RATE_PARENT, SLCR_GEM1_CLK_CTRL, 20, 6, | |
422 | CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, | |
423 | &gem1clk_lock); | |
765b7d4c | 424 | clk = clk_register_mux(NULL, "gem1_emio_mux", gem1_mux_parents, 2, |
bef4a0ab LT |
425 | CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, |
426 | SLCR_GEM1_CLK_CTRL, 6, 1, 0, | |
765b7d4c | 427 | &gem1clk_lock); |
0ee52b15 SB |
428 | clks[gem1] = clk_register_gate(NULL, clk_output_name[gem1], |
429 | "gem1_emio_mux", CLK_SET_RATE_PARENT, | |
430 | SLCR_GEM1_CLK_CTRL, 0, 0, &gem1clk_lock); | |
431 | ||
432 | tmp = strlen("mio_clk_00x"); | |
433 | clk_name = kmalloc(tmp, GFP_KERNEL); | |
434 | for (i = 0; i < NUM_MIO_PINS; i++) { | |
435 | int idx; | |
436 | ||
437 | snprintf(clk_name, tmp, "mio_clk_%2.2d", i); | |
438 | idx = of_property_match_string(np, "clock-names", clk_name); | |
439 | if (idx >= 0) | |
440 | can_mio_mux_parents[i] = of_clk_get_parent_name(np, | |
441 | idx); | |
442 | else | |
443 | can_mio_mux_parents[i] = dummy_nm; | |
444 | } | |
445 | kfree(clk_name); | |
819c1de3 JH |
446 | clk = clk_register_mux(NULL, "can_mux", periph_parents, 4, |
447 | CLK_SET_RATE_NO_REPARENT, SLCR_CAN_CLK_CTRL, 4, 2, 0, | |
448 | &canclk_lock); | |
0ee52b15 SB |
449 | clk = clk_register_divider(NULL, "can_div0", "can_mux", 0, |
450 | SLCR_CAN_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | | |
451 | CLK_DIVIDER_ALLOW_ZERO, &canclk_lock); | |
452 | clk = clk_register_divider(NULL, "can_div1", "can_div0", | |
453 | CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 20, 6, | |
454 | CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, | |
455 | &canclk_lock); | |
456 | clk = clk_register_gate(NULL, "can0_gate", "can_div1", | |
457 | CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 0, 0, | |
458 | &canclk_lock); | |
459 | clk = clk_register_gate(NULL, "can1_gate", "can_div1", | |
460 | CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 1, 0, | |
461 | &canclk_lock); | |
462 | clk = clk_register_mux(NULL, "can0_mio_mux", | |
819c1de3 JH |
463 | can_mio_mux_parents, 54, CLK_SET_RATE_PARENT | |
464 | CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 0, 6, 0, | |
465 | &canmioclk_lock); | |
0ee52b15 | 466 | clk = clk_register_mux(NULL, "can1_mio_mux", |
819c1de3 JH |
467 | can_mio_mux_parents, 54, CLK_SET_RATE_PARENT | |
468 | CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 16, 6, | |
469 | 0, &canmioclk_lock); | |
0ee52b15 | 470 | clks[can0] = clk_register_mux(NULL, clk_output_name[can0], |
819c1de3 JH |
471 | can0_mio_mux2_parents, 2, CLK_SET_RATE_PARENT | |
472 | CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 6, 1, 0, | |
473 | &canmioclk_lock); | |
0ee52b15 | 474 | clks[can1] = clk_register_mux(NULL, clk_output_name[can1], |
819c1de3 JH |
475 | can1_mio_mux2_parents, 2, CLK_SET_RATE_PARENT | |
476 | CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 22, 1, | |
477 | 0, &canmioclk_lock); | |
0ee52b15 SB |
478 | |
479 | for (i = 0; i < ARRAY_SIZE(dbgtrc_emio_input_names); i++) { | |
480 | int idx = of_property_match_string(np, "clock-names", | |
481 | dbgtrc_emio_input_names[i]); | |
482 | if (idx >= 0) | |
483 | dbg_emio_mux_parents[i + 1] = of_clk_get_parent_name(np, | |
484 | idx); | |
485 | } | |
819c1de3 JH |
486 | clk = clk_register_mux(NULL, "dbg_mux", periph_parents, 4, |
487 | CLK_SET_RATE_NO_REPARENT, SLCR_DBG_CLK_CTRL, 4, 2, 0, | |
488 | &dbgclk_lock); | |
0ee52b15 SB |
489 | clk = clk_register_divider(NULL, "dbg_div", "dbg_mux", 0, |
490 | SLCR_DBG_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | | |
491 | CLK_DIVIDER_ALLOW_ZERO, &dbgclk_lock); | |
819c1de3 JH |
492 | clk = clk_register_mux(NULL, "dbg_emio_mux", dbg_emio_mux_parents, 2, |
493 | CLK_SET_RATE_NO_REPARENT, SLCR_DBG_CLK_CTRL, 6, 1, 0, | |
494 | &dbgclk_lock); | |
0ee52b15 SB |
495 | clks[dbg_trc] = clk_register_gate(NULL, clk_output_name[dbg_trc], |
496 | "dbg_emio_mux", CLK_SET_RATE_PARENT, SLCR_DBG_CLK_CTRL, | |
497 | 0, 0, &dbgclk_lock); | |
498 | clks[dbg_apb] = clk_register_gate(NULL, clk_output_name[dbg_apb], | |
499 | clk_output_name[cpu_1x], 0, SLCR_DBG_CLK_CTRL, 1, 0, | |
500 | &dbgclk_lock); | |
501 | ||
502 | /* One gated clock for all APER clocks. */ | |
503 | clks[dma] = clk_register_gate(NULL, clk_output_name[dma], | |
504 | clk_output_name[cpu_2x], 0, SLCR_APER_CLK_CTRL, 0, 0, | |
505 | &aperclk_lock); | |
506 | clks[usb0_aper] = clk_register_gate(NULL, clk_output_name[usb0_aper], | |
507 | clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 2, 0, | |
508 | &aperclk_lock); | |
509 | clks[usb1_aper] = clk_register_gate(NULL, clk_output_name[usb1_aper], | |
510 | clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 3, 0, | |
511 | &aperclk_lock); | |
512 | clks[gem0_aper] = clk_register_gate(NULL, clk_output_name[gem0_aper], | |
513 | clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 6, 0, | |
514 | &aperclk_lock); | |
515 | clks[gem1_aper] = clk_register_gate(NULL, clk_output_name[gem1_aper], | |
516 | clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 7, 0, | |
517 | &aperclk_lock); | |
518 | clks[sdio0_aper] = clk_register_gate(NULL, clk_output_name[sdio0_aper], | |
519 | clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 10, 0, | |
520 | &aperclk_lock); | |
521 | clks[sdio1_aper] = clk_register_gate(NULL, clk_output_name[sdio1_aper], | |
522 | clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 11, 0, | |
523 | &aperclk_lock); | |
524 | clks[spi0_aper] = clk_register_gate(NULL, clk_output_name[spi0_aper], | |
525 | clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 14, 0, | |
526 | &aperclk_lock); | |
527 | clks[spi1_aper] = clk_register_gate(NULL, clk_output_name[spi1_aper], | |
528 | clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 15, 0, | |
529 | &aperclk_lock); | |
530 | clks[can0_aper] = clk_register_gate(NULL, clk_output_name[can0_aper], | |
531 | clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 16, 0, | |
532 | &aperclk_lock); | |
533 | clks[can1_aper] = clk_register_gate(NULL, clk_output_name[can1_aper], | |
534 | clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 17, 0, | |
535 | &aperclk_lock); | |
536 | clks[i2c0_aper] = clk_register_gate(NULL, clk_output_name[i2c0_aper], | |
537 | clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 18, 0, | |
538 | &aperclk_lock); | |
539 | clks[i2c1_aper] = clk_register_gate(NULL, clk_output_name[i2c1_aper], | |
540 | clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 19, 0, | |
541 | &aperclk_lock); | |
542 | clks[uart0_aper] = clk_register_gate(NULL, clk_output_name[uart0_aper], | |
543 | clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 20, 0, | |
544 | &aperclk_lock); | |
545 | clks[uart1_aper] = clk_register_gate(NULL, clk_output_name[uart1_aper], | |
546 | clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 21, 0, | |
547 | &aperclk_lock); | |
548 | clks[gpio_aper] = clk_register_gate(NULL, clk_output_name[gpio_aper], | |
549 | clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 22, 0, | |
550 | &aperclk_lock); | |
551 | clks[lqspi_aper] = clk_register_gate(NULL, clk_output_name[lqspi_aper], | |
552 | clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 23, 0, | |
553 | &aperclk_lock); | |
554 | clks[smc_aper] = clk_register_gate(NULL, clk_output_name[smc_aper], | |
555 | clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 24, 0, | |
556 | &aperclk_lock); | |
557 | ||
558 | for (i = 0; i < ARRAY_SIZE(clks); i++) { | |
559 | if (IS_ERR(clks[i])) { | |
560 | pr_err("Zynq clk %d: register failed with %ld\n", | |
561 | i, PTR_ERR(clks[i])); | |
562 | BUG(); | |
563 | } | |
564 | } | |
565 | ||
566 | clk_data.clks = clks; | |
567 | clk_data.clk_num = ARRAY_SIZE(clks); | |
568 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); | |
569 | } | |
570 | ||
571 | CLK_OF_DECLARE(zynq_clkc, "xlnx,ps7-clkc", zynq_clk_setup); | |
572 | ||
b0504e39 | 573 | void __init zynq_clock_init(void) |
0ee52b15 | 574 | { |
b0504e39 MS |
575 | struct device_node *np; |
576 | struct device_node *slcr; | |
577 | struct resource res; | |
578 | ||
579 | np = of_find_compatible_node(NULL, NULL, "xlnx,ps7-clkc"); | |
580 | if (!np) { | |
581 | pr_err("%s: clkc node not found\n", __func__); | |
582 | goto np_err; | |
583 | } | |
584 | ||
585 | if (of_address_to_resource(np, 0, &res)) { | |
586 | pr_err("%s: failed to get resource\n", np->name); | |
587 | goto np_err; | |
588 | } | |
589 | ||
590 | slcr = of_get_parent(np); | |
591 | ||
592 | if (slcr->data) { | |
593 | zynq_clkc_base = (__force void __iomem *)slcr->data + res.start; | |
594 | } else { | |
595 | pr_err("%s: Unable to get I/O memory\n", np->name); | |
596 | of_node_put(slcr); | |
597 | goto np_err; | |
598 | } | |
599 | ||
600 | pr_info("%s: clkc starts at %p\n", __func__, zynq_clkc_base); | |
601 | ||
602 | of_node_put(slcr); | |
603 | of_node_put(np); | |
604 | ||
b0504e39 MS |
605 | return; |
606 | ||
607 | np_err: | |
608 | of_node_put(np); | |
609 | BUG(); | |
610 | return; | |
0ee52b15 | 611 | } |