Commit | Line | Data |
---|---|---|
bce5afd8 UH |
1 | /* |
2 | * Clock definitions for u8540 platform. | |
3 | * | |
4 | * Copyright (C) 2012 ST-Ericsson SA | |
5 | * Author: Ulf Hansson <ulf.hansson@linaro.org> | |
6 | * | |
7 | * License terms: GNU General Public License (GPL) version 2 | |
8 | */ | |
9 | ||
5dc0fe19 LW |
10 | #include <linux/of.h> |
11 | #include <linux/of_address.h> | |
bce5afd8 UH |
12 | #include <linux/clkdev.h> |
13 | #include <linux/clk-provider.h> | |
14 | #include <linux/mfd/dbx500-prcmu.h> | |
15 | #include <linux/platform_data/clk-ux500.h> | |
bce5afd8 UH |
16 | #include "clk.h" |
17 | ||
5dc0fe19 LW |
18 | static const struct of_device_id u8540_clk_of_match[] = { |
19 | { .compatible = "stericsson,u8540-clks", }, | |
20 | { } | |
21 | }; | |
22 | ||
23 | /* CLKRST4 is missing making it hard to index things */ | |
24 | enum clkrst_index { | |
25 | CLKRST1_INDEX = 0, | |
26 | CLKRST2_INDEX, | |
27 | CLKRST3_INDEX, | |
28 | CLKRST5_INDEX, | |
29 | CLKRST6_INDEX, | |
30 | CLKRST_MAX, | |
31 | }; | |
32 | ||
33 | void u8540_clk_init(void) | |
bce5afd8 | 34 | { |
a6a3ec7b | 35 | struct clk *clk; |
5dc0fe19 LW |
36 | struct device_node *np = NULL; |
37 | u32 bases[CLKRST_MAX]; | |
38 | int i; | |
39 | ||
40 | if (of_have_populated_dt()) | |
41 | np = of_find_matching_node(NULL, u8540_clk_of_match); | |
42 | if (!np) { | |
43 | pr_err("Either DT or U8540 Clock node not found\n"); | |
44 | return; | |
45 | } | |
46 | for (i = 0; i < ARRAY_SIZE(bases); i++) { | |
47 | struct resource r; | |
48 | ||
49 | if (of_address_to_resource(np, i, &r)) | |
50 | /* Not much choice but to continue */ | |
51 | pr_err("failed to get CLKRST %d base address\n", | |
52 | i + 1); | |
53 | bases[i] = r.start; | |
54 | } | |
a6a3ec7b PB |
55 | |
56 | /* Clock sources. */ | |
57 | /* Fixed ClockGen */ | |
58 | clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0, | |
59 | CLK_IS_ROOT|CLK_IGNORE_UNUSED); | |
60 | clk_register_clkdev(clk, "soc0_pll", NULL); | |
61 | ||
62 | clk = clk_reg_prcmu_gate("soc1_pll", NULL, PRCMU_PLLSOC1, | |
63 | CLK_IS_ROOT|CLK_IGNORE_UNUSED); | |
64 | clk_register_clkdev(clk, "soc1_pll", NULL); | |
65 | ||
66 | clk = clk_reg_prcmu_gate("ddr_pll", NULL, PRCMU_PLLDDR, | |
67 | CLK_IS_ROOT|CLK_IGNORE_UNUSED); | |
68 | clk_register_clkdev(clk, "ddr_pll", NULL); | |
69 | ||
70 | clk = clk_register_fixed_rate(NULL, "rtc32k", NULL, | |
71 | CLK_IS_ROOT|CLK_IGNORE_UNUSED, | |
72 | 32768); | |
73 | clk_register_clkdev(clk, "clk32k", NULL); | |
74 | clk_register_clkdev(clk, "apb_pclk", "rtc-pl031"); | |
75 | ||
76 | clk = clk_register_fixed_rate(NULL, "ulp38m4", NULL, | |
77 | CLK_IS_ROOT|CLK_IGNORE_UNUSED, | |
78 | 38400000); | |
79 | ||
80 | clk = clk_reg_prcmu_gate("uartclk", NULL, PRCMU_UARTCLK, CLK_IS_ROOT); | |
81 | clk_register_clkdev(clk, NULL, "UART"); | |
82 | ||
83 | /* msp02clk needs a abx500 clk as parent. Handle by abx500 clk driver */ | |
84 | clk = clk_reg_prcmu_gate("msp02clk", "ab9540_sysclk12_b1", | |
85 | PRCMU_MSP02CLK, 0); | |
86 | clk_register_clkdev(clk, NULL, "MSP02"); | |
87 | ||
88 | clk = clk_reg_prcmu_gate("msp1clk", NULL, PRCMU_MSP1CLK, CLK_IS_ROOT); | |
89 | clk_register_clkdev(clk, NULL, "MSP1"); | |
90 | ||
91 | clk = clk_reg_prcmu_gate("i2cclk", NULL, PRCMU_I2CCLK, CLK_IS_ROOT); | |
92 | clk_register_clkdev(clk, NULL, "I2C"); | |
93 | ||
94 | clk = clk_reg_prcmu_gate("slimclk", NULL, PRCMU_SLIMCLK, CLK_IS_ROOT); | |
95 | clk_register_clkdev(clk, NULL, "slim"); | |
96 | ||
97 | clk = clk_reg_prcmu_gate("per1clk", NULL, PRCMU_PER1CLK, CLK_IS_ROOT); | |
98 | clk_register_clkdev(clk, NULL, "PERIPH1"); | |
99 | ||
100 | clk = clk_reg_prcmu_gate("per2clk", NULL, PRCMU_PER2CLK, CLK_IS_ROOT); | |
101 | clk_register_clkdev(clk, NULL, "PERIPH2"); | |
102 | ||
103 | clk = clk_reg_prcmu_gate("per3clk", NULL, PRCMU_PER3CLK, CLK_IS_ROOT); | |
104 | clk_register_clkdev(clk, NULL, "PERIPH3"); | |
105 | ||
106 | clk = clk_reg_prcmu_gate("per5clk", NULL, PRCMU_PER5CLK, CLK_IS_ROOT); | |
107 | clk_register_clkdev(clk, NULL, "PERIPH5"); | |
108 | ||
109 | clk = clk_reg_prcmu_gate("per6clk", NULL, PRCMU_PER6CLK, CLK_IS_ROOT); | |
110 | clk_register_clkdev(clk, NULL, "PERIPH6"); | |
111 | ||
112 | clk = clk_reg_prcmu_gate("per7clk", NULL, PRCMU_PER7CLK, CLK_IS_ROOT); | |
113 | clk_register_clkdev(clk, NULL, "PERIPH7"); | |
114 | ||
115 | clk = clk_reg_prcmu_scalable("lcdclk", NULL, PRCMU_LCDCLK, 0, | |
116 | CLK_IS_ROOT|CLK_SET_RATE_GATE); | |
117 | clk_register_clkdev(clk, NULL, "lcd"); | |
118 | clk_register_clkdev(clk, "lcd", "mcde"); | |
119 | ||
0473b177 | 120 | clk = clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BMLCLK, |
a6a3ec7b PB |
121 | CLK_IS_ROOT); |
122 | clk_register_clkdev(clk, NULL, "bml"); | |
123 | ||
124 | clk = clk_reg_prcmu_scalable("hsitxclk", NULL, PRCMU_HSITXCLK, 0, | |
125 | CLK_IS_ROOT|CLK_SET_RATE_GATE); | |
126 | ||
127 | clk = clk_reg_prcmu_scalable("hsirxclk", NULL, PRCMU_HSIRXCLK, 0, | |
128 | CLK_IS_ROOT|CLK_SET_RATE_GATE); | |
129 | ||
130 | clk = clk_reg_prcmu_scalable("hdmiclk", NULL, PRCMU_HDMICLK, 0, | |
131 | CLK_IS_ROOT|CLK_SET_RATE_GATE); | |
132 | clk_register_clkdev(clk, NULL, "hdmi"); | |
133 | clk_register_clkdev(clk, "hdmi", "mcde"); | |
134 | ||
135 | clk = clk_reg_prcmu_gate("apeatclk", NULL, PRCMU_APEATCLK, CLK_IS_ROOT); | |
136 | clk_register_clkdev(clk, NULL, "apeat"); | |
137 | ||
138 | clk = clk_reg_prcmu_gate("apetraceclk", NULL, PRCMU_APETRACECLK, | |
139 | CLK_IS_ROOT); | |
140 | clk_register_clkdev(clk, NULL, "apetrace"); | |
141 | ||
142 | clk = clk_reg_prcmu_gate("mcdeclk", NULL, PRCMU_MCDECLK, CLK_IS_ROOT); | |
143 | clk_register_clkdev(clk, NULL, "mcde"); | |
144 | clk_register_clkdev(clk, "mcde", "mcde"); | |
145 | clk_register_clkdev(clk, NULL, "dsilink.0"); | |
146 | clk_register_clkdev(clk, NULL, "dsilink.1"); | |
147 | clk_register_clkdev(clk, NULL, "dsilink.2"); | |
148 | ||
149 | clk = clk_reg_prcmu_opp_gate("ipi2cclk", NULL, PRCMU_IPI2CCLK, | |
150 | CLK_IS_ROOT); | |
151 | clk_register_clkdev(clk, NULL, "ipi2"); | |
152 | ||
153 | clk = clk_reg_prcmu_gate("dsialtclk", NULL, PRCMU_DSIALTCLK, | |
154 | CLK_IS_ROOT); | |
155 | clk_register_clkdev(clk, NULL, "dsialt"); | |
156 | ||
157 | clk = clk_reg_prcmu_gate("dmaclk", NULL, PRCMU_DMACLK, CLK_IS_ROOT); | |
158 | clk_register_clkdev(clk, NULL, "dma40.0"); | |
159 | ||
160 | clk = clk_reg_prcmu_gate("b2r2clk", NULL, PRCMU_B2R2CLK, CLK_IS_ROOT); | |
161 | clk_register_clkdev(clk, NULL, "b2r2"); | |
162 | clk_register_clkdev(clk, NULL, "b2r2_core"); | |
163 | clk_register_clkdev(clk, NULL, "U8500-B2R2.0"); | |
164 | clk_register_clkdev(clk, NULL, "b2r2_1_core"); | |
165 | ||
166 | clk = clk_reg_prcmu_scalable("tvclk", NULL, PRCMU_TVCLK, 0, | |
167 | CLK_IS_ROOT|CLK_SET_RATE_GATE); | |
168 | clk_register_clkdev(clk, NULL, "tv"); | |
169 | clk_register_clkdev(clk, "tv", "mcde"); | |
170 | ||
171 | clk = clk_reg_prcmu_gate("sspclk", NULL, PRCMU_SSPCLK, CLK_IS_ROOT); | |
172 | clk_register_clkdev(clk, NULL, "SSP"); | |
173 | ||
174 | clk = clk_reg_prcmu_gate("rngclk", NULL, PRCMU_RNGCLK, CLK_IS_ROOT); | |
175 | clk_register_clkdev(clk, NULL, "rngclk"); | |
176 | ||
177 | clk = clk_reg_prcmu_gate("uiccclk", NULL, PRCMU_UICCCLK, CLK_IS_ROOT); | |
178 | clk_register_clkdev(clk, NULL, "uicc"); | |
179 | ||
180 | clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, CLK_IS_ROOT); | |
181 | clk_register_clkdev(clk, NULL, "mtu0"); | |
182 | clk_register_clkdev(clk, NULL, "mtu1"); | |
183 | ||
184 | clk = clk_reg_prcmu_opp_volt_scalable("sdmmcclk", NULL, | |
185 | PRCMU_SDMMCCLK, 100000000, | |
186 | CLK_IS_ROOT|CLK_SET_RATE_GATE); | |
187 | clk_register_clkdev(clk, NULL, "sdmmc"); | |
188 | ||
189 | clk = clk_reg_prcmu_opp_volt_scalable("sdmmchclk", NULL, | |
190 | PRCMU_SDMMCHCLK, 400000000, | |
191 | CLK_IS_ROOT|CLK_SET_RATE_GATE); | |
192 | clk_register_clkdev(clk, NULL, "sdmmchclk"); | |
193 | ||
194 | clk = clk_reg_prcmu_gate("hvaclk", NULL, PRCMU_HVACLK, CLK_IS_ROOT); | |
195 | clk_register_clkdev(clk, NULL, "hva"); | |
196 | ||
197 | clk = clk_reg_prcmu_gate("g1clk", NULL, PRCMU_G1CLK, CLK_IS_ROOT); | |
198 | clk_register_clkdev(clk, NULL, "g1"); | |
199 | ||
200 | clk = clk_reg_prcmu_scalable("spare1clk", NULL, PRCMU_SPARE1CLK, 0, | |
201 | CLK_IS_ROOT|CLK_SET_RATE_GATE); | |
202 | clk_register_clkdev(clk, "dsilcd", "mcde"); | |
203 | ||
204 | clk = clk_reg_prcmu_scalable("dsi_pll", "hdmiclk", | |
205 | PRCMU_PLLDSI, 0, CLK_SET_RATE_GATE); | |
206 | clk_register_clkdev(clk, "dsihs2", "mcde"); | |
207 | clk_register_clkdev(clk, "hs_clk", "dsilink.2"); | |
208 | ||
209 | clk = clk_reg_prcmu_scalable("dsilcd_pll", "spare1clk", | |
210 | PRCMU_PLLDSI_LCD, 0, CLK_SET_RATE_GATE); | |
211 | clk_register_clkdev(clk, "dsilcd_pll", "mcde"); | |
212 | ||
213 | clk = clk_reg_prcmu_scalable("dsi0clk", "dsi_pll", | |
214 | PRCMU_DSI0CLK, 0, CLK_SET_RATE_GATE); | |
215 | clk_register_clkdev(clk, "dsihs0", "mcde"); | |
216 | ||
217 | clk = clk_reg_prcmu_scalable("dsi0lcdclk", "dsilcd_pll", | |
218 | PRCMU_DSI0CLK_LCD, 0, CLK_SET_RATE_GATE); | |
219 | clk_register_clkdev(clk, "dsihs0", "mcde"); | |
220 | clk_register_clkdev(clk, "hs_clk", "dsilink.0"); | |
221 | ||
222 | clk = clk_reg_prcmu_scalable("dsi1clk", "dsi_pll", | |
223 | PRCMU_DSI1CLK, 0, CLK_SET_RATE_GATE); | |
224 | clk_register_clkdev(clk, "dsihs1", "mcde"); | |
225 | ||
226 | clk = clk_reg_prcmu_scalable("dsi1lcdclk", "dsilcd_pll", | |
227 | PRCMU_DSI1CLK_LCD, 0, CLK_SET_RATE_GATE); | |
228 | clk_register_clkdev(clk, "dsihs1", "mcde"); | |
229 | clk_register_clkdev(clk, "hs_clk", "dsilink.1"); | |
230 | ||
231 | clk = clk_reg_prcmu_scalable("dsi0escclk", "tvclk", | |
232 | PRCMU_DSI0ESCCLK, 0, CLK_SET_RATE_GATE); | |
233 | clk_register_clkdev(clk, "lp_clk", "dsilink.0"); | |
234 | clk_register_clkdev(clk, "dsilp0", "mcde"); | |
235 | ||
236 | clk = clk_reg_prcmu_scalable("dsi1escclk", "tvclk", | |
237 | PRCMU_DSI1ESCCLK, 0, CLK_SET_RATE_GATE); | |
238 | clk_register_clkdev(clk, "lp_clk", "dsilink.1"); | |
239 | clk_register_clkdev(clk, "dsilp1", "mcde"); | |
240 | ||
241 | clk = clk_reg_prcmu_scalable("dsi2escclk", "tvclk", | |
242 | PRCMU_DSI2ESCCLK, 0, CLK_SET_RATE_GATE); | |
243 | clk_register_clkdev(clk, "lp_clk", "dsilink.2"); | |
244 | clk_register_clkdev(clk, "dsilp2", "mcde"); | |
245 | ||
246 | clk = clk_reg_prcmu_scalable_rate("armss", NULL, | |
247 | PRCMU_ARMSS, 0, CLK_IS_ROOT|CLK_IGNORE_UNUSED); | |
248 | clk_register_clkdev(clk, "armss", NULL); | |
249 | ||
250 | clk = clk_register_fixed_factor(NULL, "smp_twd", "armss", | |
251 | CLK_IGNORE_UNUSED, 1, 2); | |
252 | clk_register_clkdev(clk, NULL, "smp_twd"); | |
253 | ||
254 | /* PRCC P-clocks */ | |
255 | /* Peripheral 1 : PRCC P-clocks */ | |
5dc0fe19 | 256 | clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", bases[CLKRST1_INDEX], |
a6a3ec7b PB |
257 | BIT(0), 0); |
258 | clk_register_clkdev(clk, "apb_pclk", "uart0"); | |
259 | ||
5dc0fe19 | 260 | clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", bases[CLKRST1_INDEX], |
a6a3ec7b PB |
261 | BIT(1), 0); |
262 | clk_register_clkdev(clk, "apb_pclk", "uart1"); | |
263 | ||
5dc0fe19 | 264 | clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", bases[CLKRST1_INDEX], |
a6a3ec7b PB |
265 | BIT(2), 0); |
266 | clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.1"); | |
267 | ||
5dc0fe19 | 268 | clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", bases[CLKRST1_INDEX], |
a6a3ec7b PB |
269 | BIT(3), 0); |
270 | clk_register_clkdev(clk, "apb_pclk", "msp0"); | |
271 | clk_register_clkdev(clk, "apb_pclk", "dbx5x0-msp-i2s.0"); | |
272 | ||
5dc0fe19 | 273 | clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", bases[CLKRST1_INDEX], |
a6a3ec7b PB |
274 | BIT(4), 0); |
275 | clk_register_clkdev(clk, "apb_pclk", "msp1"); | |
276 | clk_register_clkdev(clk, "apb_pclk", "dbx5x0-msp-i2s.1"); | |
277 | ||
5dc0fe19 | 278 | clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", bases[CLKRST1_INDEX], |
a6a3ec7b PB |
279 | BIT(5), 0); |
280 | clk_register_clkdev(clk, "apb_pclk", "sdi0"); | |
281 | ||
5dc0fe19 | 282 | clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", bases[CLKRST1_INDEX], |
a6a3ec7b PB |
283 | BIT(6), 0); |
284 | clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.2"); | |
285 | ||
5dc0fe19 | 286 | clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", bases[CLKRST1_INDEX], |
a6a3ec7b PB |
287 | BIT(7), 0); |
288 | clk_register_clkdev(clk, NULL, "spi3"); | |
289 | ||
5dc0fe19 | 290 | clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", bases[CLKRST1_INDEX], |
a6a3ec7b PB |
291 | BIT(8), 0); |
292 | clk_register_clkdev(clk, "apb_pclk", "slimbus0"); | |
293 | ||
5dc0fe19 | 294 | clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", bases[CLKRST1_INDEX], |
a6a3ec7b PB |
295 | BIT(9), 0); |
296 | clk_register_clkdev(clk, NULL, "gpio.0"); | |
297 | clk_register_clkdev(clk, NULL, "gpio.1"); | |
298 | clk_register_clkdev(clk, NULL, "gpioblock0"); | |
299 | clk_register_clkdev(clk, "apb_pclk", "ab85xx-codec.0"); | |
300 | ||
5dc0fe19 | 301 | clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", bases[CLKRST1_INDEX], |
a6a3ec7b PB |
302 | BIT(10), 0); |
303 | clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.4"); | |
304 | ||
5dc0fe19 | 305 | clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", bases[CLKRST1_INDEX], |
a6a3ec7b PB |
306 | BIT(11), 0); |
307 | clk_register_clkdev(clk, "apb_pclk", "msp3"); | |
308 | clk_register_clkdev(clk, "apb_pclk", "dbx5x0-msp-i2s.3"); | |
309 | ||
310 | /* Peripheral 2 : PRCC P-clocks */ | |
5dc0fe19 | 311 | clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", bases[CLKRST2_INDEX], |
a6a3ec7b PB |
312 | BIT(0), 0); |
313 | clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.3"); | |
314 | ||
5dc0fe19 | 315 | clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", bases[CLKRST2_INDEX], |
a6a3ec7b PB |
316 | BIT(1), 0); |
317 | clk_register_clkdev(clk, NULL, "spi2"); | |
318 | ||
5dc0fe19 | 319 | clk = clk_reg_prcc_pclk("p2_pclk2", "per2clk", bases[CLKRST2_INDEX], |
a6a3ec7b PB |
320 | BIT(2), 0); |
321 | clk_register_clkdev(clk, NULL, "spi1"); | |
322 | ||
5dc0fe19 | 323 | clk = clk_reg_prcc_pclk("p2_pclk3", "per2clk", bases[CLKRST2_INDEX], |
a6a3ec7b PB |
324 | BIT(3), 0); |
325 | clk_register_clkdev(clk, NULL, "pwl"); | |
326 | ||
5dc0fe19 | 327 | clk = clk_reg_prcc_pclk("p2_pclk4", "per2clk", bases[CLKRST2_INDEX], |
a6a3ec7b PB |
328 | BIT(4), 0); |
329 | clk_register_clkdev(clk, "apb_pclk", "sdi4"); | |
330 | ||
5dc0fe19 | 331 | clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", bases[CLKRST2_INDEX], |
a6a3ec7b PB |
332 | BIT(5), 0); |
333 | clk_register_clkdev(clk, "apb_pclk", "msp2"); | |
334 | clk_register_clkdev(clk, "apb_pclk", "dbx5x0-msp-i2s.2"); | |
335 | ||
5dc0fe19 | 336 | clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", bases[CLKRST2_INDEX], |
a6a3ec7b PB |
337 | BIT(6), 0); |
338 | clk_register_clkdev(clk, "apb_pclk", "sdi1"); | |
339 | ||
5dc0fe19 | 340 | clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", bases[CLKRST2_INDEX], |
a6a3ec7b PB |
341 | BIT(7), 0); |
342 | clk_register_clkdev(clk, "apb_pclk", "sdi3"); | |
343 | ||
5dc0fe19 | 344 | clk = clk_reg_prcc_pclk("p2_pclk8", "per2clk", bases[CLKRST2_INDEX], |
a6a3ec7b PB |
345 | BIT(8), 0); |
346 | clk_register_clkdev(clk, NULL, "spi0"); | |
347 | ||
5dc0fe19 | 348 | clk = clk_reg_prcc_pclk("p2_pclk9", "per2clk", bases[CLKRST2_INDEX], |
a6a3ec7b PB |
349 | BIT(9), 0); |
350 | clk_register_clkdev(clk, "hsir_hclk", "ste_hsi.0"); | |
351 | ||
5dc0fe19 | 352 | clk = clk_reg_prcc_pclk("p2_pclk10", "per2clk", bases[CLKRST2_INDEX], |
a6a3ec7b PB |
353 | BIT(10), 0); |
354 | clk_register_clkdev(clk, "hsit_hclk", "ste_hsi.0"); | |
355 | ||
5dc0fe19 | 356 | clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", bases[CLKRST2_INDEX], |
a6a3ec7b PB |
357 | BIT(11), 0); |
358 | clk_register_clkdev(clk, NULL, "gpio.6"); | |
359 | clk_register_clkdev(clk, NULL, "gpio.7"); | |
360 | clk_register_clkdev(clk, NULL, "gpioblock1"); | |
361 | ||
5dc0fe19 | 362 | clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", bases[CLKRST2_INDEX], |
a6a3ec7b PB |
363 | BIT(12), 0); |
364 | clk_register_clkdev(clk, "msp4-pclk", "ab85xx-codec.0"); | |
365 | ||
366 | /* Peripheral 3 : PRCC P-clocks */ | |
5dc0fe19 | 367 | clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", bases[CLKRST3_INDEX], |
a6a3ec7b PB |
368 | BIT(0), 0); |
369 | clk_register_clkdev(clk, NULL, "fsmc"); | |
370 | ||
5dc0fe19 | 371 | clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", bases[CLKRST3_INDEX], |
a6a3ec7b PB |
372 | BIT(1), 0); |
373 | clk_register_clkdev(clk, "apb_pclk", "ssp0"); | |
374 | ||
5dc0fe19 | 375 | clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", bases[CLKRST3_INDEX], |
a6a3ec7b PB |
376 | BIT(2), 0); |
377 | clk_register_clkdev(clk, "apb_pclk", "ssp1"); | |
378 | ||
5dc0fe19 | 379 | clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", bases[CLKRST3_INDEX], |
a6a3ec7b PB |
380 | BIT(3), 0); |
381 | clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.0"); | |
382 | ||
5dc0fe19 | 383 | clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", bases[CLKRST3_INDEX], |
a6a3ec7b PB |
384 | BIT(4), 0); |
385 | clk_register_clkdev(clk, "apb_pclk", "sdi2"); | |
386 | ||
5dc0fe19 | 387 | clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", bases[CLKRST3_INDEX], |
a6a3ec7b PB |
388 | BIT(5), 0); |
389 | clk_register_clkdev(clk, "apb_pclk", "ske"); | |
390 | clk_register_clkdev(clk, "apb_pclk", "nmk-ske-keypad"); | |
391 | ||
5dc0fe19 | 392 | clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", bases[CLKRST3_INDEX], |
a6a3ec7b PB |
393 | BIT(6), 0); |
394 | clk_register_clkdev(clk, "apb_pclk", "uart2"); | |
395 | ||
5dc0fe19 | 396 | clk = clk_reg_prcc_pclk("p3_pclk7", "per3clk", bases[CLKRST3_INDEX], |
a6a3ec7b PB |
397 | BIT(7), 0); |
398 | clk_register_clkdev(clk, "apb_pclk", "sdi5"); | |
399 | ||
5dc0fe19 | 400 | clk = clk_reg_prcc_pclk("p3_pclk8", "per3clk", bases[CLKRST3_INDEX], |
a6a3ec7b PB |
401 | BIT(8), 0); |
402 | clk_register_clkdev(clk, NULL, "gpio.2"); | |
403 | clk_register_clkdev(clk, NULL, "gpio.3"); | |
404 | clk_register_clkdev(clk, NULL, "gpio.4"); | |
405 | clk_register_clkdev(clk, NULL, "gpio.5"); | |
406 | clk_register_clkdev(clk, NULL, "gpioblock2"); | |
407 | ||
5dc0fe19 | 408 | clk = clk_reg_prcc_pclk("p3_pclk9", "per3clk", bases[CLKRST3_INDEX], |
a6a3ec7b PB |
409 | BIT(9), 0); |
410 | clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.5"); | |
411 | ||
5dc0fe19 | 412 | clk = clk_reg_prcc_pclk("p3_pclk10", "per3clk", bases[CLKRST3_INDEX], |
a6a3ec7b PB |
413 | BIT(10), 0); |
414 | clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.6"); | |
415 | ||
5dc0fe19 | 416 | clk = clk_reg_prcc_pclk("p3_pclk11", "per3clk", bases[CLKRST3_INDEX], |
a6a3ec7b PB |
417 | BIT(11), 0); |
418 | clk_register_clkdev(clk, "apb_pclk", "uart3"); | |
419 | ||
5dc0fe19 | 420 | clk = clk_reg_prcc_pclk("p3_pclk12", "per3clk", bases[CLKRST3_INDEX], |
a6a3ec7b PB |
421 | BIT(12), 0); |
422 | clk_register_clkdev(clk, "apb_pclk", "uart4"); | |
423 | ||
424 | /* Peripheral 5 : PRCC P-clocks */ | |
5dc0fe19 | 425 | clk = clk_reg_prcc_pclk("p5_pclk0", "per5clk", bases[CLKRST5_INDEX], |
a6a3ec7b PB |
426 | BIT(0), 0); |
427 | clk_register_clkdev(clk, "usb", "musb-ux500.0"); | |
428 | clk_register_clkdev(clk, "usbclk", "ab-iddet.0"); | |
429 | ||
5dc0fe19 | 430 | clk = clk_reg_prcc_pclk("p5_pclk1", "per5clk", bases[CLKRST5_INDEX], |
a6a3ec7b PB |
431 | BIT(1), 0); |
432 | clk_register_clkdev(clk, NULL, "gpio.8"); | |
433 | clk_register_clkdev(clk, NULL, "gpioblock3"); | |
434 | ||
435 | /* Peripheral 6 : PRCC P-clocks */ | |
5dc0fe19 | 436 | clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", bases[CLKRST6_INDEX], |
a6a3ec7b PB |
437 | BIT(0), 0); |
438 | clk_register_clkdev(clk, "apb_pclk", "rng"); | |
439 | ||
5dc0fe19 | 440 | clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", bases[CLKRST6_INDEX], |
a6a3ec7b PB |
441 | BIT(1), 0); |
442 | clk_register_clkdev(clk, NULL, "cryp0"); | |
443 | clk_register_clkdev(clk, NULL, "cryp1"); | |
444 | ||
5dc0fe19 | 445 | clk = clk_reg_prcc_pclk("p6_pclk2", "per6clk", bases[CLKRST6_INDEX], |
a6a3ec7b PB |
446 | BIT(2), 0); |
447 | clk_register_clkdev(clk, NULL, "hash0"); | |
448 | ||
5dc0fe19 | 449 | clk = clk_reg_prcc_pclk("p6_pclk3", "per6clk", bases[CLKRST6_INDEX], |
a6a3ec7b PB |
450 | BIT(3), 0); |
451 | clk_register_clkdev(clk, NULL, "pka"); | |
452 | ||
5dc0fe19 | 453 | clk = clk_reg_prcc_pclk("p6_pclk4", "per6clk", bases[CLKRST6_INDEX], |
a6a3ec7b PB |
454 | BIT(4), 0); |
455 | clk_register_clkdev(clk, NULL, "db8540-hash1"); | |
456 | ||
5dc0fe19 | 457 | clk = clk_reg_prcc_pclk("p6_pclk5", "per6clk", bases[CLKRST6_INDEX], |
a6a3ec7b PB |
458 | BIT(5), 0); |
459 | clk_register_clkdev(clk, NULL, "cfgreg"); | |
460 | ||
5dc0fe19 | 461 | clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", bases[CLKRST6_INDEX], |
a6a3ec7b PB |
462 | BIT(6), 0); |
463 | clk_register_clkdev(clk, "apb_pclk", "mtu0"); | |
464 | ||
5dc0fe19 | 465 | clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", bases[CLKRST6_INDEX], |
a6a3ec7b PB |
466 | BIT(7), 0); |
467 | clk_register_clkdev(clk, "apb_pclk", "mtu1"); | |
468 | ||
469 | /* | |
470 | * PRCC K-clocks ==> see table PRCC_PCKEN/PRCC_KCKEN | |
471 | * This differs from the internal implementation: | |
472 | * We don't use the PERPIH[n| clock as parent, since those _should_ | |
473 | * only be used as parents for the P-clocks. | |
474 | * TODO: "parentjoin" with corresponding P-clocks for all K-clocks. | |
475 | */ | |
476 | ||
477 | /* Peripheral 1 : PRCC K-clocks */ | |
478 | clk = clk_reg_prcc_kclk("p1_uart0_kclk", "uartclk", | |
5dc0fe19 | 479 | bases[CLKRST1_INDEX], BIT(0), CLK_SET_RATE_GATE); |
a6a3ec7b PB |
480 | clk_register_clkdev(clk, NULL, "uart0"); |
481 | ||
482 | clk = clk_reg_prcc_kclk("p1_uart1_kclk", "uartclk", | |
5dc0fe19 | 483 | bases[CLKRST1_INDEX], BIT(1), CLK_SET_RATE_GATE); |
a6a3ec7b PB |
484 | clk_register_clkdev(clk, NULL, "uart1"); |
485 | ||
486 | clk = clk_reg_prcc_kclk("p1_i2c1_kclk", "i2cclk", | |
5dc0fe19 | 487 | bases[CLKRST1_INDEX], BIT(2), CLK_SET_RATE_GATE); |
a6a3ec7b PB |
488 | clk_register_clkdev(clk, NULL, "nmk-i2c.1"); |
489 | ||
490 | clk = clk_reg_prcc_kclk("p1_msp0_kclk", "msp02clk", | |
5dc0fe19 | 491 | bases[CLKRST1_INDEX], BIT(3), CLK_SET_RATE_GATE); |
a6a3ec7b PB |
492 | clk_register_clkdev(clk, NULL, "msp0"); |
493 | clk_register_clkdev(clk, NULL, "dbx5x0-msp-i2s.0"); | |
494 | ||
495 | clk = clk_reg_prcc_kclk("p1_msp1_kclk", "msp1clk", | |
5dc0fe19 | 496 | bases[CLKRST1_INDEX], BIT(4), CLK_SET_RATE_GATE); |
a6a3ec7b PB |
497 | clk_register_clkdev(clk, NULL, "msp1"); |
498 | clk_register_clkdev(clk, NULL, "dbx5x0-msp-i2s.1"); | |
499 | ||
500 | clk = clk_reg_prcc_kclk("p1_sdi0_kclk", "sdmmchclk", | |
5dc0fe19 | 501 | bases[CLKRST1_INDEX], BIT(5), CLK_SET_RATE_GATE); |
a6a3ec7b PB |
502 | clk_register_clkdev(clk, NULL, "sdi0"); |
503 | ||
504 | clk = clk_reg_prcc_kclk("p1_i2c2_kclk", "i2cclk", | |
5dc0fe19 | 505 | bases[CLKRST1_INDEX], BIT(6), CLK_SET_RATE_GATE); |
a6a3ec7b PB |
506 | clk_register_clkdev(clk, NULL, "nmk-i2c.2"); |
507 | ||
508 | clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk", | |
5dc0fe19 | 509 | bases[CLKRST1_INDEX], BIT(8), CLK_SET_RATE_GATE); |
a6a3ec7b PB |
510 | clk_register_clkdev(clk, NULL, "slimbus0"); |
511 | ||
512 | clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk", | |
5dc0fe19 | 513 | bases[CLKRST1_INDEX], BIT(9), CLK_SET_RATE_GATE); |
a6a3ec7b PB |
514 | clk_register_clkdev(clk, NULL, "nmk-i2c.4"); |
515 | ||
516 | clk = clk_reg_prcc_kclk("p1_msp3_kclk", "msp1clk", | |
5dc0fe19 | 517 | bases[CLKRST1_INDEX], BIT(10), CLK_SET_RATE_GATE); |
a6a3ec7b PB |
518 | clk_register_clkdev(clk, NULL, "msp3"); |
519 | clk_register_clkdev(clk, NULL, "dbx5x0-msp-i2s.3"); | |
520 | ||
521 | /* Peripheral 2 : PRCC K-clocks */ | |
522 | clk = clk_reg_prcc_kclk("p2_i2c3_kclk", "i2cclk", | |
5dc0fe19 | 523 | bases[CLKRST2_INDEX], BIT(0), CLK_SET_RATE_GATE); |
a6a3ec7b PB |
524 | clk_register_clkdev(clk, NULL, "nmk-i2c.3"); |
525 | ||
526 | clk = clk_reg_prcc_kclk("p2_pwl_kclk", "rtc32k", | |
5dc0fe19 | 527 | bases[CLKRST2_INDEX], BIT(1), CLK_SET_RATE_GATE); |
a6a3ec7b PB |
528 | clk_register_clkdev(clk, NULL, "pwl"); |
529 | ||
530 | clk = clk_reg_prcc_kclk("p2_sdi4_kclk", "sdmmchclk", | |
5dc0fe19 | 531 | bases[CLKRST2_INDEX], BIT(2), CLK_SET_RATE_GATE); |
a6a3ec7b PB |
532 | clk_register_clkdev(clk, NULL, "sdi4"); |
533 | ||
534 | clk = clk_reg_prcc_kclk("p2_msp2_kclk", "msp02clk", | |
5dc0fe19 | 535 | bases[CLKRST2_INDEX], BIT(3), CLK_SET_RATE_GATE); |
a6a3ec7b PB |
536 | clk_register_clkdev(clk, NULL, "msp2"); |
537 | clk_register_clkdev(clk, NULL, "dbx5x0-msp-i2s.2"); | |
538 | ||
539 | clk = clk_reg_prcc_kclk("p2_sdi1_kclk", "sdmmchclk", | |
5dc0fe19 | 540 | bases[CLKRST2_INDEX], BIT(4), CLK_SET_RATE_GATE); |
a6a3ec7b PB |
541 | clk_register_clkdev(clk, NULL, "sdi1"); |
542 | ||
543 | clk = clk_reg_prcc_kclk("p2_sdi3_kclk", "sdmmcclk", | |
5dc0fe19 | 544 | bases[CLKRST2_INDEX], BIT(5), CLK_SET_RATE_GATE); |
a6a3ec7b PB |
545 | clk_register_clkdev(clk, NULL, "sdi3"); |
546 | ||
547 | clk = clk_reg_prcc_kclk("p2_ssirx_kclk", "hsirxclk", | |
5dc0fe19 | 548 | bases[CLKRST2_INDEX], BIT(6), |
a6a3ec7b PB |
549 | CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT); |
550 | clk_register_clkdev(clk, "hsir_hsirxclk", "ste_hsi.0"); | |
551 | ||
552 | clk = clk_reg_prcc_kclk("p2_ssitx_kclk", "hsitxclk", | |
5dc0fe19 | 553 | bases[CLKRST2_INDEX], BIT(7), |
a6a3ec7b PB |
554 | CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT); |
555 | clk_register_clkdev(clk, "hsit_hsitxclk", "ste_hsi.0"); | |
556 | ||
557 | /* Should only be 9540, but might be added for 85xx as well */ | |
558 | clk = clk_reg_prcc_kclk("p2_msp4_kclk", "msp02clk", | |
5dc0fe19 | 559 | bases[CLKRST2_INDEX], BIT(9), CLK_SET_RATE_GATE); |
a6a3ec7b PB |
560 | clk_register_clkdev(clk, NULL, "msp4"); |
561 | clk_register_clkdev(clk, "msp4", "ab85xx-codec.0"); | |
562 | ||
563 | /* Peripheral 3 : PRCC K-clocks */ | |
564 | clk = clk_reg_prcc_kclk("p3_ssp0_kclk", "sspclk", | |
5dc0fe19 | 565 | bases[CLKRST3_INDEX], BIT(1), CLK_SET_RATE_GATE); |
a6a3ec7b PB |
566 | clk_register_clkdev(clk, NULL, "ssp0"); |
567 | ||
568 | clk = clk_reg_prcc_kclk("p3_ssp1_kclk", "sspclk", | |
5dc0fe19 | 569 | bases[CLKRST3_INDEX], BIT(2), CLK_SET_RATE_GATE); |
a6a3ec7b PB |
570 | clk_register_clkdev(clk, NULL, "ssp1"); |
571 | ||
572 | clk = clk_reg_prcc_kclk("p3_i2c0_kclk", "i2cclk", | |
5dc0fe19 | 573 | bases[CLKRST3_INDEX], BIT(3), CLK_SET_RATE_GATE); |
a6a3ec7b PB |
574 | clk_register_clkdev(clk, NULL, "nmk-i2c.0"); |
575 | ||
576 | clk = clk_reg_prcc_kclk("p3_sdi2_kclk", "sdmmchclk", | |
5dc0fe19 | 577 | bases[CLKRST3_INDEX], BIT(4), CLK_SET_RATE_GATE); |
a6a3ec7b PB |
578 | clk_register_clkdev(clk, NULL, "sdi2"); |
579 | ||
580 | clk = clk_reg_prcc_kclk("p3_ske_kclk", "rtc32k", | |
5dc0fe19 | 581 | bases[CLKRST3_INDEX], BIT(5), CLK_SET_RATE_GATE); |
a6a3ec7b PB |
582 | clk_register_clkdev(clk, NULL, "ske"); |
583 | clk_register_clkdev(clk, NULL, "nmk-ske-keypad"); | |
584 | ||
585 | clk = clk_reg_prcc_kclk("p3_uart2_kclk", "uartclk", | |
5dc0fe19 | 586 | bases[CLKRST3_INDEX], BIT(6), CLK_SET_RATE_GATE); |
a6a3ec7b PB |
587 | clk_register_clkdev(clk, NULL, "uart2"); |
588 | ||
589 | clk = clk_reg_prcc_kclk("p3_sdi5_kclk", "sdmmcclk", | |
5dc0fe19 | 590 | bases[CLKRST3_INDEX], BIT(7), CLK_SET_RATE_GATE); |
a6a3ec7b PB |
591 | clk_register_clkdev(clk, NULL, "sdi5"); |
592 | ||
593 | clk = clk_reg_prcc_kclk("p3_i2c5_kclk", "i2cclk", | |
5dc0fe19 | 594 | bases[CLKRST3_INDEX], BIT(8), CLK_SET_RATE_GATE); |
a6a3ec7b PB |
595 | clk_register_clkdev(clk, NULL, "nmk-i2c.5"); |
596 | ||
597 | clk = clk_reg_prcc_kclk("p3_i2c6_kclk", "i2cclk", | |
5dc0fe19 | 598 | bases[CLKRST3_INDEX], BIT(9), CLK_SET_RATE_GATE); |
a6a3ec7b PB |
599 | clk_register_clkdev(clk, NULL, "nmk-i2c.6"); |
600 | ||
601 | clk = clk_reg_prcc_kclk("p3_uart3_kclk", "uartclk", | |
5dc0fe19 | 602 | bases[CLKRST3_INDEX], BIT(10), CLK_SET_RATE_GATE); |
a6a3ec7b PB |
603 | clk_register_clkdev(clk, NULL, "uart3"); |
604 | ||
605 | clk = clk_reg_prcc_kclk("p3_uart4_kclk", "uartclk", | |
5dc0fe19 | 606 | bases[CLKRST3_INDEX], BIT(11), CLK_SET_RATE_GATE); |
a6a3ec7b PB |
607 | clk_register_clkdev(clk, NULL, "uart4"); |
608 | ||
609 | /* Peripheral 6 : PRCC K-clocks */ | |
610 | clk = clk_reg_prcc_kclk("p6_rng_kclk", "rngclk", | |
5dc0fe19 | 611 | bases[CLKRST6_INDEX], BIT(0), CLK_SET_RATE_GATE); |
a6a3ec7b | 612 | clk_register_clkdev(clk, NULL, "rng"); |
bce5afd8 | 613 | } |