Commit | Line | Data |
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82b0f4b7 LJ |
1 | /* |
2 | * Clock definitions for u8500 platform. | |
3 | * | |
4 | * Copyright (C) 2012 ST-Ericsson SA | |
5 | * Author: Ulf Hansson <ulf.hansson@linaro.org> | |
6 | * | |
7 | * License terms: GNU General Public License (GPL) version 2 | |
8 | */ | |
9 | ||
dec759d8 | 10 | #include <linux/of.h> |
5dc0fe19 | 11 | #include <linux/of_address.h> |
82b0f4b7 LJ |
12 | #include <linux/clk-provider.h> |
13 | #include <linux/mfd/dbx500-prcmu.h> | |
82b0f4b7 LJ |
14 | #include "clk.h" |
15 | ||
2d080300 LJ |
16 | #define PRCC_NUM_PERIPH_CLUSTERS 6 |
17 | #define PRCC_PERIPHS_PER_CLUSTER 32 | |
18 | ||
f9fcb8e8 | 19 | static struct clk *prcmu_clk[PRCMU_NUM_CLKS]; |
2d080300 | 20 | static struct clk *prcc_pclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER]; |
89da2dfa | 21 | static struct clk *prcc_kclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER]; |
f9fcb8e8 | 22 | |
b4bdc81b LJ |
23 | #define PRCC_SHOW(clk, base, bit) \ |
24 | clk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] | |
2d080300 LJ |
25 | #define PRCC_PCLK_STORE(clk, base, bit) \ |
26 | prcc_pclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk | |
89da2dfa LJ |
27 | #define PRCC_KCLK_STORE(clk, base, bit) \ |
28 | prcc_kclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk | |
b4bdc81b | 29 | |
c112c1d8 SK |
30 | static struct clk *ux500_twocell_get(struct of_phandle_args *clkspec, |
31 | void *data) | |
b4bdc81b LJ |
32 | { |
33 | struct clk **clk_data = data; | |
34 | unsigned int base, bit; | |
35 | ||
36 | if (clkspec->args_count != 2) | |
37 | return ERR_PTR(-EINVAL); | |
38 | ||
39 | base = clkspec->args[0]; | |
40 | bit = clkspec->args[1]; | |
41 | ||
42 | if (base != 1 && base != 2 && base != 3 && base != 5 && base != 6) { | |
43 | pr_err("%s: invalid PRCC base %d\n", __func__, base); | |
44 | return ERR_PTR(-EINVAL); | |
45 | } | |
46 | ||
47 | return PRCC_SHOW(clk_data, base, bit); | |
48 | } | |
49 | ||
5dc0fe19 LW |
50 | /* CLKRST4 is missing making it hard to index things */ |
51 | enum clkrst_index { | |
52 | CLKRST1_INDEX = 0, | |
53 | CLKRST2_INDEX, | |
54 | CLKRST3_INDEX, | |
55 | CLKRST5_INDEX, | |
56 | CLKRST6_INDEX, | |
57 | CLKRST_MAX, | |
58 | }; | |
59 | ||
269f1aac | 60 | static void u8500_clk_init(struct device_node *np) |
82b0f4b7 LJ |
61 | { |
62 | struct prcmu_fw_version *fw_version; | |
dec759d8 | 63 | struct device_node *child = NULL; |
82b0f4b7 | 64 | const char *sgaclk_parent = NULL; |
4e334660 | 65 | struct clk *clk, *rtc_clk, *twd_clk; |
5dc0fe19 LW |
66 | u32 bases[CLKRST_MAX]; |
67 | int i; | |
82b0f4b7 | 68 | |
5dc0fe19 LW |
69 | for (i = 0; i < ARRAY_SIZE(bases); i++) { |
70 | struct resource r; | |
71 | ||
72 | if (of_address_to_resource(np, i, &r)) | |
73 | /* Not much choice but to continue */ | |
74 | pr_err("failed to get CLKRST %d base address\n", | |
75 | i + 1); | |
76 | bases[i] = r.start; | |
77 | } | |
dec759d8 | 78 | |
82b0f4b7 LJ |
79 | /* Clock sources */ |
80 | clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0, | |
66f4ae77 | 81 | CLK_IGNORE_UNUSED); |
f9fcb8e8 | 82 | prcmu_clk[PRCMU_PLLSOC0] = clk; |
82b0f4b7 LJ |
83 | |
84 | clk = clk_reg_prcmu_gate("soc1_pll", NULL, PRCMU_PLLSOC1, | |
66f4ae77 | 85 | CLK_IGNORE_UNUSED); |
f9fcb8e8 | 86 | prcmu_clk[PRCMU_PLLSOC1] = clk; |
82b0f4b7 LJ |
87 | |
88 | clk = clk_reg_prcmu_gate("ddr_pll", NULL, PRCMU_PLLDDR, | |
66f4ae77 | 89 | CLK_IGNORE_UNUSED); |
f9fcb8e8 | 90 | prcmu_clk[PRCMU_PLLDDR] = clk; |
82b0f4b7 LJ |
91 | |
92 | /* FIXME: Add sys, ulp and int clocks here. */ | |
93 | ||
d625a730 | 94 | rtc_clk = clk_register_fixed_rate(NULL, "rtc32k", "NULL", |
66f4ae77 | 95 | CLK_IGNORE_UNUSED, |
82b0f4b7 LJ |
96 | 32768); |
97 | ||
98 | /* PRCMU clocks */ | |
99 | fw_version = prcmu_get_fw_version(); | |
100 | if (fw_version != NULL) { | |
101 | switch (fw_version->project) { | |
102 | case PRCMU_FW_PROJECT_U8500_C2: | |
103 | case PRCMU_FW_PROJECT_U8520: | |
104 | case PRCMU_FW_PROJECT_U8420: | |
105 | sgaclk_parent = "soc0_pll"; | |
106 | break; | |
107 | default: | |
108 | break; | |
109 | } | |
110 | } | |
111 | ||
112 | if (sgaclk_parent) | |
113 | clk = clk_reg_prcmu_gate("sgclk", sgaclk_parent, | |
114 | PRCMU_SGACLK, 0); | |
115 | else | |
66f4ae77 | 116 | clk = clk_reg_prcmu_gate("sgclk", NULL, PRCMU_SGACLK, 0); |
f9fcb8e8 | 117 | prcmu_clk[PRCMU_SGACLK] = clk; |
82b0f4b7 | 118 | |
66f4ae77 | 119 | clk = clk_reg_prcmu_gate("uartclk", NULL, PRCMU_UARTCLK, 0); |
f9fcb8e8 | 120 | prcmu_clk[PRCMU_UARTCLK] = clk; |
82b0f4b7 | 121 | |
66f4ae77 | 122 | clk = clk_reg_prcmu_gate("msp02clk", NULL, PRCMU_MSP02CLK, 0); |
f9fcb8e8 | 123 | prcmu_clk[PRCMU_MSP02CLK] = clk; |
82b0f4b7 | 124 | |
66f4ae77 | 125 | clk = clk_reg_prcmu_gate("msp1clk", NULL, PRCMU_MSP1CLK, 0); |
f9fcb8e8 | 126 | prcmu_clk[PRCMU_MSP1CLK] = clk; |
82b0f4b7 | 127 | |
66f4ae77 | 128 | clk = clk_reg_prcmu_gate("i2cclk", NULL, PRCMU_I2CCLK, 0); |
f9fcb8e8 | 129 | prcmu_clk[PRCMU_I2CCLK] = clk; |
82b0f4b7 | 130 | |
66f4ae77 | 131 | clk = clk_reg_prcmu_gate("slimclk", NULL, PRCMU_SLIMCLK, 0); |
f9fcb8e8 | 132 | prcmu_clk[PRCMU_SLIMCLK] = clk; |
82b0f4b7 | 133 | |
66f4ae77 | 134 | clk = clk_reg_prcmu_gate("per1clk", NULL, PRCMU_PER1CLK, 0); |
f9fcb8e8 | 135 | prcmu_clk[PRCMU_PER1CLK] = clk; |
82b0f4b7 | 136 | |
66f4ae77 | 137 | clk = clk_reg_prcmu_gate("per2clk", NULL, PRCMU_PER2CLK, 0); |
f9fcb8e8 | 138 | prcmu_clk[PRCMU_PER2CLK] = clk; |
82b0f4b7 | 139 | |
66f4ae77 | 140 | clk = clk_reg_prcmu_gate("per3clk", NULL, PRCMU_PER3CLK, 0); |
f9fcb8e8 | 141 | prcmu_clk[PRCMU_PER3CLK] = clk; |
82b0f4b7 | 142 | |
66f4ae77 | 143 | clk = clk_reg_prcmu_gate("per5clk", NULL, PRCMU_PER5CLK, 0); |
f9fcb8e8 | 144 | prcmu_clk[PRCMU_PER5CLK] = clk; |
82b0f4b7 | 145 | |
66f4ae77 | 146 | clk = clk_reg_prcmu_gate("per6clk", NULL, PRCMU_PER6CLK, 0); |
f9fcb8e8 | 147 | prcmu_clk[PRCMU_PER6CLK] = clk; |
82b0f4b7 | 148 | |
66f4ae77 | 149 | clk = clk_reg_prcmu_gate("per7clk", NULL, PRCMU_PER7CLK, 0); |
f9fcb8e8 | 150 | prcmu_clk[PRCMU_PER7CLK] = clk; |
82b0f4b7 LJ |
151 | |
152 | clk = clk_reg_prcmu_scalable("lcdclk", NULL, PRCMU_LCDCLK, 0, | |
66f4ae77 | 153 | CLK_SET_RATE_GATE); |
f9fcb8e8 | 154 | prcmu_clk[PRCMU_LCDCLK] = clk; |
82b0f4b7 | 155 | |
66f4ae77 | 156 | clk = clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BMLCLK, 0); |
f9fcb8e8 | 157 | prcmu_clk[PRCMU_BMLCLK] = clk; |
82b0f4b7 LJ |
158 | |
159 | clk = clk_reg_prcmu_scalable("hsitxclk", NULL, PRCMU_HSITXCLK, 0, | |
66f4ae77 | 160 | CLK_SET_RATE_GATE); |
f9fcb8e8 | 161 | prcmu_clk[PRCMU_HSITXCLK] = clk; |
82b0f4b7 LJ |
162 | |
163 | clk = clk_reg_prcmu_scalable("hsirxclk", NULL, PRCMU_HSIRXCLK, 0, | |
66f4ae77 | 164 | CLK_SET_RATE_GATE); |
f9fcb8e8 | 165 | prcmu_clk[PRCMU_HSIRXCLK] = clk; |
82b0f4b7 LJ |
166 | |
167 | clk = clk_reg_prcmu_scalable("hdmiclk", NULL, PRCMU_HDMICLK, 0, | |
66f4ae77 | 168 | CLK_SET_RATE_GATE); |
f9fcb8e8 | 169 | prcmu_clk[PRCMU_HDMICLK] = clk; |
82b0f4b7 | 170 | |
66f4ae77 | 171 | clk = clk_reg_prcmu_gate("apeatclk", NULL, PRCMU_APEATCLK, 0); |
f9fcb8e8 | 172 | prcmu_clk[PRCMU_APEATCLK] = clk; |
82b0f4b7 | 173 | |
a6ae41b5 | 174 | clk = clk_reg_prcmu_scalable("apetraceclk", NULL, PRCMU_APETRACECLK, 0, |
66f4ae77 | 175 | CLK_SET_RATE_GATE); |
f9fcb8e8 | 176 | prcmu_clk[PRCMU_APETRACECLK] = clk; |
82b0f4b7 | 177 | |
66f4ae77 | 178 | clk = clk_reg_prcmu_gate("mcdeclk", NULL, PRCMU_MCDECLK, 0); |
f9fcb8e8 | 179 | prcmu_clk[PRCMU_MCDECLK] = clk; |
82b0f4b7 | 180 | |
66f4ae77 | 181 | clk = clk_reg_prcmu_opp_gate("ipi2cclk", NULL, PRCMU_IPI2CCLK, 0); |
f9fcb8e8 | 182 | prcmu_clk[PRCMU_IPI2CCLK] = clk; |
82b0f4b7 | 183 | |
66f4ae77 | 184 | clk = clk_reg_prcmu_gate("dsialtclk", NULL, PRCMU_DSIALTCLK, 0); |
f9fcb8e8 | 185 | prcmu_clk[PRCMU_DSIALTCLK] = clk; |
82b0f4b7 | 186 | |
66f4ae77 | 187 | clk = clk_reg_prcmu_gate("dmaclk", NULL, PRCMU_DMACLK, 0); |
f9fcb8e8 | 188 | prcmu_clk[PRCMU_DMACLK] = clk; |
82b0f4b7 | 189 | |
66f4ae77 | 190 | clk = clk_reg_prcmu_gate("b2r2clk", NULL, PRCMU_B2R2CLK, 0); |
f9fcb8e8 | 191 | prcmu_clk[PRCMU_B2R2CLK] = clk; |
82b0f4b7 LJ |
192 | |
193 | clk = clk_reg_prcmu_scalable("tvclk", NULL, PRCMU_TVCLK, 0, | |
66f4ae77 | 194 | CLK_SET_RATE_GATE); |
f9fcb8e8 | 195 | prcmu_clk[PRCMU_TVCLK] = clk; |
82b0f4b7 | 196 | |
66f4ae77 | 197 | clk = clk_reg_prcmu_gate("sspclk", NULL, PRCMU_SSPCLK, 0); |
f9fcb8e8 | 198 | prcmu_clk[PRCMU_SSPCLK] = clk; |
82b0f4b7 | 199 | |
66f4ae77 | 200 | clk = clk_reg_prcmu_gate("rngclk", NULL, PRCMU_RNGCLK, 0); |
f9fcb8e8 | 201 | prcmu_clk[PRCMU_RNGCLK] = clk; |
82b0f4b7 | 202 | |
66f4ae77 | 203 | clk = clk_reg_prcmu_gate("uiccclk", NULL, PRCMU_UICCCLK, 0); |
f9fcb8e8 | 204 | prcmu_clk[PRCMU_UICCCLK] = clk; |
82b0f4b7 | 205 | |
66f4ae77 | 206 | clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, 0); |
f9fcb8e8 | 207 | prcmu_clk[PRCMU_TIMCLK] = clk; |
82b0f4b7 | 208 | |
689a318c LW |
209 | clk = clk_reg_prcmu_gate("ab8500_sysclk", NULL, PRCMU_SYSCLK, 0); |
210 | prcmu_clk[PRCMU_SYSCLK] = clk; | |
211 | ||
82b0f4b7 | 212 | clk = clk_reg_prcmu_opp_volt_scalable("sdmmcclk", NULL, PRCMU_SDMMCCLK, |
66f4ae77 | 213 | 100000000, CLK_SET_RATE_GATE); |
f9fcb8e8 | 214 | prcmu_clk[PRCMU_SDMMCCLK] = clk; |
82b0f4b7 LJ |
215 | |
216 | clk = clk_reg_prcmu_scalable("dsi_pll", "hdmiclk", | |
217 | PRCMU_PLLDSI, 0, CLK_SET_RATE_GATE); | |
f9fcb8e8 | 218 | prcmu_clk[PRCMU_PLLDSI] = clk; |
82b0f4b7 LJ |
219 | |
220 | clk = clk_reg_prcmu_scalable("dsi0clk", "dsi_pll", | |
221 | PRCMU_DSI0CLK, 0, CLK_SET_RATE_GATE); | |
f9fcb8e8 | 222 | prcmu_clk[PRCMU_DSI0CLK] = clk; |
82b0f4b7 LJ |
223 | |
224 | clk = clk_reg_prcmu_scalable("dsi1clk", "dsi_pll", | |
225 | PRCMU_DSI1CLK, 0, CLK_SET_RATE_GATE); | |
f9fcb8e8 | 226 | prcmu_clk[PRCMU_DSI1CLK] = clk; |
82b0f4b7 LJ |
227 | |
228 | clk = clk_reg_prcmu_scalable("dsi0escclk", "tvclk", | |
229 | PRCMU_DSI0ESCCLK, 0, CLK_SET_RATE_GATE); | |
f9fcb8e8 | 230 | prcmu_clk[PRCMU_DSI0ESCCLK] = clk; |
82b0f4b7 LJ |
231 | |
232 | clk = clk_reg_prcmu_scalable("dsi1escclk", "tvclk", | |
233 | PRCMU_DSI1ESCCLK, 0, CLK_SET_RATE_GATE); | |
f9fcb8e8 | 234 | prcmu_clk[PRCMU_DSI1ESCCLK] = clk; |
82b0f4b7 LJ |
235 | |
236 | clk = clk_reg_prcmu_scalable("dsi2escclk", "tvclk", | |
237 | PRCMU_DSI2ESCCLK, 0, CLK_SET_RATE_GATE); | |
f9fcb8e8 | 238 | prcmu_clk[PRCMU_DSI2ESCCLK] = clk; |
82b0f4b7 LJ |
239 | |
240 | clk = clk_reg_prcmu_scalable_rate("armss", NULL, | |
66f4ae77 | 241 | PRCMU_ARMSS, 0, CLK_IGNORE_UNUSED); |
257015a2 | 242 | prcmu_clk[PRCMU_ARMSS] = clk; |
82b0f4b7 | 243 | |
4e334660 | 244 | twd_clk = clk_register_fixed_factor(NULL, "smp_twd", "armss", |
82b0f4b7 LJ |
245 | CLK_IGNORE_UNUSED, 1, 2); |
246 | ||
247 | /* | |
248 | * FIXME: Add special handled PRCMU clocks here: | |
249 | * 1. clkout0yuv, use PRCMU as parent + need regulator + pinctrl. | |
250 | * 2. ab9540_clkout1yuv, see clkout0yuv | |
251 | */ | |
252 | ||
253 | /* PRCC P-clocks */ | |
5dc0fe19 | 254 | clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", bases[CLKRST1_INDEX], |
82b0f4b7 | 255 | BIT(0), 0); |
2d080300 | 256 | PRCC_PCLK_STORE(clk, 1, 0); |
82b0f4b7 | 257 | |
5dc0fe19 | 258 | clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", bases[CLKRST1_INDEX], |
82b0f4b7 | 259 | BIT(1), 0); |
2d080300 | 260 | PRCC_PCLK_STORE(clk, 1, 1); |
82b0f4b7 | 261 | |
5dc0fe19 | 262 | clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", bases[CLKRST1_INDEX], |
82b0f4b7 | 263 | BIT(2), 0); |
2d080300 | 264 | PRCC_PCLK_STORE(clk, 1, 2); |
82b0f4b7 | 265 | |
5dc0fe19 | 266 | clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", bases[CLKRST1_INDEX], |
82b0f4b7 | 267 | BIT(3), 0); |
2d080300 | 268 | PRCC_PCLK_STORE(clk, 1, 3); |
82b0f4b7 | 269 | |
5dc0fe19 | 270 | clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", bases[CLKRST1_INDEX], |
82b0f4b7 | 271 | BIT(4), 0); |
2d080300 | 272 | PRCC_PCLK_STORE(clk, 1, 4); |
82b0f4b7 | 273 | |
5dc0fe19 | 274 | clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", bases[CLKRST1_INDEX], |
82b0f4b7 | 275 | BIT(5), 0); |
2d080300 | 276 | PRCC_PCLK_STORE(clk, 1, 5); |
82b0f4b7 | 277 | |
5dc0fe19 | 278 | clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", bases[CLKRST1_INDEX], |
82b0f4b7 | 279 | BIT(6), 0); |
2d080300 | 280 | PRCC_PCLK_STORE(clk, 1, 6); |
82b0f4b7 | 281 | |
5dc0fe19 | 282 | clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", bases[CLKRST1_INDEX], |
82b0f4b7 | 283 | BIT(7), 0); |
2d080300 | 284 | PRCC_PCLK_STORE(clk, 1, 7); |
82b0f4b7 | 285 | |
5dc0fe19 | 286 | clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", bases[CLKRST1_INDEX], |
82b0f4b7 | 287 | BIT(8), 0); |
2d080300 | 288 | PRCC_PCLK_STORE(clk, 1, 8); |
82b0f4b7 | 289 | |
5dc0fe19 | 290 | clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", bases[CLKRST1_INDEX], |
82b0f4b7 | 291 | BIT(9), 0); |
2d080300 | 292 | PRCC_PCLK_STORE(clk, 1, 9); |
82b0f4b7 | 293 | |
5dc0fe19 | 294 | clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", bases[CLKRST1_INDEX], |
82b0f4b7 | 295 | BIT(10), 0); |
2d080300 | 296 | PRCC_PCLK_STORE(clk, 1, 10); |
82b0f4b7 | 297 | |
5dc0fe19 | 298 | clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", bases[CLKRST1_INDEX], |
82b0f4b7 | 299 | BIT(11), 0); |
2d080300 | 300 | PRCC_PCLK_STORE(clk, 1, 11); |
82b0f4b7 | 301 | |
5dc0fe19 | 302 | clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", bases[CLKRST2_INDEX], |
82b0f4b7 | 303 | BIT(0), 0); |
2d080300 | 304 | PRCC_PCLK_STORE(clk, 2, 0); |
82b0f4b7 | 305 | |
5dc0fe19 | 306 | clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", bases[CLKRST2_INDEX], |
82b0f4b7 | 307 | BIT(1), 0); |
2d080300 | 308 | PRCC_PCLK_STORE(clk, 2, 1); |
82b0f4b7 | 309 | |
5dc0fe19 | 310 | clk = clk_reg_prcc_pclk("p2_pclk2", "per2clk", bases[CLKRST2_INDEX], |
82b0f4b7 | 311 | BIT(2), 0); |
2d080300 | 312 | PRCC_PCLK_STORE(clk, 2, 2); |
82b0f4b7 | 313 | |
5dc0fe19 | 314 | clk = clk_reg_prcc_pclk("p2_pclk3", "per2clk", bases[CLKRST2_INDEX], |
82b0f4b7 | 315 | BIT(3), 0); |
2d080300 | 316 | PRCC_PCLK_STORE(clk, 2, 3); |
82b0f4b7 | 317 | |
5dc0fe19 | 318 | clk = clk_reg_prcc_pclk("p2_pclk4", "per2clk", bases[CLKRST2_INDEX], |
82b0f4b7 | 319 | BIT(4), 0); |
2d080300 | 320 | PRCC_PCLK_STORE(clk, 2, 4); |
82b0f4b7 | 321 | |
5dc0fe19 | 322 | clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", bases[CLKRST2_INDEX], |
82b0f4b7 | 323 | BIT(5), 0); |
2d080300 | 324 | PRCC_PCLK_STORE(clk, 2, 5); |
82b0f4b7 | 325 | |
5dc0fe19 | 326 | clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", bases[CLKRST2_INDEX], |
82b0f4b7 | 327 | BIT(6), 0); |
2d080300 | 328 | PRCC_PCLK_STORE(clk, 2, 6); |
82b0f4b7 | 329 | |
5dc0fe19 | 330 | clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", bases[CLKRST2_INDEX], |
82b0f4b7 | 331 | BIT(7), 0); |
2d080300 | 332 | PRCC_PCLK_STORE(clk, 2, 7); |
82b0f4b7 | 333 | |
5dc0fe19 | 334 | clk = clk_reg_prcc_pclk("p2_pclk8", "per2clk", bases[CLKRST2_INDEX], |
82b0f4b7 | 335 | BIT(8), 0); |
2d080300 | 336 | PRCC_PCLK_STORE(clk, 2, 8); |
82b0f4b7 | 337 | |
5dc0fe19 | 338 | clk = clk_reg_prcc_pclk("p2_pclk9", "per2clk", bases[CLKRST2_INDEX], |
82b0f4b7 | 339 | BIT(9), 0); |
2d080300 | 340 | PRCC_PCLK_STORE(clk, 2, 9); |
82b0f4b7 | 341 | |
5dc0fe19 | 342 | clk = clk_reg_prcc_pclk("p2_pclk10", "per2clk", bases[CLKRST2_INDEX], |
82b0f4b7 | 343 | BIT(10), 0); |
2d080300 | 344 | PRCC_PCLK_STORE(clk, 2, 10); |
82b0f4b7 | 345 | |
5dc0fe19 | 346 | clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", bases[CLKRST2_INDEX], |
82b0f4b7 | 347 | BIT(11), 0); |
f5ff9a11 | 348 | PRCC_PCLK_STORE(clk, 2, 11); |
82b0f4b7 | 349 | |
5dc0fe19 | 350 | clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", bases[CLKRST2_INDEX], |
82b0f4b7 | 351 | BIT(12), 0); |
2d080300 | 352 | PRCC_PCLK_STORE(clk, 2, 12); |
82b0f4b7 | 353 | |
5dc0fe19 | 354 | clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", bases[CLKRST3_INDEX], |
82b0f4b7 | 355 | BIT(0), 0); |
2d080300 | 356 | PRCC_PCLK_STORE(clk, 3, 0); |
82b0f4b7 | 357 | |
5dc0fe19 | 358 | clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", bases[CLKRST3_INDEX], |
82b0f4b7 | 359 | BIT(1), 0); |
2d080300 | 360 | PRCC_PCLK_STORE(clk, 3, 1); |
82b0f4b7 | 361 | |
5dc0fe19 | 362 | clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", bases[CLKRST3_INDEX], |
82b0f4b7 | 363 | BIT(2), 0); |
2d080300 | 364 | PRCC_PCLK_STORE(clk, 3, 2); |
82b0f4b7 | 365 | |
5dc0fe19 | 366 | clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", bases[CLKRST3_INDEX], |
82b0f4b7 | 367 | BIT(3), 0); |
2d080300 | 368 | PRCC_PCLK_STORE(clk, 3, 3); |
82b0f4b7 | 369 | |
5dc0fe19 | 370 | clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", bases[CLKRST3_INDEX], |
82b0f4b7 | 371 | BIT(4), 0); |
2d080300 | 372 | PRCC_PCLK_STORE(clk, 3, 4); |
82b0f4b7 | 373 | |
5dc0fe19 | 374 | clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", bases[CLKRST3_INDEX], |
82b0f4b7 | 375 | BIT(5), 0); |
2d080300 | 376 | PRCC_PCLK_STORE(clk, 3, 5); |
82b0f4b7 | 377 | |
5dc0fe19 | 378 | clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", bases[CLKRST3_INDEX], |
82b0f4b7 | 379 | BIT(6), 0); |
2d080300 | 380 | PRCC_PCLK_STORE(clk, 3, 6); |
82b0f4b7 | 381 | |
5dc0fe19 | 382 | clk = clk_reg_prcc_pclk("p3_pclk7", "per3clk", bases[CLKRST3_INDEX], |
82b0f4b7 | 383 | BIT(7), 0); |
2d080300 | 384 | PRCC_PCLK_STORE(clk, 3, 7); |
82b0f4b7 | 385 | |
5dc0fe19 | 386 | clk = clk_reg_prcc_pclk("p3_pclk8", "per3clk", bases[CLKRST3_INDEX], |
82b0f4b7 | 387 | BIT(8), 0); |
2d080300 | 388 | PRCC_PCLK_STORE(clk, 3, 8); |
82b0f4b7 | 389 | |
5dc0fe19 | 390 | clk = clk_reg_prcc_pclk("p5_pclk0", "per5clk", bases[CLKRST5_INDEX], |
82b0f4b7 | 391 | BIT(0), 0); |
2d080300 | 392 | PRCC_PCLK_STORE(clk, 5, 0); |
82b0f4b7 | 393 | |
5dc0fe19 | 394 | clk = clk_reg_prcc_pclk("p5_pclk1", "per5clk", bases[CLKRST5_INDEX], |
82b0f4b7 | 395 | BIT(1), 0); |
2d080300 | 396 | PRCC_PCLK_STORE(clk, 5, 1); |
82b0f4b7 | 397 | |
5dc0fe19 | 398 | clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", bases[CLKRST6_INDEX], |
82b0f4b7 | 399 | BIT(0), 0); |
2d080300 | 400 | PRCC_PCLK_STORE(clk, 6, 0); |
82b0f4b7 | 401 | |
5dc0fe19 | 402 | clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", bases[CLKRST6_INDEX], |
82b0f4b7 | 403 | BIT(1), 0); |
2d080300 | 404 | PRCC_PCLK_STORE(clk, 6, 1); |
82b0f4b7 | 405 | |
5dc0fe19 | 406 | clk = clk_reg_prcc_pclk("p6_pclk2", "per6clk", bases[CLKRST6_INDEX], |
82b0f4b7 | 407 | BIT(2), 0); |
2d080300 | 408 | PRCC_PCLK_STORE(clk, 6, 2); |
82b0f4b7 | 409 | |
5dc0fe19 | 410 | clk = clk_reg_prcc_pclk("p6_pclk3", "per6clk", bases[CLKRST6_INDEX], |
82b0f4b7 | 411 | BIT(3), 0); |
2d080300 | 412 | PRCC_PCLK_STORE(clk, 6, 3); |
82b0f4b7 | 413 | |
5dc0fe19 | 414 | clk = clk_reg_prcc_pclk("p6_pclk4", "per6clk", bases[CLKRST6_INDEX], |
82b0f4b7 | 415 | BIT(4), 0); |
2d080300 | 416 | PRCC_PCLK_STORE(clk, 6, 4); |
82b0f4b7 | 417 | |
5dc0fe19 | 418 | clk = clk_reg_prcc_pclk("p6_pclk5", "per6clk", bases[CLKRST6_INDEX], |
82b0f4b7 | 419 | BIT(5), 0); |
2d080300 | 420 | PRCC_PCLK_STORE(clk, 6, 5); |
82b0f4b7 | 421 | |
5dc0fe19 | 422 | clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", bases[CLKRST6_INDEX], |
82b0f4b7 | 423 | BIT(6), 0); |
2d080300 | 424 | PRCC_PCLK_STORE(clk, 6, 6); |
82b0f4b7 | 425 | |
5dc0fe19 | 426 | clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", bases[CLKRST6_INDEX], |
82b0f4b7 | 427 | BIT(7), 0); |
2d080300 | 428 | PRCC_PCLK_STORE(clk, 6, 7); |
82b0f4b7 LJ |
429 | |
430 | /* PRCC K-clocks | |
431 | * | |
432 | * FIXME: Some drivers requires PERPIH[n| to be automatically enabled | |
433 | * by enabling just the K-clock, even if it is not a valid parent to | |
434 | * the K-clock. Until drivers get fixed we might need some kind of | |
435 | * "parent muxed join". | |
436 | */ | |
437 | ||
438 | /* Periph1 */ | |
439 | clk = clk_reg_prcc_kclk("p1_uart0_kclk", "uartclk", | |
5dc0fe19 | 440 | bases[CLKRST1_INDEX], BIT(0), CLK_SET_RATE_GATE); |
89da2dfa | 441 | PRCC_KCLK_STORE(clk, 1, 0); |
82b0f4b7 LJ |
442 | |
443 | clk = clk_reg_prcc_kclk("p1_uart1_kclk", "uartclk", | |
5dc0fe19 | 444 | bases[CLKRST1_INDEX], BIT(1), CLK_SET_RATE_GATE); |
89da2dfa | 445 | PRCC_KCLK_STORE(clk, 1, 1); |
82b0f4b7 LJ |
446 | |
447 | clk = clk_reg_prcc_kclk("p1_i2c1_kclk", "i2cclk", | |
5dc0fe19 | 448 | bases[CLKRST1_INDEX], BIT(2), CLK_SET_RATE_GATE); |
89da2dfa | 449 | PRCC_KCLK_STORE(clk, 1, 2); |
82b0f4b7 LJ |
450 | |
451 | clk = clk_reg_prcc_kclk("p1_msp0_kclk", "msp02clk", | |
5dc0fe19 | 452 | bases[CLKRST1_INDEX], BIT(3), CLK_SET_RATE_GATE); |
89da2dfa | 453 | PRCC_KCLK_STORE(clk, 1, 3); |
82b0f4b7 LJ |
454 | |
455 | clk = clk_reg_prcc_kclk("p1_msp1_kclk", "msp1clk", | |
5dc0fe19 | 456 | bases[CLKRST1_INDEX], BIT(4), CLK_SET_RATE_GATE); |
89da2dfa | 457 | PRCC_KCLK_STORE(clk, 1, 4); |
82b0f4b7 LJ |
458 | |
459 | clk = clk_reg_prcc_kclk("p1_sdi0_kclk", "sdmmcclk", | |
5dc0fe19 | 460 | bases[CLKRST1_INDEX], BIT(5), CLK_SET_RATE_GATE); |
89da2dfa | 461 | PRCC_KCLK_STORE(clk, 1, 5); |
82b0f4b7 LJ |
462 | |
463 | clk = clk_reg_prcc_kclk("p1_i2c2_kclk", "i2cclk", | |
5dc0fe19 | 464 | bases[CLKRST1_INDEX], BIT(6), CLK_SET_RATE_GATE); |
89da2dfa | 465 | PRCC_KCLK_STORE(clk, 1, 6); |
82b0f4b7 LJ |
466 | |
467 | clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk", | |
5dc0fe19 | 468 | bases[CLKRST1_INDEX], BIT(8), CLK_SET_RATE_GATE); |
89da2dfa | 469 | PRCC_KCLK_STORE(clk, 1, 8); |
82b0f4b7 LJ |
470 | |
471 | clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk", | |
5dc0fe19 | 472 | bases[CLKRST1_INDEX], BIT(9), CLK_SET_RATE_GATE); |
89da2dfa | 473 | PRCC_KCLK_STORE(clk, 1, 9); |
82b0f4b7 LJ |
474 | |
475 | clk = clk_reg_prcc_kclk("p1_msp3_kclk", "msp1clk", | |
5dc0fe19 | 476 | bases[CLKRST1_INDEX], BIT(10), CLK_SET_RATE_GATE); |
89da2dfa | 477 | PRCC_KCLK_STORE(clk, 1, 10); |
82b0f4b7 LJ |
478 | |
479 | /* Periph2 */ | |
480 | clk = clk_reg_prcc_kclk("p2_i2c3_kclk", "i2cclk", | |
5dc0fe19 | 481 | bases[CLKRST2_INDEX], BIT(0), CLK_SET_RATE_GATE); |
89da2dfa | 482 | PRCC_KCLK_STORE(clk, 2, 0); |
82b0f4b7 LJ |
483 | |
484 | clk = clk_reg_prcc_kclk("p2_sdi4_kclk", "sdmmcclk", | |
5dc0fe19 | 485 | bases[CLKRST2_INDEX], BIT(2), CLK_SET_RATE_GATE); |
89da2dfa | 486 | PRCC_KCLK_STORE(clk, 2, 2); |
82b0f4b7 LJ |
487 | |
488 | clk = clk_reg_prcc_kclk("p2_msp2_kclk", "msp02clk", | |
5dc0fe19 | 489 | bases[CLKRST2_INDEX], BIT(3), CLK_SET_RATE_GATE); |
89da2dfa | 490 | PRCC_KCLK_STORE(clk, 2, 3); |
82b0f4b7 LJ |
491 | |
492 | clk = clk_reg_prcc_kclk("p2_sdi1_kclk", "sdmmcclk", | |
5dc0fe19 | 493 | bases[CLKRST2_INDEX], BIT(4), CLK_SET_RATE_GATE); |
89da2dfa | 494 | PRCC_KCLK_STORE(clk, 2, 4); |
82b0f4b7 LJ |
495 | |
496 | clk = clk_reg_prcc_kclk("p2_sdi3_kclk", "sdmmcclk", | |
5dc0fe19 | 497 | bases[CLKRST2_INDEX], BIT(5), CLK_SET_RATE_GATE); |
89da2dfa | 498 | PRCC_KCLK_STORE(clk, 2, 5); |
82b0f4b7 LJ |
499 | |
500 | /* Note that rate is received from parent. */ | |
501 | clk = clk_reg_prcc_kclk("p2_ssirx_kclk", "hsirxclk", | |
5dc0fe19 | 502 | bases[CLKRST2_INDEX], BIT(6), |
82b0f4b7 | 503 | CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT); |
89da2dfa LJ |
504 | PRCC_KCLK_STORE(clk, 2, 6); |
505 | ||
82b0f4b7 | 506 | clk = clk_reg_prcc_kclk("p2_ssitx_kclk", "hsitxclk", |
5dc0fe19 | 507 | bases[CLKRST2_INDEX], BIT(7), |
82b0f4b7 | 508 | CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT); |
89da2dfa | 509 | PRCC_KCLK_STORE(clk, 2, 7); |
82b0f4b7 LJ |
510 | |
511 | /* Periph3 */ | |
512 | clk = clk_reg_prcc_kclk("p3_ssp0_kclk", "sspclk", | |
5dc0fe19 | 513 | bases[CLKRST3_INDEX], BIT(1), CLK_SET_RATE_GATE); |
89da2dfa | 514 | PRCC_KCLK_STORE(clk, 3, 1); |
82b0f4b7 LJ |
515 | |
516 | clk = clk_reg_prcc_kclk("p3_ssp1_kclk", "sspclk", | |
5dc0fe19 | 517 | bases[CLKRST3_INDEX], BIT(2), CLK_SET_RATE_GATE); |
89da2dfa | 518 | PRCC_KCLK_STORE(clk, 3, 2); |
82b0f4b7 LJ |
519 | |
520 | clk = clk_reg_prcc_kclk("p3_i2c0_kclk", "i2cclk", | |
5dc0fe19 | 521 | bases[CLKRST3_INDEX], BIT(3), CLK_SET_RATE_GATE); |
89da2dfa | 522 | PRCC_KCLK_STORE(clk, 3, 3); |
82b0f4b7 LJ |
523 | |
524 | clk = clk_reg_prcc_kclk("p3_sdi2_kclk", "sdmmcclk", | |
5dc0fe19 | 525 | bases[CLKRST3_INDEX], BIT(4), CLK_SET_RATE_GATE); |
89da2dfa | 526 | PRCC_KCLK_STORE(clk, 3, 4); |
82b0f4b7 LJ |
527 | |
528 | clk = clk_reg_prcc_kclk("p3_ske_kclk", "rtc32k", | |
5dc0fe19 | 529 | bases[CLKRST3_INDEX], BIT(5), CLK_SET_RATE_GATE); |
89da2dfa | 530 | PRCC_KCLK_STORE(clk, 3, 5); |
82b0f4b7 LJ |
531 | |
532 | clk = clk_reg_prcc_kclk("p3_uart2_kclk", "uartclk", | |
5dc0fe19 | 533 | bases[CLKRST3_INDEX], BIT(6), CLK_SET_RATE_GATE); |
89da2dfa | 534 | PRCC_KCLK_STORE(clk, 3, 6); |
82b0f4b7 LJ |
535 | |
536 | clk = clk_reg_prcc_kclk("p3_sdi5_kclk", "sdmmcclk", | |
5dc0fe19 | 537 | bases[CLKRST3_INDEX], BIT(7), CLK_SET_RATE_GATE); |
89da2dfa | 538 | PRCC_KCLK_STORE(clk, 3, 7); |
82b0f4b7 LJ |
539 | |
540 | /* Periph6 */ | |
541 | clk = clk_reg_prcc_kclk("p3_rng_kclk", "rngclk", | |
5dc0fe19 | 542 | bases[CLKRST6_INDEX], BIT(0), CLK_SET_RATE_GATE); |
89da2dfa | 543 | PRCC_KCLK_STORE(clk, 6, 0); |
dec759d8 LJ |
544 | |
545 | for_each_child_of_node(np, child) { | |
f9fcb8e8 LJ |
546 | static struct clk_onecell_data clk_data; |
547 | ||
548 | if (!of_node_cmp(child->name, "prcmu-clock")) { | |
549 | clk_data.clks = prcmu_clk; | |
550 | clk_data.clk_num = ARRAY_SIZE(prcmu_clk); | |
551 | of_clk_add_provider(child, of_clk_src_onecell_get, &clk_data); | |
552 | } | |
2d080300 LJ |
553 | if (!of_node_cmp(child->name, "prcc-periph-clock")) |
554 | of_clk_add_provider(child, ux500_twocell_get, prcc_pclk); | |
89da2dfa LJ |
555 | |
556 | if (!of_node_cmp(child->name, "prcc-kernel-clock")) | |
557 | of_clk_add_provider(child, ux500_twocell_get, prcc_kclk); | |
d625a730 LJ |
558 | |
559 | if (!of_node_cmp(child->name, "rtc32k-clock")) | |
560 | of_clk_add_provider(child, of_clk_src_simple_get, rtc_clk); | |
4e334660 LJ |
561 | |
562 | if (!of_node_cmp(child->name, "smp-twd-clock")) | |
563 | of_clk_add_provider(child, of_clk_src_simple_get, twd_clk); | |
dec759d8 | 564 | } |
82b0f4b7 | 565 | } |
269f1aac | 566 | CLK_OF_DECLARE(u8500_clks, "stericsson,u8500-clks", u8500_clk_init); |