[linux-2.6-block.git] / drivers / clk / ti / mux.c

/*
 * TI Multiplexer Clock
 *
 * Copyright (C) 2013 Texas Instruments, Inc.
 *
 * Tero Kristo <t-kristo@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/clk-provider.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/clk/ti.h>
#include "clock.h"

#undef pr_fmt
#define pr_fmt(fmt) "%s: " fmt, __func__

static u8 ti_clk_mux_get_parent(struct clk_hw *hw)
{
	struct clk_omap_mux *mux = to_clk_omap_mux(hw);
	int num_parents = clk_hw_get_num_parents(hw);
	u32 val;

	/*
	 * FIXME need a mux-specific flag to determine if val is bitwise or
	 * numeric. e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges
	 * from 0x1 to 0x7 (index starts at one)
	 * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
	 * val = 0x4 really means "bit 2, index starts at bit 0"
	 */
	val = ti_clk_ll_ops->clk_readl(&mux->reg) >> mux->shift;
	val &= mux->mask;

	if (mux->table) {
		int i;

		for (i = 0; i < num_parents; i++)
			if (mux->table[i] == val)
				return i;
		return -EINVAL;
	}

	if (val && (mux->flags & CLK_MUX_INDEX_BIT))
		val = ffs(val) - 1;

	if (val && (mux->flags & CLK_MUX_INDEX_ONE))
		val--;

	if (val >= num_parents)
		return -EINVAL;

	return val;
}

static int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index)
{
	struct clk_omap_mux *mux = to_clk_omap_mux(hw);
	u32 val;

	if (mux->table) {
		index = mux->table[index];
	} else {
		if (mux->flags & CLK_MUX_INDEX_BIT)
			index = (1 << ffs(index));

		if (mux->flags & CLK_MUX_INDEX_ONE)
			index++;
	}

	if (mux->flags & CLK_MUX_HIWORD_MASK) {
		val = mux->mask << (mux->shift + 16);
	} else {
		val = ti_clk_ll_ops->clk_readl(&mux->reg);
		val &= ~(mux->mask << mux->shift);
	}
	val |= index << mux->shift;
	ti_clk_ll_ops->clk_writel(val, &mux->reg);
	ti_clk_latch(&mux->reg, mux->latch);

	return 0;
}

/**
 * clk_mux_save_context - Save the parent selcted in the mux
 * @hw: pointer  struct clk_hw
 *
 * Save the parent mux value.
 */
static int clk_mux_save_context(struct clk_hw *hw)
{
	struct clk_omap_mux *mux = to_clk_omap_mux(hw);

	mux->saved_parent = ti_clk_mux_get_parent(hw);
	return 0;
}

/**
 * clk_mux_restore_context - Restore the parent in the mux
 * @hw: pointer  struct clk_hw
 *
 * Restore the saved parent mux value.
 */
static void clk_mux_restore_context(struct clk_hw *hw)
{
	struct clk_omap_mux *mux = to_clk_omap_mux(hw);

	ti_clk_mux_set_parent(hw, mux->saved_parent);
}

const struct clk_ops ti_clk_mux_ops = {
	.get_parent = ti_clk_mux_get_parent,
	.set_parent = ti_clk_mux_set_parent,
	.determine_rate = __clk_mux_determine_rate,
	.save_context = clk_mux_save_context,
	.restore_context = clk_mux_restore_context,
};

static struct clk *_register_mux(struct device *dev, const char *name,
				 const char * const *parent_names,
				 u8 num_parents, unsigned long flags,
				 struct clk_omap_reg *reg, u8 shift, u32 mask,
				 s8 latch, u8 clk_mux_flags, u32 *table)
{
	struct clk_omap_mux *mux;
	struct clk *clk;
	struct clk_init_data init;

	/* allocate the mux */
	mux = kzalloc(sizeof(*mux), GFP_KERNEL);
	if (!mux)
		return ERR_PTR(-ENOMEM);

	init.name = name;
	init.ops = &ti_clk_mux_ops;
	init.flags = flags;
	init.parent_names = parent_names;
	init.num_parents = num_parents;

	/* struct clk_mux assignments */
	memcpy(&mux->reg, reg, sizeof(*reg));
	mux->shift = shift;
	mux->mask = mask;
	mux->latch = latch;
	mux->flags = clk_mux_flags;
	mux->table = table;
	mux->hw.init = &init;

	clk = ti_clk_register(dev, &mux->hw, name);

	if (IS_ERR(clk))
		kfree(mux);

	return clk;
}

/**
 * of_mux_clk_setup - Setup function for simple mux rate clock
 * @node: DT node for the clock
 *
 * Sets up a basic clock multiplexer.
 */
static void of_mux_clk_setup(struct device_node *node)
{
	struct clk *clk;
	struct clk_omap_reg reg;
	unsigned int num_parents;
	const char **parent_names;
	u8 clk_mux_flags = 0;
	u32 mask = 0;
	u32 shift = 0;
	s32 latch = -EINVAL;
	u32 flags = CLK_SET_RATE_NO_REPARENT;

	num_parents = of_clk_get_parent_count(node);
	if (num_parents < 2) {
		pr_err("mux-clock %pOFn must have parents\n", node);
		return;
	}
	parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL);
	if (!parent_names)
		goto cleanup;

	of_clk_parent_fill(node, parent_names, num_parents);

	if (ti_clk_get_reg_addr(node, 0, &reg))
		goto cleanup;

	of_property_read_u32(node, "ti,bit-shift", &shift);

	of_property_read_u32(node, "ti,latch-bit", &latch);

	if (of_property_read_bool(node, "ti,index-starts-at-one"))
		clk_mux_flags |= CLK_MUX_INDEX_ONE;

	if (of_property_read_bool(node, "ti,set-rate-parent"))
		flags |= CLK_SET_RATE_PARENT;

	/* Generate bit-mask based on parent info */
	mask = num_parents;
	if (!(clk_mux_flags & CLK_MUX_INDEX_ONE))
		mask--;

	mask = (1 << fls(mask)) - 1;

	clk = _register_mux(NULL, node->name, parent_names, num_parents,
			    flags, &reg, shift, mask, latch, clk_mux_flags,
			    NULL);

	if (!IS_ERR(clk))
		of_clk_add_provider(node, of_clk_src_simple_get, clk);

cleanup:
	kfree(parent_names);
}
CLK_OF_DECLARE(mux_clk, "ti,mux-clock", of_mux_clk_setup);

struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup)
{
	struct clk_omap_mux *mux;
	int num_parents;

	if (!setup)
		return NULL;

	mux = kzalloc(sizeof(*mux), GFP_KERNEL);
	if (!mux)
		return ERR_PTR(-ENOMEM);

	mux->shift = setup->bit_shift;
	mux->latch = -EINVAL;

	mux->reg.index = setup->module;
	mux->reg.offset = setup->reg;

	if (setup->flags & CLKF_INDEX_STARTS_AT_ONE)
		mux->flags |= CLK_MUX_INDEX_ONE;

	num_parents = setup->num_parents;

	mux->mask = num_parents - 1;
	mux->mask = (1 << fls(mux->mask)) - 1;

	return &mux->hw;
}

static void __init of_ti_composite_mux_clk_setup(struct device_node *node)
{
	struct clk_omap_mux *mux;
	unsigned int num_parents;
	u32 val;

	mux = kzalloc(sizeof(*mux), GFP_KERNEL);
	if (!mux)
		return;

	if (ti_clk_get_reg_addr(node, 0, &mux->reg))
		goto cleanup;

	if (!of_property_read_u32(node, "ti,bit-shift", &val))
		mux->shift = val;

	if (of_property_read_bool(node, "ti,index-starts-at-one"))
		mux->flags |= CLK_MUX_INDEX_ONE;

	num_parents = of_clk_get_parent_count(node);

	if (num_parents < 2) {
		pr_err("%pOFn must have parents\n", node);
		goto cleanup;
	}

	mux->mask = num_parents - 1;
	mux->mask = (1 << fls(mux->mask)) - 1;

	if (!ti_clk_add_component(node, &mux->hw, CLK_COMPONENT_TYPE_MUX))
		return;

cleanup:
	kfree(mux);
}
CLK_OF_DECLARE(ti_composite_mux_clk_setup, "ti,composite-mux-clock",
	       of_ti_composite_mux_clk_setup);
Commit	Line	Data
6a369c58 TK	1	/*
	2	* TI Multiplexer Clock
	3	*
	4	* Copyright (C) 2013 Texas Instruments, Inc.
	5	*
	6	* Tero Kristo <t-kristo@ti.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*
	12	* This program is distributed "as is" WITHOUT ANY WARRANTY of any
	13	* kind, whether express or implied; without even the implied warranty
	14	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*/
	17
	18	#include <linux/clk-provider.h>
	19	#include <linux/slab.h>
	20	#include <linux/err.h>
	21	#include <linux/of.h>
	22	#include <linux/of_address.h>
	23	#include <linux/clk/ti.h>
7c18a65c	24	#include "clock.h"
6a369c58 TK	25
	26	#undef pr_fmt
	27	#define pr_fmt(fmt) "%s: " fmt, __func__
	28
6a369c58 TK	29	static u8 ti_clk_mux_get_parent(struct clk_hw *hw)
6a369c58 TK	30	{
d83bc5b6	31	struct clk_omap_mux *mux = to_clk_omap_mux(hw);
497295af	32	int num_parents = clk_hw_get_num_parents(hw);
6a369c58 TK	33	u32 val;
	34
	35	/*
	36	* FIXME need a mux-specific flag to determine if val is bitwise or
	37	* numeric. e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges
	38	* from 0x1 to 0x7 (index starts at one)
	39	* OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
	40	* val = 0x4 really means "bit 2, index starts at bit 0"
	41	*/
6c0afb50	42	val = ti_clk_ll_ops->clk_readl(&mux->reg) >> mux->shift;
6a369c58 TK	43	val &= mux->mask;
	44
	45	if (mux->table) {
	46	int i;
	47
	48	for (i = 0; i < num_parents; i++)
	49	if (mux->table[i] == val)
	50	return i;
	51	return -EINVAL;
	52	}
	53
	54	if (val && (mux->flags & CLK_MUX_INDEX_BIT))
	55	val = ffs(val) - 1;
	56
	57	if (val && (mux->flags & CLK_MUX_INDEX_ONE))
	58	val--;
	59
	60	if (val >= num_parents)
	61	return -EINVAL;
	62
	63	return val;
	64	}
	65
	66	static int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index)
	67	{
d83bc5b6	68	struct clk_omap_mux *mux = to_clk_omap_mux(hw);
6a369c58	69	u32 val;
6a369c58 TK	70
	71	if (mux->table) {
	72	index = mux->table[index];
	73	} else {
	74	if (mux->flags & CLK_MUX_INDEX_BIT)
	75	index = (1 << ffs(index));
	76
	77	if (mux->flags & CLK_MUX_INDEX_ONE)
	78	index++;
	79	}
	80
6a369c58 TK	81	if (mux->flags & CLK_MUX_HIWORD_MASK) {
	82	val = mux->mask << (mux->shift + 16);
	83	} else {
6c0afb50	84	val = ti_clk_ll_ops->clk_readl(&mux->reg);
6a369c58 TK	85	val &= ~(mux->mask << mux->shift);
	86	}
	87	val \|= index << mux->shift;
6c0afb50	88	ti_clk_ll_ops->clk_writel(val, &mux->reg);
ee2fc3c5	89	ti_clk_latch(&mux->reg, mux->latch);
6a369c58	90
6a369c58 TK	91	return 0;
	92	}
	93
d6e7bbc1 RD	94	/**
	95	* clk_mux_save_context - Save the parent selcted in the mux
	96	* @hw: pointer struct clk_hw
	97	*
	98	* Save the parent mux value.
	99	*/
	100	static int clk_mux_save_context(struct clk_hw *hw)
	101	{
	102	struct clk_omap_mux *mux = to_clk_omap_mux(hw);
	103
	104	mux->saved_parent = ti_clk_mux_get_parent(hw);
	105	return 0;
	106	}
	107
	108	/**
	109	* clk_mux_restore_context - Restore the parent in the mux
	110	* @hw: pointer struct clk_hw
	111	*
	112	* Restore the saved parent mux value.
	113	*/
	114	static void clk_mux_restore_context(struct clk_hw *hw)
	115	{
	116	struct clk_omap_mux *mux = to_clk_omap_mux(hw);
	117
	118	ti_clk_mux_set_parent(hw, mux->saved_parent);
	119	}
	120
6a369c58 TK	121	const struct clk_ops ti_clk_mux_ops = {
	122	.get_parent = ti_clk_mux_get_parent,
	123	.set_parent = ti_clk_mux_set_parent,
	124	.determine_rate = __clk_mux_determine_rate,
d6e7bbc1 RD	125	.save_context = clk_mux_save_context,
d6e7bbc1 RD	126	.restore_context = clk_mux_restore_context,
6a369c58 TK	127	};
	128
	129	static struct clk _register_mux(struct device dev, const char *name,
ce382d47 TK	130	const char * const *parent_names,
ce382d47 TK	131	u8 num_parents, unsigned long flags,
6c0afb50	132	struct clk_omap_reg *reg, u8 shift, u32 mask,
ee2fc3c5	133	s8 latch, u8 clk_mux_flags, u32 *table)
6a369c58	134	{
d83bc5b6	135	struct clk_omap_mux *mux;
6a369c58 TK	136	struct clk *clk;
	137	struct clk_init_data init;
	138
	139	/* allocate the mux */
	140	mux = kzalloc(sizeof(*mux), GFP_KERNEL);
f80c8a29	141	if (!mux)
6a369c58	142	return ERR_PTR(-ENOMEM);
6a369c58 TK	143
	144	init.name = name;
	145	init.ops = &ti_clk_mux_ops;
8aa09cf3	146	init.flags = flags;
6a369c58 TK	147	init.parent_names = parent_names;
	148	init.num_parents = num_parents;
	149
	150	/* struct clk_mux assignments */
6c0afb50	151	memcpy(&mux->reg, reg, sizeof(*reg));
6a369c58 TK	152	mux->shift = shift;
6a369c58 TK	153	mux->mask = mask;
ee2fc3c5	154	mux->latch = latch;
6a369c58	155	mux->flags = clk_mux_flags;
6a369c58 TK	156	mux->table = table;
	157	mux->hw.init = &init;
	158
1ae79c46	159	clk = ti_clk_register(dev, &mux->hw, name);
6a369c58 TK	160
	161	if (IS_ERR(clk))
	162	kfree(mux);
	163
	164	return clk;
	165	}
	166
	167	/**
	168	* of_mux_clk_setup - Setup function for simple mux rate clock
	169	* @node: DT node for the clock
	170	*
	171	* Sets up a basic clock multiplexer.
	172	*/
	173	static void of_mux_clk_setup(struct device_node *node)
	174	{
	175	struct clk *clk;
6c0afb50	176	struct clk_omap_reg reg;
921bacfa	177	unsigned int num_parents;
6a369c58	178	const char **parent_names;
6a369c58 TK	179	u8 clk_mux_flags = 0;
	180	u32 mask = 0;
	181	u32 shift = 0;
ee2fc3c5	182	s32 latch = -EINVAL;
7d5fc85d	183	u32 flags = CLK_SET_RATE_NO_REPARENT;
6a369c58 TK	184
	185	num_parents = of_clk_get_parent_count(node);
	186	if (num_parents < 2) {
e665f029	187	pr_err("mux-clock %pOFn must have parents\n", node);
6a369c58 TK	188	return;
	189	}
	190	parent_names = kzalloc((sizeof(char ) num_parents), GFP_KERNEL);
	191	if (!parent_names)
	192	goto cleanup;
	193
9da9e761	194	of_clk_parent_fill(node, parent_names, num_parents);
6a369c58	195
6c0afb50	196	if (ti_clk_get_reg_addr(node, 0, &reg))
6a369c58 TK	197	goto cleanup;
	198
	199	of_property_read_u32(node, "ti,bit-shift", &shift);
	200
ee2fc3c5 TK	201	of_property_read_u32(node, "ti,latch-bit", &latch);
ee2fc3c5 TK	202
6a369c58 TK	203	if (of_property_read_bool(node, "ti,index-starts-at-one"))
	204	clk_mux_flags \|= CLK_MUX_INDEX_ONE;
	205
	206	if (of_property_read_bool(node, "ti,set-rate-parent"))
	207	flags \|= CLK_SET_RATE_PARENT;
	208
	209	/* Generate bit-mask based on parent info */
	210	mask = num_parents;
	211	if (!(clk_mux_flags & CLK_MUX_INDEX_ONE))
	212	mask--;
	213
	214	mask = (1 << fls(mask)) - 1;
	215
7c18a65c	216	clk = _register_mux(NULL, node->name, parent_names, num_parents,
ee2fc3c5 TK	217	flags, &reg, shift, mask, latch, clk_mux_flags,
ee2fc3c5 TK	218	NULL);
6a369c58 TK	219
	220	if (!IS_ERR(clk))
	221	of_clk_add_provider(node, of_clk_src_simple_get, clk);
	222
	223	cleanup:
	224	kfree(parent_names);
	225	}
	226	CLK_OF_DECLARE(mux_clk, "ti,mux-clock", of_mux_clk_setup);
	227
7c18a65c TK	228	struct clk_hw ti_clk_build_component_mux(struct ti_clk_mux setup)
7c18a65c TK	229	{
d83bc5b6	230	struct clk_omap_mux *mux;
7c18a65c TK	231	int num_parents;
	232
	233	if (!setup)
	234	return NULL;
	235
	236	mux = kzalloc(sizeof(*mux), GFP_KERNEL);
	237	if (!mux)
	238	return ERR_PTR(-ENOMEM);
	239
7c18a65c	240	mux->shift = setup->bit_shift;
ee2fc3c5	241	mux->latch = -EINVAL;
7c18a65c	242
6c0afb50 TK	243	mux->reg.index = setup->module;
6c0afb50 TK	244	mux->reg.offset = setup->reg;
7c18a65c TK	245
	246	if (setup->flags & CLKF_INDEX_STARTS_AT_ONE)
	247	mux->flags \|= CLK_MUX_INDEX_ONE;
	248
	249	num_parents = setup->num_parents;
	250
	251	mux->mask = num_parents - 1;
	252	mux->mask = (1 << fls(mux->mask)) - 1;
	253
	254	return &mux->hw;
	255	}
	256
6a369c58 TK	257	static void __init of_ti_composite_mux_clk_setup(struct device_node *node)
6a369c58 TK	258	{
d83bc5b6	259	struct clk_omap_mux *mux;
921bacfa	260	unsigned int num_parents;
6a369c58 TK	261	u32 val;
	262
	263	mux = kzalloc(sizeof(*mux), GFP_KERNEL);
	264	if (!mux)
	265	return;
	266
6c0afb50	267	if (ti_clk_get_reg_addr(node, 0, &mux->reg))
6a369c58 TK	268	goto cleanup;
	269
	270	if (!of_property_read_u32(node, "ti,bit-shift", &val))
	271	mux->shift = val;
	272
	273	if (of_property_read_bool(node, "ti,index-starts-at-one"))
	274	mux->flags \|= CLK_MUX_INDEX_ONE;
	275
	276	num_parents = of_clk_get_parent_count(node);
	277
	278	if (num_parents < 2) {
e665f029	279	pr_err("%pOFn must have parents\n", node);
6a369c58 TK	280	goto cleanup;
	281	}
	282
	283	mux->mask = num_parents - 1;
	284	mux->mask = (1 << fls(mux->mask)) - 1;
	285
	286	if (!ti_clk_add_component(node, &mux->hw, CLK_COMPONENT_TYPE_MUX))
	287	return;
	288
	289	cleanup:
	290	kfree(mux);
	291	}
	292	CLK_OF_DECLARE(ti_composite_mux_clk_setup, "ti,composite-mux-clock",
	293	of_ti_composite_mux_clk_setup);