Commit | Line | Data |
---|---|---|
a1391d27 RN |
1 | /* |
2 | * OMAP3/4 - specific DPLL control functions | |
3 | * | |
358965d7 RW |
4 | * Copyright (C) 2009-2010 Texas Instruments, Inc. |
5 | * Copyright (C) 2009-2010 Nokia Corporation | |
a1391d27 RN |
6 | * |
7 | * Written by Paul Walmsley | |
358965d7 RW |
8 | * Testing and integration fixes by Jouni Högander |
9 | * | |
10 | * 36xx support added by Vishwanath BS, Richard Woodruff, and Nishanth | |
11 | * Menon | |
a1391d27 RN |
12 | * |
13 | * Parts of this code are based on code written by | |
14 | * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License version 2 as | |
18 | * published by the Free Software Foundation. | |
19 | */ | |
20 | ||
a1391d27 RN |
21 | #include <linux/kernel.h> |
22 | #include <linux/device.h> | |
23 | #include <linux/list.h> | |
24 | #include <linux/errno.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/clk.h> | |
27 | #include <linux/io.h> | |
a1391d27 | 28 | #include <linux/bitops.h> |
6d803ba7 | 29 | #include <linux/clkdev.h> |
0565fb16 | 30 | #include <linux/clk/ti.h> |
a1391d27 | 31 | |
a1391d27 | 32 | #include "clock.h" |
a1391d27 RN |
33 | |
34 | /* CM_AUTOIDLE_PLL*.AUTO_* bit values */ | |
35 | #define DPLL_AUTOIDLE_DISABLE 0x0 | |
36 | #define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1 | |
37 | ||
38 | #define MAX_DPLL_WAIT_TRIES 1000000 | |
39 | ||
0565fb16 TK |
40 | #define OMAP3XXX_EN_DPLL_LOCKED 0x7 |
41 | ||
42 | /* Forward declarations */ | |
43 | static u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk); | |
44 | static void omap3_dpll_deny_idle(struct clk_hw_omap *clk); | |
45 | static void omap3_dpll_allow_idle(struct clk_hw_omap *clk); | |
46 | ||
60c3f651 | 47 | /* Private functions */ |
a1391d27 RN |
48 | |
49 | /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */ | |
32cc0021 | 50 | static void _omap3_dpll_write_clken(struct clk_hw_omap *clk, u8 clken_bits) |
a1391d27 RN |
51 | { |
52 | const struct dpll_data *dd; | |
53 | u32 v; | |
54 | ||
55 | dd = clk->dpll_data; | |
56 | ||
0565fb16 | 57 | v = ti_clk_ll_ops->clk_readl(dd->control_reg); |
a1391d27 RN |
58 | v &= ~dd->enable_mask; |
59 | v |= clken_bits << __ffs(dd->enable_mask); | |
0565fb16 | 60 | ti_clk_ll_ops->clk_writel(v, dd->control_reg); |
a1391d27 RN |
61 | } |
62 | ||
63 | /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */ | |
32cc0021 | 64 | static int _omap3_wait_dpll_status(struct clk_hw_omap *clk, u8 state) |
a1391d27 RN |
65 | { |
66 | const struct dpll_data *dd; | |
67 | int i = 0; | |
68 | int ret = -EINVAL; | |
5dcc3b97 | 69 | const char *clk_name; |
a1391d27 RN |
70 | |
71 | dd = clk->dpll_data; | |
a53ad8ef | 72 | clk_name = clk_hw_get_name(&clk->hw); |
a1391d27 RN |
73 | |
74 | state <<= __ffs(dd->idlest_mask); | |
75 | ||
0565fb16 | 76 | while (((ti_clk_ll_ops->clk_readl(dd->idlest_reg) & dd->idlest_mask) |
519ab8b2 | 77 | != state) && i < MAX_DPLL_WAIT_TRIES) { |
a1391d27 RN |
78 | i++; |
79 | udelay(1); | |
80 | } | |
81 | ||
82 | if (i == MAX_DPLL_WAIT_TRIES) { | |
0565fb16 | 83 | pr_err("clock: %s failed transition to '%s'\n", |
5dcc3b97 | 84 | clk_name, (state) ? "locked" : "bypassed"); |
a1391d27 RN |
85 | } else { |
86 | pr_debug("clock: %s transition to '%s' in %d loops\n", | |
5dcc3b97 | 87 | clk_name, (state) ? "locked" : "bypassed", i); |
a1391d27 RN |
88 | |
89 | ret = 0; | |
90 | } | |
91 | ||
92 | return ret; | |
93 | } | |
94 | ||
95 | /* From 3430 TRM ES2 4.7.6.2 */ | |
32cc0021 | 96 | static u16 _omap3_dpll_compute_freqsel(struct clk_hw_omap *clk, u8 n) |
a1391d27 RN |
97 | { |
98 | unsigned long fint; | |
99 | u16 f = 0; | |
100 | ||
b6f51284 | 101 | fint = clk_hw_get_rate(clk->dpll_data->clk_ref) / n; |
a1391d27 RN |
102 | |
103 | pr_debug("clock: fint is %lu\n", fint); | |
104 | ||
105 | if (fint >= 750000 && fint <= 1000000) | |
106 | f = 0x3; | |
107 | else if (fint > 1000000 && fint <= 1250000) | |
108 | f = 0x4; | |
109 | else if (fint > 1250000 && fint <= 1500000) | |
110 | f = 0x5; | |
111 | else if (fint > 1500000 && fint <= 1750000) | |
112 | f = 0x6; | |
113 | else if (fint > 1750000 && fint <= 2100000) | |
114 | f = 0x7; | |
115 | else if (fint > 7500000 && fint <= 10000000) | |
116 | f = 0xB; | |
117 | else if (fint > 10000000 && fint <= 12500000) | |
118 | f = 0xC; | |
119 | else if (fint > 12500000 && fint <= 15000000) | |
120 | f = 0xD; | |
121 | else if (fint > 15000000 && fint <= 17500000) | |
122 | f = 0xE; | |
123 | else if (fint > 17500000 && fint <= 21000000) | |
124 | f = 0xF; | |
125 | else | |
126 | pr_debug("clock: unknown freqsel setting for %d\n", n); | |
127 | ||
128 | return f; | |
129 | } | |
130 | ||
a1391d27 RN |
131 | /* |
132 | * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness | |
133 | * @clk: pointer to a DPLL struct clk | |
134 | * | |
135 | * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report | |
136 | * readiness before returning. Will save and restore the DPLL's | |
137 | * autoidle state across the enable, per the CDP code. If the DPLL | |
138 | * locked successfully, return 0; if the DPLL did not lock in the time | |
139 | * allotted, or DPLL3 was passed in, return -EINVAL. | |
140 | */ | |
32cc0021 | 141 | static int _omap3_noncore_dpll_lock(struct clk_hw_omap *clk) |
a1391d27 | 142 | { |
55ffe163 | 143 | const struct dpll_data *dd; |
a1391d27 | 144 | u8 ai; |
55ffe163 VP |
145 | u8 state = 1; |
146 | int r = 0; | |
a1391d27 | 147 | |
a53ad8ef | 148 | pr_debug("clock: locking DPLL %s\n", clk_hw_get_name(&clk->hw)); |
a1391d27 | 149 | |
55ffe163 VP |
150 | dd = clk->dpll_data; |
151 | state <<= __ffs(dd->idlest_mask); | |
152 | ||
153 | /* Check if already locked */ | |
0565fb16 TK |
154 | if ((ti_clk_ll_ops->clk_readl(dd->idlest_reg) & dd->idlest_mask) == |
155 | state) | |
55ffe163 VP |
156 | goto done; |
157 | ||
a1391d27 RN |
158 | ai = omap3_dpll_autoidle_read(clk); |
159 | ||
d76316fe VB |
160 | if (ai) |
161 | omap3_dpll_deny_idle(clk); | |
a1391d27 RN |
162 | |
163 | _omap3_dpll_write_clken(clk, DPLL_LOCKED); | |
164 | ||
165 | r = _omap3_wait_dpll_status(clk, 1); | |
166 | ||
167 | if (ai) | |
168 | omap3_dpll_allow_idle(clk); | |
169 | ||
55ffe163 | 170 | done: |
a1391d27 RN |
171 | return r; |
172 | } | |
173 | ||
174 | /* | |
175 | * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness | |
176 | * @clk: pointer to a DPLL struct clk | |
177 | * | |
178 | * Instructs a non-CORE DPLL to enter low-power bypass mode. In | |
179 | * bypass mode, the DPLL's rate is set equal to its parent clock's | |
180 | * rate. Waits for the DPLL to report readiness before returning. | |
181 | * Will save and restore the DPLL's autoidle state across the enable, | |
182 | * per the CDP code. If the DPLL entered bypass mode successfully, | |
183 | * return 0; if the DPLL did not enter bypass in the time allotted, or | |
184 | * DPLL3 was passed in, or the DPLL does not support low-power bypass, | |
185 | * return -EINVAL. | |
186 | */ | |
32cc0021 | 187 | static int _omap3_noncore_dpll_bypass(struct clk_hw_omap *clk) |
a1391d27 RN |
188 | { |
189 | int r; | |
190 | u8 ai; | |
191 | ||
192 | if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) | |
193 | return -EINVAL; | |
194 | ||
195 | pr_debug("clock: configuring DPLL %s for low-power bypass\n", | |
a53ad8ef | 196 | clk_hw_get_name(&clk->hw)); |
a1391d27 RN |
197 | |
198 | ai = omap3_dpll_autoidle_read(clk); | |
199 | ||
200 | _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS); | |
201 | ||
202 | r = _omap3_wait_dpll_status(clk, 0); | |
203 | ||
204 | if (ai) | |
205 | omap3_dpll_allow_idle(clk); | |
a1391d27 RN |
206 | |
207 | return r; | |
208 | } | |
209 | ||
210 | /* | |
211 | * _omap3_noncore_dpll_stop - instruct a DPLL to stop | |
212 | * @clk: pointer to a DPLL struct clk | |
213 | * | |
214 | * Instructs a non-CORE DPLL to enter low-power stop. Will save and | |
215 | * restore the DPLL's autoidle state across the stop, per the CDP | |
216 | * code. If DPLL3 was passed in, or the DPLL does not support | |
217 | * low-power stop, return -EINVAL; otherwise, return 0. | |
218 | */ | |
32cc0021 | 219 | static int _omap3_noncore_dpll_stop(struct clk_hw_omap *clk) |
a1391d27 RN |
220 | { |
221 | u8 ai; | |
222 | ||
223 | if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP))) | |
224 | return -EINVAL; | |
225 | ||
a53ad8ef | 226 | pr_debug("clock: stopping DPLL %s\n", clk_hw_get_name(&clk->hw)); |
a1391d27 RN |
227 | |
228 | ai = omap3_dpll_autoidle_read(clk); | |
229 | ||
230 | _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP); | |
231 | ||
232 | if (ai) | |
233 | omap3_dpll_allow_idle(clk); | |
a1391d27 RN |
234 | |
235 | return 0; | |
236 | } | |
237 | ||
358965d7 | 238 | /** |
a36795c1 | 239 | * _lookup_dco - Lookup DCO used by j-type DPLL |
358965d7 RW |
240 | * @clk: pointer to a DPLL struct clk |
241 | * @dco: digital control oscillator selector | |
358965d7 RW |
242 | * @m: DPLL multiplier to set |
243 | * @n: DPLL divider to set | |
244 | * | |
245 | * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)" | |
246 | * | |
247 | * XXX This code is not needed for 3430/AM35xx; can it be optimized | |
248 | * out in non-multi-OMAP builds for those chips? | |
249 | */ | |
32cc0021 | 250 | static void _lookup_dco(struct clk_hw_omap *clk, u8 *dco, u16 m, u8 n) |
358965d7 | 251 | { |
a36795c1 | 252 | unsigned long fint, clkinp; /* watch out for overflow */ |
358965d7 | 253 | |
a53ad8ef | 254 | clkinp = clk_hw_get_rate(clk_hw_get_parent(&clk->hw)); |
358965d7 RW |
255 | fint = (clkinp / n) * m; |
256 | ||
257 | if (fint < 1000000000) | |
258 | *dco = 2; | |
259 | else | |
260 | *dco = 4; | |
a36795c1 JH |
261 | } |
262 | ||
263 | /** | |
264 | * _lookup_sddiv - Calculate sigma delta divider for j-type DPLL | |
265 | * @clk: pointer to a DPLL struct clk | |
266 | * @sd_div: target sigma-delta divider | |
267 | * @m: DPLL multiplier to set | |
268 | * @n: DPLL divider to set | |
269 | * | |
270 | * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)" | |
271 | * | |
272 | * XXX This code is not needed for 3430/AM35xx; can it be optimized | |
273 | * out in non-multi-OMAP builds for those chips? | |
274 | */ | |
32cc0021 | 275 | static void _lookup_sddiv(struct clk_hw_omap *clk, u8 *sd_div, u16 m, u8 n) |
a36795c1 JH |
276 | { |
277 | unsigned long clkinp, sd; /* watch out for overflow */ | |
278 | int mod1, mod2; | |
279 | ||
a53ad8ef | 280 | clkinp = clk_hw_get_rate(clk_hw_get_parent(&clk->hw)); |
a36795c1 | 281 | |
358965d7 RW |
282 | /* |
283 | * target sigma-delta to near 250MHz | |
284 | * sd = ceil[(m/(n+1)) * (clkinp_MHz / 250)] | |
285 | */ | |
286 | clkinp /= 100000; /* shift from MHz to 10*Hz for 38.4 and 19.2 */ | |
287 | mod1 = (clkinp * m) % (250 * n); | |
288 | sd = (clkinp * m) / (250 * n); | |
289 | mod2 = sd % 10; | |
290 | sd /= 10; | |
291 | ||
292 | if (mod1 || mod2) | |
293 | sd++; | |
294 | *sd_div = sd; | |
295 | } | |
296 | ||
60c3f651 PW |
297 | /* |
298 | * _omap3_noncore_dpll_program - set non-core DPLL M,N values directly | |
3ff51ed8 JH |
299 | * @clk: struct clk * of DPLL to set |
300 | * @freqsel: FREQSEL value to set | |
60c3f651 | 301 | * |
3ff51ed8 JH |
302 | * Program the DPLL with the last M, N values calculated, and wait for |
303 | * the DPLL to lock. Returns -EINVAL upon error, or 0 upon success. | |
60c3f651 | 304 | */ |
3ff51ed8 | 305 | static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel) |
60c3f651 PW |
306 | { |
307 | struct dpll_data *dd = clk->dpll_data; | |
07ff73a9 | 308 | u8 dco, sd_div, ai = 0; |
60c3f651 | 309 | u32 v; |
07ff73a9 | 310 | bool errata_i810; |
60c3f651 PW |
311 | |
312 | /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */ | |
313 | _omap3_noncore_dpll_bypass(clk); | |
314 | ||
5eb75f55 | 315 | /* |
ecf51648 RN |
316 | * Set jitter correction. Jitter correction applicable for OMAP343X |
317 | * only since freqsel field is no longer present on other devices. | |
5eb75f55 | 318 | */ |
f3b19aa5 | 319 | if (ti_clk_get_features()->flags & TI_CLK_DPLL_HAS_FREQSEL) { |
0565fb16 | 320 | v = ti_clk_ll_ops->clk_readl(dd->control_reg); |
60c3f651 PW |
321 | v &= ~dd->freqsel_mask; |
322 | v |= freqsel << __ffs(dd->freqsel_mask); | |
0565fb16 | 323 | ti_clk_ll_ops->clk_writel(v, dd->control_reg); |
60c3f651 PW |
324 | } |
325 | ||
326 | /* Set DPLL multiplier, divider */ | |
0565fb16 | 327 | v = ti_clk_ll_ops->clk_readl(dd->mult_div1_reg); |
ce369a54 AT |
328 | |
329 | /* Handle Duty Cycle Correction */ | |
330 | if (dd->dcc_mask) { | |
331 | if (dd->last_rounded_rate >= dd->dcc_rate) | |
332 | v |= dd->dcc_mask; /* Enable DCC */ | |
333 | else | |
334 | v &= ~dd->dcc_mask; /* Disable DCC */ | |
335 | } | |
336 | ||
60c3f651 | 337 | v &= ~(dd->mult_mask | dd->div1_mask); |
3ff51ed8 JH |
338 | v |= dd->last_rounded_m << __ffs(dd->mult_mask); |
339 | v |= (dd->last_rounded_n - 1) << __ffs(dd->div1_mask); | |
358965d7 | 340 | |
a36795c1 JH |
341 | /* Configure dco and sd_div for dplls that have these fields */ |
342 | if (dd->dco_mask) { | |
3ff51ed8 | 343 | _lookup_dco(clk, &dco, dd->last_rounded_m, dd->last_rounded_n); |
a36795c1 JH |
344 | v &= ~(dd->dco_mask); |
345 | v |= dco << __ffs(dd->dco_mask); | |
346 | } | |
347 | if (dd->sddiv_mask) { | |
3ff51ed8 JH |
348 | _lookup_sddiv(clk, &sd_div, dd->last_rounded_m, |
349 | dd->last_rounded_n); | |
a36795c1 JH |
350 | v &= ~(dd->sddiv_mask); |
351 | v |= sd_div << __ffs(dd->sddiv_mask); | |
358965d7 RW |
352 | } |
353 | ||
07ff73a9 TK |
354 | /* |
355 | * Errata i810 - DPLL controller can get stuck while transitioning | |
356 | * to a power saving state. Software must ensure the DPLL can not | |
357 | * transition to a low power state while changing M/N values. | |
358 | * Easiest way to accomplish this is to prevent DPLL autoidle | |
359 | * before doing the M/N re-program. | |
360 | */ | |
361 | errata_i810 = ti_clk_get_features()->flags & TI_CLK_ERRATA_I810; | |
362 | ||
363 | if (errata_i810) { | |
364 | ai = omap3_dpll_autoidle_read(clk); | |
365 | if (ai) { | |
366 | omap3_dpll_deny_idle(clk); | |
367 | ||
368 | /* OCP barrier */ | |
369 | omap3_dpll_autoidle_read(clk); | |
370 | } | |
371 | } | |
372 | ||
0565fb16 | 373 | ti_clk_ll_ops->clk_writel(v, dd->mult_div1_reg); |
60c3f651 | 374 | |
3ff51ed8 JH |
375 | /* Set 4X multiplier and low-power mode */ |
376 | if (dd->m4xen_mask || dd->lpmode_mask) { | |
0565fb16 | 377 | v = ti_clk_ll_ops->clk_readl(dd->control_reg); |
3ff51ed8 JH |
378 | |
379 | if (dd->m4xen_mask) { | |
380 | if (dd->last_rounded_m4xen) | |
381 | v |= dd->m4xen_mask; | |
382 | else | |
383 | v &= ~dd->m4xen_mask; | |
384 | } | |
385 | ||
386 | if (dd->lpmode_mask) { | |
387 | if (dd->last_rounded_lpmode) | |
388 | v |= dd->lpmode_mask; | |
389 | else | |
390 | v &= ~dd->lpmode_mask; | |
391 | } | |
392 | ||
0565fb16 | 393 | ti_clk_ll_ops->clk_writel(v, dd->control_reg); |
3ff51ed8 JH |
394 | } |
395 | ||
60c3f651 PW |
396 | /* We let the clock framework set the other output dividers later */ |
397 | ||
398 | /* REVISIT: Set ramp-up delay? */ | |
399 | ||
400 | _omap3_noncore_dpll_lock(clk); | |
401 | ||
07ff73a9 TK |
402 | if (errata_i810 && ai) |
403 | omap3_dpll_allow_idle(clk); | |
404 | ||
60c3f651 PW |
405 | return 0; |
406 | } | |
407 | ||
408 | /* Public functions */ | |
409 | ||
410 | /** | |
411 | * omap3_dpll_recalc - recalculate DPLL rate | |
412 | * @clk: DPLL struct clk | |
413 | * | |
414 | * Recalculate and propagate the DPLL rate. | |
415 | */ | |
32cc0021 MT |
416 | unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate) |
417 | { | |
418 | struct clk_hw_omap *clk = to_clk_hw_omap(hw); | |
455db9c9 | 419 | |
60c3f651 PW |
420 | return omap2_get_dpll_rate(clk); |
421 | } | |
422 | ||
423 | /* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */ | |
424 | ||
a1391d27 RN |
425 | /** |
426 | * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode | |
427 | * @clk: pointer to a DPLL struct clk | |
428 | * | |
429 | * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock. | |
430 | * The choice of modes depends on the DPLL's programmed rate: if it is | |
431 | * the same as the DPLL's parent clock, it will enter bypass; | |
432 | * otherwise, it will enter lock. This code will wait for the DPLL to | |
433 | * indicate readiness before returning, unless the DPLL takes too long | |
434 | * to enter the target state. Intended to be used as the struct clk's | |
435 | * enable function. If DPLL3 was passed in, or the DPLL does not | |
436 | * support low-power stop, or if the DPLL took too long to enter | |
437 | * bypass or lock, return -EINVAL; otherwise, return 0. | |
438 | */ | |
32cc0021 MT |
439 | int omap3_noncore_dpll_enable(struct clk_hw *hw) |
440 | { | |
441 | struct clk_hw_omap *clk = to_clk_hw_omap(hw); | |
a1391d27 RN |
442 | int r; |
443 | struct dpll_data *dd; | |
035a61c3 | 444 | struct clk_hw *parent; |
a1391d27 RN |
445 | |
446 | dd = clk->dpll_data; | |
447 | if (!dd) | |
448 | return -EINVAL; | |
449 | ||
32cc0021 | 450 | if (clk->clkdm) { |
0565fb16 | 451 | r = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk); |
32cc0021 MT |
452 | if (r) { |
453 | WARN(1, | |
454 | "%s: could not enable %s's clockdomain %s: %d\n", | |
a53ad8ef | 455 | __func__, clk_hw_get_name(hw), |
0565fb16 | 456 | clk->clkdm_name, r); |
32cc0021 MT |
457 | return r; |
458 | } | |
459 | } | |
460 | ||
a53ad8ef | 461 | parent = clk_hw_get_parent(hw); |
32cc0021 | 462 | |
b6f51284 TK |
463 | if (clk_hw_get_rate(hw) == clk_hw_get_rate(dd->clk_bypass)) { |
464 | WARN_ON(parent != dd->clk_bypass); | |
a1391d27 RN |
465 | r = _omap3_noncore_dpll_bypass(clk); |
466 | } else { | |
b6f51284 | 467 | WARN_ON(parent != dd->clk_ref); |
a1391d27 RN |
468 | r = _omap3_noncore_dpll_lock(clk); |
469 | } | |
32cc0021 | 470 | |
a1391d27 RN |
471 | return r; |
472 | } | |
473 | ||
474 | /** | |
475 | * omap3_noncore_dpll_disable - instruct a DPLL to enter low-power stop | |
476 | * @clk: pointer to a DPLL struct clk | |
477 | * | |
478 | * Instructs a non-CORE DPLL to enter low-power stop. This function is | |
479 | * intended for use in struct clkops. No return value. | |
480 | */ | |
32cc0021 MT |
481 | void omap3_noncore_dpll_disable(struct clk_hw *hw) |
482 | { | |
483 | struct clk_hw_omap *clk = to_clk_hw_omap(hw); | |
484 | ||
485 | _omap3_noncore_dpll_stop(clk); | |
486 | if (clk->clkdm) | |
0565fb16 | 487 | ti_clk_ll_ops->clkdm_clk_disable(clk->clkdm, hw->clk); |
a1391d27 RN |
488 | } |
489 | ||
a1391d27 RN |
490 | /* Non-CORE DPLL rate set code */ |
491 | ||
d539efa3 TK |
492 | /** |
493 | * omap3_noncore_dpll_determine_rate - determine rate for a DPLL | |
494 | * @hw: pointer to the clock to determine rate for | |
0817b62c | 495 | * @req: target rate request |
d539efa3 TK |
496 | * |
497 | * Determines which DPLL mode to use for reaching a desired target rate. | |
498 | * Checks whether the DPLL shall be in bypass or locked mode, and if | |
499 | * locked, calculates the M,N values for the DPLL via round-rate. | |
0817b62c | 500 | * Returns a 0 on success, negative error value in failure. |
d539efa3 | 501 | */ |
0817b62c BB |
502 | int omap3_noncore_dpll_determine_rate(struct clk_hw *hw, |
503 | struct clk_rate_request *req) | |
d539efa3 TK |
504 | { |
505 | struct clk_hw_omap *clk = to_clk_hw_omap(hw); | |
506 | struct dpll_data *dd; | |
507 | ||
0817b62c | 508 | if (!req->rate) |
d539efa3 TK |
509 | return -EINVAL; |
510 | ||
511 | dd = clk->dpll_data; | |
512 | if (!dd) | |
513 | return -EINVAL; | |
514 | ||
b6f51284 | 515 | if (clk_hw_get_rate(dd->clk_bypass) == req->rate && |
d539efa3 | 516 | (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) { |
b6f51284 | 517 | req->best_parent_hw = dd->clk_bypass; |
d539efa3 | 518 | } else { |
0817b62c BB |
519 | req->rate = omap2_dpll_round_rate(hw, req->rate, |
520 | &req->best_parent_rate); | |
b6f51284 | 521 | req->best_parent_hw = dd->clk_ref; |
d539efa3 TK |
522 | } |
523 | ||
0817b62c | 524 | req->best_parent_rate = req->rate; |
d539efa3 | 525 | |
0817b62c | 526 | return 0; |
d539efa3 TK |
527 | } |
528 | ||
529 | /** | |
530 | * omap3_noncore_dpll_set_parent - set parent for a DPLL clock | |
531 | * @hw: pointer to the clock to set parent for | |
532 | * @index: parent index to select | |
533 | * | |
534 | * Sets parent for a DPLL clock. This sets the DPLL into bypass or | |
535 | * locked mode. Returns 0 with success, negative error value otherwise. | |
536 | */ | |
537 | int omap3_noncore_dpll_set_parent(struct clk_hw *hw, u8 index) | |
538 | { | |
539 | struct clk_hw_omap *clk = to_clk_hw_omap(hw); | |
540 | int ret; | |
541 | ||
542 | if (!hw) | |
543 | return -EINVAL; | |
544 | ||
545 | if (index) | |
546 | ret = _omap3_noncore_dpll_bypass(clk); | |
547 | else | |
548 | ret = _omap3_noncore_dpll_lock(clk); | |
549 | ||
550 | return ret; | |
551 | } | |
552 | ||
553 | /** | |
2e1a7b01 | 554 | * omap3_noncore_dpll_set_rate - set rate for a DPLL clock |
d539efa3 TK |
555 | * @hw: pointer to the clock to set parent for |
556 | * @rate: target rate for the clock | |
557 | * @parent_rate: rate of the parent clock | |
558 | * | |
559 | * Sets rate for a DPLL clock. First checks if the clock parent is | |
560 | * reference clock (in bypass mode, the rate of the clock can't be | |
561 | * changed) and proceeds with the rate change operation. Returns 0 | |
562 | * with success, negative error value otherwise. | |
563 | */ | |
2e1a7b01 TK |
564 | int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, |
565 | unsigned long parent_rate) | |
d539efa3 TK |
566 | { |
567 | struct clk_hw_omap *clk = to_clk_hw_omap(hw); | |
568 | struct dpll_data *dd; | |
569 | u16 freqsel = 0; | |
570 | int ret; | |
571 | ||
572 | if (!hw || !rate) | |
573 | return -EINVAL; | |
574 | ||
575 | dd = clk->dpll_data; | |
576 | if (!dd) | |
577 | return -EINVAL; | |
578 | ||
b6f51284 | 579 | if (clk_hw_get_parent(hw) != dd->clk_ref) |
d539efa3 TK |
580 | return -EINVAL; |
581 | ||
582 | if (dd->last_rounded_rate == 0) | |
583 | return -EINVAL; | |
584 | ||
585 | /* Freqsel is available only on OMAP343X devices */ | |
f3b19aa5 | 586 | if (ti_clk_get_features()->flags & TI_CLK_DPLL_HAS_FREQSEL) { |
d539efa3 TK |
587 | freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n); |
588 | WARN_ON(!freqsel); | |
589 | } | |
590 | ||
591 | pr_debug("%s: %s: set rate: locking rate to %lu.\n", __func__, | |
a53ad8ef | 592 | clk_hw_get_name(hw), rate); |
d539efa3 TK |
593 | |
594 | ret = omap3_noncore_dpll_program(clk, freqsel); | |
595 | ||
596 | return ret; | |
597 | } | |
598 | ||
599 | /** | |
600 | * omap3_noncore_dpll_set_rate_and_parent - set rate and parent for a DPLL clock | |
601 | * @hw: pointer to the clock to set rate and parent for | |
602 | * @rate: target rate for the DPLL | |
603 | * @parent_rate: clock rate of the DPLL parent | |
604 | * @index: new parent index for the DPLL, 0 - reference, 1 - bypass | |
605 | * | |
606 | * Sets rate and parent for a DPLL clock. If new parent is the bypass | |
607 | * clock, only selects the parent. Otherwise proceeds with a rate | |
608 | * change, as this will effectively also change the parent as the | |
609 | * DPLL is put into locked mode. Returns 0 with success, negative error | |
610 | * value otherwise. | |
611 | */ | |
612 | int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw, | |
613 | unsigned long rate, | |
614 | unsigned long parent_rate, | |
615 | u8 index) | |
616 | { | |
617 | int ret; | |
618 | ||
619 | if (!hw || !rate) | |
620 | return -EINVAL; | |
621 | ||
622 | /* | |
623 | * clk-ref at index[0], in which case we only need to set rate, | |
624 | * the parent will be changed automatically with the lock sequence. | |
625 | * With clk-bypass case we only need to change parent. | |
626 | */ | |
627 | if (index) | |
628 | ret = omap3_noncore_dpll_set_parent(hw, index); | |
629 | else | |
2e1a7b01 | 630 | ret = omap3_noncore_dpll_set_rate(hw, rate, parent_rate); |
d539efa3 TK |
631 | |
632 | return ret; | |
633 | } | |
634 | ||
a1391d27 RN |
635 | /* DPLL autoidle read/set code */ |
636 | ||
637 | /** | |
638 | * omap3_dpll_autoidle_read - read a DPLL's autoidle bits | |
639 | * @clk: struct clk * of the DPLL to read | |
640 | * | |
641 | * Return the DPLL's autoidle bits, shifted down to bit 0. Returns | |
642 | * -EINVAL if passed a null pointer or if the struct clk does not | |
643 | * appear to refer to a DPLL. | |
644 | */ | |
0565fb16 | 645 | static u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk) |
a1391d27 RN |
646 | { |
647 | const struct dpll_data *dd; | |
648 | u32 v; | |
649 | ||
650 | if (!clk || !clk->dpll_data) | |
651 | return -EINVAL; | |
652 | ||
653 | dd = clk->dpll_data; | |
654 | ||
d76316fe VB |
655 | if (!dd->autoidle_reg) |
656 | return -EINVAL; | |
657 | ||
0565fb16 | 658 | v = ti_clk_ll_ops->clk_readl(dd->autoidle_reg); |
a1391d27 RN |
659 | v &= dd->autoidle_mask; |
660 | v >>= __ffs(dd->autoidle_mask); | |
661 | ||
662 | return v; | |
663 | } | |
664 | ||
665 | /** | |
666 | * omap3_dpll_allow_idle - enable DPLL autoidle bits | |
667 | * @clk: struct clk * of the DPLL to operate on | |
668 | * | |
669 | * Enable DPLL automatic idle control. This automatic idle mode | |
670 | * switching takes effect only when the DPLL is locked, at least on | |
671 | * OMAP3430. The DPLL will enter low-power stop when its downstream | |
672 | * clocks are gated. No return value. | |
673 | */ | |
0565fb16 | 674 | static void omap3_dpll_allow_idle(struct clk_hw_omap *clk) |
a1391d27 RN |
675 | { |
676 | const struct dpll_data *dd; | |
677 | u32 v; | |
678 | ||
679 | if (!clk || !clk->dpll_data) | |
680 | return; | |
681 | ||
682 | dd = clk->dpll_data; | |
683 | ||
455db9c9 | 684 | if (!dd->autoidle_reg) |
d76316fe | 685 | return; |
d76316fe | 686 | |
a1391d27 RN |
687 | /* |
688 | * REVISIT: CORE DPLL can optionally enter low-power bypass | |
689 | * by writing 0x5 instead of 0x1. Add some mechanism to | |
690 | * optionally enter this mode. | |
691 | */ | |
0565fb16 | 692 | v = ti_clk_ll_ops->clk_readl(dd->autoidle_reg); |
a1391d27 RN |
693 | v &= ~dd->autoidle_mask; |
694 | v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask); | |
0565fb16 | 695 | ti_clk_ll_ops->clk_writel(v, dd->autoidle_reg); |
a1391d27 RN |
696 | } |
697 | ||
698 | /** | |
699 | * omap3_dpll_deny_idle - prevent DPLL from automatically idling | |
700 | * @clk: struct clk * of the DPLL to operate on | |
701 | * | |
702 | * Disable DPLL automatic idle control. No return value. | |
703 | */ | |
0565fb16 | 704 | static void omap3_dpll_deny_idle(struct clk_hw_omap *clk) |
a1391d27 RN |
705 | { |
706 | const struct dpll_data *dd; | |
707 | u32 v; | |
708 | ||
709 | if (!clk || !clk->dpll_data) | |
710 | return; | |
711 | ||
712 | dd = clk->dpll_data; | |
713 | ||
455db9c9 | 714 | if (!dd->autoidle_reg) |
d76316fe | 715 | return; |
d76316fe | 716 | |
0565fb16 | 717 | v = ti_clk_ll_ops->clk_readl(dd->autoidle_reg); |
a1391d27 RN |
718 | v &= ~dd->autoidle_mask; |
719 | v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask); | |
0565fb16 | 720 | ti_clk_ll_ops->clk_writel(v, dd->autoidle_reg); |
a1391d27 RN |
721 | } |
722 | ||
723 | /* Clock control for DPLL outputs */ | |
724 | ||
994c41ee TV |
725 | /* Find the parent DPLL for the given clkoutx2 clock */ |
726 | static struct clk_hw_omap *omap3_find_clkoutx2_dpll(struct clk_hw *hw) | |
727 | { | |
728 | struct clk_hw_omap *pclk = NULL; | |
994c41ee TV |
729 | |
730 | /* Walk up the parents of clk, looking for a DPLL */ | |
731 | do { | |
732 | do { | |
a53ad8ef | 733 | hw = clk_hw_get_parent(hw); |
98d8a60e | 734 | } while (hw && (clk_hw_get_flags(hw) & CLK_IS_BASIC)); |
994c41ee TV |
735 | if (!hw) |
736 | break; | |
737 | pclk = to_clk_hw_omap(hw); | |
738 | } while (pclk && !pclk->dpll_data); | |
739 | ||
740 | /* clk does not have a DPLL as a parent? error in the clock data */ | |
741 | if (!pclk) { | |
742 | WARN_ON(1); | |
743 | return NULL; | |
744 | } | |
745 | ||
746 | return pclk; | |
747 | } | |
748 | ||
a1391d27 RN |
749 | /** |
750 | * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate | |
751 | * @clk: DPLL output struct clk | |
752 | * | |
753 | * Using parent clock DPLL data, look up DPLL state. If locked, set our | |
754 | * rate to the dpll_clk * 2; otherwise, just use dpll_clk. | |
755 | */ | |
32cc0021 MT |
756 | unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw, |
757 | unsigned long parent_rate) | |
758 | { | |
759 | const struct dpll_data *dd; | |
760 | unsigned long rate; | |
761 | u32 v; | |
762 | struct clk_hw_omap *pclk = NULL; | |
32cc0021 | 763 | |
519ab8b2 TK |
764 | if (!parent_rate) |
765 | return 0; | |
766 | ||
994c41ee | 767 | pclk = omap3_find_clkoutx2_dpll(hw); |
a1391d27 | 768 | |
994c41ee | 769 | if (!pclk) |
a032d33b | 770 | return 0; |
a1391d27 RN |
771 | |
772 | dd = pclk->dpll_data; | |
773 | ||
774 | WARN_ON(!dd->enable_mask); | |
775 | ||
0565fb16 | 776 | v = ti_clk_ll_ops->clk_readl(dd->control_reg) & dd->enable_mask; |
a1391d27 | 777 | v >>= __ffs(dd->enable_mask); |
358965d7 | 778 | if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE)) |
5dcc3b97 | 779 | rate = parent_rate; |
a1391d27 | 780 | else |
5dcc3b97 | 781 | rate = parent_rate * 2; |
a1391d27 RN |
782 | return rate; |
783 | } | |
353cec46 | 784 | |
0565fb16 TK |
785 | /* OMAP3/4 non-CORE DPLL clkops */ |
786 | const struct clk_hw_omap_ops clkhwops_omap3_dpll = { | |
787 | .allow_idle = omap3_dpll_allow_idle, | |
788 | .deny_idle = omap3_dpll_deny_idle, | |
789 | }; | |
994c41ee | 790 | |
0565fb16 TK |
791 | /** |
792 | * omap3_dpll4_set_rate - set rate for omap3 per-dpll | |
793 | * @hw: clock to change | |
794 | * @rate: target rate for clock | |
795 | * @parent_rate: rate of the parent clock | |
796 | * | |
797 | * Check if the current SoC supports the per-dpll reprogram operation | |
798 | * or not, and then do the rate change if supported. Returns -EINVAL | |
799 | * if not supported, 0 for success, and potential error codes from the | |
800 | * clock rate change. | |
801 | */ | |
802 | int omap3_dpll4_set_rate(struct clk_hw *hw, unsigned long rate, | |
803 | unsigned long parent_rate) | |
994c41ee | 804 | { |
0565fb16 TK |
805 | /* |
806 | * According to the 12-5 CDP code from TI, "Limitation 2.5" | |
807 | * on 3430ES1 prevents us from changing DPLL multipliers or dividers | |
808 | * on DPLL4. | |
809 | */ | |
810 | if (ti_clk_get_features()->flags & TI_CLK_DPLL4_DENY_REPROGRAM) { | |
811 | pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n"); | |
812 | return -EINVAL; | |
994c41ee TV |
813 | } |
814 | ||
0565fb16 TK |
815 | return omap3_noncore_dpll_set_rate(hw, rate, parent_rate); |
816 | } | |
994c41ee | 817 | |
0565fb16 TK |
818 | /** |
819 | * omap3_dpll4_set_rate_and_parent - set rate and parent for omap3 per-dpll | |
820 | * @hw: clock to change | |
821 | * @rate: target rate for clock | |
822 | * @parent_rate: rate of the parent clock | |
823 | * @index: parent index, 0 - reference clock, 1 - bypass clock | |
824 | * | |
825 | * Check if the current SoC support the per-dpll reprogram operation | |
826 | * or not, and then do the rate + parent change if supported. Returns | |
827 | * -EINVAL if not supported, 0 for success, and potential error codes | |
828 | * from the clock rate change. | |
829 | */ | |
830 | int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate, | |
831 | unsigned long parent_rate, u8 index) | |
832 | { | |
833 | if (ti_clk_get_features()->flags & TI_CLK_DPLL4_DENY_REPROGRAM) { | |
834 | pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n"); | |
835 | return -EINVAL; | |
994c41ee TV |
836 | } |
837 | ||
0565fb16 TK |
838 | return omap3_noncore_dpll_set_rate_and_parent(hw, rate, parent_rate, |
839 | index); | |
994c41ee | 840 | } |