Commit | Line | Data |
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f38b0dd6 TK |
1 | /* |
2 | * OMAP DPLL clock support | |
3 | * | |
4 | * Copyright (C) 2013 Texas Instruments, Inc. | |
5 | * | |
6 | * Tero Kristo <t-kristo@ti.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
13 | * kind, whether express or implied; without even the implied warranty | |
14 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | */ | |
17 | ||
1b29e601 | 18 | #include <linux/clk.h> |
f38b0dd6 TK |
19 | #include <linux/clk-provider.h> |
20 | #include <linux/slab.h> | |
21 | #include <linux/err.h> | |
22 | #include <linux/of.h> | |
23 | #include <linux/of_address.h> | |
24 | #include <linux/clk/ti.h> | |
ed405a23 | 25 | #include "clock.h" |
f38b0dd6 TK |
26 | |
27 | #undef pr_fmt | |
28 | #define pr_fmt(fmt) "%s: " fmt, __func__ | |
29 | ||
f38b0dd6 TK |
30 | #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ |
31 | defined(CONFIG_SOC_DRA7XX) | |
32 | static const struct clk_ops dpll_m4xen_ck_ops = { | |
33 | .enable = &omap3_noncore_dpll_enable, | |
34 | .disable = &omap3_noncore_dpll_disable, | |
35 | .recalc_rate = &omap4_dpll_regm4xen_recalc, | |
36 | .round_rate = &omap4_dpll_regm4xen_round_rate, | |
37 | .set_rate = &omap3_noncore_dpll_set_rate, | |
2e1a7b01 TK |
38 | .set_parent = &omap3_noncore_dpll_set_parent, |
39 | .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent, | |
40 | .determine_rate = &omap4_dpll_regm4xen_determine_rate, | |
f38b0dd6 TK |
41 | .get_parent = &omap2_init_dpll_parent, |
42 | }; | |
aa76fcf4 TK |
43 | #else |
44 | static const struct clk_ops dpll_m4xen_ck_ops = {}; | |
f38b0dd6 TK |
45 | #endif |
46 | ||
aa76fcf4 TK |
47 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) || \ |
48 | defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX) || \ | |
49 | defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX) | |
f38b0dd6 TK |
50 | static const struct clk_ops dpll_core_ck_ops = { |
51 | .recalc_rate = &omap3_dpll_recalc, | |
52 | .get_parent = &omap2_init_dpll_parent, | |
53 | }; | |
54 | ||
f38b0dd6 TK |
55 | static const struct clk_ops dpll_ck_ops = { |
56 | .enable = &omap3_noncore_dpll_enable, | |
57 | .disable = &omap3_noncore_dpll_disable, | |
58 | .recalc_rate = &omap3_dpll_recalc, | |
59 | .round_rate = &omap2_dpll_round_rate, | |
60 | .set_rate = &omap3_noncore_dpll_set_rate, | |
2e1a7b01 TK |
61 | .set_parent = &omap3_noncore_dpll_set_parent, |
62 | .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent, | |
63 | .determine_rate = &omap3_noncore_dpll_determine_rate, | |
f38b0dd6 TK |
64 | .get_parent = &omap2_init_dpll_parent, |
65 | }; | |
66 | ||
67 | static const struct clk_ops dpll_no_gate_ck_ops = { | |
68 | .recalc_rate = &omap3_dpll_recalc, | |
69 | .get_parent = &omap2_init_dpll_parent, | |
70 | .round_rate = &omap2_dpll_round_rate, | |
71 | .set_rate = &omap3_noncore_dpll_set_rate, | |
2e1a7b01 TK |
72 | .set_parent = &omap3_noncore_dpll_set_parent, |
73 | .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent, | |
74 | .determine_rate = &omap3_noncore_dpll_determine_rate, | |
f38b0dd6 | 75 | }; |
aa76fcf4 TK |
76 | #else |
77 | static const struct clk_ops dpll_core_ck_ops = {}; | |
78 | static const struct clk_ops dpll_ck_ops = {}; | |
79 | static const struct clk_ops dpll_no_gate_ck_ops = {}; | |
80 | const struct clk_hw_omap_ops clkhwops_omap3_dpll = {}; | |
81 | #endif | |
82 | ||
83 | #ifdef CONFIG_ARCH_OMAP2 | |
84 | static const struct clk_ops omap2_dpll_core_ck_ops = { | |
85 | .get_parent = &omap2_init_dpll_parent, | |
86 | .recalc_rate = &omap2_dpllcore_recalc, | |
87 | .round_rate = &omap2_dpll_round_rate, | |
88 | .set_rate = &omap2_reprogram_dpllcore, | |
89 | }; | |
90 | #else | |
91 | static const struct clk_ops omap2_dpll_core_ck_ops = {}; | |
92 | #endif | |
93 | ||
94 | #ifdef CONFIG_ARCH_OMAP3 | |
95 | static const struct clk_ops omap3_dpll_core_ck_ops = { | |
96 | .get_parent = &omap2_init_dpll_parent, | |
97 | .recalc_rate = &omap3_dpll_recalc, | |
98 | .round_rate = &omap2_dpll_round_rate, | |
99 | }; | |
100 | #else | |
101 | static const struct clk_ops omap3_dpll_core_ck_ops = {}; | |
102 | #endif | |
f38b0dd6 TK |
103 | |
104 | #ifdef CONFIG_ARCH_OMAP3 | |
105 | static const struct clk_ops omap3_dpll_ck_ops = { | |
106 | .enable = &omap3_noncore_dpll_enable, | |
107 | .disable = &omap3_noncore_dpll_disable, | |
108 | .get_parent = &omap2_init_dpll_parent, | |
109 | .recalc_rate = &omap3_dpll_recalc, | |
110 | .set_rate = &omap3_noncore_dpll_set_rate, | |
2e1a7b01 TK |
111 | .set_parent = &omap3_noncore_dpll_set_parent, |
112 | .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent, | |
113 | .determine_rate = &omap3_noncore_dpll_determine_rate, | |
f38b0dd6 TK |
114 | .round_rate = &omap2_dpll_round_rate, |
115 | }; | |
116 | ||
035cd485 RW |
117 | static const struct clk_ops omap3_dpll5_ck_ops = { |
118 | .enable = &omap3_noncore_dpll_enable, | |
119 | .disable = &omap3_noncore_dpll_disable, | |
120 | .get_parent = &omap2_init_dpll_parent, | |
121 | .recalc_rate = &omap3_dpll_recalc, | |
122 | .set_rate = &omap3_dpll5_set_rate, | |
123 | .set_parent = &omap3_noncore_dpll_set_parent, | |
124 | .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent, | |
125 | .determine_rate = &omap3_noncore_dpll_determine_rate, | |
126 | .round_rate = &omap2_dpll_round_rate, | |
127 | }; | |
128 | ||
f38b0dd6 TK |
129 | static const struct clk_ops omap3_dpll_per_ck_ops = { |
130 | .enable = &omap3_noncore_dpll_enable, | |
131 | .disable = &omap3_noncore_dpll_disable, | |
132 | .get_parent = &omap2_init_dpll_parent, | |
133 | .recalc_rate = &omap3_dpll_recalc, | |
134 | .set_rate = &omap3_dpll4_set_rate, | |
2e1a7b01 TK |
135 | .set_parent = &omap3_noncore_dpll_set_parent, |
136 | .set_rate_and_parent = &omap3_dpll4_set_rate_and_parent, | |
137 | .determine_rate = &omap3_noncore_dpll_determine_rate, | |
f38b0dd6 TK |
138 | .round_rate = &omap2_dpll_round_rate, |
139 | }; | |
140 | #endif | |
141 | ||
142 | static const struct clk_ops dpll_x2_ck_ops = { | |
143 | .recalc_rate = &omap3_clkoutx2_recalc, | |
144 | }; | |
145 | ||
146 | /** | |
ed405a23 | 147 | * _register_dpll - low level registration of a DPLL clock |
f38b0dd6 TK |
148 | * @hw: hardware clock definition for the clock |
149 | * @node: device node for the clock | |
150 | * | |
151 | * Finalizes DPLL registration process. In case a failure (clk-ref or | |
152 | * clk-bypass is missing), the clock is added to retry list and | |
153 | * the initialization is retried on later stage. | |
154 | */ | |
ffb009b2 | 155 | static void __init _register_dpll(void *user, |
ed405a23 | 156 | struct device_node *node) |
f38b0dd6 | 157 | { |
ffb009b2 | 158 | struct clk_hw *hw = user; |
f38b0dd6 TK |
159 | struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw); |
160 | struct dpll_data *dd = clk_hw->dpll_data; | |
161 | struct clk *clk; | |
162 | ||
b6f51284 TK |
163 | clk = of_clk_get(node, 0); |
164 | if (IS_ERR(clk)) { | |
165 | pr_debug("clk-ref missing for %s, retry later\n", | |
166 | node->name); | |
167 | if (!ti_clk_retry_init(node, hw, _register_dpll)) | |
168 | return; | |
f38b0dd6 | 169 | |
b6f51284 TK |
170 | goto cleanup; |
171 | } | |
172 | ||
173 | dd->clk_ref = __clk_get_hw(clk); | |
174 | ||
175 | clk = of_clk_get(node, 1); | |
176 | ||
177 | if (IS_ERR(clk)) { | |
178 | pr_debug("clk-bypass missing for %s, retry later\n", | |
f38b0dd6 | 179 | node->name); |
ed405a23 | 180 | if (!ti_clk_retry_init(node, hw, _register_dpll)) |
f38b0dd6 TK |
181 | return; |
182 | ||
183 | goto cleanup; | |
184 | } | |
185 | ||
b6f51284 TK |
186 | dd->clk_bypass = __clk_get_hw(clk); |
187 | ||
f38b0dd6 | 188 | /* register the clock */ |
1ae79c46 | 189 | clk = ti_clk_register(NULL, &clk_hw->hw, node->name); |
f38b0dd6 TK |
190 | |
191 | if (!IS_ERR(clk)) { | |
98d8a60e | 192 | omap2_init_clk_hw_omap_clocks(&clk_hw->hw); |
f38b0dd6 TK |
193 | of_clk_add_provider(node, of_clk_src_simple_get, clk); |
194 | kfree(clk_hw->hw.init->parent_names); | |
195 | kfree(clk_hw->hw.init); | |
196 | return; | |
197 | } | |
198 | ||
199 | cleanup: | |
200 | kfree(clk_hw->dpll_data); | |
201 | kfree(clk_hw->hw.init->parent_names); | |
202 | kfree(clk_hw->hw.init); | |
203 | kfree(clk_hw); | |
204 | } | |
205 | ||
206 | #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ | |
4332ec1a RQ |
207 | defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM33XX) || \ |
208 | defined(CONFIG_SOC_AM43XX) | |
f38b0dd6 | 209 | /** |
ed405a23 | 210 | * _register_dpll_x2 - Registers a DPLLx2 clock |
f38b0dd6 TK |
211 | * @node: device node for this clock |
212 | * @ops: clk_ops for this clock | |
213 | * @hw_ops: clk_hw_ops for this clock | |
214 | * | |
215 | * Initializes a DPLL x 2 clock from device tree data. | |
216 | */ | |
ed405a23 TK |
217 | static void _register_dpll_x2(struct device_node *node, |
218 | const struct clk_ops *ops, | |
219 | const struct clk_hw_omap_ops *hw_ops) | |
f38b0dd6 TK |
220 | { |
221 | struct clk *clk; | |
222 | struct clk_init_data init = { NULL }; | |
223 | struct clk_hw_omap *clk_hw; | |
224 | const char *name = node->name; | |
225 | const char *parent_name; | |
226 | ||
227 | parent_name = of_clk_get_parent_name(node, 0); | |
228 | if (!parent_name) { | |
229 | pr_err("%s must have parent\n", node->name); | |
230 | return; | |
231 | } | |
232 | ||
233 | clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); | |
234 | if (!clk_hw) | |
235 | return; | |
236 | ||
237 | clk_hw->ops = hw_ops; | |
238 | clk_hw->hw.init = &init; | |
239 | ||
240 | init.name = name; | |
241 | init.ops = ops; | |
242 | init.parent_names = &parent_name; | |
243 | init.num_parents = 1; | |
244 | ||
2158a093 AB |
245 | #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ |
246 | defined(CONFIG_SOC_DRA7XX) | |
473adbf4 | 247 | if (hw_ops == &clkhwops_omap4_dpllmx) { |
2158a093 AB |
248 | int ret; |
249 | ||
473adbf4 TK |
250 | /* Check if register defined, if not, drop hw-ops */ |
251 | ret = of_property_count_elems_of_size(node, "reg", 1); | |
252 | if (ret <= 0) { | |
2158a093 | 253 | clk_hw->ops = NULL; |
6c0afb50 TK |
254 | } else if (ti_clk_get_reg_addr(node, 0, &clk_hw->clksel_reg)) { |
255 | kfree(clk_hw); | |
256 | return; | |
473adbf4 TK |
257 | } |
258 | } | |
2158a093 | 259 | #endif |
473adbf4 | 260 | |
f38b0dd6 | 261 | /* register the clock */ |
1ae79c46 | 262 | clk = ti_clk_register(NULL, &clk_hw->hw, name); |
f38b0dd6 TK |
263 | |
264 | if (IS_ERR(clk)) { | |
265 | kfree(clk_hw); | |
266 | } else { | |
98d8a60e | 267 | omap2_init_clk_hw_omap_clocks(&clk_hw->hw); |
f38b0dd6 TK |
268 | of_clk_add_provider(node, of_clk_src_simple_get, clk); |
269 | } | |
270 | } | |
271 | #endif | |
272 | ||
273 | /** | |
274 | * of_ti_dpll_setup - Setup function for OMAP DPLL clocks | |
275 | * @node: device node containing the DPLL info | |
276 | * @ops: ops for the DPLL | |
277 | * @ddt: DPLL data template to use | |
f38b0dd6 TK |
278 | * |
279 | * Initializes a DPLL clock from device tree data. | |
280 | */ | |
281 | static void __init of_ti_dpll_setup(struct device_node *node, | |
282 | const struct clk_ops *ops, | |
a6fe3771 | 283 | const struct dpll_data *ddt) |
f38b0dd6 TK |
284 | { |
285 | struct clk_hw_omap *clk_hw = NULL; | |
286 | struct clk_init_data *init = NULL; | |
287 | const char **parent_names = NULL; | |
288 | struct dpll_data *dd = NULL; | |
f38b0dd6 TK |
289 | u8 dpll_mode = 0; |
290 | ||
291 | dd = kzalloc(sizeof(*dd), GFP_KERNEL); | |
292 | clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); | |
293 | init = kzalloc(sizeof(*init), GFP_KERNEL); | |
294 | if (!dd || !clk_hw || !init) | |
295 | goto cleanup; | |
296 | ||
297 | memcpy(dd, ddt, sizeof(*dd)); | |
298 | ||
299 | clk_hw->dpll_data = dd; | |
300 | clk_hw->ops = &clkhwops_omap3_dpll; | |
301 | clk_hw->hw.init = init; | |
f38b0dd6 TK |
302 | |
303 | init->name = node->name; | |
304 | init->ops = ops; | |
305 | ||
306 | init->num_parents = of_clk_get_parent_count(node); | |
921bacfa | 307 | if (!init->num_parents) { |
f38b0dd6 TK |
308 | pr_err("%s must have parent(s)\n", node->name); |
309 | goto cleanup; | |
310 | } | |
311 | ||
6396bb22 | 312 | parent_names = kcalloc(init->num_parents, sizeof(char *), GFP_KERNEL); |
f38b0dd6 TK |
313 | if (!parent_names) |
314 | goto cleanup; | |
315 | ||
9da9e761 | 316 | of_clk_parent_fill(node, parent_names, init->num_parents); |
f38b0dd6 TK |
317 | |
318 | init->parent_names = parent_names; | |
319 | ||
6c0afb50 TK |
320 | if (ti_clk_get_reg_addr(node, 0, &dd->control_reg)) |
321 | goto cleanup; | |
f38b0dd6 | 322 | |
aa76fcf4 TK |
323 | /* |
324 | * Special case for OMAP2 DPLL, register order is different due to | |
325 | * missing idlest_reg, also clkhwops is different. Detected from | |
326 | * missing idlest_mask. | |
327 | */ | |
328 | if (!dd->idlest_mask) { | |
6c0afb50 TK |
329 | if (ti_clk_get_reg_addr(node, 1, &dd->mult_div1_reg)) |
330 | goto cleanup; | |
aa76fcf4 TK |
331 | #ifdef CONFIG_ARCH_OMAP2 |
332 | clk_hw->ops = &clkhwops_omap2xxx_dpll; | |
333 | omap2xxx_clkt_dpllcore_init(&clk_hw->hw); | |
334 | #endif | |
335 | } else { | |
6c0afb50 | 336 | if (ti_clk_get_reg_addr(node, 1, &dd->idlest_reg)) |
aa76fcf4 TK |
337 | goto cleanup; |
338 | ||
6c0afb50 TK |
339 | if (ti_clk_get_reg_addr(node, 2, &dd->mult_div1_reg)) |
340 | goto cleanup; | |
aa76fcf4 TK |
341 | } |
342 | ||
a6fe3771 | 343 | if (dd->autoidle_mask) { |
6c0afb50 | 344 | if (ti_clk_get_reg_addr(node, 3, &dd->autoidle_reg)) |
f38b0dd6 TK |
345 | goto cleanup; |
346 | } | |
347 | ||
348 | if (of_property_read_bool(node, "ti,low-power-stop")) | |
349 | dpll_mode |= 1 << DPLL_LOW_POWER_STOP; | |
350 | ||
351 | if (of_property_read_bool(node, "ti,low-power-bypass")) | |
352 | dpll_mode |= 1 << DPLL_LOW_POWER_BYPASS; | |
353 | ||
354 | if (of_property_read_bool(node, "ti,lock")) | |
355 | dpll_mode |= 1 << DPLL_LOCKED; | |
356 | ||
357 | if (dpll_mode) | |
358 | dd->modes = dpll_mode; | |
359 | ||
ed405a23 | 360 | _register_dpll(&clk_hw->hw, node); |
f38b0dd6 TK |
361 | return; |
362 | ||
363 | cleanup: | |
364 | kfree(dd); | |
365 | kfree(parent_names); | |
366 | kfree(init); | |
367 | kfree(clk_hw); | |
368 | } | |
369 | ||
370 | #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ | |
371 | defined(CONFIG_SOC_DRA7XX) | |
372 | static void __init of_ti_omap4_dpll_x2_setup(struct device_node *node) | |
373 | { | |
ed405a23 | 374 | _register_dpll_x2(node, &dpll_x2_ck_ops, &clkhwops_omap4_dpllmx); |
f38b0dd6 TK |
375 | } |
376 | CLK_OF_DECLARE(ti_omap4_dpll_x2_clock, "ti,omap4-dpll-x2-clock", | |
377 | of_ti_omap4_dpll_x2_setup); | |
378 | #endif | |
379 | ||
4332ec1a | 380 | #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX) |
f38b0dd6 TK |
381 | static void __init of_ti_am3_dpll_x2_setup(struct device_node *node) |
382 | { | |
ed405a23 | 383 | _register_dpll_x2(node, &dpll_x2_ck_ops, NULL); |
f38b0dd6 TK |
384 | } |
385 | CLK_OF_DECLARE(ti_am3_dpll_x2_clock, "ti,am3-dpll-x2-clock", | |
386 | of_ti_am3_dpll_x2_setup); | |
387 | #endif | |
388 | ||
389 | #ifdef CONFIG_ARCH_OMAP3 | |
390 | static void __init of_ti_omap3_dpll_setup(struct device_node *node) | |
391 | { | |
392 | const struct dpll_data dd = { | |
393 | .idlest_mask = 0x1, | |
394 | .enable_mask = 0x7, | |
395 | .autoidle_mask = 0x7, | |
396 | .mult_mask = 0x7ff << 8, | |
397 | .div1_mask = 0x7f, | |
398 | .max_multiplier = 2047, | |
399 | .max_divider = 128, | |
400 | .min_divider = 1, | |
401 | .freqsel_mask = 0xf0, | |
402 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), | |
403 | }; | |
404 | ||
035cd485 RW |
405 | if ((of_machine_is_compatible("ti,omap3630") || |
406 | of_machine_is_compatible("ti,omap36xx")) && | |
407 | !strcmp(node->name, "dpll5_ck")) | |
408 | of_ti_dpll_setup(node, &omap3_dpll5_ck_ops, &dd); | |
409 | else | |
410 | of_ti_dpll_setup(node, &omap3_dpll_ck_ops, &dd); | |
f38b0dd6 TK |
411 | } |
412 | CLK_OF_DECLARE(ti_omap3_dpll_clock, "ti,omap3-dpll-clock", | |
413 | of_ti_omap3_dpll_setup); | |
414 | ||
415 | static void __init of_ti_omap3_core_dpll_setup(struct device_node *node) | |
416 | { | |
417 | const struct dpll_data dd = { | |
418 | .idlest_mask = 0x1, | |
419 | .enable_mask = 0x7, | |
420 | .autoidle_mask = 0x7, | |
421 | .mult_mask = 0x7ff << 16, | |
422 | .div1_mask = 0x7f << 8, | |
423 | .max_multiplier = 2047, | |
424 | .max_divider = 128, | |
425 | .min_divider = 1, | |
426 | .freqsel_mask = 0xf0, | |
427 | }; | |
428 | ||
a6fe3771 | 429 | of_ti_dpll_setup(node, &omap3_dpll_core_ck_ops, &dd); |
f38b0dd6 TK |
430 | } |
431 | CLK_OF_DECLARE(ti_omap3_core_dpll_clock, "ti,omap3-dpll-core-clock", | |
432 | of_ti_omap3_core_dpll_setup); | |
433 | ||
434 | static void __init of_ti_omap3_per_dpll_setup(struct device_node *node) | |
435 | { | |
436 | const struct dpll_data dd = { | |
437 | .idlest_mask = 0x1 << 1, | |
438 | .enable_mask = 0x7 << 16, | |
439 | .autoidle_mask = 0x7 << 3, | |
440 | .mult_mask = 0x7ff << 8, | |
441 | .div1_mask = 0x7f, | |
442 | .max_multiplier = 2047, | |
443 | .max_divider = 128, | |
444 | .min_divider = 1, | |
445 | .freqsel_mask = 0xf00000, | |
446 | .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), | |
447 | }; | |
448 | ||
a6fe3771 | 449 | of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd); |
f38b0dd6 TK |
450 | } |
451 | CLK_OF_DECLARE(ti_omap3_per_dpll_clock, "ti,omap3-dpll-per-clock", | |
452 | of_ti_omap3_per_dpll_setup); | |
453 | ||
454 | static void __init of_ti_omap3_per_jtype_dpll_setup(struct device_node *node) | |
455 | { | |
456 | const struct dpll_data dd = { | |
457 | .idlest_mask = 0x1 << 1, | |
458 | .enable_mask = 0x7 << 16, | |
459 | .autoidle_mask = 0x7 << 3, | |
460 | .mult_mask = 0xfff << 8, | |
461 | .div1_mask = 0x7f, | |
462 | .max_multiplier = 4095, | |
463 | .max_divider = 128, | |
464 | .min_divider = 1, | |
465 | .sddiv_mask = 0xff << 24, | |
466 | .dco_mask = 0xe << 20, | |
467 | .flags = DPLL_J_TYPE, | |
468 | .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), | |
469 | }; | |
470 | ||
a6fe3771 | 471 | of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd); |
f38b0dd6 TK |
472 | } |
473 | CLK_OF_DECLARE(ti_omap3_per_jtype_dpll_clock, "ti,omap3-dpll-per-j-type-clock", | |
474 | of_ti_omap3_per_jtype_dpll_setup); | |
475 | #endif | |
476 | ||
477 | static void __init of_ti_omap4_dpll_setup(struct device_node *node) | |
478 | { | |
479 | const struct dpll_data dd = { | |
480 | .idlest_mask = 0x1, | |
481 | .enable_mask = 0x7, | |
482 | .autoidle_mask = 0x7, | |
483 | .mult_mask = 0x7ff << 8, | |
484 | .div1_mask = 0x7f, | |
485 | .max_multiplier = 2047, | |
486 | .max_divider = 128, | |
487 | .min_divider = 1, | |
488 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), | |
489 | }; | |
490 | ||
a6fe3771 | 491 | of_ti_dpll_setup(node, &dpll_ck_ops, &dd); |
f38b0dd6 TK |
492 | } |
493 | CLK_OF_DECLARE(ti_omap4_dpll_clock, "ti,omap4-dpll-clock", | |
494 | of_ti_omap4_dpll_setup); | |
495 | ||
b4be0189 NM |
496 | static void __init of_ti_omap5_mpu_dpll_setup(struct device_node *node) |
497 | { | |
498 | const struct dpll_data dd = { | |
499 | .idlest_mask = 0x1, | |
500 | .enable_mask = 0x7, | |
501 | .autoidle_mask = 0x7, | |
502 | .mult_mask = 0x7ff << 8, | |
503 | .div1_mask = 0x7f, | |
504 | .max_multiplier = 2047, | |
505 | .max_divider = 128, | |
506 | .dcc_mask = BIT(22), | |
507 | .dcc_rate = 1400000000, /* DCC beyond 1.4GHz */ | |
508 | .min_divider = 1, | |
509 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), | |
510 | }; | |
511 | ||
512 | of_ti_dpll_setup(node, &dpll_ck_ops, &dd); | |
513 | } | |
514 | CLK_OF_DECLARE(of_ti_omap5_mpu_dpll_clock, "ti,omap5-mpu-dpll-clock", | |
515 | of_ti_omap5_mpu_dpll_setup); | |
516 | ||
f38b0dd6 TK |
517 | static void __init of_ti_omap4_core_dpll_setup(struct device_node *node) |
518 | { | |
519 | const struct dpll_data dd = { | |
520 | .idlest_mask = 0x1, | |
521 | .enable_mask = 0x7, | |
522 | .autoidle_mask = 0x7, | |
523 | .mult_mask = 0x7ff << 8, | |
524 | .div1_mask = 0x7f, | |
525 | .max_multiplier = 2047, | |
526 | .max_divider = 128, | |
527 | .min_divider = 1, | |
528 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), | |
529 | }; | |
530 | ||
a6fe3771 | 531 | of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd); |
f38b0dd6 TK |
532 | } |
533 | CLK_OF_DECLARE(ti_omap4_core_dpll_clock, "ti,omap4-dpll-core-clock", | |
534 | of_ti_omap4_core_dpll_setup); | |
535 | ||
536 | #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ | |
537 | defined(CONFIG_SOC_DRA7XX) | |
538 | static void __init of_ti_omap4_m4xen_dpll_setup(struct device_node *node) | |
539 | { | |
540 | const struct dpll_data dd = { | |
541 | .idlest_mask = 0x1, | |
542 | .enable_mask = 0x7, | |
543 | .autoidle_mask = 0x7, | |
544 | .mult_mask = 0x7ff << 8, | |
545 | .div1_mask = 0x7f, | |
546 | .max_multiplier = 2047, | |
547 | .max_divider = 128, | |
548 | .min_divider = 1, | |
549 | .m4xen_mask = 0x800, | |
550 | .lpmode_mask = 1 << 10, | |
551 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), | |
552 | }; | |
553 | ||
a6fe3771 | 554 | of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd); |
f38b0dd6 TK |
555 | } |
556 | CLK_OF_DECLARE(ti_omap4_m4xen_dpll_clock, "ti,omap4-dpll-m4xen-clock", | |
557 | of_ti_omap4_m4xen_dpll_setup); | |
558 | ||
559 | static void __init of_ti_omap4_jtype_dpll_setup(struct device_node *node) | |
560 | { | |
561 | const struct dpll_data dd = { | |
562 | .idlest_mask = 0x1, | |
563 | .enable_mask = 0x7, | |
564 | .autoidle_mask = 0x7, | |
565 | .mult_mask = 0xfff << 8, | |
566 | .div1_mask = 0xff, | |
567 | .max_multiplier = 4095, | |
568 | .max_divider = 256, | |
569 | .min_divider = 1, | |
570 | .sddiv_mask = 0xff << 24, | |
571 | .flags = DPLL_J_TYPE, | |
572 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), | |
573 | }; | |
574 | ||
a6fe3771 | 575 | of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd); |
f38b0dd6 TK |
576 | } |
577 | CLK_OF_DECLARE(ti_omap4_jtype_dpll_clock, "ti,omap4-dpll-j-type-clock", | |
578 | of_ti_omap4_jtype_dpll_setup); | |
579 | #endif | |
580 | ||
581 | static void __init of_ti_am3_no_gate_dpll_setup(struct device_node *node) | |
582 | { | |
583 | const struct dpll_data dd = { | |
584 | .idlest_mask = 0x1, | |
585 | .enable_mask = 0x7, | |
f38b0dd6 TK |
586 | .mult_mask = 0x7ff << 8, |
587 | .div1_mask = 0x7f, | |
588 | .max_multiplier = 2047, | |
589 | .max_divider = 128, | |
590 | .min_divider = 1, | |
3db5ca27 | 591 | .max_rate = 1000000000, |
f38b0dd6 TK |
592 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), |
593 | }; | |
594 | ||
a6fe3771 | 595 | of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd); |
f38b0dd6 TK |
596 | } |
597 | CLK_OF_DECLARE(ti_am3_no_gate_dpll_clock, "ti,am3-dpll-no-gate-clock", | |
598 | of_ti_am3_no_gate_dpll_setup); | |
599 | ||
600 | static void __init of_ti_am3_jtype_dpll_setup(struct device_node *node) | |
601 | { | |
602 | const struct dpll_data dd = { | |
603 | .idlest_mask = 0x1, | |
604 | .enable_mask = 0x7, | |
f38b0dd6 TK |
605 | .mult_mask = 0x7ff << 8, |
606 | .div1_mask = 0x7f, | |
607 | .max_multiplier = 4095, | |
608 | .max_divider = 256, | |
609 | .min_divider = 2, | |
610 | .flags = DPLL_J_TYPE, | |
3db5ca27 | 611 | .max_rate = 2000000000, |
f38b0dd6 TK |
612 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), |
613 | }; | |
614 | ||
a6fe3771 | 615 | of_ti_dpll_setup(node, &dpll_ck_ops, &dd); |
f38b0dd6 TK |
616 | } |
617 | CLK_OF_DECLARE(ti_am3_jtype_dpll_clock, "ti,am3-dpll-j-type-clock", | |
618 | of_ti_am3_jtype_dpll_setup); | |
619 | ||
620 | static void __init of_ti_am3_no_gate_jtype_dpll_setup(struct device_node *node) | |
621 | { | |
622 | const struct dpll_data dd = { | |
623 | .idlest_mask = 0x1, | |
624 | .enable_mask = 0x7, | |
f38b0dd6 TK |
625 | .mult_mask = 0x7ff << 8, |
626 | .div1_mask = 0x7f, | |
627 | .max_multiplier = 2047, | |
628 | .max_divider = 128, | |
629 | .min_divider = 1, | |
3db5ca27 | 630 | .max_rate = 2000000000, |
f38b0dd6 TK |
631 | .flags = DPLL_J_TYPE, |
632 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), | |
633 | }; | |
634 | ||
a6fe3771 | 635 | of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd); |
f38b0dd6 TK |
636 | } |
637 | CLK_OF_DECLARE(ti_am3_no_gate_jtype_dpll_clock, | |
638 | "ti,am3-dpll-no-gate-j-type-clock", | |
639 | of_ti_am3_no_gate_jtype_dpll_setup); | |
640 | ||
641 | static void __init of_ti_am3_dpll_setup(struct device_node *node) | |
642 | { | |
643 | const struct dpll_data dd = { | |
644 | .idlest_mask = 0x1, | |
645 | .enable_mask = 0x7, | |
f38b0dd6 TK |
646 | .mult_mask = 0x7ff << 8, |
647 | .div1_mask = 0x7f, | |
648 | .max_multiplier = 2047, | |
649 | .max_divider = 128, | |
650 | .min_divider = 1, | |
3db5ca27 | 651 | .max_rate = 1000000000, |
f38b0dd6 TK |
652 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), |
653 | }; | |
654 | ||
a6fe3771 | 655 | of_ti_dpll_setup(node, &dpll_ck_ops, &dd); |
f38b0dd6 TK |
656 | } |
657 | CLK_OF_DECLARE(ti_am3_dpll_clock, "ti,am3-dpll-clock", of_ti_am3_dpll_setup); | |
658 | ||
659 | static void __init of_ti_am3_core_dpll_setup(struct device_node *node) | |
660 | { | |
661 | const struct dpll_data dd = { | |
662 | .idlest_mask = 0x1, | |
663 | .enable_mask = 0x7, | |
f38b0dd6 TK |
664 | .mult_mask = 0x7ff << 8, |
665 | .div1_mask = 0x7f, | |
666 | .max_multiplier = 2047, | |
667 | .max_divider = 128, | |
668 | .min_divider = 1, | |
3db5ca27 | 669 | .max_rate = 1000000000, |
f38b0dd6 TK |
670 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), |
671 | }; | |
672 | ||
a6fe3771 | 673 | of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd); |
f38b0dd6 TK |
674 | } |
675 | CLK_OF_DECLARE(ti_am3_core_dpll_clock, "ti,am3-dpll-core-clock", | |
676 | of_ti_am3_core_dpll_setup); | |
aa76fcf4 TK |
677 | |
678 | static void __init of_ti_omap2_core_dpll_setup(struct device_node *node) | |
679 | { | |
680 | const struct dpll_data dd = { | |
681 | .enable_mask = 0x3, | |
682 | .mult_mask = 0x3ff << 12, | |
683 | .div1_mask = 0xf << 8, | |
684 | .max_divider = 16, | |
685 | .min_divider = 1, | |
686 | }; | |
687 | ||
688 | of_ti_dpll_setup(node, &omap2_dpll_core_ck_ops, &dd); | |
689 | } | |
690 | CLK_OF_DECLARE(ti_omap2_core_dpll_clock, "ti,omap2-dpll-core-clock", | |
691 | of_ti_omap2_core_dpll_setup); |