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Merge tag 'irqchip-fixes-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/maz...
[linux-2.6-block.git] / drivers / clk / ti / dpll.c
CommitLineData
f38b0dd6
TK		 1/*
2 * OMAP DPLL clock support
3 *
4 * Copyright (C) 2013 Texas Instruments, Inc.
5 *
6 * Tero Kristo <t-kristo@ti.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
1b29e601 18#include <linux/clk.h>
f38b0dd6
TK		 19#include <linux/clk-provider.h>
20#include <linux/slab.h>
21#include <linux/err.h>
22#include <linux/of.h>
23#include <linux/of_address.h>
24#include <linux/clk/ti.h>
ed405a23 25#include "clock.h"
f38b0dd6
TK		 26
27#undef pr_fmt
28#define pr_fmt(fmt) "%s: " fmt, __func__
29
f38b0dd6
TK		 30#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
31 defined(CONFIG_SOC_DRA7XX)
32static const struct clk_ops dpll_m4xen_ck_ops = {
33 .enable = &omap3_noncore_dpll_enable,
34 .disable = &omap3_noncore_dpll_disable,
35 .recalc_rate = &omap4_dpll_regm4xen_recalc,
36 .round_rate = &omap4_dpll_regm4xen_round_rate,
37 .set_rate = &omap3_noncore_dpll_set_rate,
2e1a7b01
TK		 38 .set_parent = &omap3_noncore_dpll_set_parent,
39 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
40 .determine_rate = &omap4_dpll_regm4xen_determine_rate,
f38b0dd6 41 .get_parent = &omap2_init_dpll_parent,
d6e7bbc1
RD		 42 .save_context = &omap3_core_dpll_save_context,
43 .restore_context = &omap3_core_dpll_restore_context,
f38b0dd6 44};
aa76fcf4
TK		 45#else
46static const struct clk_ops dpll_m4xen_ck_ops = {};
f38b0dd6
TK		 47#endif
48
aa76fcf4
TK		 49#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) || \
50 defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX) || \
51 defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
f38b0dd6
TK		 52static const struct clk_ops dpll_core_ck_ops = {
53 .recalc_rate = &omap3_dpll_recalc,
54 .get_parent = &omap2_init_dpll_parent,
55};
56
f38b0dd6
TK		 57static const struct clk_ops dpll_ck_ops = {
58 .enable = &omap3_noncore_dpll_enable,
59 .disable = &omap3_noncore_dpll_disable,
60 .recalc_rate = &omap3_dpll_recalc,
61 .round_rate = &omap2_dpll_round_rate,
62 .set_rate = &omap3_noncore_dpll_set_rate,
2e1a7b01
TK		 63 .set_parent = &omap3_noncore_dpll_set_parent,
64 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
65 .determine_rate = &omap3_noncore_dpll_determine_rate,
f38b0dd6 66 .get_parent = &omap2_init_dpll_parent,
d6e7bbc1
RD		 67 .save_context = &omap3_noncore_dpll_save_context,
68 .restore_context = &omap3_noncore_dpll_restore_context,
f38b0dd6
TK		 69};
70
71static const struct clk_ops dpll_no_gate_ck_ops = {
72 .recalc_rate = &omap3_dpll_recalc,
73 .get_parent = &omap2_init_dpll_parent,
74 .round_rate = &omap2_dpll_round_rate,
75 .set_rate = &omap3_noncore_dpll_set_rate,
2e1a7b01
TK		 76 .set_parent = &omap3_noncore_dpll_set_parent,
77 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
78 .determine_rate = &omap3_noncore_dpll_determine_rate,
d6e7bbc1
RD		 79 .save_context = &omap3_noncore_dpll_save_context,
80 .restore_context = &omap3_noncore_dpll_restore_context
f38b0dd6 81};
aa76fcf4
TK		 82#else
83static const struct clk_ops dpll_core_ck_ops = {};
84static const struct clk_ops dpll_ck_ops = {};
85static const struct clk_ops dpll_no_gate_ck_ops = {};
86const struct clk_hw_omap_ops clkhwops_omap3_dpll = {};
87#endif
88
89#ifdef CONFIG_ARCH_OMAP2
90static const struct clk_ops omap2_dpll_core_ck_ops = {
91 .get_parent = &omap2_init_dpll_parent,
92 .recalc_rate = &omap2_dpllcore_recalc,
93 .round_rate = &omap2_dpll_round_rate,
94 .set_rate = &omap2_reprogram_dpllcore,
95};
96#else
97static const struct clk_ops omap2_dpll_core_ck_ops = {};
98#endif
99
100#ifdef CONFIG_ARCH_OMAP3
101static const struct clk_ops omap3_dpll_core_ck_ops = {
102 .get_parent = &omap2_init_dpll_parent,
103 .recalc_rate = &omap3_dpll_recalc,
104 .round_rate = &omap2_dpll_round_rate,
105};
106#else
107static const struct clk_ops omap3_dpll_core_ck_ops = {};
108#endif
f38b0dd6
TK		 109
110#ifdef CONFIG_ARCH_OMAP3
111static const struct clk_ops omap3_dpll_ck_ops = {
112 .enable = &omap3_noncore_dpll_enable,
113 .disable = &omap3_noncore_dpll_disable,
114 .get_parent = &omap2_init_dpll_parent,
115 .recalc_rate = &omap3_dpll_recalc,
116 .set_rate = &omap3_noncore_dpll_set_rate,
2e1a7b01
TK		 117 .set_parent = &omap3_noncore_dpll_set_parent,
118 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
119 .determine_rate = &omap3_noncore_dpll_determine_rate,
f38b0dd6
TK		 120 .round_rate = &omap2_dpll_round_rate,
121};
122
035cd485
RW		 123static const struct clk_ops omap3_dpll5_ck_ops = {
124 .enable = &omap3_noncore_dpll_enable,
125 .disable = &omap3_noncore_dpll_disable,
126 .get_parent = &omap2_init_dpll_parent,
127 .recalc_rate = &omap3_dpll_recalc,
128 .set_rate = &omap3_dpll5_set_rate,
129 .set_parent = &omap3_noncore_dpll_set_parent,
130 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
131 .determine_rate = &omap3_noncore_dpll_determine_rate,
132 .round_rate = &omap2_dpll_round_rate,
133};
134
f38b0dd6
TK		 135static const struct clk_ops omap3_dpll_per_ck_ops = {
136 .enable = &omap3_noncore_dpll_enable,
137 .disable = &omap3_noncore_dpll_disable,
138 .get_parent = &omap2_init_dpll_parent,
139 .recalc_rate = &omap3_dpll_recalc,
140 .set_rate = &omap3_dpll4_set_rate,
2e1a7b01
TK		 141 .set_parent = &omap3_noncore_dpll_set_parent,
142 .set_rate_and_parent = &omap3_dpll4_set_rate_and_parent,
143 .determine_rate = &omap3_noncore_dpll_determine_rate,
f38b0dd6
TK		 144 .round_rate = &omap2_dpll_round_rate,
145};
146#endif
147
148static const struct clk_ops dpll_x2_ck_ops = {
149 .recalc_rate = &omap3_clkoutx2_recalc,
150};
151
152/**
ed405a23 153 * _register_dpll - low level registration of a DPLL clock
f38b0dd6
TK		 154 * @hw: hardware clock definition for the clock
155 * @node: device node for the clock
156 *
157 * Finalizes DPLL registration process. In case a failure (clk-ref or
158 * clk-bypass is missing), the clock is added to retry list and
159 * the initialization is retried on later stage.
160 */
ffb009b2 161static void __init _register_dpll(void *user,
ed405a23 162 struct device_node *node)
f38b0dd6 163{
ffb009b2 164 struct clk_hw *hw = user;
f38b0dd6
TK		 165 struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw);
166 struct dpll_data *dd = clk_hw->dpll_data;
167 struct clk *clk;
168
b6f51284
TK		 169 clk = of_clk_get(node, 0);
170 if (IS_ERR(clk)) {
e665f029
RH		 171 pr_debug("clk-ref missing for %pOFn, retry later\n",
172 node);
b6f51284
TK		 173 if (!ti_clk_retry_init(node, hw, _register_dpll))
174 return;
f38b0dd6 175
b6f51284
TK		 176 goto cleanup;
177 }
178
179 dd->clk_ref = __clk_get_hw(clk);
180
181 clk = of_clk_get(node, 1);
182
183 if (IS_ERR(clk)) {
e665f029
RH		 184 pr_debug("clk-bypass missing for %pOFn, retry later\n",
185 node);
ed405a23 186 if (!ti_clk_retry_init(node, hw, _register_dpll))
f38b0dd6
TK		 187 return;
188
189 goto cleanup;
190 }
191
b6f51284
TK		 192 dd->clk_bypass = __clk_get_hw(clk);
193
f38b0dd6 194 /* register the clock */
ead47825 195 clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, node->name);
f38b0dd6
TK		 196
197 if (!IS_ERR(clk)) {
f38b0dd6
TK		 198 of_clk_add_provider(node, of_clk_src_simple_get, clk);
199 kfree(clk_hw->hw.init->parent_names);
200 kfree(clk_hw->hw.init);
201 return;
202 }
203
204cleanup:
205 kfree(clk_hw->dpll_data);
206 kfree(clk_hw->hw.init->parent_names);
207 kfree(clk_hw->hw.init);
208 kfree(clk_hw);
209}
210
211#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
4332ec1a
RQ		 212 defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM33XX) || \
213 defined(CONFIG_SOC_AM43XX)
f38b0dd6 214/**
ed405a23 215 * _register_dpll_x2 - Registers a DPLLx2 clock
f38b0dd6
TK		 216 * @node: device node for this clock
217 * @ops: clk_ops for this clock
218 * @hw_ops: clk_hw_ops for this clock
219 *
220 * Initializes a DPLL x 2 clock from device tree data.
221 */
ed405a23
TK		 222static void _register_dpll_x2(struct device_node *node,
223 const struct clk_ops *ops,
224 const struct clk_hw_omap_ops *hw_ops)
f38b0dd6
TK		 225{
226 struct clk *clk;
227 struct clk_init_data init = { NULL };
228 struct clk_hw_omap *clk_hw;
229 const char *name = node->name;
230 const char *parent_name;
231
232 parent_name = of_clk_get_parent_name(node, 0);
233 if (!parent_name) {
e665f029 234 pr_err("%pOFn must have parent\n", node);
f38b0dd6
TK		 235 return;
236 }
237
238 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
239 if (!clk_hw)
240 return;
241
242 clk_hw->ops = hw_ops;
243 clk_hw->hw.init = &init;
244
245 init.name = name;
246 init.ops = ops;
247 init.parent_names = &parent_name;
248 init.num_parents = 1;
249
2158a093
AB		 250#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
251 defined(CONFIG_SOC_DRA7XX)
473adbf4 252 if (hw_ops == &clkhwops_omap4_dpllmx) {
2158a093
AB		 253 int ret;
254
473adbf4
TK		 255 /* Check if register defined, if not, drop hw-ops */
256 ret = of_property_count_elems_of_size(node, "reg", 1);
257 if (ret <= 0) {
2158a093 258 clk_hw->ops = NULL;
6c0afb50
TK		 259 } else if (ti_clk_get_reg_addr(node, 0, &clk_hw->clksel_reg)) {
260 kfree(clk_hw);
261 return;
473adbf4
TK		 262 }
263 }
2158a093 264#endif
473adbf4 265
f38b0dd6 266 /* register the clock */
ead47825 267 clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, name);
f38b0dd6 268
ead47825 269 if (IS_ERR(clk))
f38b0dd6 270 kfree(clk_hw);
ead47825 271 else
f38b0dd6 272 of_clk_add_provider(node, of_clk_src_simple_get, clk);
f38b0dd6
TK		 273}
274#endif
275
276/**
277 * of_ti_dpll_setup - Setup function for OMAP DPLL clocks
278 * @node: device node containing the DPLL info
279 * @ops: ops for the DPLL
280 * @ddt: DPLL data template to use
f38b0dd6
TK		 281 *
282 * Initializes a DPLL clock from device tree data.
283 */
284static void __init of_ti_dpll_setup(struct device_node *node,
285 const struct clk_ops *ops,
a6fe3771 286 const struct dpll_data *ddt)
f38b0dd6
TK		 287{
288 struct clk_hw_omap *clk_hw = NULL;
289 struct clk_init_data *init = NULL;
290 const char **parent_names = NULL;
291 struct dpll_data *dd = NULL;
f38b0dd6
TK		 292 u8 dpll_mode = 0;
293
294 dd = kzalloc(sizeof(*dd), GFP_KERNEL);
295 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
296 init = kzalloc(sizeof(*init), GFP_KERNEL);
297 if (!dd || !clk_hw || !init)
298 goto cleanup;
299
300 memcpy(dd, ddt, sizeof(*dd));
301
302 clk_hw->dpll_data = dd;
303 clk_hw->ops = &clkhwops_omap3_dpll;
304 clk_hw->hw.init = init;
f38b0dd6
TK		 305
306 init->name = node->name;
307 init->ops = ops;
308
309 init->num_parents = of_clk_get_parent_count(node);
921bacfa 310 if (!init->num_parents) {
e665f029 311 pr_err("%pOFn must have parent(s)\n", node);
f38b0dd6
TK		 312 goto cleanup;
313 }
314
6396bb22 315 parent_names = kcalloc(init->num_parents, sizeof(char *), GFP_KERNEL);
f38b0dd6
TK		 316 if (!parent_names)
317 goto cleanup;
318
9da9e761 319 of_clk_parent_fill(node, parent_names, init->num_parents);
f38b0dd6
TK		 320
321 init->parent_names = parent_names;
322
6c0afb50
TK		 323 if (ti_clk_get_reg_addr(node, 0, &dd->control_reg))
324 goto cleanup;
f38b0dd6 325
aa76fcf4
TK		 326 /*
327 * Special case for OMAP2 DPLL, register order is different due to
328 * missing idlest_reg, also clkhwops is different. Detected from
329 * missing idlest_mask.
330 */
331 if (!dd->idlest_mask) {
6c0afb50
TK		 332 if (ti_clk_get_reg_addr(node, 1, &dd->mult_div1_reg))
333 goto cleanup;
aa76fcf4
TK		 334#ifdef CONFIG_ARCH_OMAP2
335 clk_hw->ops = &clkhwops_omap2xxx_dpll;
336 omap2xxx_clkt_dpllcore_init(&clk_hw->hw);
337#endif
338 } else {
6c0afb50 339 if (ti_clk_get_reg_addr(node, 1, &dd->idlest_reg))
aa76fcf4
TK		 340 goto cleanup;
341
6c0afb50
TK		 342 if (ti_clk_get_reg_addr(node, 2, &dd->mult_div1_reg))
343 goto cleanup;
aa76fcf4
TK		 344 }
345
a6fe3771 346 if (dd->autoidle_mask) {
6c0afb50 347 if (ti_clk_get_reg_addr(node, 3, &dd->autoidle_reg))
f38b0dd6
TK		 348 goto cleanup;
349 }
350
351 if (of_property_read_bool(node, "ti,low-power-stop"))
352 dpll_mode |= 1 << DPLL_LOW_POWER_STOP;
353
354 if (of_property_read_bool(node, "ti,low-power-bypass"))
355 dpll_mode |= 1 << DPLL_LOW_POWER_BYPASS;
356
357 if (of_property_read_bool(node, "ti,lock"))
358 dpll_mode |= 1 << DPLL_LOCKED;
359
360 if (dpll_mode)
361 dd->modes = dpll_mode;
362
ed405a23 363 _register_dpll(&clk_hw->hw, node);
f38b0dd6
TK		 364 return;
365
366cleanup:
367 kfree(dd);
368 kfree(parent_names);
369 kfree(init);
370 kfree(clk_hw);
371}
372
373#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
374 defined(CONFIG_SOC_DRA7XX)
375static void __init of_ti_omap4_dpll_x2_setup(struct device_node *node)
376{
ed405a23 377 _register_dpll_x2(node, &dpll_x2_ck_ops, &clkhwops_omap4_dpllmx);
f38b0dd6
TK		 378}
379CLK_OF_DECLARE(ti_omap4_dpll_x2_clock, "ti,omap4-dpll-x2-clock",
380 of_ti_omap4_dpll_x2_setup);
381#endif
382
4332ec1a 383#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
f38b0dd6
TK		 384static void __init of_ti_am3_dpll_x2_setup(struct device_node *node)
385{
ed405a23 386 _register_dpll_x2(node, &dpll_x2_ck_ops, NULL);
f38b0dd6
TK		 387}
388CLK_OF_DECLARE(ti_am3_dpll_x2_clock, "ti,am3-dpll-x2-clock",
389 of_ti_am3_dpll_x2_setup);
390#endif
391
392#ifdef CONFIG_ARCH_OMAP3
393static void __init of_ti_omap3_dpll_setup(struct device_node *node)
394{
395 const struct dpll_data dd = {
396 .idlest_mask = 0x1,
397 .enable_mask = 0x7,
398 .autoidle_mask = 0x7,
399 .mult_mask = 0x7ff << 8,
400 .div1_mask = 0x7f,
401 .max_multiplier = 2047,
402 .max_divider = 128,
403 .min_divider = 1,
404 .freqsel_mask = 0xf0,
405 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
406 };
407
035cd485
RW		 408 if ((of_machine_is_compatible("ti,omap3630") ||
409 of_machine_is_compatible("ti,omap36xx")) &&
87ab1151 410 of_node_name_eq(node, "dpll5_ck"))
035cd485
RW		 411 of_ti_dpll_setup(node, &omap3_dpll5_ck_ops, &dd);
412 else
413 of_ti_dpll_setup(node, &omap3_dpll_ck_ops, &dd);
f38b0dd6
TK		 414}
415CLK_OF_DECLARE(ti_omap3_dpll_clock, "ti,omap3-dpll-clock",
416 of_ti_omap3_dpll_setup);
417
418static void __init of_ti_omap3_core_dpll_setup(struct device_node *node)
419{
420 const struct dpll_data dd = {
421 .idlest_mask = 0x1,
422 .enable_mask = 0x7,
423 .autoidle_mask = 0x7,
424 .mult_mask = 0x7ff << 16,
425 .div1_mask = 0x7f << 8,
426 .max_multiplier = 2047,
427 .max_divider = 128,
428 .min_divider = 1,
429 .freqsel_mask = 0xf0,
430 };
431
a6fe3771 432 of_ti_dpll_setup(node, &omap3_dpll_core_ck_ops, &dd);
f38b0dd6
TK		 433}
434CLK_OF_DECLARE(ti_omap3_core_dpll_clock, "ti,omap3-dpll-core-clock",
435 of_ti_omap3_core_dpll_setup);
436
437static void __init of_ti_omap3_per_dpll_setup(struct device_node *node)
438{
439 const struct dpll_data dd = {
440 .idlest_mask = 0x1 << 1,
441 .enable_mask = 0x7 << 16,
442 .autoidle_mask = 0x7 << 3,
443 .mult_mask = 0x7ff << 8,
444 .div1_mask = 0x7f,
445 .max_multiplier = 2047,
446 .max_divider = 128,
447 .min_divider = 1,
448 .freqsel_mask = 0xf00000,
449 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
450 };
451
a6fe3771 452 of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd);
f38b0dd6
TK		 453}
454CLK_OF_DECLARE(ti_omap3_per_dpll_clock, "ti,omap3-dpll-per-clock",
455 of_ti_omap3_per_dpll_setup);
456
457static void __init of_ti_omap3_per_jtype_dpll_setup(struct device_node *node)
458{
459 const struct dpll_data dd = {
460 .idlest_mask = 0x1 << 1,
461 .enable_mask = 0x7 << 16,
462 .autoidle_mask = 0x7 << 3,
463 .mult_mask = 0xfff << 8,
464 .div1_mask = 0x7f,
465 .max_multiplier = 4095,
466 .max_divider = 128,
467 .min_divider = 1,
468 .sddiv_mask = 0xff << 24,
469 .dco_mask = 0xe << 20,
470 .flags = DPLL_J_TYPE,
471 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
472 };
473
a6fe3771 474 of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd);
f38b0dd6
TK		 475}
476CLK_OF_DECLARE(ti_omap3_per_jtype_dpll_clock, "ti,omap3-dpll-per-j-type-clock",
477 of_ti_omap3_per_jtype_dpll_setup);
478#endif
479
480static void __init of_ti_omap4_dpll_setup(struct device_node *node)
481{
482 const struct dpll_data dd = {
483 .idlest_mask = 0x1,
484 .enable_mask = 0x7,
485 .autoidle_mask = 0x7,
486 .mult_mask = 0x7ff << 8,
487 .div1_mask = 0x7f,
488 .max_multiplier = 2047,
489 .max_divider = 128,
490 .min_divider = 1,
491 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
492 };
493
a6fe3771 494 of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
f38b0dd6
TK		 495}
496CLK_OF_DECLARE(ti_omap4_dpll_clock, "ti,omap4-dpll-clock",
497 of_ti_omap4_dpll_setup);
498
b4be0189
NM		 499static void __init of_ti_omap5_mpu_dpll_setup(struct device_node *node)
500{
501 const struct dpll_data dd = {
502 .idlest_mask = 0x1,
503 .enable_mask = 0x7,
504 .autoidle_mask = 0x7,
505 .mult_mask = 0x7ff << 8,
506 .div1_mask = 0x7f,
507 .max_multiplier = 2047,
508 .max_divider = 128,
509 .dcc_mask = BIT(22),
510 .dcc_rate = 1400000000, /* DCC beyond 1.4GHz */
511 .min_divider = 1,
512 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
513 };
514
515 of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
516}
517CLK_OF_DECLARE(of_ti_omap5_mpu_dpll_clock, "ti,omap5-mpu-dpll-clock",
518 of_ti_omap5_mpu_dpll_setup);
519
f38b0dd6
TK		 520static void __init of_ti_omap4_core_dpll_setup(struct device_node *node)
521{
522 const struct dpll_data dd = {
523 .idlest_mask = 0x1,
524 .enable_mask = 0x7,
525 .autoidle_mask = 0x7,
526 .mult_mask = 0x7ff << 8,
527 .div1_mask = 0x7f,
528 .max_multiplier = 2047,
529 .max_divider = 128,
530 .min_divider = 1,
531 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
532 };
533
a6fe3771 534 of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd);
f38b0dd6
TK		 535}
536CLK_OF_DECLARE(ti_omap4_core_dpll_clock, "ti,omap4-dpll-core-clock",
537 of_ti_omap4_core_dpll_setup);
538
539#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
540 defined(CONFIG_SOC_DRA7XX)
541static void __init of_ti_omap4_m4xen_dpll_setup(struct device_node *node)
542{
543 const struct dpll_data dd = {
544 .idlest_mask = 0x1,
545 .enable_mask = 0x7,
546 .autoidle_mask = 0x7,
547 .mult_mask = 0x7ff << 8,
548 .div1_mask = 0x7f,
549 .max_multiplier = 2047,
550 .max_divider = 128,
551 .min_divider = 1,
552 .m4xen_mask = 0x800,
553 .lpmode_mask = 1 << 10,
554 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
555 };
556
a6fe3771 557 of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd);
f38b0dd6
TK		 558}
559CLK_OF_DECLARE(ti_omap4_m4xen_dpll_clock, "ti,omap4-dpll-m4xen-clock",
560 of_ti_omap4_m4xen_dpll_setup);
561
562static void __init of_ti_omap4_jtype_dpll_setup(struct device_node *node)
563{
564 const struct dpll_data dd = {
565 .idlest_mask = 0x1,
566 .enable_mask = 0x7,
567 .autoidle_mask = 0x7,
568 .mult_mask = 0xfff << 8,
569 .div1_mask = 0xff,
570 .max_multiplier = 4095,
571 .max_divider = 256,
572 .min_divider = 1,
573 .sddiv_mask = 0xff << 24,
574 .flags = DPLL_J_TYPE,
575 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
576 };
577
a6fe3771 578 of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd);
f38b0dd6
TK		 579}
580CLK_OF_DECLARE(ti_omap4_jtype_dpll_clock, "ti,omap4-dpll-j-type-clock",
581 of_ti_omap4_jtype_dpll_setup);
582#endif
583
584static void __init of_ti_am3_no_gate_dpll_setup(struct device_node *node)
585{
586 const struct dpll_data dd = {
587 .idlest_mask = 0x1,
588 .enable_mask = 0x7,
f38b0dd6
TK		 589 .mult_mask = 0x7ff << 8,
590 .div1_mask = 0x7f,
591 .max_multiplier = 2047,
592 .max_divider = 128,
593 .min_divider = 1,
3db5ca27 594 .max_rate = 1000000000,
f38b0dd6
TK		 595 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
596 };
597
a6fe3771 598 of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd);
f38b0dd6
TK		 599}
600CLK_OF_DECLARE(ti_am3_no_gate_dpll_clock, "ti,am3-dpll-no-gate-clock",
601 of_ti_am3_no_gate_dpll_setup);
602
603static void __init of_ti_am3_jtype_dpll_setup(struct device_node *node)
604{
605 const struct dpll_data dd = {
606 .idlest_mask = 0x1,
607 .enable_mask = 0x7,
f38b0dd6
TK		 608 .mult_mask = 0x7ff << 8,
609 .div1_mask = 0x7f,
610 .max_multiplier = 4095,
611 .max_divider = 256,
612 .min_divider = 2,
613 .flags = DPLL_J_TYPE,
3db5ca27 614 .max_rate = 2000000000,
f38b0dd6
TK		 615 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
616 };
617
a6fe3771 618 of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
f38b0dd6
TK		 619}
620CLK_OF_DECLARE(ti_am3_jtype_dpll_clock, "ti,am3-dpll-j-type-clock",
621 of_ti_am3_jtype_dpll_setup);
622
623static void __init of_ti_am3_no_gate_jtype_dpll_setup(struct device_node *node)
624{
625 const struct dpll_data dd = {
626 .idlest_mask = 0x1,
627 .enable_mask = 0x7,
f38b0dd6
TK		 628 .mult_mask = 0x7ff << 8,
629 .div1_mask = 0x7f,
630 .max_multiplier = 2047,
631 .max_divider = 128,
632 .min_divider = 1,
3db5ca27 633 .max_rate = 2000000000,
f38b0dd6
TK		 634 .flags = DPLL_J_TYPE,
635 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
636 };
637
a6fe3771 638 of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd);
f38b0dd6
TK		 639}
640CLK_OF_DECLARE(ti_am3_no_gate_jtype_dpll_clock,
641 "ti,am3-dpll-no-gate-j-type-clock",
642 of_ti_am3_no_gate_jtype_dpll_setup);
643
644static void __init of_ti_am3_dpll_setup(struct device_node *node)
645{
646 const struct dpll_data dd = {
647 .idlest_mask = 0x1,
648 .enable_mask = 0x7,
f38b0dd6
TK		 649 .mult_mask = 0x7ff << 8,
650 .div1_mask = 0x7f,
651 .max_multiplier = 2047,
652 .max_divider = 128,
653 .min_divider = 1,
3db5ca27 654 .max_rate = 1000000000,
f38b0dd6
TK		 655 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
656 };
657
a6fe3771 658 of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
f38b0dd6
TK		 659}
660CLK_OF_DECLARE(ti_am3_dpll_clock, "ti,am3-dpll-clock", of_ti_am3_dpll_setup);
661
662static void __init of_ti_am3_core_dpll_setup(struct device_node *node)
663{
664 const struct dpll_data dd = {
665 .idlest_mask = 0x1,
666 .enable_mask = 0x7,
f38b0dd6
TK		 667 .mult_mask = 0x7ff << 8,
668 .div1_mask = 0x7f,
669 .max_multiplier = 2047,
670 .max_divider = 128,
671 .min_divider = 1,
3db5ca27 672 .max_rate = 1000000000,
f38b0dd6
TK		 673 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
674 };
675
a6fe3771 676 of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd);
f38b0dd6
TK		 677}
678CLK_OF_DECLARE(ti_am3_core_dpll_clock, "ti,am3-dpll-core-clock",
679 of_ti_am3_core_dpll_setup);
aa76fcf4
TK		 680
681static void __init of_ti_omap2_core_dpll_setup(struct device_node *node)
682{
683 const struct dpll_data dd = {
684 .enable_mask = 0x3,
685 .mult_mask = 0x3ff << 12,
686 .div1_mask = 0xf << 8,
687 .max_divider = 16,
688 .min_divider = 1,
689 };
690
691 of_ti_dpll_setup(node, &omap2_dpll_core_ck_ops, &dd);
692}
693CLK_OF_DECLARE(ti_omap2_core_dpll_clock, "ti,omap2-dpll-core-clock",
694 of_ti_omap2_core_dpll_setup);
Linux 6.x block layer and io_uring tree(s)