projects / linux-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
clk: ti: am33xx: rename existing clkctrl data as compat data
[linux-block.git] / drivers / clk / ti / clock.h
CommitLineData
c82f8957
TK		 1/*
2 * TI Clock driver internal definitions
3 *
4 * Copyright (C) 2014 Texas Instruments, Inc
5 * Tero Kristo (t-kristo@ti.com)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16#ifndef __DRIVERS_CLK_TI_CLOCK__
17#define __DRIVERS_CLK_TI_CLOCK__
18
6dbde947
TK		 19struct clk_omap_divider {
20 struct clk_hw hw;
6c0afb50 21 struct clk_omap_reg reg;
6dbde947
TK		 22 u8 shift;
23 u8 width;
24 u8 flags;
b44a0300 25 s8 latch;
6dbde947
TK		 26 const struct clk_div_table *table;
27};
28
29#define to_clk_omap_divider(_hw) container_of(_hw, struct clk_omap_divider, hw)
30
d83bc5b6
TK		 31struct clk_omap_mux {
32 struct clk_hw hw;
6c0afb50 33 struct clk_omap_reg reg;
d83bc5b6
TK		 34 u32 *table;
35 u32 mask;
36 u8 shift;
ee2fc3c5 37 s8 latch;
d83bc5b6
TK		 38 u8 flags;
39};
40
41#define to_clk_omap_mux(_hw) container_of(_hw, struct clk_omap_mux, hw)
42
c82f8957
TK		 43enum {
44 TI_CLK_FIXED,
45 TI_CLK_MUX,
46 TI_CLK_DIVIDER,
47 TI_CLK_COMPOSITE,
48 TI_CLK_FIXED_FACTOR,
49 TI_CLK_GATE,
50 TI_CLK_DPLL,
51};
52
53/* Global flags */
54#define CLKF_INDEX_POWER_OF_TWO (1 << 0)
55#define CLKF_INDEX_STARTS_AT_ONE (1 << 1)
56#define CLKF_SET_RATE_PARENT (1 << 2)
57#define CLKF_OMAP3 (1 << 3)
58#define CLKF_AM35XX (1 << 4)
59
60/* Gate flags */
61#define CLKF_SET_BIT_TO_DISABLE (1 << 5)
62#define CLKF_INTERFACE (1 << 6)
63#define CLKF_SSI (1 << 7)
64#define CLKF_DSS (1 << 8)
65#define CLKF_HSOTGUSB (1 << 9)
66#define CLKF_WAIT (1 << 10)
67#define CLKF_NO_WAIT (1 << 11)
68#define CLKF_HSDIV (1 << 12)
69#define CLKF_CLKDM (1 << 13)
70
71/* DPLL flags */
72#define CLKF_LOW_POWER_STOP (1 << 5)
73#define CLKF_LOCK (1 << 6)
74#define CLKF_LOW_POWER_BYPASS (1 << 7)
75#define CLKF_PER (1 << 8)
76#define CLKF_CORE (1 << 9)
77#define CLKF_J_TYPE (1 << 10)
78
269bd202
TK		 79/* CLKCTRL flags */
80#define CLKF_SW_SUP BIT(5)
81#define CLKF_HW_SUP BIT(6)
82#define CLKF_NO_IDLEST BIT(7)
83
c82f8957
TK		 84#define CLK(dev, con, ck) \
85 { \
86 .lk = { \
87 .dev_id = dev, \
88 .con_id = con, \
89 }, \
90 .clk = ck, \
91 }
92
93struct ti_clk {
94 const char *name;
95 const char *clkdm_name;
96 int type;
97 void *data;
98 struct ti_clk *patch;
99 struct clk *clk;
100};
101
c82f8957
TK		 102struct ti_clk_mux {
103 u8 bit_shift;
104 int num_parents;
105 u16 reg;
106 u8 module;
ce382d47 107 const char * const *parents;
c82f8957
TK		 108 u16 flags;
109};
110
111struct ti_clk_divider {
112 const char *parent;
113 u8 bit_shift;
114 u16 max_div;
115 u16 reg;
116 u8 module;
117 int *dividers;
118 int num_dividers;
119 u16 flags;
120};
121
c82f8957
TK		 122struct ti_clk_gate {
123 const char *parent;
124 u8 bit_shift;
125 u16 reg;
126 u8 module;
127 u16 flags;
128};
129
a3314e9c
TK		 130/* Composite clock component types */
131enum {
132 CLK_COMPONENT_TYPE_GATE = 0,
133 CLK_COMPONENT_TYPE_DIVIDER,
134 CLK_COMPONENT_TYPE_MUX,
135 CLK_COMPONENT_TYPE_MAX,
136};
137
138/**
139 * struct ti_dt_clk - OMAP DT clock alias declarations
140 * @lk: clock lookup definition
141 * @node_name: clock DT node to map to
142 */
143struct ti_dt_clk {
144 struct clk_lookup lk;
145 char *node_name;
146};
147
148#define DT_CLK(dev, con, name) \
149 { \
150 .lk = { \
151 .dev_id = dev, \
152 .con_id = con, \
153 }, \
154 .node_name = name, \
155 }
156
88a17252
TK		 157/* CLKCTRL type definitions */
158struct omap_clkctrl_div_data {
159 const int *dividers;
160 int max_div;
49eec6fb 161 u32 flags;
88a17252
TK		 162};
163
164struct omap_clkctrl_bit_data {
165 u8 bit;
166 u8 type;
167 const char * const *parents;
168 const void *data;
169};
170
171struct omap_clkctrl_reg_data {
172 u16 offset;
173 const struct omap_clkctrl_bit_data *bit_data;
174 u16 flags;
175 const char *parent;
ddfb183e 176 const char *clkdm_name;
88a17252
TK		 177};
178
179struct omap_clkctrl_data {
180 u32 addr;
181 const struct omap_clkctrl_reg_data *regs;
182};
183
1c881b5a 184extern const struct omap_clkctrl_data omap4_clkctrl_data[];
0ad902f6 185extern const struct omap_clkctrl_data omap5_clkctrl_data[];
24d504a3 186extern const struct omap_clkctrl_data dra7_clkctrl_data[];
e97017f9
TK		 187extern const struct omap_clkctrl_data am3_clkctrl_compat_data[];
188extern struct ti_dt_clk am33xx_compat_clks[];
a3da10b7
TK		 189extern const struct omap_clkctrl_data am4_clkctrl_data[];
190extern const struct omap_clkctrl_data am438x_clkctrl_data[];
26ca2e97 191extern const struct omap_clkctrl_data dm814_clkctrl_data[];
50ef5089 192extern const struct omap_clkctrl_data dm816_clkctrl_data[];
1c881b5a 193
ffb009b2 194typedef void (*ti_of_clk_init_cb_t)(void *, struct device_node *);
a3314e9c 195
21f0bf2d
TK		 196struct clk *ti_clk_register(struct device *dev, struct clk_hw *hw,
197 const char *con);
198int ti_clk_add_alias(struct device *dev, struct clk *clk, const char *con);
c17435c5 199void ti_clk_add_aliases(void);
7c18a65c 200
e31922ed
TK		 201void ti_clk_latch(struct clk_omap_reg *reg, s8 shift);
202
7c18a65c
TK		 203struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup);
204
4f6be565
TK		 205int ti_clk_parse_divider_data(int *div_table, int num_dividers, int max_div,
206 u8 flags, u8 *width,
207 const struct clk_div_table **table);
208
6c0afb50
TK		 209int ti_clk_get_reg_addr(struct device_node *node, int index,
210 struct clk_omap_reg *reg);
a3314e9c 211void ti_dt_clocks_register(struct ti_dt_clk *oclks);
ffb009b2 212int ti_clk_retry_init(struct device_node *node, void *user,
a3314e9c
TK		 213 ti_of_clk_init_cb_t func);
214int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type);
215
a53ad8ef 216void omap2_init_clk_hw_omap_clocks(struct clk_hw *hw);
bf22bae7 217int of_ti_clk_autoidle_setup(struct device_node *node);
a5aa8a60 218void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
bf22bae7 219
0565fb16 220extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
59245ce0 221extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
9f37e90e 222extern const struct clk_hw_omap_ops clkhwops_wait;
ef14db09
TK		 223extern const struct clk_hw_omap_ops clkhwops_iclk;
224extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
d5a04ddd 225extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait;
f2671d5c
TK		 226extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
227extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
228extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
229extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
c9a58b0a
TK		 230extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
231extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait;
59245ce0 232
a3314e9c
TK		 233extern const struct clk_ops ti_clk_divider_ops;
234extern const struct clk_ops ti_clk_mux_ops;
9a00fa68 235extern const struct clk_ops omap_gate_clk_ops;
a3314e9c 236
47b00dcf
TK		 237extern struct ti_clk_features ti_clk_features;
238
2e1a294c 239void omap2_init_clk_clkdm(struct clk_hw *hw);
bd86cfdc
TK		 240int omap2_clkops_enable_clkdm(struct clk_hw *hw);
241void omap2_clkops_disable_clkdm(struct clk_hw *hw);
242
9f37e90e
TK		 243int omap2_dflt_clk_enable(struct clk_hw *hw);
244void omap2_dflt_clk_disable(struct clk_hw *hw);
245int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
a3314e9c 246void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
6c0afb50 247 struct clk_omap_reg *other_reg,
a3314e9c
TK		 248 u8 *other_bit);
249void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
6c0afb50 250 struct clk_omap_reg *idlest_reg,
a3314e9c
TK		 251 u8 *idlest_bit, u8 *idlest_val);
252
253void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk);
254void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);
9f37e90e 255
b138b028 256u8 omap2_init_dpll_parent(struct clk_hw *hw);
0565fb16
TK		 257int omap3_noncore_dpll_enable(struct clk_hw *hw);
258void omap3_noncore_dpll_disable(struct clk_hw *hw);
259int omap3_noncore_dpll_set_parent(struct clk_hw *hw, u8 index);
260int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
261 unsigned long parent_rate);
262int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw,
263 unsigned long rate,
264 unsigned long parent_rate,
265 u8 index);
4d341056
SB		 266int omap3_noncore_dpll_determine_rate(struct clk_hw *hw,
267 struct clk_rate_request *req);
0565fb16
TK		 268long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
269 unsigned long *parent_rate);
270unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
271 unsigned long parent_rate);
272
035cd485
RW		 273/*
274 * OMAP3_DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks
275 * that are sourced by DPLL5, and both of these require this clock
276 * to be at 120 MHz for proper operation.
277 */
278#define OMAP3_DPLL5_FREQ_FOR_USBHOST 120000000
279
0565fb16
TK		 280unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
281int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
282 unsigned long parent_rate);
283int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
284 unsigned long parent_rate, u8 index);
035cd485
RW		 285int omap3_dpll5_set_rate(struct clk_hw *hw, unsigned long rate,
286 unsigned long parent_rate);
0565fb16 287void omap3_clk_lock_dpll5(void);
b138b028 288
59245ce0
TK		 289unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
290 unsigned long parent_rate);
291long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
292 unsigned long target_rate,
293 unsigned long *parent_rate);
4d341056
SB		 294int omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw,
295 struct clk_rate_request *req);
59245ce0 296
e9e63088
TK		 297extern struct ti_clk_ll_ops *ti_clk_ll_ops;
298
c82f8957 299#endif
Linux 6.x block layer and io_uring tree(s)