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c82f8957 TK |
1 | /* |
2 | * TI Clock driver internal definitions | |
3 | * | |
4 | * Copyright (C) 2014 Texas Instruments, Inc | |
5 | * Tero Kristo (t-kristo@ti.com) | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation version 2. | |
10 | * | |
11 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
12 | * kind, whether express or implied; without even the implied warranty | |
13 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | */ | |
16 | #ifndef __DRIVERS_CLK_TI_CLOCK__ | |
17 | #define __DRIVERS_CLK_TI_CLOCK__ | |
18 | ||
6dbde947 TK |
19 | struct clk_omap_divider { |
20 | struct clk_hw hw; | |
6c0afb50 | 21 | struct clk_omap_reg reg; |
6dbde947 | 22 | u8 shift; |
6dbde947 | 23 | u8 flags; |
b44a0300 | 24 | s8 latch; |
8ffea6ee TK |
25 | u16 min; |
26 | u16 max; | |
27 | u16 mask; | |
6dbde947 | 28 | const struct clk_div_table *table; |
d6e7bbc1 | 29 | u32 context; |
6dbde947 TK |
30 | }; |
31 | ||
32 | #define to_clk_omap_divider(_hw) container_of(_hw, struct clk_omap_divider, hw) | |
33 | ||
d83bc5b6 TK |
34 | struct clk_omap_mux { |
35 | struct clk_hw hw; | |
6c0afb50 | 36 | struct clk_omap_reg reg; |
d83bc5b6 TK |
37 | u32 *table; |
38 | u32 mask; | |
39 | u8 shift; | |
ee2fc3c5 | 40 | s8 latch; |
d83bc5b6 | 41 | u8 flags; |
d6e7bbc1 | 42 | u8 saved_parent; |
d83bc5b6 TK |
43 | }; |
44 | ||
45 | #define to_clk_omap_mux(_hw) container_of(_hw, struct clk_omap_mux, hw) | |
46 | ||
c82f8957 TK |
47 | enum { |
48 | TI_CLK_FIXED, | |
49 | TI_CLK_MUX, | |
50 | TI_CLK_DIVIDER, | |
51 | TI_CLK_COMPOSITE, | |
52 | TI_CLK_FIXED_FACTOR, | |
53 | TI_CLK_GATE, | |
54 | TI_CLK_DPLL, | |
55 | }; | |
56 | ||
57 | /* Global flags */ | |
58 | #define CLKF_INDEX_POWER_OF_TWO (1 << 0) | |
59 | #define CLKF_INDEX_STARTS_AT_ONE (1 << 1) | |
60 | #define CLKF_SET_RATE_PARENT (1 << 2) | |
61 | #define CLKF_OMAP3 (1 << 3) | |
62 | #define CLKF_AM35XX (1 << 4) | |
63 | ||
64 | /* Gate flags */ | |
65 | #define CLKF_SET_BIT_TO_DISABLE (1 << 5) | |
66 | #define CLKF_INTERFACE (1 << 6) | |
67 | #define CLKF_SSI (1 << 7) | |
68 | #define CLKF_DSS (1 << 8) | |
69 | #define CLKF_HSOTGUSB (1 << 9) | |
70 | #define CLKF_WAIT (1 << 10) | |
71 | #define CLKF_NO_WAIT (1 << 11) | |
72 | #define CLKF_HSDIV (1 << 12) | |
73 | #define CLKF_CLKDM (1 << 13) | |
74 | ||
75 | /* DPLL flags */ | |
76 | #define CLKF_LOW_POWER_STOP (1 << 5) | |
77 | #define CLKF_LOCK (1 << 6) | |
78 | #define CLKF_LOW_POWER_BYPASS (1 << 7) | |
79 | #define CLKF_PER (1 << 8) | |
80 | #define CLKF_CORE (1 << 9) | |
81 | #define CLKF_J_TYPE (1 << 10) | |
82 | ||
269bd202 TK |
83 | /* CLKCTRL flags */ |
84 | #define CLKF_SW_SUP BIT(5) | |
85 | #define CLKF_HW_SUP BIT(6) | |
86 | #define CLKF_NO_IDLEST BIT(7) | |
87 | ||
869decd1 | 88 | #define CLKF_SOC_MASK GENMASK(11, 8) |
2b1202d7 | 89 | |
869decd1 TK |
90 | #define CLKF_SOC_NONSEC BIT(8) |
91 | #define CLKF_SOC_DRA72 BIT(9) | |
92 | #define CLKF_SOC_DRA74 BIT(10) | |
93 | #define CLKF_SOC_DRA76 BIT(11) | |
2b1202d7 | 94 | |
c82f8957 TK |
95 | #define CLK(dev, con, ck) \ |
96 | { \ | |
97 | .lk = { \ | |
98 | .dev_id = dev, \ | |
99 | .con_id = con, \ | |
100 | }, \ | |
101 | .clk = ck, \ | |
102 | } | |
103 | ||
104 | struct ti_clk { | |
105 | const char *name; | |
106 | const char *clkdm_name; | |
107 | int type; | |
108 | void *data; | |
109 | struct ti_clk *patch; | |
110 | struct clk *clk; | |
111 | }; | |
112 | ||
c82f8957 TK |
113 | struct ti_clk_mux { |
114 | u8 bit_shift; | |
115 | int num_parents; | |
116 | u16 reg; | |
117 | u8 module; | |
ce382d47 | 118 | const char * const *parents; |
c82f8957 TK |
119 | u16 flags; |
120 | }; | |
121 | ||
122 | struct ti_clk_divider { | |
123 | const char *parent; | |
124 | u8 bit_shift; | |
125 | u16 max_div; | |
126 | u16 reg; | |
127 | u8 module; | |
128 | int *dividers; | |
129 | int num_dividers; | |
130 | u16 flags; | |
131 | }; | |
132 | ||
c82f8957 TK |
133 | struct ti_clk_gate { |
134 | const char *parent; | |
135 | u8 bit_shift; | |
136 | u16 reg; | |
137 | u8 module; | |
138 | u16 flags; | |
139 | }; | |
140 | ||
a3314e9c TK |
141 | /* Composite clock component types */ |
142 | enum { | |
143 | CLK_COMPONENT_TYPE_GATE = 0, | |
144 | CLK_COMPONENT_TYPE_DIVIDER, | |
145 | CLK_COMPONENT_TYPE_MUX, | |
146 | CLK_COMPONENT_TYPE_MAX, | |
147 | }; | |
148 | ||
149 | /** | |
150 | * struct ti_dt_clk - OMAP DT clock alias declarations | |
151 | * @lk: clock lookup definition | |
152 | * @node_name: clock DT node to map to | |
153 | */ | |
154 | struct ti_dt_clk { | |
155 | struct clk_lookup lk; | |
156 | char *node_name; | |
157 | }; | |
158 | ||
159 | #define DT_CLK(dev, con, name) \ | |
160 | { \ | |
161 | .lk = { \ | |
162 | .dev_id = dev, \ | |
163 | .con_id = con, \ | |
164 | }, \ | |
165 | .node_name = name, \ | |
166 | } | |
167 | ||
88a17252 TK |
168 | /* CLKCTRL type definitions */ |
169 | struct omap_clkctrl_div_data { | |
170 | const int *dividers; | |
171 | int max_div; | |
49eec6fb | 172 | u32 flags; |
88a17252 TK |
173 | }; |
174 | ||
175 | struct omap_clkctrl_bit_data { | |
176 | u8 bit; | |
177 | u8 type; | |
178 | const char * const *parents; | |
179 | const void *data; | |
180 | }; | |
181 | ||
182 | struct omap_clkctrl_reg_data { | |
183 | u16 offset; | |
184 | const struct omap_clkctrl_bit_data *bit_data; | |
185 | u16 flags; | |
186 | const char *parent; | |
ddfb183e | 187 | const char *clkdm_name; |
88a17252 TK |
188 | }; |
189 | ||
190 | struct omap_clkctrl_data { | |
191 | u32 addr; | |
192 | const struct omap_clkctrl_reg_data *regs; | |
193 | }; | |
194 | ||
1c881b5a | 195 | extern const struct omap_clkctrl_data omap4_clkctrl_data[]; |
0ad902f6 | 196 | extern const struct omap_clkctrl_data omap5_clkctrl_data[]; |
dffa9051 | 197 | extern const struct omap_clkctrl_data dra7_clkctrl_data[]; |
43c56e04 TK |
198 | extern const struct omap_clkctrl_data dra7_clkctrl_compat_data[]; |
199 | extern struct ti_dt_clk dra7xx_compat_clks[]; | |
296e583e | 200 | extern const struct omap_clkctrl_data am3_clkctrl_data[]; |
e97017f9 TK |
201 | extern const struct omap_clkctrl_data am3_clkctrl_compat_data[]; |
202 | extern struct ti_dt_clk am33xx_compat_clks[]; | |
76a1049b | 203 | extern const struct omap_clkctrl_data am4_clkctrl_data[]; |
131ee08f TK |
204 | extern const struct omap_clkctrl_data am4_clkctrl_compat_data[]; |
205 | extern struct ti_dt_clk am43xx_compat_clks[]; | |
76a1049b | 206 | extern const struct omap_clkctrl_data am438x_clkctrl_data[]; |
131ee08f | 207 | extern const struct omap_clkctrl_data am438x_clkctrl_compat_data[]; |
26ca2e97 | 208 | extern const struct omap_clkctrl_data dm814_clkctrl_data[]; |
50ef5089 | 209 | extern const struct omap_clkctrl_data dm816_clkctrl_data[]; |
1c881b5a | 210 | |
ffb009b2 | 211 | typedef void (*ti_of_clk_init_cb_t)(void *, struct device_node *); |
a3314e9c | 212 | |
21f0bf2d TK |
213 | struct clk *ti_clk_register(struct device *dev, struct clk_hw *hw, |
214 | const char *con); | |
ead47825 TK |
215 | struct clk *ti_clk_register_omap_hw(struct device *dev, struct clk_hw *hw, |
216 | const char *con); | |
21f0bf2d | 217 | int ti_clk_add_alias(struct device *dev, struct clk *clk, const char *con); |
c17435c5 | 218 | void ti_clk_add_aliases(void); |
7c18a65c | 219 | |
e31922ed TK |
220 | void ti_clk_latch(struct clk_omap_reg *reg, s8 shift); |
221 | ||
7c18a65c TK |
222 | struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup); |
223 | ||
4f6be565 | 224 | int ti_clk_parse_divider_data(int *div_table, int num_dividers, int max_div, |
a229965c | 225 | u8 flags, struct clk_omap_divider *div); |
4f6be565 | 226 | |
6c0afb50 TK |
227 | int ti_clk_get_reg_addr(struct device_node *node, int index, |
228 | struct clk_omap_reg *reg); | |
a3314e9c | 229 | void ti_dt_clocks_register(struct ti_dt_clk *oclks); |
ffb009b2 | 230 | int ti_clk_retry_init(struct device_node *node, void *user, |
a3314e9c TK |
231 | ti_of_clk_init_cb_t func); |
232 | int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type); | |
233 | ||
bf22bae7 | 234 | int of_ti_clk_autoidle_setup(struct device_node *node); |
a5aa8a60 | 235 | void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks); |
bf22bae7 | 236 | |
0565fb16 | 237 | extern const struct clk_hw_omap_ops clkhwops_omap3_dpll; |
59245ce0 | 238 | extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx; |
9f37e90e | 239 | extern const struct clk_hw_omap_ops clkhwops_wait; |
ef14db09 TK |
240 | extern const struct clk_hw_omap_ops clkhwops_iclk; |
241 | extern const struct clk_hw_omap_ops clkhwops_iclk_wait; | |
d5a04ddd | 242 | extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait; |
f2671d5c TK |
243 | extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait; |
244 | extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait; | |
245 | extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait; | |
246 | extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait; | |
c9a58b0a TK |
247 | extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait; |
248 | extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait; | |
59245ce0 | 249 | |
a3314e9c TK |
250 | extern const struct clk_ops ti_clk_divider_ops; |
251 | extern const struct clk_ops ti_clk_mux_ops; | |
9a00fa68 | 252 | extern const struct clk_ops omap_gate_clk_ops; |
a3314e9c | 253 | |
47b00dcf TK |
254 | extern struct ti_clk_features ti_clk_features; |
255 | ||
89d079dc | 256 | int omap2_init_clk_clkdm(struct clk_hw *hw); |
bd86cfdc TK |
257 | int omap2_clkops_enable_clkdm(struct clk_hw *hw); |
258 | void omap2_clkops_disable_clkdm(struct clk_hw *hw); | |
259 | ||
9f37e90e TK |
260 | int omap2_dflt_clk_enable(struct clk_hw *hw); |
261 | void omap2_dflt_clk_disable(struct clk_hw *hw); | |
262 | int omap2_dflt_clk_is_enabled(struct clk_hw *hw); | |
a3314e9c | 263 | void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, |
6c0afb50 | 264 | struct clk_omap_reg *other_reg, |
a3314e9c TK |
265 | u8 *other_bit); |
266 | void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, | |
6c0afb50 | 267 | struct clk_omap_reg *idlest_reg, |
a3314e9c TK |
268 | u8 *idlest_bit, u8 *idlest_val); |
269 | ||
270 | void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk); | |
271 | void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk); | |
9f37e90e | 272 | |
b138b028 | 273 | u8 omap2_init_dpll_parent(struct clk_hw *hw); |
0565fb16 TK |
274 | int omap3_noncore_dpll_enable(struct clk_hw *hw); |
275 | void omap3_noncore_dpll_disable(struct clk_hw *hw); | |
276 | int omap3_noncore_dpll_set_parent(struct clk_hw *hw, u8 index); | |
277 | int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, | |
278 | unsigned long parent_rate); | |
279 | int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw, | |
280 | unsigned long rate, | |
281 | unsigned long parent_rate, | |
282 | u8 index); | |
4d341056 SB |
283 | int omap3_noncore_dpll_determine_rate(struct clk_hw *hw, |
284 | struct clk_rate_request *req); | |
0565fb16 TK |
285 | long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, |
286 | unsigned long *parent_rate); | |
287 | unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw, | |
288 | unsigned long parent_rate); | |
289 | ||
035cd485 RW |
290 | /* |
291 | * OMAP3_DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks | |
292 | * that are sourced by DPLL5, and both of these require this clock | |
293 | * to be at 120 MHz for proper operation. | |
294 | */ | |
295 | #define OMAP3_DPLL5_FREQ_FOR_USBHOST 120000000 | |
296 | ||
0565fb16 TK |
297 | unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate); |
298 | int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate, | |
299 | unsigned long parent_rate); | |
300 | int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate, | |
301 | unsigned long parent_rate, u8 index); | |
035cd485 RW |
302 | int omap3_dpll5_set_rate(struct clk_hw *hw, unsigned long rate, |
303 | unsigned long parent_rate); | |
0565fb16 | 304 | void omap3_clk_lock_dpll5(void); |
b138b028 | 305 | |
59245ce0 TK |
306 | unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, |
307 | unsigned long parent_rate); | |
308 | long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw, | |
309 | unsigned long target_rate, | |
310 | unsigned long *parent_rate); | |
4d341056 SB |
311 | int omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, |
312 | struct clk_rate_request *req); | |
77b773ae | 313 | int omap2_clk_for_each(int (*fn)(struct clk_hw_omap *hw)); |
59245ce0 | 314 | |
e9e63088 TK |
315 | extern struct ti_clk_ll_ops *ti_clk_ll_ops; |
316 | ||
c82f8957 | 317 | #endif |