[linux-block.git] / drivers / clk / ti / clock.h

/*
 * TI Clock driver internal definitions
 *
 * Copyright (C) 2014 Texas Instruments, Inc
 *     Tero Kristo (t-kristo@ti.com)
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation version 2.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 */
#ifndef __DRIVERS_CLK_TI_CLOCK__
#define __DRIVERS_CLK_TI_CLOCK__

enum {
	TI_CLK_FIXED,
	TI_CLK_MUX,
	TI_CLK_DIVIDER,
	TI_CLK_COMPOSITE,
	TI_CLK_FIXED_FACTOR,
	TI_CLK_GATE,
	TI_CLK_DPLL,
};

/* Global flags */
#define CLKF_INDEX_POWER_OF_TWO		(1 << 0)
#define CLKF_INDEX_STARTS_AT_ONE	(1 << 1)
#define CLKF_SET_RATE_PARENT		(1 << 2)
#define CLKF_OMAP3			(1 << 3)
#define CLKF_AM35XX			(1 << 4)

/* Gate flags */
#define CLKF_SET_BIT_TO_DISABLE		(1 << 5)
#define CLKF_INTERFACE			(1 << 6)
#define CLKF_SSI			(1 << 7)
#define CLKF_DSS			(1 << 8)
#define CLKF_HSOTGUSB			(1 << 9)
#define CLKF_WAIT			(1 << 10)
#define CLKF_NO_WAIT			(1 << 11)
#define CLKF_HSDIV			(1 << 12)
#define CLKF_CLKDM			(1 << 13)

/* DPLL flags */
#define CLKF_LOW_POWER_STOP		(1 << 5)
#define CLKF_LOCK			(1 << 6)
#define CLKF_LOW_POWER_BYPASS		(1 << 7)
#define CLKF_PER			(1 << 8)
#define CLKF_CORE			(1 << 9)
#define CLKF_J_TYPE			(1 << 10)

#define CLK(dev, con, ck)		\
	{				\
		.lk = {			\
			.dev_id = dev,	\
			.con_id = con,	\
		},			\
		.clk = ck,		\
	}

struct ti_clk {
	const char *name;
	const char *clkdm_name;
	int type;
	void *data;
	struct ti_clk *patch;
	struct clk *clk;
};

struct ti_clk_alias {
	struct ti_clk *clk;
	struct clk_lookup lk;
	struct list_head link;
};

struct ti_clk_fixed {
	u32 frequency;
	u16 flags;
};

struct ti_clk_mux {
	u8 bit_shift;
	int num_parents;
	u16 reg;
	u8 module;
	const char **parents;
	u16 flags;
};

struct ti_clk_divider {
	const char *parent;
	u8 bit_shift;
	u16 max_div;
	u16 reg;
	u8 module;
	int *dividers;
	int num_dividers;
	u16 flags;
};

struct ti_clk_fixed_factor {
	const char *parent;
	u16 div;
	u16 mult;
	u16 flags;
};

struct ti_clk_gate {
	const char *parent;
	u8 bit_shift;
	u16 reg;
	u8 module;
	u16 flags;
};

struct ti_clk_composite {
	struct ti_clk_divider *divider;
	struct ti_clk_mux *mux;
	struct ti_clk_gate *gate;
	u16 flags;
};

struct ti_clk_clkdm_gate {
	const char *parent;
	u16 flags;
};

struct ti_clk_dpll {
	int num_parents;
	u16 control_reg;
	u16 idlest_reg;
	u16 autoidle_reg;
	u16 mult_div1_reg;
	u8 module;
	const char **parents;
	u16 flags;
	u8 modes;
	u32 mult_mask;
	u32 div1_mask;
	u32 enable_mask;
	u32 autoidle_mask;
	u32 freqsel_mask;
	u32 idlest_mask;
	u32 dco_mask;
	u32 sddiv_mask;
	u16 max_multiplier;
	u16 max_divider;
	u8 min_divider;
	u8 auto_recal_bit;
	u8 recal_en_bit;
	u8 recal_st_bit;
};

/* Composite clock component types */
enum {
	CLK_COMPONENT_TYPE_GATE = 0,
	CLK_COMPONENT_TYPE_DIVIDER,
	CLK_COMPONENT_TYPE_MUX,
	CLK_COMPONENT_TYPE_MAX,
};

/**
 * struct ti_dt_clk - OMAP DT clock alias declarations
 * @lk: clock lookup definition
 * @node_name: clock DT node to map to
 */
struct ti_dt_clk {
	struct clk_lookup		lk;
	char				*node_name;
};

#define DT_CLK(dev, con, name)		\
	{				\
		.lk = {			\
			.dev_id = dev,	\
			.con_id = con,	\
		},			\
		.node_name = name,	\
	}

typedef void (*ti_of_clk_init_cb_t)(struct clk_hw *, struct device_node *);

struct clk *ti_clk_register_gate(struct ti_clk *setup);
struct clk *ti_clk_register_interface(struct ti_clk *setup);
struct clk *ti_clk_register_mux(struct ti_clk *setup);
struct clk *ti_clk_register_divider(struct ti_clk *setup);
struct clk *ti_clk_register_composite(struct ti_clk *setup);
struct clk *ti_clk_register_dpll(struct ti_clk *setup);
struct clk *ti_clk_register(struct device *dev, struct clk_hw *hw,
			    const char *con);
int ti_clk_add_alias(struct device *dev, struct clk *clk, const char *con);
void ti_clk_add_aliases(void);

struct clk_hw *ti_clk_build_component_div(struct ti_clk_divider *setup);
struct clk_hw *ti_clk_build_component_gate(struct ti_clk_gate *setup);
struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup);

void ti_clk_patch_legacy_clks(struct ti_clk **patch);
struct clk *ti_clk_register_clk(struct ti_clk *setup);
int ti_clk_register_legacy_clks(struct ti_clk_alias *clks);

void __iomem *ti_clk_get_reg_addr(struct device_node *node, int index);
void ti_dt_clocks_register(struct ti_dt_clk *oclks);
int ti_clk_retry_init(struct device_node *node, struct clk_hw *hw,
		      ti_of_clk_init_cb_t func);
int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type);

void omap2_init_clk_hw_omap_clocks(struct clk_hw *hw);
int of_ti_clk_autoidle_setup(struct device_node *node);
void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);

extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
extern const struct clk_hw_omap_ops clkhwops_wait;
extern const struct clk_hw_omap_ops clkhwops_iclk;
extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait;
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait;

extern const struct clk_ops ti_clk_divider_ops;
extern const struct clk_ops ti_clk_mux_ops;

int omap2_clkops_enable_clkdm(struct clk_hw *hw);
void omap2_clkops_disable_clkdm(struct clk_hw *hw);

int omap2_dflt_clk_enable(struct clk_hw *hw);
void omap2_dflt_clk_disable(struct clk_hw *hw);
int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
				   void __iomem **other_reg,
				   u8 *other_bit);
void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
				void __iomem **idlest_reg,
				u8 *idlest_bit, u8 *idlest_val);

void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk);
void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);

u8 omap2_init_dpll_parent(struct clk_hw *hw);
int omap3_noncore_dpll_enable(struct clk_hw *hw);
void omap3_noncore_dpll_disable(struct clk_hw *hw);
int omap3_noncore_dpll_set_parent(struct clk_hw *hw, u8 index);
int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
				unsigned long parent_rate);
int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw,
					   unsigned long rate,
					   unsigned long parent_rate,
					   u8 index);
int omap3_noncore_dpll_determine_rate(struct clk_hw *hw,
				      struct clk_rate_request *req);
long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
			   unsigned long *parent_rate);
unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
				    unsigned long parent_rate);

/*
 * OMAP3_DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks
 * that are sourced by DPLL5, and both of these require this clock
 * to be at 120 MHz for proper operation.
 */
#define OMAP3_DPLL5_FREQ_FOR_USBHOST	120000000

unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
			 unsigned long parent_rate);
int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
				    unsigned long parent_rate, u8 index);
int omap3_dpll5_set_rate(struct clk_hw *hw, unsigned long rate,
			 unsigned long parent_rate);
void omap3_clk_lock_dpll5(void);

unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
					 unsigned long parent_rate);
long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
				    unsigned long target_rate,
				    unsigned long *parent_rate);
int omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw,
				       struct clk_rate_request *req);

extern struct ti_clk_ll_ops *ti_clk_ll_ops;

#endif
Commit	Line	Data
c82f8957 TK	1	/*
	2	* TI Clock driver internal definitions
	3	*
	4	* Copyright (C) 2014 Texas Instruments, Inc
	5	* Tero Kristo (t-kristo@ti.com)
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation version 2.
	10	*
	11	* This program is distributed "as is" WITHOUT ANY WARRANTY of any
	12	* kind, whether express or implied; without even the implied warranty
	13	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*/
	16	#ifndef __DRIVERS_CLK_TI_CLOCK__
	17	#define __DRIVERS_CLK_TI_CLOCK__
	18
	19	enum {
	20	TI_CLK_FIXED,
	21	TI_CLK_MUX,
	22	TI_CLK_DIVIDER,
	23	TI_CLK_COMPOSITE,
	24	TI_CLK_FIXED_FACTOR,
	25	TI_CLK_GATE,
	26	TI_CLK_DPLL,
	27	};
	28
	29	/* Global flags */
	30	#define CLKF_INDEX_POWER_OF_TWO (1 << 0)
	31	#define CLKF_INDEX_STARTS_AT_ONE (1 << 1)
	32	#define CLKF_SET_RATE_PARENT (1 << 2)
	33	#define CLKF_OMAP3 (1 << 3)
	34	#define CLKF_AM35XX (1 << 4)
	35
	36	/* Gate flags */
	37	#define CLKF_SET_BIT_TO_DISABLE (1 << 5)
	38	#define CLKF_INTERFACE (1 << 6)
	39	#define CLKF_SSI (1 << 7)
	40	#define CLKF_DSS (1 << 8)
	41	#define CLKF_HSOTGUSB (1 << 9)
	42	#define CLKF_WAIT (1 << 10)
	43	#define CLKF_NO_WAIT (1 << 11)
	44	#define CLKF_HSDIV (1 << 12)
	45	#define CLKF_CLKDM (1 << 13)
	46
	47	/* DPLL flags */
	48	#define CLKF_LOW_POWER_STOP (1 << 5)
	49	#define CLKF_LOCK (1 << 6)
	50	#define CLKF_LOW_POWER_BYPASS (1 << 7)
	51	#define CLKF_PER (1 << 8)
	52	#define CLKF_CORE (1 << 9)
	53	#define CLKF_J_TYPE (1 << 10)
	54
	55	#define CLK(dev, con, ck) \
	56	{ \
	57	.lk = { \
	58	.dev_id = dev, \
	59	.con_id = con, \
	60	}, \
	61	.clk = ck, \
	62	}
	63
	64	struct ti_clk {
65	const char *name;
66	const char *clkdm_name;
67	int type;
68	void *data;
69	struct ti_clk *patch;
70	struct clk *clk;
71	};
72
73	struct ti_clk_alias {
74	struct ti_clk *clk;
75	struct clk_lookup lk;
76	struct list_head link;
77	};
78
79	struct ti_clk_fixed {
80	u32 frequency;
81	u16 flags;
82	};
83
84	struct ti_clk_mux {
85	u8 bit_shift;
86	int num_parents;
87	u16 reg;
88	u8 module;
89	const char **parents;
90	u16 flags;
91	};
92
93	struct ti_clk_divider {
94	const char *parent;
95	u8 bit_shift;
96	u16 max_div;
97	u16 reg;
98	u8 module;
99	int *dividers;
100	int num_dividers;
101	u16 flags;
102	};
103
104	struct ti_clk_fixed_factor {
105	const char *parent;
106	u16 div;
107	u16 mult;
108	u16 flags;
109	};
110
111	struct ti_clk_gate {
112	const char *parent;
113	u8 bit_shift;
114	u16 reg;
115	u8 module;
116	u16 flags;
117	};
118
119	struct ti_clk_composite {
120	struct ti_clk_divider *divider;
121	struct ti_clk_mux *mux;
122	struct ti_clk_gate *gate;
123	u16 flags;
124	};
125
126	struct ti_clk_clkdm_gate {
127	const char *parent;
128	u16 flags;
129	};
130
131	struct ti_clk_dpll {
132	int num_parents;
133	u16 control_reg;
134	u16 idlest_reg;
135	u16 autoidle_reg;
136	u16 mult_div1_reg;
137	u8 module;
138	const char **parents;
139	u16 flags;
140	u8 modes;
141	u32 mult_mask;
142	u32 div1_mask;
143	u32 enable_mask;
144	u32 autoidle_mask;
145	u32 freqsel_mask;
146	u32 idlest_mask;
147	u32 dco_mask;
148	u32 sddiv_mask;
149	u16 max_multiplier;
150	u16 max_divider;
ed405a23	151	u8 min_divider;
c82f8957 TK	152	u8 auto_recal_bit;
	153	u8 recal_en_bit;
	154	u8 recal_st_bit;
	155	};
	156
a3314e9c TK	157	/* Composite clock component types */
	158	enum {
	159	CLK_COMPONENT_TYPE_GATE = 0,
	160	CLK_COMPONENT_TYPE_DIVIDER,
	161	CLK_COMPONENT_TYPE_MUX,
	162	CLK_COMPONENT_TYPE_MAX,
	163	};
	164
	165	/**
	166	* struct ti_dt_clk - OMAP DT clock alias declarations
	167	* @lk: clock lookup definition
	168	* @node_name: clock DT node to map to
	169	*/
	170	struct ti_dt_clk {
	171	struct clk_lookup lk;
	172	char *node_name;
	173	};
	174
	175	#define DT_CLK(dev, con, name) \
	176	{ \
	177	.lk = { \
	178	.dev_id = dev, \
	179	.con_id = con, \
	180	}, \
	181	.node_name = name, \
	182	}
	183
	184	typedef void (ti_of_clk_init_cb_t)(struct clk_hw , struct device_node *);
	185
f187616b	186	struct clk ti_clk_register_gate(struct ti_clk setup);
06524fa4	187	struct clk ti_clk_register_interface(struct ti_clk setup);
7c18a65c	188	struct clk ti_clk_register_mux(struct ti_clk setup);
d96f774b	189	struct clk ti_clk_register_divider(struct ti_clk setup);
b26bcf9b	190	struct clk ti_clk_register_composite(struct ti_clk setup);
ed405a23	191	struct clk ti_clk_register_dpll(struct ti_clk setup);
21f0bf2d TK	192	struct clk ti_clk_register(struct device dev, struct clk_hw *hw,
	193	const char *con);
	194	int ti_clk_add_alias(struct device dev, struct clk clk, const char *con);
c17435c5	195	void ti_clk_add_aliases(void);
7c18a65c	196
d96f774b	197	struct clk_hw ti_clk_build_component_div(struct ti_clk_divider setup);
f187616b	198	struct clk_hw ti_clk_build_component_gate(struct ti_clk_gate setup);
7c18a65c TK	199	struct clk_hw ti_clk_build_component_mux(struct ti_clk_mux setup);
7c18a65c TK	200
c82f8957 TK	201	void ti_clk_patch_legacy_clks(struct ti_clk **patch);
	202	struct clk ti_clk_register_clk(struct ti_clk setup);
	203	int ti_clk_register_legacy_clks(struct ti_clk_alias *clks);
	204
a3314e9c TK	205	void __iomem ti_clk_get_reg_addr(struct device_node node, int index);
	206	void ti_dt_clocks_register(struct ti_dt_clk *oclks);
	207	int ti_clk_retry_init(struct device_node node, struct clk_hw hw,
	208	ti_of_clk_init_cb_t func);
	209	int ti_clk_add_component(struct device_node node, struct clk_hw hw, int type);
	210
a53ad8ef	211	void omap2_init_clk_hw_omap_clocks(struct clk_hw *hw);
bf22bae7	212	int of_ti_clk_autoidle_setup(struct device_node *node);
a5aa8a60	213	void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
bf22bae7	214
0565fb16	215	extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
59245ce0	216	extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
9f37e90e	217	extern const struct clk_hw_omap_ops clkhwops_wait;
ef14db09 TK	218	extern const struct clk_hw_omap_ops clkhwops_iclk;
ef14db09 TK	219	extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
d5a04ddd	220	extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait;
f2671d5c TK	221	extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
	222	extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
	223	extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
	224	extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
c9a58b0a TK	225	extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
c9a58b0a TK	226	extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait;
59245ce0	227
a3314e9c TK	228	extern const struct clk_ops ti_clk_divider_ops;
	229	extern const struct clk_ops ti_clk_mux_ops;
	230
bd86cfdc TK	231	int omap2_clkops_enable_clkdm(struct clk_hw *hw);
	232	void omap2_clkops_disable_clkdm(struct clk_hw *hw);
	233
9f37e90e TK	234	int omap2_dflt_clk_enable(struct clk_hw *hw);
	235	void omap2_dflt_clk_disable(struct clk_hw *hw);
	236	int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
a3314e9c TK	237	void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
	238	void __iomem **other_reg,
	239	u8 *other_bit);
	240	void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
	241	void __iomem **idlest_reg,
	242	u8 idlest_bit, u8 idlest_val);
	243
	244	void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk);
	245	void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);
9f37e90e	246
b138b028	247	u8 omap2_init_dpll_parent(struct clk_hw *hw);
0565fb16 TK	248	int omap3_noncore_dpll_enable(struct clk_hw *hw);
	249	void omap3_noncore_dpll_disable(struct clk_hw *hw);
	250	int omap3_noncore_dpll_set_parent(struct clk_hw *hw, u8 index);
	251	int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
	252	unsigned long parent_rate);
	253	int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw,
	254	unsigned long rate,
	255	unsigned long parent_rate,
	256	u8 index);
4d341056 SB	257	int omap3_noncore_dpll_determine_rate(struct clk_hw *hw,
4d341056 SB	258	struct clk_rate_request *req);
0565fb16 TK	259	long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
	260	unsigned long *parent_rate);
	261	unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
	262	unsigned long parent_rate);
	263
035cd485 RW	264	/*
	265	* OMAP3_DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks
	266	* that are sourced by DPLL5, and both of these require this clock
	267	* to be at 120 MHz for proper operation.
	268	*/
	269	#define OMAP3_DPLL5_FREQ_FOR_USBHOST 120000000
	270
0565fb16 TK	271	unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
	272	int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
	273	unsigned long parent_rate);
	274	int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
	275	unsigned long parent_rate, u8 index);
035cd485 RW	276	int omap3_dpll5_set_rate(struct clk_hw *hw, unsigned long rate,
035cd485 RW	277	unsigned long parent_rate);
0565fb16	278	void omap3_clk_lock_dpll5(void);
b138b028	279
59245ce0 TK	280	unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
	281	unsigned long parent_rate);
	282	long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
	283	unsigned long target_rate,
	284	unsigned long *parent_rate);
4d341056 SB	285	int omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw,
4d341056 SB	286	struct clk_rate_request *req);
59245ce0	287
e9e63088 TK	288	extern struct ti_clk_ll_ops *ti_clk_ll_ops;
e9e63088 TK	289
c82f8957	290	#endif