[linux-block.git] / drivers / clk / ti / clock.h

/*
 * TI Clock driver internal definitions
 *
 * Copyright (C) 2014 Texas Instruments, Inc
 *     Tero Kristo (t-kristo@ti.com)
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation version 2.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 */
#ifndef __DRIVERS_CLK_TI_CLOCK__
#define __DRIVERS_CLK_TI_CLOCK__

struct clk_omap_divider {
	struct clk_hw		hw;
	struct clk_omap_reg	reg;
	u8			shift;
	u8			width;
	u8			flags;
	s8			latch;
	const struct clk_div_table	*table;
};

#define to_clk_omap_divider(_hw) container_of(_hw, struct clk_omap_divider, hw)

struct clk_omap_mux {
	struct clk_hw		hw;
	struct clk_omap_reg	reg;
	u32			*table;
	u32			mask;
	u8			shift;
	s8			latch;
	u8			flags;
};

#define to_clk_omap_mux(_hw) container_of(_hw, struct clk_omap_mux, hw)

enum {
	TI_CLK_FIXED,
	TI_CLK_MUX,
	TI_CLK_DIVIDER,
	TI_CLK_COMPOSITE,
	TI_CLK_FIXED_FACTOR,
	TI_CLK_GATE,
	TI_CLK_DPLL,
};

/* Global flags */
#define CLKF_INDEX_POWER_OF_TWO		(1 << 0)
#define CLKF_INDEX_STARTS_AT_ONE	(1 << 1)
#define CLKF_SET_RATE_PARENT		(1 << 2)
#define CLKF_OMAP3			(1 << 3)
#define CLKF_AM35XX			(1 << 4)

/* Gate flags */
#define CLKF_SET_BIT_TO_DISABLE		(1 << 5)
#define CLKF_INTERFACE			(1 << 6)
#define CLKF_SSI			(1 << 7)
#define CLKF_DSS			(1 << 8)
#define CLKF_HSOTGUSB			(1 << 9)
#define CLKF_WAIT			(1 << 10)
#define CLKF_NO_WAIT			(1 << 11)
#define CLKF_HSDIV			(1 << 12)
#define CLKF_CLKDM			(1 << 13)

/* DPLL flags */
#define CLKF_LOW_POWER_STOP		(1 << 5)
#define CLKF_LOCK			(1 << 6)
#define CLKF_LOW_POWER_BYPASS		(1 << 7)
#define CLKF_PER			(1 << 8)
#define CLKF_CORE			(1 << 9)
#define CLKF_J_TYPE			(1 << 10)

/* CLKCTRL flags */
#define CLKF_SW_SUP			BIT(5)
#define CLKF_HW_SUP			BIT(6)
#define CLKF_NO_IDLEST			BIT(7)

#define CLK(dev, con, ck)		\
	{				\
		.lk = {			\
			.dev_id = dev,	\
			.con_id = con,	\
		},			\
		.clk = ck,		\
	}

struct ti_clk {
	const char *name;
	const char *clkdm_name;
	int type;
	void *data;
	struct ti_clk *patch;
	struct clk *clk;
};

struct ti_clk_mux {
	u8 bit_shift;
	int num_parents;
	u16 reg;
	u8 module;
	const char * const *parents;
	u16 flags;
};

struct ti_clk_divider {
	const char *parent;
	u8 bit_shift;
	u16 max_div;
	u16 reg;
	u8 module;
	int *dividers;
	int num_dividers;
	u16 flags;
};

struct ti_clk_gate {
	const char *parent;
	u8 bit_shift;
	u16 reg;
	u8 module;
	u16 flags;
};

/* Composite clock component types */
enum {
	CLK_COMPONENT_TYPE_GATE = 0,
	CLK_COMPONENT_TYPE_DIVIDER,
	CLK_COMPONENT_TYPE_MUX,
	CLK_COMPONENT_TYPE_MAX,
};

/**
 * struct ti_dt_clk - OMAP DT clock alias declarations
 * @lk: clock lookup definition
 * @node_name: clock DT node to map to
 */
struct ti_dt_clk {
	struct clk_lookup		lk;
	char				*node_name;
};

#define DT_CLK(dev, con, name)		\
	{				\
		.lk = {			\
			.dev_id = dev,	\
			.con_id = con,	\
		},			\
		.node_name = name,	\
	}

/* CLKCTRL type definitions */
struct omap_clkctrl_div_data {
	const int *dividers;
	int max_div;
	u32 flags;
};

struct omap_clkctrl_bit_data {
	u8 bit;
	u8 type;
	const char * const *parents;
	const void *data;
};

struct omap_clkctrl_reg_data {
	u16 offset;
	const struct omap_clkctrl_bit_data *bit_data;
	u16 flags;
	const char *parent;
	const char *clkdm_name;
};

struct omap_clkctrl_data {
	u32 addr;
	const struct omap_clkctrl_reg_data *regs;
};

extern const struct omap_clkctrl_data omap4_clkctrl_data[];
extern const struct omap_clkctrl_data omap5_clkctrl_data[];
extern const struct omap_clkctrl_data dra7_clkctrl_data[];
extern const struct omap_clkctrl_data dra7_clkctrl_compat_data[];
extern struct ti_dt_clk dra7xx_compat_clks[];
extern const struct omap_clkctrl_data am3_clkctrl_data[];
extern const struct omap_clkctrl_data am3_clkctrl_compat_data[];
extern struct ti_dt_clk am33xx_compat_clks[];
extern const struct omap_clkctrl_data am4_clkctrl_data[];
extern const struct omap_clkctrl_data am4_clkctrl_compat_data[];
extern struct ti_dt_clk am43xx_compat_clks[];
extern const struct omap_clkctrl_data am438x_clkctrl_data[];
extern const struct omap_clkctrl_data am438x_clkctrl_compat_data[];
extern const struct omap_clkctrl_data dm814_clkctrl_data[];
extern const struct omap_clkctrl_data dm816_clkctrl_data[];

typedef void (*ti_of_clk_init_cb_t)(void *, struct device_node *);

struct clk *ti_clk_register(struct device *dev, struct clk_hw *hw,
			    const char *con);
int ti_clk_add_alias(struct device *dev, struct clk *clk, const char *con);
void ti_clk_add_aliases(void);

void ti_clk_latch(struct clk_omap_reg *reg, s8 shift);

struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup);

int ti_clk_parse_divider_data(int *div_table, int num_dividers, int max_div,
			      u8 flags, u8 *width,
			      const struct clk_div_table **table);

int ti_clk_get_reg_addr(struct device_node *node, int index,
			struct clk_omap_reg *reg);
void ti_dt_clocks_register(struct ti_dt_clk *oclks);
int ti_clk_retry_init(struct device_node *node, void *user,
		      ti_of_clk_init_cb_t func);
int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type);

void omap2_init_clk_hw_omap_clocks(struct clk_hw *hw);
int of_ti_clk_autoidle_setup(struct device_node *node);
void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);

extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
extern const struct clk_hw_omap_ops clkhwops_wait;
extern const struct clk_hw_omap_ops clkhwops_iclk;
extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait;
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait;

extern const struct clk_ops ti_clk_divider_ops;
extern const struct clk_ops ti_clk_mux_ops;
extern const struct clk_ops omap_gate_clk_ops;

extern struct ti_clk_features ti_clk_features;

void omap2_init_clk_clkdm(struct clk_hw *hw);
int omap2_clkops_enable_clkdm(struct clk_hw *hw);
void omap2_clkops_disable_clkdm(struct clk_hw *hw);

int omap2_dflt_clk_enable(struct clk_hw *hw);
void omap2_dflt_clk_disable(struct clk_hw *hw);
int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
				   struct clk_omap_reg *other_reg,
				   u8 *other_bit);
void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
				struct clk_omap_reg *idlest_reg,
				u8 *idlest_bit, u8 *idlest_val);

void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk);
void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);

u8 omap2_init_dpll_parent(struct clk_hw *hw);
int omap3_noncore_dpll_enable(struct clk_hw *hw);
void omap3_noncore_dpll_disable(struct clk_hw *hw);
int omap3_noncore_dpll_set_parent(struct clk_hw *hw, u8 index);
int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
				unsigned long parent_rate);
int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw,
					   unsigned long rate,
					   unsigned long parent_rate,
					   u8 index);
int omap3_noncore_dpll_determine_rate(struct clk_hw *hw,
				      struct clk_rate_request *req);
long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
			   unsigned long *parent_rate);
unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
				    unsigned long parent_rate);

/*
 * OMAP3_DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks
 * that are sourced by DPLL5, and both of these require this clock
 * to be at 120 MHz for proper operation.
 */
#define OMAP3_DPLL5_FREQ_FOR_USBHOST	120000000

unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
			 unsigned long parent_rate);
int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
				    unsigned long parent_rate, u8 index);
int omap3_dpll5_set_rate(struct clk_hw *hw, unsigned long rate,
			 unsigned long parent_rate);
void omap3_clk_lock_dpll5(void);

unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
					 unsigned long parent_rate);
long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
				    unsigned long target_rate,
				    unsigned long *parent_rate);
int omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw,
				       struct clk_rate_request *req);

extern struct ti_clk_ll_ops *ti_clk_ll_ops;

#endif
Commit	Line	Data
c82f8957 TK	1	/*
	2	* TI Clock driver internal definitions
	3	*
	4	* Copyright (C) 2014 Texas Instruments, Inc
	5	* Tero Kristo (t-kristo@ti.com)
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation version 2.
	10	*
	11	* This program is distributed "as is" WITHOUT ANY WARRANTY of any
	12	* kind, whether express or implied; without even the implied warranty
	13	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*/
	16	#ifndef __DRIVERS_CLK_TI_CLOCK__
	17	#define __DRIVERS_CLK_TI_CLOCK__
	18
6dbde947 TK	19	struct clk_omap_divider {
6dbde947 TK	20	struct clk_hw hw;
6c0afb50	21	struct clk_omap_reg reg;
6dbde947 TK	22	u8 shift;
	23	u8 width;
	24	u8 flags;
b44a0300	25	s8 latch;
6dbde947 TK	26	const struct clk_div_table *table;
	27	};
	28
	29	#define to_clk_omap_divider(_hw) container_of(_hw, struct clk_omap_divider, hw)
	30
d83bc5b6 TK	31	struct clk_omap_mux {
d83bc5b6 TK	32	struct clk_hw hw;
6c0afb50	33	struct clk_omap_reg reg;
d83bc5b6 TK	34	u32 *table;
	35	u32 mask;
	36	u8 shift;
ee2fc3c5	37	s8 latch;
d83bc5b6 TK	38	u8 flags;
	39	};
	40
	41	#define to_clk_omap_mux(_hw) container_of(_hw, struct clk_omap_mux, hw)
	42
c82f8957 TK	43	enum {
	44	TI_CLK_FIXED,
	45	TI_CLK_MUX,
	46	TI_CLK_DIVIDER,
	47	TI_CLK_COMPOSITE,
	48	TI_CLK_FIXED_FACTOR,
	49	TI_CLK_GATE,
	50	TI_CLK_DPLL,
	51	};
	52
	53	/* Global flags */
	54	#define CLKF_INDEX_POWER_OF_TWO (1 << 0)
	55	#define CLKF_INDEX_STARTS_AT_ONE (1 << 1)
	56	#define CLKF_SET_RATE_PARENT (1 << 2)
	57	#define CLKF_OMAP3 (1 << 3)
	58	#define CLKF_AM35XX (1 << 4)
	59
	60	/* Gate flags */
	61	#define CLKF_SET_BIT_TO_DISABLE (1 << 5)
	62	#define CLKF_INTERFACE (1 << 6)
	63	#define CLKF_SSI (1 << 7)
	64	#define CLKF_DSS (1 << 8)
	65	#define CLKF_HSOTGUSB (1 << 9)
	66	#define CLKF_WAIT (1 << 10)
	67	#define CLKF_NO_WAIT (1 << 11)
	68	#define CLKF_HSDIV (1 << 12)
	69	#define CLKF_CLKDM (1 << 13)
	70
	71	/* DPLL flags */
	72	#define CLKF_LOW_POWER_STOP (1 << 5)
	73	#define CLKF_LOCK (1 << 6)
	74	#define CLKF_LOW_POWER_BYPASS (1 << 7)
	75	#define CLKF_PER (1 << 8)
	76	#define CLKF_CORE (1 << 9)
	77	#define CLKF_J_TYPE (1 << 10)
	78
269bd202 TK	79	/* CLKCTRL flags */
	80	#define CLKF_SW_SUP BIT(5)
	81	#define CLKF_HW_SUP BIT(6)
	82	#define CLKF_NO_IDLEST BIT(7)
	83
c82f8957 TK	84	#define CLK(dev, con, ck) \
	85	{ \
	86	.lk = { \
	87	.dev_id = dev, \
	88	.con_id = con, \
	89	}, \
	90	.clk = ck, \
	91	}
	92
	93	struct ti_clk {
	94	const char *name;
	95	const char *clkdm_name;
	96	int type;
	97	void *data;
	98	struct ti_clk *patch;
	99	struct clk *clk;
	100	};
	101
c82f8957 TK	102	struct ti_clk_mux {
	103	u8 bit_shift;
	104	int num_parents;
	105	u16 reg;
	106	u8 module;
ce382d47	107	const char * const *parents;
c82f8957 TK	108	u16 flags;
	109	};
	110
	111	struct ti_clk_divider {
	112	const char *parent;
	113	u8 bit_shift;
	114	u16 max_div;
	115	u16 reg;
	116	u8 module;
	117	int *dividers;
	118	int num_dividers;
	119	u16 flags;
	120	};
	121
c82f8957 TK	122	struct ti_clk_gate {
	123	const char *parent;
	124	u8 bit_shift;
	125	u16 reg;
	126	u8 module;
	127	u16 flags;
	128	};
	129
a3314e9c TK	130	/* Composite clock component types */
	131	enum {
	132	CLK_COMPONENT_TYPE_GATE = 0,
	133	CLK_COMPONENT_TYPE_DIVIDER,
	134	CLK_COMPONENT_TYPE_MUX,
	135	CLK_COMPONENT_TYPE_MAX,
	136	};
	137
	138	/**
	139	* struct ti_dt_clk - OMAP DT clock alias declarations
	140	* @lk: clock lookup definition
	141	* @node_name: clock DT node to map to
	142	*/
	143	struct ti_dt_clk {
	144	struct clk_lookup lk;
	145	char *node_name;
	146	};
	147
	148	#define DT_CLK(dev, con, name) \
	149	{ \
	150	.lk = { \
	151	.dev_id = dev, \
	152	.con_id = con, \
	153	}, \
	154	.node_name = name, \
	155	}
	156
88a17252 TK	157	/* CLKCTRL type definitions */
	158	struct omap_clkctrl_div_data {
	159	const int *dividers;
	160	int max_div;
49eec6fb	161	u32 flags;
88a17252 TK	162	};
	163
	164	struct omap_clkctrl_bit_data {
	165	u8 bit;
	166	u8 type;
	167	const char * const *parents;
	168	const void *data;
	169	};
	170
	171	struct omap_clkctrl_reg_data {
	172	u16 offset;
	173	const struct omap_clkctrl_bit_data *bit_data;
	174	u16 flags;
	175	const char *parent;
ddfb183e	176	const char *clkdm_name;
88a17252 TK	177	};
	178
	179	struct omap_clkctrl_data {
	180	u32 addr;
	181	const struct omap_clkctrl_reg_data *regs;
	182	};
	183
1c881b5a	184	extern const struct omap_clkctrl_data omap4_clkctrl_data[];
0ad902f6	185	extern const struct omap_clkctrl_data omap5_clkctrl_data[];
dffa9051	186	extern const struct omap_clkctrl_data dra7_clkctrl_data[];
43c56e04 TK	187	extern const struct omap_clkctrl_data dra7_clkctrl_compat_data[];
43c56e04 TK	188	extern struct ti_dt_clk dra7xx_compat_clks[];
296e583e	189	extern const struct omap_clkctrl_data am3_clkctrl_data[];
e97017f9 TK	190	extern const struct omap_clkctrl_data am3_clkctrl_compat_data[];
e97017f9 TK	191	extern struct ti_dt_clk am33xx_compat_clks[];
76a1049b	192	extern const struct omap_clkctrl_data am4_clkctrl_data[];
131ee08f TK	193	extern const struct omap_clkctrl_data am4_clkctrl_compat_data[];
131ee08f TK	194	extern struct ti_dt_clk am43xx_compat_clks[];
76a1049b	195	extern const struct omap_clkctrl_data am438x_clkctrl_data[];
131ee08f	196	extern const struct omap_clkctrl_data am438x_clkctrl_compat_data[];
26ca2e97	197	extern const struct omap_clkctrl_data dm814_clkctrl_data[];
50ef5089	198	extern const struct omap_clkctrl_data dm816_clkctrl_data[];
1c881b5a	199
ffb009b2	200	typedef void (ti_of_clk_init_cb_t)(void , struct device_node *);
a3314e9c	201
21f0bf2d TK	202	struct clk ti_clk_register(struct device dev, struct clk_hw *hw,
	203	const char *con);
	204	int ti_clk_add_alias(struct device dev, struct clk clk, const char *con);
c17435c5	205	void ti_clk_add_aliases(void);
7c18a65c	206
e31922ed TK	207	void ti_clk_latch(struct clk_omap_reg *reg, s8 shift);
e31922ed TK	208
7c18a65c TK	209	struct clk_hw ti_clk_build_component_mux(struct ti_clk_mux setup);
7c18a65c TK	210
4f6be565 TK	211	int ti_clk_parse_divider_data(int *div_table, int num_dividers, int max_div,
	212	u8 flags, u8 *width,
	213	const struct clk_div_table **table);
	214
6c0afb50 TK	215	int ti_clk_get_reg_addr(struct device_node *node, int index,
6c0afb50 TK	216	struct clk_omap_reg *reg);
a3314e9c	217	void ti_dt_clocks_register(struct ti_dt_clk *oclks);
ffb009b2	218	int ti_clk_retry_init(struct device_node node, void user,
a3314e9c TK	219	ti_of_clk_init_cb_t func);
	220	int ti_clk_add_component(struct device_node node, struct clk_hw hw, int type);
	221
a53ad8ef	222	void omap2_init_clk_hw_omap_clocks(struct clk_hw *hw);
bf22bae7	223	int of_ti_clk_autoidle_setup(struct device_node *node);
a5aa8a60	224	void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
bf22bae7	225
0565fb16	226	extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
59245ce0	227	extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
9f37e90e	228	extern const struct clk_hw_omap_ops clkhwops_wait;
ef14db09 TK	229	extern const struct clk_hw_omap_ops clkhwops_iclk;
ef14db09 TK	230	extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
d5a04ddd	231	extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait;
f2671d5c TK	232	extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
	233	extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
	234	extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
	235	extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
c9a58b0a TK	236	extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
c9a58b0a TK	237	extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait;
59245ce0	238
a3314e9c TK	239	extern const struct clk_ops ti_clk_divider_ops;
a3314e9c TK	240	extern const struct clk_ops ti_clk_mux_ops;
9a00fa68	241	extern const struct clk_ops omap_gate_clk_ops;
a3314e9c	242
47b00dcf TK	243	extern struct ti_clk_features ti_clk_features;
47b00dcf TK	244
2e1a294c	245	void omap2_init_clk_clkdm(struct clk_hw *hw);
bd86cfdc TK	246	int omap2_clkops_enable_clkdm(struct clk_hw *hw);
	247	void omap2_clkops_disable_clkdm(struct clk_hw *hw);
	248
9f37e90e TK	249	int omap2_dflt_clk_enable(struct clk_hw *hw);
	250	void omap2_dflt_clk_disable(struct clk_hw *hw);
	251	int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
a3314e9c	252	void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
6c0afb50	253	struct clk_omap_reg *other_reg,
a3314e9c TK	254	u8 *other_bit);
a3314e9c TK	255	void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
6c0afb50	256	struct clk_omap_reg *idlest_reg,
a3314e9c TK	257	u8 idlest_bit, u8 idlest_val);
	258
	259	void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk);
	260	void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);
9f37e90e	261
b138b028	262	u8 omap2_init_dpll_parent(struct clk_hw *hw);
0565fb16 TK	263	int omap3_noncore_dpll_enable(struct clk_hw *hw);
	264	void omap3_noncore_dpll_disable(struct clk_hw *hw);
	265	int omap3_noncore_dpll_set_parent(struct clk_hw *hw, u8 index);
	266	int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
	267	unsigned long parent_rate);
	268	int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw,
	269	unsigned long rate,
	270	unsigned long parent_rate,
	271	u8 index);
4d341056 SB	272	int omap3_noncore_dpll_determine_rate(struct clk_hw *hw,
4d341056 SB	273	struct clk_rate_request *req);
0565fb16 TK	274	long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
	275	unsigned long *parent_rate);
	276	unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
	277	unsigned long parent_rate);
	278
035cd485 RW	279	/*
	280	* OMAP3_DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks
	281	* that are sourced by DPLL5, and both of these require this clock
	282	* to be at 120 MHz for proper operation.
	283	*/
	284	#define OMAP3_DPLL5_FREQ_FOR_USBHOST 120000000
	285
0565fb16 TK	286	unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
	287	int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
	288	unsigned long parent_rate);
	289	int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
	290	unsigned long parent_rate, u8 index);
035cd485 RW	291	int omap3_dpll5_set_rate(struct clk_hw *hw, unsigned long rate,
035cd485 RW	292	unsigned long parent_rate);
0565fb16	293	void omap3_clk_lock_dpll5(void);
b138b028	294
59245ce0 TK	295	unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
	296	unsigned long parent_rate);
	297	long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
	298	unsigned long target_rate,
	299	unsigned long *parent_rate);
4d341056 SB	300	int omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw,
4d341056 SB	301	struct clk_rate_request *req);
59245ce0	302
e9e63088 TK	303	extern struct ti_clk_ll_ops *ti_clk_ll_ops;
e9e63088 TK	304
c82f8957	305	#endif