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a10e763b | 1 | // SPDX-License-Identifier: GPL-2.0-only |
9cf705de TL |
2 | |
3 | #include <linux/kernel.h> | |
21330497 | 4 | #include <linux/clk.h> |
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5 | #include <linux/clk-provider.h> |
6 | #include <linux/clk/ti.h> | |
21330497 | 7 | #include <linux/of_platform.h> |
26ca2e97 | 8 | #include <dt-bindings/clock/dm814.h> |
9cf705de | 9 | |
f9511a4f SR |
10 | #include "clock.h" |
11 | ||
26ca2e97 TK |
12 | static const struct omap_clkctrl_reg_data dm814_default_clkctrl_regs[] __initconst = { |
13 | { DM814_USB_OTG_HS_CLKCTRL, NULL, CLKF_SW_SUP, "pll260dcoclkldo" }, | |
14 | { 0 }, | |
15 | }; | |
16 | ||
17 | static const struct omap_clkctrl_reg_data dm814_alwon_clkctrl_regs[] __initconst = { | |
18 | { DM814_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" }, | |
19 | { DM814_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" }, | |
20 | { DM814_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" }, | |
21 | { DM814_GPIO1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" }, | |
22 | { DM814_GPIO2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" }, | |
23 | { DM814_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" }, | |
24 | { DM814_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" }, | |
25 | { DM814_WD_TIMER_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk18_ck" }, | |
26 | { DM814_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" }, | |
27 | { DM814_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" }, | |
28 | { DM814_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk" }, | |
29 | { DM814_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "mpu_ck" }, | |
30 | { DM814_RTC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk18_ck" }, | |
31 | { DM814_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" }, | |
32 | { DM814_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" }, | |
33 | { DM814_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" }, | |
34 | { DM814_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" }, | |
35 | { DM814_TPTC3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" }, | |
36 | { DM814_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk8_ck" }, | |
37 | { DM814_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk8_ck" }, | |
38 | { DM814_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk8_ck" }, | |
39 | { 0 }, | |
40 | }; | |
41 | ||
42 | const struct omap_clkctrl_data dm814_clkctrl_data[] __initconst = { | |
43 | { 0x48180500, dm814_default_clkctrl_regs }, | |
44 | { 0x48181400, dm814_alwon_clkctrl_regs }, | |
45 | { 0 }, | |
46 | }; | |
47 | ||
9cf705de | 48 | static struct ti_dt_clk dm814_clks[] = { |
9cf705de | 49 | DT_CLK(NULL, "timer_sys_ck", "devosc_ck"), |
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50 | { .node_name = NULL }, |
51 | }; | |
52 | ||
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53 | static bool timer_clocks_initialized; |
54 | ||
8a8b6eb7 | 55 | static int __init dm814x_adpll_early_init(void) |
21330497 TL |
56 | { |
57 | struct device_node *np; | |
58 | ||
59 | if (!timer_clocks_initialized) | |
60 | return -ENODEV; | |
61 | ||
62 | np = of_find_node_by_name(NULL, "pllss"); | |
63 | if (!np) { | |
64 | pr_err("Could not find node for plls\n"); | |
65 | return -ENODEV; | |
66 | } | |
67 | ||
68 | of_platform_populate(np, NULL, NULL, NULL); | |
69 | ||
70 | return 0; | |
71 | } | |
72 | core_initcall(dm814x_adpll_early_init); | |
73 | ||
74 | static const char * const init_clocks[] = { | |
75 | "pll040clkout", /* MPU 481c5040.adpll.clkout */ | |
76 | "pll290clkout", /* DDR 481c5290.adpll.clkout */ | |
77 | }; | |
78 | ||
8a8b6eb7 | 79 | static int __init dm814x_adpll_enable_init_clocks(void) |
21330497 TL |
80 | { |
81 | int i, err; | |
82 | ||
83 | if (!timer_clocks_initialized) | |
84 | return -ENODEV; | |
85 | ||
86 | for (i = 0; i < ARRAY_SIZE(init_clocks); i++) { | |
87 | struct clk *clock; | |
88 | ||
89 | clock = clk_get(NULL, init_clocks[i]); | |
90 | if (WARN(IS_ERR(clock), "could not find init clock %s\n", | |
91 | init_clocks[i])) | |
92 | continue; | |
93 | err = clk_prepare_enable(clock); | |
94 | if (WARN(err, "could not enable init clock %s\n", | |
95 | init_clocks[i])) | |
96 | continue; | |
97 | } | |
98 | ||
99 | return 0; | |
100 | } | |
101 | postcore_initcall(dm814x_adpll_enable_init_clocks); | |
102 | ||
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103 | int __init dm814x_dt_clk_init(void) |
104 | { | |
105 | ti_dt_clocks_register(dm814_clks); | |
106 | omap2_clk_disable_autoidle_all(); | |
44d2b566 | 107 | ti_clk_add_aliases(); |
9cf705de | 108 | omap2_clk_enable_init_clocks(NULL, 0); |
21330497 | 109 | timer_clocks_initialized = true; |
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110 | |
111 | return 0; | |
112 | } |