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Merge tag 'rpmsg-v5.3' of git://github.com/andersson/remoteproc
[linux-2.6-block.git] / drivers / clk / ti / clk-54xx.c
CommitLineData
d2912cb1 1// SPDX-License-Identifier: GPL-2.0-only
52b14728
TK		 2/*
3 * OMAP5 Clock init
4 *
5 * Copyright (C) 2013 Texas Instruments, Inc.
6 *
7 * Tero Kristo (t-kristo@ti.com)
52b14728
TK		 8 */
9
10#include <linux/kernel.h>
11#include <linux/list.h>
e387088a 12#include <linux/clk.h>
52b14728
TK		 13#include <linux/clkdev.h>
14#include <linux/io.h>
15#include <linux/clk/ti.h>
0ad902f6 16#include <dt-bindings/clock/omap5.h>
52b14728 17
a3314e9c
TK		 18#include "clock.h"
19
52b14728
TK		 20#define OMAP5_DPLL_ABE_DEFFREQ 98304000
21
62125a46
RQ		 22/*
23 * OMAP543x TRM, section "3.6.3.9.5 DPLL_USB Preferred Settings"
24 * states it must be at 960MHz
25 */
26#define OMAP5_DPLL_USB_DEFFREQ 960000000
27
0ad902f6
TK		 28static const struct omap_clkctrl_reg_data omap5_mpu_clkctrl_regs[] __initconst = {
29 { OMAP5_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" },
30 { 0 },
31};
32
33static const struct omap_clkctrl_reg_data omap5_dsp_clkctrl_regs[] __initconst = {
34 { OMAP5_MMU_DSP_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_h11x2_ck" },
35 { 0 },
36};
37
38static const char * const omap5_dmic_gfclk_parents[] __initconst = {
39 "abe_cm:clk:0018:26",
40 "pad_clks_ck",
41 "slimbus_clk",
42 NULL,
43};
44
45static const char * const omap5_dmic_sync_mux_ck_parents[] __initconst = {
46 "abe_24m_fclk",
47 "dss_syc_gfclk_div",
48 "func_24m_clk",
49 NULL,
50};
51
52static const struct omap_clkctrl_bit_data omap5_dmic_bit_data[] __initconst = {
53 { 24, TI_CLK_MUX, omap5_dmic_gfclk_parents, NULL },
54 { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
55 { 0 },
56};
57
58static const char * const omap5_mcbsp1_gfclk_parents[] __initconst = {
59 "abe_cm:clk:0028:26",
60 "pad_clks_ck",
61 "slimbus_clk",
62 NULL,
63};
64
65static const struct omap_clkctrl_bit_data omap5_mcbsp1_bit_data[] __initconst = {
66 { 24, TI_CLK_MUX, omap5_mcbsp1_gfclk_parents, NULL },
67 { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
68 { 0 },
69};
70
71static const char * const omap5_mcbsp2_gfclk_parents[] __initconst = {
72 "abe_cm:clk:0030:26",
73 "pad_clks_ck",
74 "slimbus_clk",
75 NULL,
76};
77
78static const struct omap_clkctrl_bit_data omap5_mcbsp2_bit_data[] __initconst = {
79 { 24, TI_CLK_MUX, omap5_mcbsp2_gfclk_parents, NULL },
80 { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
81 { 0 },
82};
83
84static const char * const omap5_mcbsp3_gfclk_parents[] __initconst = {
85 "abe_cm:clk:0038:26",
86 "pad_clks_ck",
87 "slimbus_clk",
88 NULL,
89};
90
91static const struct omap_clkctrl_bit_data omap5_mcbsp3_bit_data[] __initconst = {
92 { 24, TI_CLK_MUX, omap5_mcbsp3_gfclk_parents, NULL },
93 { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
94 { 0 },
95};
96
97static const char * const omap5_timer5_gfclk_mux_parents[] __initconst = {
98 "dss_syc_gfclk_div",
99 "sys_32k_ck",
100 NULL,
101};
102
103static const struct omap_clkctrl_bit_data omap5_timer5_bit_data[] __initconst = {
104 { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
105 { 0 },
106};
107
108static const struct omap_clkctrl_bit_data omap5_timer6_bit_data[] __initconst = {
109 { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
110 { 0 },
111};
112
113static const struct omap_clkctrl_bit_data omap5_timer7_bit_data[] __initconst = {
114 { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
115 { 0 },
116};
117
118static const struct omap_clkctrl_bit_data omap5_timer8_bit_data[] __initconst = {
119 { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
120 { 0 },
121};
122
123static const struct omap_clkctrl_reg_data omap5_abe_clkctrl_regs[] __initconst = {
124 { OMAP5_L4_ABE_CLKCTRL, NULL, 0, "abe_iclk" },
125 { OMAP5_MCPDM_CLKCTRL, NULL, CLKF_SW_SUP, "pad_clks_ck" },
126 { OMAP5_DMIC_CLKCTRL, omap5_dmic_bit_data, CLKF_SW_SUP, "abe_cm:clk:0018:24" },
127 { OMAP5_MCBSP1_CLKCTRL, omap5_mcbsp1_bit_data, CLKF_SW_SUP, "abe_cm:clk:0028:24" },
128 { OMAP5_MCBSP2_CLKCTRL, omap5_mcbsp2_bit_data, CLKF_SW_SUP, "abe_cm:clk:0030:24" },
129 { OMAP5_MCBSP3_CLKCTRL, omap5_mcbsp3_bit_data, CLKF_SW_SUP, "abe_cm:clk:0038:24" },
130 { OMAP5_TIMER5_CLKCTRL, omap5_timer5_bit_data, CLKF_SW_SUP, "abe_cm:clk:0048:24" },
131 { OMAP5_TIMER6_CLKCTRL, omap5_timer6_bit_data, CLKF_SW_SUP, "abe_cm:clk:0050:24" },
132 { OMAP5_TIMER7_CLKCTRL, omap5_timer7_bit_data, CLKF_SW_SUP, "abe_cm:clk:0058:24" },
133 { OMAP5_TIMER8_CLKCTRL, omap5_timer8_bit_data, CLKF_SW_SUP, "abe_cm:clk:0060:24" },
134 { 0 },
135};
136
137static const struct omap_clkctrl_reg_data omap5_l3main1_clkctrl_regs[] __initconst = {
138 { OMAP5_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_iclk_div" },
139 { 0 },
140};
141
142static const struct omap_clkctrl_reg_data omap5_l3main2_clkctrl_regs[] __initconst = {
143 { OMAP5_L3_MAIN_2_CLKCTRL, NULL, 0, "l3_iclk_div" },
144 { 0 },
145};
146
147static const struct omap_clkctrl_reg_data omap5_ipu_clkctrl_regs[] __initconst = {
148 { OMAP5_MMU_IPU_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h22x2_ck" },
149 { 0 },
150};
151
152static const struct omap_clkctrl_reg_data omap5_dma_clkctrl_regs[] __initconst = {
153 { OMAP5_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_iclk_div" },
154 { 0 },
155};
156
157static const struct omap_clkctrl_reg_data omap5_emif_clkctrl_regs[] __initconst = {
158 { OMAP5_DMM_CLKCTRL, NULL, 0, "l3_iclk_div" },
159 { OMAP5_EMIF1_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h11x2_ck" },
160 { OMAP5_EMIF2_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h11x2_ck" },
161 { 0 },
162};
163
164static const struct omap_clkctrl_reg_data omap5_l4cfg_clkctrl_regs[] __initconst = {
165 { OMAP5_L4_CFG_CLKCTRL, NULL, 0, "l4_root_clk_div" },
166 { OMAP5_SPINLOCK_CLKCTRL, NULL, 0, "l4_root_clk_div" },
167 { OMAP5_MAILBOX_CLKCTRL, NULL, 0, "l4_root_clk_div" },
168 { 0 },
169};
170
171static const struct omap_clkctrl_reg_data omap5_l3instr_clkctrl_regs[] __initconst = {
172 { OMAP5_L3_MAIN_3_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
173 { OMAP5_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
174 { 0 },
175};
176
177static const char * const omap5_timer10_gfclk_mux_parents[] __initconst = {
178 "sys_clkin",
179 "sys_32k_ck",
180 NULL,
181};
182
183static const struct omap_clkctrl_bit_data omap5_timer10_bit_data[] __initconst = {
184 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
185 { 0 },
186};
187
188static const struct omap_clkctrl_bit_data omap5_timer11_bit_data[] __initconst = {
189 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
190 { 0 },
191};
192
193static const struct omap_clkctrl_bit_data omap5_timer2_bit_data[] __initconst = {
194 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
195 { 0 },
196};
197
198static const struct omap_clkctrl_bit_data omap5_timer3_bit_data[] __initconst = {
199 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
200 { 0 },
201};
202
203static const struct omap_clkctrl_bit_data omap5_timer4_bit_data[] __initconst = {
204 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
205 { 0 },
206};
207
208static const struct omap_clkctrl_bit_data omap5_timer9_bit_data[] __initconst = {
209 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
210 { 0 },
211};
212
213static const char * const omap5_gpio2_dbclk_parents[] __initconst = {
214 "sys_32k_ck",
215 NULL,
216};
217
218static const struct omap_clkctrl_bit_data omap5_gpio2_bit_data[] __initconst = {
219 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
220 { 0 },
221};
222
223static const struct omap_clkctrl_bit_data omap5_gpio3_bit_data[] __initconst = {
224 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
225 { 0 },
226};
227
228static const struct omap_clkctrl_bit_data omap5_gpio4_bit_data[] __initconst = {
229 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
230 { 0 },
231};
232
233static const struct omap_clkctrl_bit_data omap5_gpio5_bit_data[] __initconst = {
234 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
235 { 0 },
236};
237
238static const struct omap_clkctrl_bit_data omap5_gpio6_bit_data[] __initconst = {
239 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
240 { 0 },
241};
242
243static const struct omap_clkctrl_bit_data omap5_gpio7_bit_data[] __initconst = {
244 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
245 { 0 },
246};
247
248static const struct omap_clkctrl_bit_data omap5_gpio8_bit_data[] __initconst = {
249 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
250 { 0 },
251};
252
253static const struct omap_clkctrl_reg_data omap5_l4per_clkctrl_regs[] __initconst = {
254 { OMAP5_TIMER10_CLKCTRL, omap5_timer10_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0008:24" },
255 { OMAP5_TIMER11_CLKCTRL, omap5_timer11_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0010:24" },
256 { OMAP5_TIMER2_CLKCTRL, omap5_timer2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0018:24" },
257 { OMAP5_TIMER3_CLKCTRL, omap5_timer3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0020:24" },
258 { OMAP5_TIMER4_CLKCTRL, omap5_timer4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0028:24" },
259 { OMAP5_TIMER9_CLKCTRL, omap5_timer9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0030:24" },
260 { OMAP5_GPIO2_CLKCTRL, omap5_gpio2_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
261 { OMAP5_GPIO3_CLKCTRL, omap5_gpio3_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
262 { OMAP5_GPIO4_CLKCTRL, omap5_gpio4_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
263 { OMAP5_GPIO5_CLKCTRL, omap5_gpio5_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
264 { OMAP5_GPIO6_CLKCTRL, omap5_gpio6_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
265 { OMAP5_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
266 { OMAP5_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
267 { OMAP5_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
268 { OMAP5_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
269 { OMAP5_L4_PER_CLKCTRL, NULL, 0, "l4_root_clk_div" },
270 { OMAP5_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
271 { OMAP5_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
272 { OMAP5_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
273 { OMAP5_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
274 { OMAP5_GPIO7_CLKCTRL, omap5_gpio7_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
275 { OMAP5_GPIO8_CLKCTRL, omap5_gpio8_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
276 { OMAP5_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
277 { OMAP5_MMC4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
278 { OMAP5_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
279 { OMAP5_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
280 { OMAP5_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
281 { OMAP5_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
282 { OMAP5_MMC5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
283 { OMAP5_I2C5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
284 { OMAP5_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
285 { OMAP5_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
286 { 0 },
287};
288
289static const char * const omap5_dss_dss_clk_parents[] __initconst = {
290 "dpll_per_h12x2_ck",
291 NULL,
292};
293
294static const char * const omap5_dss_48mhz_clk_parents[] __initconst = {
295 "func_48m_fclk",
296 NULL,
297};
298
299static const char * const omap5_dss_sys_clk_parents[] __initconst = {
300 "dss_syc_gfclk_div",
301 NULL,
302};
303
304static const struct omap_clkctrl_bit_data omap5_dss_core_bit_data[] __initconst = {
305 { 8, TI_CLK_GATE, omap5_dss_dss_clk_parents, NULL },
306 { 9, TI_CLK_GATE, omap5_dss_48mhz_clk_parents, NULL },
307 { 10, TI_CLK_GATE, omap5_dss_sys_clk_parents, NULL },
308 { 11, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
309 { 0 },
310};
311
312static const struct omap_clkctrl_reg_data omap5_dss_clkctrl_regs[] __initconst = {
313 { OMAP5_DSS_CORE_CLKCTRL, omap5_dss_core_bit_data, CLKF_SW_SUP, "dss_cm:clk:0000:8" },
314 { 0 },
315};
316
317static const char * const omap5_mmc1_fclk_mux_parents[] __initconst = {
318 "func_128m_clk",
319 "dpll_per_m2x2_ck",
320 NULL,
321};
322
323static const char * const omap5_mmc1_fclk_parents[] __initconst = {
324 "l3init_cm:clk:0008:24",
325 NULL,
326};
327
328static const struct omap_clkctrl_div_data omap5_mmc1_fclk_data __initconst = {
329 .max_div = 2,
330};
331
332static const struct omap_clkctrl_bit_data omap5_mmc1_bit_data[] __initconst = {
333 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
334 { 24, TI_CLK_MUX, omap5_mmc1_fclk_mux_parents, NULL },
335 { 25, TI_CLK_DIVIDER, omap5_mmc1_fclk_parents, &omap5_mmc1_fclk_data },
336 { 0 },
337};
338
339static const char * const omap5_mmc2_fclk_parents[] __initconst = {
340 "l3init_cm:clk:0010:24",
341 NULL,
342};
343
344static const struct omap_clkctrl_div_data omap5_mmc2_fclk_data __initconst = {
345 .max_div = 2,
346};
347
348static const struct omap_clkctrl_bit_data omap5_mmc2_bit_data[] __initconst = {
349 { 24, TI_CLK_MUX, omap5_mmc1_fclk_mux_parents, NULL },
350 { 25, TI_CLK_DIVIDER, omap5_mmc2_fclk_parents, &omap5_mmc2_fclk_data },
351 { 0 },
352};
353
354static const char * const omap5_usb_host_hs_hsic60m_p3_clk_parents[] __initconst = {
355 "l3init_60m_fclk",
356 NULL,
357};
358
359static const char * const omap5_usb_host_hs_hsic480m_p3_clk_parents[] __initconst = {
360 "dpll_usb_m2_ck",
361 NULL,
362};
363
364static const char * const omap5_usb_host_hs_utmi_p1_clk_parents[] __initconst = {
365 "l3init_cm:clk:0038:24",
366 NULL,
367};
368
369static const char * const omap5_usb_host_hs_utmi_p2_clk_parents[] __initconst = {
370 "l3init_cm:clk:0038:25",
371 NULL,
372};
373
374static const char * const omap5_utmi_p1_gfclk_parents[] __initconst = {
375 "l3init_60m_fclk",
376 "xclk60mhsp1_ck",
377 NULL,
378};
379
380static const char * const omap5_utmi_p2_gfclk_parents[] __initconst = {
381 "l3init_60m_fclk",
382 "xclk60mhsp2_ck",
383 NULL,
384};
385
386static const struct omap_clkctrl_bit_data omap5_usb_host_hs_bit_data[] __initconst = {
387 { 6, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
388 { 7, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL },
389 { 8, TI_CLK_GATE, omap5_usb_host_hs_utmi_p1_clk_parents, NULL },
390 { 9, TI_CLK_GATE, omap5_usb_host_hs_utmi_p2_clk_parents, NULL },
391 { 10, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
392 { 11, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
393 { 12, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
394 { 13, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL },
395 { 14, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL },
396 { 24, TI_CLK_MUX, omap5_utmi_p1_gfclk_parents, NULL },
397 { 25, TI_CLK_MUX, omap5_utmi_p2_gfclk_parents, NULL },
398 { 0 },
399};
400
401static const struct omap_clkctrl_bit_data omap5_usb_tll_hs_bit_data[] __initconst = {
402 { 8, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
403 { 9, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
404 { 10, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
405 { 0 },
406};
407
408static const char * const omap5_sata_ref_clk_parents[] __initconst = {
409 "sys_clkin",
410 NULL,
411};
412
413static const struct omap_clkctrl_bit_data omap5_sata_bit_data[] __initconst = {
414 { 8, TI_CLK_GATE, omap5_sata_ref_clk_parents, NULL },
415 { 0 },
416};
417
418static const char * const omap5_usb_otg_ss_refclk960m_parents[] __initconst = {
419 "dpll_usb_clkdcoldo",
420 NULL,
421};
422
423static const struct omap_clkctrl_bit_data omap5_usb_otg_ss_bit_data[] __initconst = {
424 { 8, TI_CLK_GATE, omap5_usb_otg_ss_refclk960m_parents, NULL },
425 { 0 },
426};
427
428static const struct omap_clkctrl_reg_data omap5_l3init_clkctrl_regs[] __initconst = {
429 { OMAP5_MMC1_CLKCTRL, omap5_mmc1_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0008:25" },
430 { OMAP5_MMC2_CLKCTRL, omap5_mmc2_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0010:25" },
431 { OMAP5_USB_HOST_HS_CLKCTRL, omap5_usb_host_hs_bit_data, CLKF_SW_SUP, "l3init_60m_fclk" },
432 { OMAP5_USB_TLL_HS_CLKCTRL, omap5_usb_tll_hs_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
433 { OMAP5_SATA_CLKCTRL, omap5_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" },
434 { OMAP5_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
435 { OMAP5_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
436 { OMAP5_USB_OTG_SS_CLKCTRL, omap5_usb_otg_ss_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
437 { 0 },
438};
439
440static const struct omap_clkctrl_bit_data omap5_gpio1_bit_data[] __initconst = {
441 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
442 { 0 },
443};
444
445static const struct omap_clkctrl_bit_data omap5_timer1_bit_data[] __initconst = {
446 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
447 { 0 },
448};
449
450static const struct omap_clkctrl_reg_data omap5_wkupaon_clkctrl_regs[] __initconst = {
451 { OMAP5_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
452 { OMAP5_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
453 { OMAP5_GPIO1_CLKCTRL, omap5_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" },
454 { OMAP5_TIMER1_CLKCTRL, omap5_timer1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0020:24" },
455 { OMAP5_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
456 { OMAP5_KBD_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
457 { 0 },
458};
459
460const struct omap_clkctrl_data omap5_clkctrl_data[] __initconst = {
461 { 0x4a004320, omap5_mpu_clkctrl_regs },
462 { 0x4a004420, omap5_dsp_clkctrl_regs },
463 { 0x4a004520, omap5_abe_clkctrl_regs },
464 { 0x4a008720, omap5_l3main1_clkctrl_regs },
465 { 0x4a008820, omap5_l3main2_clkctrl_regs },
466 { 0x4a008920, omap5_ipu_clkctrl_regs },
467 { 0x4a008a20, omap5_dma_clkctrl_regs },
468 { 0x4a008b20, omap5_emif_clkctrl_regs },
469 { 0x4a008d20, omap5_l4cfg_clkctrl_regs },
470 { 0x4a008e20, omap5_l3instr_clkctrl_regs },
471 { 0x4a009020, omap5_l4per_clkctrl_regs },
472 { 0x4a009420, omap5_dss_clkctrl_regs },
473 { 0x4a009620, omap5_l3init_clkctrl_regs },
474 { 0x4ae07920, omap5_wkupaon_clkctrl_regs },
475 { 0 },
476};
477
52b14728 478static struct ti_dt_clk omap54xx_clks[] = {
52b14728 479 DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
d5630b7a 480 DT_CLK(NULL, "sys_clkin_ck", "sys_clkin"),
0ad902f6
TK		 481 DT_CLK(NULL, "dmic_gfclk", "abe_cm:0018:24"),
482 DT_CLK(NULL, "dmic_sync_mux_ck", "abe_cm:0018:26"),
483 DT_CLK(NULL, "dss_32khz_clk", "dss_cm:0000:11"),
484 DT_CLK(NULL, "dss_48mhz_clk", "dss_cm:0000:9"),
485 DT_CLK(NULL, "dss_dss_clk", "dss_cm:0000:8"),
486 DT_CLK(NULL, "dss_sys_clk", "dss_cm:0000:10"),
487 DT_CLK(NULL, "gpio1_dbclk", "wkupaon_cm:0018:8"),
488 DT_CLK(NULL, "gpio2_dbclk", "l4per_cm:0040:8"),
489 DT_CLK(NULL, "gpio3_dbclk", "l4per_cm:0048:8"),
490 DT_CLK(NULL, "gpio4_dbclk", "l4per_cm:0050:8"),
491 DT_CLK(NULL, "gpio5_dbclk", "l4per_cm:0058:8"),
492 DT_CLK(NULL, "gpio6_dbclk", "l4per_cm:0060:8"),
493 DT_CLK(NULL, "gpio7_dbclk", "l4per_cm:00f0:8"),
494 DT_CLK(NULL, "gpio8_dbclk", "l4per_cm:00f8:8"),
495 DT_CLK(NULL, "mcbsp1_gfclk", "abe_cm:0028:24"),
496 DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe_cm:0028:26"),
497 DT_CLK(NULL, "mcbsp2_gfclk", "abe_cm:0030:24"),
498 DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe_cm:0030:26"),
499 DT_CLK(NULL, "mcbsp3_gfclk", "abe_cm:0038:24"),
500 DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe_cm:0038:26"),
501 DT_CLK(NULL, "mmc1_32khz_clk", "l3init_cm:0008:8"),
502 DT_CLK(NULL, "mmc1_fclk", "l3init_cm:0008:25"),
503 DT_CLK(NULL, "mmc1_fclk_mux", "l3init_cm:0008:24"),
504 DT_CLK(NULL, "mmc2_fclk", "l3init_cm:0010:25"),
505 DT_CLK(NULL, "mmc2_fclk_mux", "l3init_cm:0010:24"),
506 DT_CLK(NULL, "sata_ref_clk", "l3init_cm:0068:8"),
507 DT_CLK(NULL, "timer10_gfclk_mux", "l4per_cm:0008:24"),
508 DT_CLK(NULL, "timer11_gfclk_mux", "l4per_cm:0010:24"),
509 DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon_cm:0020:24"),
510 DT_CLK(NULL, "timer2_gfclk_mux", "l4per_cm:0018:24"),
511 DT_CLK(NULL, "timer3_gfclk_mux", "l4per_cm:0020:24"),
512 DT_CLK(NULL, "timer4_gfclk_mux", "l4per_cm:0028:24"),
513 DT_CLK(NULL, "timer5_gfclk_mux", "abe_cm:0048:24"),
514 DT_CLK(NULL, "timer6_gfclk_mux", "abe_cm:0050:24"),
515 DT_CLK(NULL, "timer7_gfclk_mux", "abe_cm:0058:24"),
516 DT_CLK(NULL, "timer8_gfclk_mux", "abe_cm:0060:24"),
517 DT_CLK(NULL, "timer9_gfclk_mux", "l4per_cm:0030:24"),
518 DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3init_cm:0038:13"),
519 DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3init_cm:0038:14"),
520 DT_CLK(NULL, "usb_host_hs_hsic480m_p3_clk", "l3init_cm:0038:7"),
521 DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3init_cm:0038:11"),
522 DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3init_cm:0038:12"),
523 DT_CLK(NULL, "usb_host_hs_hsic60m_p3_clk", "l3init_cm:0038:6"),
524 DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3init_cm:0038:8"),
525 DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3init_cm:0038:9"),
526 DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3init_cm:0038:10"),
527 DT_CLK(NULL, "usb_otg_ss_refclk960m", "l3init_cm:00d0:8"),
528 DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3init_cm:0048:8"),
529 DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3init_cm:0048:9"),
530 DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3init_cm:0048:10"),
531 DT_CLK(NULL, "utmi_p1_gfclk", "l3init_cm:0038:24"),
532 DT_CLK(NULL, "utmi_p2_gfclk", "l3init_cm:0038:25"),
52b14728
TK		 533 { .node_name = NULL },
534};
535
536int __init omap5xxx_dt_clk_init(void)
537{
538 int rc;
62125a46 539 struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll;
52b14728
TK		 540
541 ti_dt_clocks_register(omap54xx_clks);
542
543 omap2_clk_disable_autoidle_all();
544
d41e5304
TK		 545 ti_clk_add_aliases();
546
52b14728
TK		 547 abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_clk_mux");
548 sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck");
549 rc = clk_set_parent(abe_dpll_ref, sys_32k_ck);
550 abe_dpll = clk_get_sys(NULL, "dpll_abe_ck");
551 if (!rc)
552 rc = clk_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ);
553 if (rc)
554 pr_err("%s: failed to configure ABE DPLL!\n", __func__);
555
81c7e03a
PU		 556 abe_dpll = clk_get_sys(NULL, "dpll_abe_m2x2_ck");
557 if (!rc)
558 rc = clk_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ * 2);
559 if (rc)
560 pr_err("%s: failed to configure ABE m2x2 DPLL!\n", __func__);
561
62125a46
RQ		 562 usb_dpll = clk_get_sys(NULL, "dpll_usb_ck");
563 rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ);
564 if (rc)
565 pr_err("%s: failed to configure USB DPLL!\n", __func__);
566
567 usb_dpll = clk_get_sys(NULL, "dpll_usb_m2_ck");
568 rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ/2);
569 if (rc)
570 pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__);
571
52b14728
TK		 572 return 0;
573}
Linux 6.x block layer and io_uring tree(s)