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ffab2399 TK |
1 | /* |
2 | * AM43XX Clock init | |
3 | * | |
4 | * Copyright (C) 2013 Texas Instruments, Inc | |
5 | * Tero Kristo (t-kristo@ti.com) | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation version 2. | |
10 | * | |
11 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
12 | * kind, whether express or implied; without even the implied warranty | |
13 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | */ | |
16 | ||
17 | #include <linux/kernel.h> | |
18 | #include <linux/list.h> | |
1b29e601 | 19 | #include <linux/clk.h> |
ffab2399 TK |
20 | #include <linux/clk-provider.h> |
21 | #include <linux/clk/ti.h> | |
22 | ||
a3314e9c TK |
23 | #include "clock.h" |
24 | ||
ffab2399 TK |
25 | static struct ti_dt_clk am43xx_clks[] = { |
26 | DT_CLK(NULL, "clk_32768_ck", "clk_32768_ck"), | |
27 | DT_CLK(NULL, "clk_rc32k_ck", "clk_rc32k_ck"), | |
28 | DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"), | |
29 | DT_CLK(NULL, "virt_24000000_ck", "virt_24000000_ck"), | |
30 | DT_CLK(NULL, "virt_25000000_ck", "virt_25000000_ck"), | |
31 | DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"), | |
32 | DT_CLK(NULL, "sys_clkin_ck", "sys_clkin_ck"), | |
33 | DT_CLK(NULL, "tclkin_ck", "tclkin_ck"), | |
34 | DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"), | |
35 | DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"), | |
36 | DT_CLK(NULL, "dpll_core_m4_ck", "dpll_core_m4_ck"), | |
37 | DT_CLK(NULL, "dpll_core_m5_ck", "dpll_core_m5_ck"), | |
38 | DT_CLK(NULL, "dpll_core_m6_ck", "dpll_core_m6_ck"), | |
39 | DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"), | |
40 | DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"), | |
41 | DT_CLK(NULL, "dpll_ddr_ck", "dpll_ddr_ck"), | |
42 | DT_CLK(NULL, "dpll_ddr_m2_ck", "dpll_ddr_m2_ck"), | |
43 | DT_CLK(NULL, "dpll_disp_ck", "dpll_disp_ck"), | |
44 | DT_CLK(NULL, "dpll_disp_m2_ck", "dpll_disp_m2_ck"), | |
45 | DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"), | |
46 | DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"), | |
47 | DT_CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", "dpll_per_m2_div4_wkupdm_ck"), | |
48 | DT_CLK(NULL, "dpll_per_m2_div4_ck", "dpll_per_m2_div4_ck"), | |
49 | DT_CLK(NULL, "adc_tsc_fck", "adc_tsc_fck"), | |
50 | DT_CLK(NULL, "clkdiv32k_ck", "clkdiv32k_ck"), | |
51 | DT_CLK(NULL, "clkdiv32k_ick", "clkdiv32k_ick"), | |
52 | DT_CLK(NULL, "dcan0_fck", "dcan0_fck"), | |
53 | DT_CLK(NULL, "dcan1_fck", "dcan1_fck"), | |
54 | DT_CLK(NULL, "pruss_ocp_gclk", "pruss_ocp_gclk"), | |
55 | DT_CLK(NULL, "mcasp0_fck", "mcasp0_fck"), | |
56 | DT_CLK(NULL, "mcasp1_fck", "mcasp1_fck"), | |
57 | DT_CLK(NULL, "smartreflex0_fck", "smartreflex0_fck"), | |
58 | DT_CLK(NULL, "smartreflex1_fck", "smartreflex1_fck"), | |
59 | DT_CLK(NULL, "sha0_fck", "sha0_fck"), | |
60 | DT_CLK(NULL, "aes0_fck", "aes0_fck"), | |
61 | DT_CLK(NULL, "timer1_fck", "timer1_fck"), | |
62 | DT_CLK(NULL, "timer2_fck", "timer2_fck"), | |
63 | DT_CLK(NULL, "timer3_fck", "timer3_fck"), | |
64 | DT_CLK(NULL, "timer4_fck", "timer4_fck"), | |
65 | DT_CLK(NULL, "timer5_fck", "timer5_fck"), | |
66 | DT_CLK(NULL, "timer6_fck", "timer6_fck"), | |
67 | DT_CLK(NULL, "timer7_fck", "timer7_fck"), | |
68 | DT_CLK(NULL, "wdt1_fck", "wdt1_fck"), | |
69 | DT_CLK(NULL, "l3_gclk", "l3_gclk"), | |
70 | DT_CLK(NULL, "dpll_core_m4_div2_ck", "dpll_core_m4_div2_ck"), | |
71 | DT_CLK(NULL, "l4hs_gclk", "l4hs_gclk"), | |
72 | DT_CLK(NULL, "l3s_gclk", "l3s_gclk"), | |
73 | DT_CLK(NULL, "l4ls_gclk", "l4ls_gclk"), | |
74 | DT_CLK(NULL, "clk_24mhz", "clk_24mhz"), | |
75 | DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"), | |
76 | DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"), | |
93c03a2c | 77 | DT_CLK(NULL, "dpll_clksel_mac_clk", "dpll_clksel_mac_clk"), |
ffab2399 TK |
78 | DT_CLK(NULL, "gpio0_dbclk_mux_ck", "gpio0_dbclk_mux_ck"), |
79 | DT_CLK(NULL, "gpio0_dbclk", "gpio0_dbclk"), | |
80 | DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"), | |
81 | DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"), | |
82 | DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"), | |
83 | DT_CLK(NULL, "gpio4_dbclk", "gpio4_dbclk"), | |
84 | DT_CLK(NULL, "gpio5_dbclk", "gpio5_dbclk"), | |
85 | DT_CLK(NULL, "mmc_clk", "mmc_clk"), | |
86 | DT_CLK(NULL, "gfx_fclk_clksel_ck", "gfx_fclk_clksel_ck"), | |
87 | DT_CLK(NULL, "gfx_fck_div_ck", "gfx_fck_div_ck"), | |
88 | DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"), | |
89 | DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"), | |
90 | DT_CLK(NULL, "sysclk_div", "sysclk_div"), | |
91 | DT_CLK(NULL, "disp_clk", "disp_clk"), | |
92 | DT_CLK(NULL, "clk_32k_mosc_ck", "clk_32k_mosc_ck"), | |
93 | DT_CLK(NULL, "clk_32k_tpm_ck", "clk_32k_tpm_ck"), | |
94 | DT_CLK(NULL, "dpll_extdev_ck", "dpll_extdev_ck"), | |
95 | DT_CLK(NULL, "dpll_extdev_m2_ck", "dpll_extdev_m2_ck"), | |
96 | DT_CLK(NULL, "mux_synctimer32k_ck", "mux_synctimer32k_ck"), | |
97 | DT_CLK(NULL, "synctimer_32kclk", "synctimer_32kclk"), | |
98 | DT_CLK(NULL, "timer8_fck", "timer8_fck"), | |
99 | DT_CLK(NULL, "timer9_fck", "timer9_fck"), | |
100 | DT_CLK(NULL, "timer10_fck", "timer10_fck"), | |
101 | DT_CLK(NULL, "timer11_fck", "timer11_fck"), | |
102 | DT_CLK(NULL, "cpsw_50m_clkdiv", "cpsw_50m_clkdiv"), | |
103 | DT_CLK(NULL, "cpsw_5m_clkdiv", "cpsw_5m_clkdiv"), | |
104 | DT_CLK(NULL, "dpll_ddr_x2_ck", "dpll_ddr_x2_ck"), | |
105 | DT_CLK(NULL, "dpll_ddr_m4_ck", "dpll_ddr_m4_ck"), | |
106 | DT_CLK(NULL, "dpll_per_clkdcoldo", "dpll_per_clkdcoldo"), | |
107 | DT_CLK(NULL, "dll_aging_clk_div", "dll_aging_clk_div"), | |
108 | DT_CLK(NULL, "div_core_25m_ck", "div_core_25m_ck"), | |
109 | DT_CLK(NULL, "func_12m_clk", "func_12m_clk"), | |
110 | DT_CLK(NULL, "vtp_clk_div", "vtp_clk_div"), | |
111 | DT_CLK(NULL, "usbphy_32khz_clkmux", "usbphy_32khz_clkmux"), | |
4da1c677 PS |
112 | DT_CLK("48300200.ehrpwm", "tbclk", "ehrpwm0_tbclk"), |
113 | DT_CLK("48302200.ehrpwm", "tbclk", "ehrpwm1_tbclk"), | |
114 | DT_CLK("48304200.ehrpwm", "tbclk", "ehrpwm2_tbclk"), | |
115 | DT_CLK("48306200.ehrpwm", "tbclk", "ehrpwm3_tbclk"), | |
116 | DT_CLK("48308200.ehrpwm", "tbclk", "ehrpwm4_tbclk"), | |
117 | DT_CLK("4830a200.ehrpwm", "tbclk", "ehrpwm5_tbclk"), | |
ffab2399 TK |
118 | { .node_name = NULL }, |
119 | }; | |
120 | ||
121 | int __init am43xx_dt_clk_init(void) | |
122 | { | |
f9786f41 GC |
123 | struct clk *clk1, *clk2; |
124 | ||
ffab2399 TK |
125 | ti_dt_clocks_register(am43xx_clks); |
126 | ||
127 | omap2_clk_disable_autoidle_all(); | |
128 | ||
f9786f41 GC |
129 | /* |
130 | * cpsw_cpts_rft_clk has got the choice of 3 clocksources | |
131 | * dpll_core_m4_ck, dpll_core_m5_ck and dpll_disp_m2_ck. | |
132 | * By default dpll_core_m4_ck is selected, witn this as clock | |
133 | * source the CPTS doesnot work properly. It gives clockcheck errors | |
134 | * while running PTP. | |
135 | * clockcheck: clock jumped backward or running slower than expected! | |
136 | * By selecting dpll_core_m5_ck as the clocksource fixes this issue. | |
137 | * In AM335x dpll_core_m5_ck is the default clocksource. | |
138 | */ | |
139 | clk1 = clk_get_sys(NULL, "cpsw_cpts_rft_clk"); | |
140 | clk2 = clk_get_sys(NULL, "dpll_core_m5_ck"); | |
141 | clk_set_parent(clk1, clk2); | |
142 | ||
ffab2399 TK |
143 | return 0; |
144 | } |