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3cf467a9 K |
1 | /* |
2 | * OMAP APLL clock support | |
3 | * | |
4 | * Copyright (C) 2013 Texas Instruments, Inc. | |
5 | * | |
6 | * J Keerthy <j-keerthy@ti.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
13 | * kind, whether express or implied; without even the implied warranty | |
14 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | */ | |
17 | ||
1b29e601 | 18 | #include <linux/clk.h> |
3cf467a9 K |
19 | #include <linux/clk-provider.h> |
20 | #include <linux/module.h> | |
21 | #include <linux/slab.h> | |
22 | #include <linux/io.h> | |
23 | #include <linux/err.h> | |
24 | #include <linux/string.h> | |
25 | #include <linux/log2.h> | |
26 | #include <linux/of.h> | |
27 | #include <linux/of_address.h> | |
28 | #include <linux/clk/ti.h> | |
29 | #include <linux/delay.h> | |
30 | ||
a3314e9c TK |
31 | #include "clock.h" |
32 | ||
3cf467a9 K |
33 | #define APLL_FORCE_LOCK 0x1 |
34 | #define APLL_AUTO_IDLE 0x2 | |
35 | #define MAX_APLL_WAIT_TRIES 1000000 | |
36 | ||
37 | #undef pr_fmt | |
38 | #define pr_fmt(fmt) "%s: " fmt, __func__ | |
39 | ||
40 | static int dra7_apll_enable(struct clk_hw *hw) | |
41 | { | |
42 | struct clk_hw_omap *clk = to_clk_hw_omap(hw); | |
43 | int r = 0, i = 0; | |
44 | struct dpll_data *ad; | |
45 | const char *clk_name; | |
46 | u8 state = 1; | |
47 | u32 v; | |
48 | ||
49 | ad = clk->dpll_data; | |
50 | if (!ad) | |
51 | return -EINVAL; | |
52 | ||
836ee0f7 | 53 | clk_name = clk_hw_get_name(&clk->hw); |
3cf467a9 K |
54 | |
55 | state <<= __ffs(ad->idlest_mask); | |
56 | ||
57 | /* Check is already locked */ | |
58 | v = ti_clk_ll_ops->clk_readl(ad->idlest_reg); | |
59 | ||
60 | if ((v & ad->idlest_mask) == state) | |
61 | return r; | |
62 | ||
63 | v = ti_clk_ll_ops->clk_readl(ad->control_reg); | |
64 | v &= ~ad->enable_mask; | |
65 | v |= APLL_FORCE_LOCK << __ffs(ad->enable_mask); | |
66 | ti_clk_ll_ops->clk_writel(v, ad->control_reg); | |
67 | ||
68 | state <<= __ffs(ad->idlest_mask); | |
69 | ||
70 | while (1) { | |
71 | v = ti_clk_ll_ops->clk_readl(ad->idlest_reg); | |
72 | if ((v & ad->idlest_mask) == state) | |
73 | break; | |
74 | if (i > MAX_APLL_WAIT_TRIES) | |
75 | break; | |
76 | i++; | |
77 | udelay(1); | |
78 | } | |
79 | ||
80 | if (i == MAX_APLL_WAIT_TRIES) { | |
81 | pr_warn("clock: %s failed transition to '%s'\n", | |
82 | clk_name, (state) ? "locked" : "bypassed"); | |
8d2f9e8e JL |
83 | r = -EBUSY; |
84 | } else | |
3cf467a9 K |
85 | pr_debug("clock: %s transition to '%s' in %d loops\n", |
86 | clk_name, (state) ? "locked" : "bypassed", i); | |
87 | ||
3cf467a9 K |
88 | return r; |
89 | } | |
90 | ||
91 | static void dra7_apll_disable(struct clk_hw *hw) | |
92 | { | |
93 | struct clk_hw_omap *clk = to_clk_hw_omap(hw); | |
94 | struct dpll_data *ad; | |
95 | u8 state = 1; | |
96 | u32 v; | |
97 | ||
98 | ad = clk->dpll_data; | |
99 | ||
100 | state <<= __ffs(ad->idlest_mask); | |
101 | ||
102 | v = ti_clk_ll_ops->clk_readl(ad->control_reg); | |
103 | v &= ~ad->enable_mask; | |
104 | v |= APLL_AUTO_IDLE << __ffs(ad->enable_mask); | |
105 | ti_clk_ll_ops->clk_writel(v, ad->control_reg); | |
106 | } | |
107 | ||
108 | static int dra7_apll_is_enabled(struct clk_hw *hw) | |
109 | { | |
110 | struct clk_hw_omap *clk = to_clk_hw_omap(hw); | |
111 | struct dpll_data *ad; | |
112 | u32 v; | |
113 | ||
114 | ad = clk->dpll_data; | |
115 | ||
116 | v = ti_clk_ll_ops->clk_readl(ad->control_reg); | |
117 | v &= ad->enable_mask; | |
118 | ||
119 | v >>= __ffs(ad->enable_mask); | |
120 | ||
121 | return v == APLL_AUTO_IDLE ? 0 : 1; | |
122 | } | |
123 | ||
124 | static u8 dra7_init_apll_parent(struct clk_hw *hw) | |
125 | { | |
126 | return 0; | |
127 | } | |
128 | ||
129 | static const struct clk_ops apll_ck_ops = { | |
130 | .enable = &dra7_apll_enable, | |
131 | .disable = &dra7_apll_disable, | |
132 | .is_enabled = &dra7_apll_is_enabled, | |
133 | .get_parent = &dra7_init_apll_parent, | |
134 | }; | |
135 | ||
136 | static void __init omap_clk_register_apll(struct clk_hw *hw, | |
137 | struct device_node *node) | |
138 | { | |
139 | struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw); | |
140 | struct dpll_data *ad = clk_hw->dpll_data; | |
141 | struct clk *clk; | |
142 | ||
b6f51284 TK |
143 | clk = of_clk_get(node, 0); |
144 | if (IS_ERR(clk)) { | |
145 | pr_debug("clk-ref for %s not ready, retry\n", | |
146 | node->name); | |
147 | if (!ti_clk_retry_init(node, hw, omap_clk_register_apll)) | |
148 | return; | |
149 | ||
150 | goto cleanup; | |
151 | } | |
3cf467a9 | 152 | |
b6f51284 TK |
153 | ad->clk_ref = __clk_get_hw(clk); |
154 | ||
155 | clk = of_clk_get(node, 1); | |
156 | if (IS_ERR(clk)) { | |
157 | pr_debug("clk-bypass for %s not ready, retry\n", | |
3cf467a9 K |
158 | node->name); |
159 | if (!ti_clk_retry_init(node, hw, omap_clk_register_apll)) | |
160 | return; | |
161 | ||
162 | goto cleanup; | |
163 | } | |
164 | ||
b6f51284 TK |
165 | ad->clk_bypass = __clk_get_hw(clk); |
166 | ||
1ae79c46 | 167 | clk = ti_clk_register(NULL, &clk_hw->hw, node->name); |
3cf467a9 K |
168 | if (!IS_ERR(clk)) { |
169 | of_clk_add_provider(node, of_clk_src_simple_get, clk); | |
170 | kfree(clk_hw->hw.init->parent_names); | |
171 | kfree(clk_hw->hw.init); | |
172 | return; | |
173 | } | |
174 | ||
175 | cleanup: | |
176 | kfree(clk_hw->dpll_data); | |
177 | kfree(clk_hw->hw.init->parent_names); | |
178 | kfree(clk_hw->hw.init); | |
179 | kfree(clk_hw); | |
180 | } | |
181 | ||
182 | static void __init of_dra7_apll_setup(struct device_node *node) | |
183 | { | |
184 | struct dpll_data *ad = NULL; | |
185 | struct clk_hw_omap *clk_hw = NULL; | |
186 | struct clk_init_data *init = NULL; | |
187 | const char **parent_names = NULL; | |
3cf467a9 K |
188 | |
189 | ad = kzalloc(sizeof(*ad), GFP_KERNEL); | |
190 | clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); | |
191 | init = kzalloc(sizeof(*init), GFP_KERNEL); | |
192 | if (!ad || !clk_hw || !init) | |
193 | goto cleanup; | |
194 | ||
195 | clk_hw->dpll_data = ad; | |
196 | clk_hw->hw.init = init; | |
3cf467a9 K |
197 | |
198 | init->name = node->name; | |
199 | init->ops = &apll_ck_ops; | |
200 | ||
201 | init->num_parents = of_clk_get_parent_count(node); | |
202 | if (init->num_parents < 1) { | |
203 | pr_err("dra7 apll %s must have parent(s)\n", node->name); | |
204 | goto cleanup; | |
205 | } | |
206 | ||
207 | parent_names = kzalloc(sizeof(char *) * init->num_parents, GFP_KERNEL); | |
208 | if (!parent_names) | |
209 | goto cleanup; | |
210 | ||
9da9e761 | 211 | of_clk_parent_fill(node, parent_names, init->num_parents); |
3cf467a9 K |
212 | |
213 | init->parent_names = parent_names; | |
214 | ||
215 | ad->control_reg = ti_clk_get_reg_addr(node, 0); | |
216 | ad->idlest_reg = ti_clk_get_reg_addr(node, 1); | |
217 | ||
c807dbed | 218 | if (IS_ERR(ad->control_reg) || IS_ERR(ad->idlest_reg)) |
3cf467a9 K |
219 | goto cleanup; |
220 | ||
221 | ad->idlest_mask = 0x1; | |
222 | ad->enable_mask = 0x3; | |
223 | ||
224 | omap_clk_register_apll(&clk_hw->hw, node); | |
225 | return; | |
226 | ||
227 | cleanup: | |
228 | kfree(parent_names); | |
229 | kfree(ad); | |
230 | kfree(clk_hw); | |
231 | kfree(init); | |
232 | } | |
233 | CLK_OF_DECLARE(dra7_apll_clock, "ti,dra7-apll-clock", of_dra7_apll_setup); | |
4d008589 TK |
234 | |
235 | #define OMAP2_EN_APLL_LOCKED 0x3 | |
236 | #define OMAP2_EN_APLL_STOPPED 0x0 | |
237 | ||
238 | static int omap2_apll_is_enabled(struct clk_hw *hw) | |
239 | { | |
240 | struct clk_hw_omap *clk = to_clk_hw_omap(hw); | |
241 | struct dpll_data *ad = clk->dpll_data; | |
242 | u32 v; | |
243 | ||
244 | v = ti_clk_ll_ops->clk_readl(ad->control_reg); | |
245 | v &= ad->enable_mask; | |
246 | ||
247 | v >>= __ffs(ad->enable_mask); | |
248 | ||
249 | return v == OMAP2_EN_APLL_LOCKED ? 1 : 0; | |
250 | } | |
251 | ||
252 | static unsigned long omap2_apll_recalc(struct clk_hw *hw, | |
253 | unsigned long parent_rate) | |
254 | { | |
255 | struct clk_hw_omap *clk = to_clk_hw_omap(hw); | |
256 | ||
257 | if (omap2_apll_is_enabled(hw)) | |
258 | return clk->fixed_rate; | |
259 | ||
260 | return 0; | |
261 | } | |
262 | ||
263 | static int omap2_apll_enable(struct clk_hw *hw) | |
264 | { | |
265 | struct clk_hw_omap *clk = to_clk_hw_omap(hw); | |
266 | struct dpll_data *ad = clk->dpll_data; | |
267 | u32 v; | |
268 | int i = 0; | |
269 | ||
270 | v = ti_clk_ll_ops->clk_readl(ad->control_reg); | |
271 | v &= ~ad->enable_mask; | |
272 | v |= OMAP2_EN_APLL_LOCKED << __ffs(ad->enable_mask); | |
273 | ti_clk_ll_ops->clk_writel(v, ad->control_reg); | |
274 | ||
275 | while (1) { | |
276 | v = ti_clk_ll_ops->clk_readl(ad->idlest_reg); | |
277 | if (v & ad->idlest_mask) | |
278 | break; | |
279 | if (i > MAX_APLL_WAIT_TRIES) | |
280 | break; | |
281 | i++; | |
282 | udelay(1); | |
283 | } | |
284 | ||
285 | if (i == MAX_APLL_WAIT_TRIES) { | |
286 | pr_warn("%s failed to transition to locked\n", | |
836ee0f7 | 287 | clk_hw_get_name(&clk->hw)); |
4d008589 TK |
288 | return -EBUSY; |
289 | } | |
290 | ||
291 | return 0; | |
292 | } | |
293 | ||
294 | static void omap2_apll_disable(struct clk_hw *hw) | |
295 | { | |
296 | struct clk_hw_omap *clk = to_clk_hw_omap(hw); | |
297 | struct dpll_data *ad = clk->dpll_data; | |
298 | u32 v; | |
299 | ||
300 | v = ti_clk_ll_ops->clk_readl(ad->control_reg); | |
301 | v &= ~ad->enable_mask; | |
302 | v |= OMAP2_EN_APLL_STOPPED << __ffs(ad->enable_mask); | |
303 | ti_clk_ll_ops->clk_writel(v, ad->control_reg); | |
304 | } | |
305 | ||
306 | static struct clk_ops omap2_apll_ops = { | |
307 | .enable = &omap2_apll_enable, | |
308 | .disable = &omap2_apll_disable, | |
309 | .is_enabled = &omap2_apll_is_enabled, | |
310 | .recalc_rate = &omap2_apll_recalc, | |
311 | }; | |
312 | ||
313 | static void omap2_apll_set_autoidle(struct clk_hw_omap *clk, u32 val) | |
314 | { | |
315 | struct dpll_data *ad = clk->dpll_data; | |
316 | u32 v; | |
317 | ||
318 | v = ti_clk_ll_ops->clk_readl(ad->autoidle_reg); | |
319 | v &= ~ad->autoidle_mask; | |
320 | v |= val << __ffs(ad->autoidle_mask); | |
321 | ti_clk_ll_ops->clk_writel(v, ad->control_reg); | |
322 | } | |
323 | ||
324 | #define OMAP2_APLL_AUTOIDLE_LOW_POWER_STOP 0x3 | |
325 | #define OMAP2_APLL_AUTOIDLE_DISABLE 0x0 | |
326 | ||
327 | static void omap2_apll_allow_idle(struct clk_hw_omap *clk) | |
328 | { | |
329 | omap2_apll_set_autoidle(clk, OMAP2_APLL_AUTOIDLE_LOW_POWER_STOP); | |
330 | } | |
331 | ||
332 | static void omap2_apll_deny_idle(struct clk_hw_omap *clk) | |
333 | { | |
334 | omap2_apll_set_autoidle(clk, OMAP2_APLL_AUTOIDLE_DISABLE); | |
335 | } | |
336 | ||
d687767a | 337 | static const struct clk_hw_omap_ops omap2_apll_hwops = { |
4d008589 TK |
338 | .allow_idle = &omap2_apll_allow_idle, |
339 | .deny_idle = &omap2_apll_deny_idle, | |
340 | }; | |
341 | ||
342 | static void __init of_omap2_apll_setup(struct device_node *node) | |
343 | { | |
344 | struct dpll_data *ad = NULL; | |
345 | struct clk_hw_omap *clk_hw = NULL; | |
346 | struct clk_init_data *init = NULL; | |
347 | struct clk *clk; | |
348 | const char *parent_name; | |
349 | u32 val; | |
350 | ||
6c7ee890 | 351 | ad = kzalloc(sizeof(*ad), GFP_KERNEL); |
4d008589 TK |
352 | clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); |
353 | init = kzalloc(sizeof(*init), GFP_KERNEL); | |
354 | ||
355 | if (!ad || !clk_hw || !init) | |
356 | goto cleanup; | |
357 | ||
358 | clk_hw->dpll_data = ad; | |
359 | clk_hw->hw.init = init; | |
360 | init->ops = &omap2_apll_ops; | |
361 | init->name = node->name; | |
362 | clk_hw->ops = &omap2_apll_hwops; | |
363 | ||
364 | init->num_parents = of_clk_get_parent_count(node); | |
365 | if (init->num_parents != 1) { | |
366 | pr_err("%s must have one parent\n", node->name); | |
367 | goto cleanup; | |
368 | } | |
369 | ||
370 | parent_name = of_clk_get_parent_name(node, 0); | |
371 | init->parent_names = &parent_name; | |
372 | ||
373 | if (of_property_read_u32(node, "ti,clock-frequency", &val)) { | |
374 | pr_err("%s missing clock-frequency\n", node->name); | |
375 | goto cleanup; | |
376 | } | |
377 | clk_hw->fixed_rate = val; | |
378 | ||
379 | if (of_property_read_u32(node, "ti,bit-shift", &val)) { | |
380 | pr_err("%s missing bit-shift\n", node->name); | |
381 | goto cleanup; | |
382 | } | |
383 | ||
384 | clk_hw->enable_bit = val; | |
385 | ad->enable_mask = 0x3 << val; | |
386 | ad->autoidle_mask = 0x3 << val; | |
387 | ||
388 | if (of_property_read_u32(node, "ti,idlest-shift", &val)) { | |
389 | pr_err("%s missing idlest-shift\n", node->name); | |
390 | goto cleanup; | |
391 | } | |
392 | ||
393 | ad->idlest_mask = 1 << val; | |
394 | ||
395 | ad->control_reg = ti_clk_get_reg_addr(node, 0); | |
396 | ad->autoidle_reg = ti_clk_get_reg_addr(node, 1); | |
397 | ad->idlest_reg = ti_clk_get_reg_addr(node, 2); | |
398 | ||
c807dbed TK |
399 | if (IS_ERR(ad->control_reg) || IS_ERR(ad->autoidle_reg) || |
400 | IS_ERR(ad->idlest_reg)) | |
4d008589 TK |
401 | goto cleanup; |
402 | ||
403 | clk = clk_register(NULL, &clk_hw->hw); | |
404 | if (!IS_ERR(clk)) { | |
405 | of_clk_add_provider(node, of_clk_src_simple_get, clk); | |
406 | kfree(init); | |
407 | return; | |
408 | } | |
409 | cleanup: | |
410 | kfree(ad); | |
411 | kfree(clk_hw); | |
412 | kfree(init); | |
413 | } | |
414 | CLK_OF_DECLARE(omap2_apll_clock, "ti,omap2-apll-clock", | |
415 | of_omap2_apll_setup); |