[linux-block.git] / drivers / clk / ti / apll.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * OMAP APLL clock support
 *
 * Copyright (C) 2013 Texas Instruments, Inc.
 *
 * J Keerthy <j-keerthy@ti.com>
 */

#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/err.h>
#include <linux/string.h>
#include <linux/log2.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/clk/ti.h>
#include <linux/delay.h>

#include "clock.h"

#define APLL_FORCE_LOCK 0x1
#define APLL_AUTO_IDLE	0x2
#define MAX_APLL_WAIT_TRIES		1000000

#undef pr_fmt
#define pr_fmt(fmt) "%s: " fmt, __func__

static int dra7_apll_enable(struct clk_hw *hw)
{
	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
	int r = 0, i = 0;
	struct dpll_data *ad;
	const char *clk_name;
	u8 state = 1;
	u32 v;

	ad = clk->dpll_data;
	if (!ad)
		return -EINVAL;

	clk_name = clk_hw_get_name(&clk->hw);

	state <<= __ffs(ad->idlest_mask);

	/* Check is already locked */
	v = ti_clk_ll_ops->clk_readl(&ad->idlest_reg);

	if ((v & ad->idlest_mask) == state)
		return r;

	v = ti_clk_ll_ops->clk_readl(&ad->control_reg);
	v &= ~ad->enable_mask;
	v |= APLL_FORCE_LOCK << __ffs(ad->enable_mask);
	ti_clk_ll_ops->clk_writel(v, &ad->control_reg);

	state <<= __ffs(ad->idlest_mask);

	while (1) {
		v = ti_clk_ll_ops->clk_readl(&ad->idlest_reg);
		if ((v & ad->idlest_mask) == state)
			break;
		if (i > MAX_APLL_WAIT_TRIES)
			break;
		i++;
		udelay(1);
	}

	if (i == MAX_APLL_WAIT_TRIES) {
		pr_warn("clock: %s failed transition to '%s'\n",
			clk_name, (state) ? "locked" : "bypassed");
		r = -EBUSY;
	} else
		pr_debug("clock: %s transition to '%s' in %d loops\n",
			 clk_name, (state) ? "locked" : "bypassed", i);

	return r;
}

static void dra7_apll_disable(struct clk_hw *hw)
{
	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
	struct dpll_data *ad;
	u8 state = 1;
	u32 v;

	ad = clk->dpll_data;

	state <<= __ffs(ad->idlest_mask);

	v = ti_clk_ll_ops->clk_readl(&ad->control_reg);
	v &= ~ad->enable_mask;
	v |= APLL_AUTO_IDLE << __ffs(ad->enable_mask);
	ti_clk_ll_ops->clk_writel(v, &ad->control_reg);
}

static int dra7_apll_is_enabled(struct clk_hw *hw)
{
	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
	struct dpll_data *ad;
	u32 v;

	ad = clk->dpll_data;

	v = ti_clk_ll_ops->clk_readl(&ad->control_reg);
	v &= ad->enable_mask;

	v >>= __ffs(ad->enable_mask);

	return v == APLL_AUTO_IDLE ? 0 : 1;
}

static u8 dra7_init_apll_parent(struct clk_hw *hw)
{
	return 0;
}

static const struct clk_ops apll_ck_ops = {
	.enable		= &dra7_apll_enable,
	.disable	= &dra7_apll_disable,
	.is_enabled	= &dra7_apll_is_enabled,
	.get_parent	= &dra7_init_apll_parent,
};

static void __init omap_clk_register_apll(void *user,
					  struct device_node *node)
{
	struct clk_hw *hw = user;
	struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw);
	struct dpll_data *ad = clk_hw->dpll_data;
	const char *name;
	struct clk *clk;
	const struct clk_init_data *init = clk_hw->hw.init;

	clk = of_clk_get(node, 0);
	if (IS_ERR(clk)) {
		pr_debug("clk-ref for %pOFn not ready, retry\n",
			 node);
		if (!ti_clk_retry_init(node, hw, omap_clk_register_apll))
			return;

		goto cleanup;
	}

	ad->clk_ref = __clk_get_hw(clk);

	clk = of_clk_get(node, 1);
	if (IS_ERR(clk)) {
		pr_debug("clk-bypass for %pOFn not ready, retry\n",
			 node);
		if (!ti_clk_retry_init(node, hw, omap_clk_register_apll))
			return;

		goto cleanup;
	}

	ad->clk_bypass = __clk_get_hw(clk);

	name = ti_dt_clk_name(node);
	clk = of_ti_clk_register_omap_hw(node, &clk_hw->hw, name);
	if (!IS_ERR(clk)) {
		of_clk_add_provider(node, of_clk_src_simple_get, clk);
		kfree(init->parent_names);
		kfree(init);
		return;
	}

cleanup:
	kfree(clk_hw->dpll_data);
	kfree(init->parent_names);
	kfree(init);
	kfree(clk_hw);
}

static void __init of_dra7_apll_setup(struct device_node *node)
{
	struct dpll_data *ad = NULL;
	struct clk_hw_omap *clk_hw = NULL;
	struct clk_init_data *init = NULL;
	const char **parent_names = NULL;
	int ret;

	ad = kzalloc(sizeof(*ad), GFP_KERNEL);
	clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
	init = kzalloc(sizeof(*init), GFP_KERNEL);
	if (!ad || !clk_hw || !init)
		goto cleanup;

	clk_hw->dpll_data = ad;
	clk_hw->hw.init = init;

	init->name = ti_dt_clk_name(node);
	init->ops = &apll_ck_ops;

	init->num_parents = of_clk_get_parent_count(node);
	if (init->num_parents < 1) {
		pr_err("dra7 apll %pOFn must have parent(s)\n", node);
		goto cleanup;
	}

	parent_names = kcalloc(init->num_parents, sizeof(char *), GFP_KERNEL);
	if (!parent_names)
		goto cleanup;

	of_clk_parent_fill(node, parent_names, init->num_parents);

	init->parent_names = parent_names;

	ret = ti_clk_get_reg_addr(node, 0, &ad->control_reg);
	ret |= ti_clk_get_reg_addr(node, 1, &ad->idlest_reg);

	if (ret)
		goto cleanup;

	ad->idlest_mask = 0x1;
	ad->enable_mask = 0x3;

	omap_clk_register_apll(&clk_hw->hw, node);
	return;

cleanup:
	kfree(parent_names);
	kfree(ad);
	kfree(clk_hw);
	kfree(init);
}
CLK_OF_DECLARE(dra7_apll_clock, "ti,dra7-apll-clock", of_dra7_apll_setup);

#define OMAP2_EN_APLL_LOCKED	0x3
#define OMAP2_EN_APLL_STOPPED	0x0

static int omap2_apll_is_enabled(struct clk_hw *hw)
{
	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
	struct dpll_data *ad = clk->dpll_data;
	u32 v;

	v = ti_clk_ll_ops->clk_readl(&ad->control_reg);
	v &= ad->enable_mask;

	v >>= __ffs(ad->enable_mask);

	return v == OMAP2_EN_APLL_LOCKED ? 1 : 0;
}

static unsigned long omap2_apll_recalc(struct clk_hw *hw,
				       unsigned long parent_rate)
{
	struct clk_hw_omap *clk = to_clk_hw_omap(hw);

	if (omap2_apll_is_enabled(hw))
		return clk->fixed_rate;

	return 0;
}

static int omap2_apll_enable(struct clk_hw *hw)
{
	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
	struct dpll_data *ad = clk->dpll_data;
	u32 v;
	int i = 0;

	v = ti_clk_ll_ops->clk_readl(&ad->control_reg);
	v &= ~ad->enable_mask;
	v |= OMAP2_EN_APLL_LOCKED << __ffs(ad->enable_mask);
	ti_clk_ll_ops->clk_writel(v, &ad->control_reg);

	while (1) {
		v = ti_clk_ll_ops->clk_readl(&ad->idlest_reg);
		if (v & ad->idlest_mask)
			break;
		if (i > MAX_APLL_WAIT_TRIES)
			break;
		i++;
		udelay(1);
	}

	if (i == MAX_APLL_WAIT_TRIES) {
		pr_warn("%s failed to transition to locked\n",
			clk_hw_get_name(&clk->hw));
		return -EBUSY;
	}

	return 0;
}

static void omap2_apll_disable(struct clk_hw *hw)
{
	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
	struct dpll_data *ad = clk->dpll_data;
	u32 v;

	v = ti_clk_ll_ops->clk_readl(&ad->control_reg);
	v &= ~ad->enable_mask;
	v |= OMAP2_EN_APLL_STOPPED << __ffs(ad->enable_mask);
	ti_clk_ll_ops->clk_writel(v, &ad->control_reg);
}

static const struct clk_ops omap2_apll_ops = {
	.enable		= &omap2_apll_enable,
	.disable	= &omap2_apll_disable,
	.is_enabled	= &omap2_apll_is_enabled,
	.recalc_rate	= &omap2_apll_recalc,
};

static void omap2_apll_set_autoidle(struct clk_hw_omap *clk, u32 val)
{
	struct dpll_data *ad = clk->dpll_data;
	u32 v;

	v = ti_clk_ll_ops->clk_readl(&ad->autoidle_reg);
	v &= ~ad->autoidle_mask;
	v |= val << __ffs(ad->autoidle_mask);
	ti_clk_ll_ops->clk_writel(v, &ad->control_reg);
}

#define OMAP2_APLL_AUTOIDLE_LOW_POWER_STOP	0x3
#define OMAP2_APLL_AUTOIDLE_DISABLE		0x0

static void omap2_apll_allow_idle(struct clk_hw_omap *clk)
{
	omap2_apll_set_autoidle(clk, OMAP2_APLL_AUTOIDLE_LOW_POWER_STOP);
}

static void omap2_apll_deny_idle(struct clk_hw_omap *clk)
{
	omap2_apll_set_autoidle(clk, OMAP2_APLL_AUTOIDLE_DISABLE);
}

static const struct clk_hw_omap_ops omap2_apll_hwops = {
	.allow_idle	= &omap2_apll_allow_idle,
	.deny_idle	= &omap2_apll_deny_idle,
};

static void __init of_omap2_apll_setup(struct device_node *node)
{
	struct dpll_data *ad = NULL;
	struct clk_hw_omap *clk_hw = NULL;
	struct clk_init_data *init = NULL;
	const char *name;
	struct clk *clk;
	const char *parent_name;
	u32 val;
	int ret;

	ad = kzalloc(sizeof(*ad), GFP_KERNEL);
	clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
	init = kzalloc(sizeof(*init), GFP_KERNEL);

	if (!ad || !clk_hw || !init)
		goto cleanup;

	clk_hw->dpll_data = ad;
	clk_hw->hw.init = init;
	init->ops = &omap2_apll_ops;
	name = ti_dt_clk_name(node);
	init->name = name;
	clk_hw->ops = &omap2_apll_hwops;

	init->num_parents = of_clk_get_parent_count(node);
	if (init->num_parents != 1) {
		pr_err("%pOFn must have one parent\n", node);
		goto cleanup;
	}

	parent_name = of_clk_get_parent_name(node, 0);
	init->parent_names = &parent_name;

	if (of_property_read_u32(node, "ti,clock-frequency", &val)) {
		pr_err("%pOFn missing clock-frequency\n", node);
		goto cleanup;
	}
	clk_hw->fixed_rate = val;

	if (of_property_read_u32(node, "ti,bit-shift", &val)) {
		pr_err("%pOFn missing bit-shift\n", node);
		goto cleanup;
	}

	clk_hw->enable_bit = val;
	ad->enable_mask = 0x3 << val;
	ad->autoidle_mask = 0x3 << val;

	if (of_property_read_u32(node, "ti,idlest-shift", &val)) {
		pr_err("%pOFn missing idlest-shift\n", node);
		goto cleanup;
	}

	ad->idlest_mask = 1 << val;

	ret = ti_clk_get_reg_addr(node, 0, &ad->control_reg);
	ret |= ti_clk_get_reg_addr(node, 1, &ad->autoidle_reg);
	ret |= ti_clk_get_reg_addr(node, 2, &ad->idlest_reg);

	if (ret)
		goto cleanup;

	name = ti_dt_clk_name(node);
	clk = of_ti_clk_register_omap_hw(node, &clk_hw->hw, name);
	if (!IS_ERR(clk)) {
		of_clk_add_provider(node, of_clk_src_simple_get, clk);
		kfree(init);
		return;
	}
cleanup:
	kfree(ad);
	kfree(clk_hw);
	kfree(init);
}
CLK_OF_DECLARE(omap2_apll_clock, "ti,omap2-apll-clock",
	       of_omap2_apll_setup);
Commit	Line	Data
5a729246	1	// SPDX-License-Identifier: GPL-2.0-only
3cf467a9 K	2	/*
	3	* OMAP APLL clock support
	4	*
	5	* Copyright (C) 2013 Texas Instruments, Inc.
	6	*
	7	* J Keerthy <j-keerthy@ti.com>
3cf467a9 K	8	*/
3cf467a9 K	9
1b29e601	10	#include <linux/clk.h>
3cf467a9 K	11	#include <linux/clk-provider.h>
	12	#include <linux/module.h>
	13	#include <linux/slab.h>
	14	#include <linux/io.h>
	15	#include <linux/err.h>
	16	#include <linux/string.h>
	17	#include <linux/log2.h>
	18	#include <linux/of.h>
	19	#include <linux/of_address.h>
	20	#include <linux/clk/ti.h>
	21	#include <linux/delay.h>
	22
a3314e9c TK	23	#include "clock.h"
a3314e9c TK	24
3cf467a9 K	25	#define APLL_FORCE_LOCK 0x1
	26	#define APLL_AUTO_IDLE 0x2
	27	#define MAX_APLL_WAIT_TRIES 1000000
	28
	29	#undef pr_fmt
	30	#define pr_fmt(fmt) "%s: " fmt, __func__
	31
	32	static int dra7_apll_enable(struct clk_hw *hw)
	33	{
	34	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
	35	int r = 0, i = 0;
	36	struct dpll_data *ad;
	37	const char *clk_name;
	38	u8 state = 1;
	39	u32 v;
	40
	41	ad = clk->dpll_data;
	42	if (!ad)
	43	return -EINVAL;
	44
836ee0f7	45	clk_name = clk_hw_get_name(&clk->hw);
3cf467a9 K	46
	47	state <<= __ffs(ad->idlest_mask);
	48
	49	/* Check is already locked */
6c0afb50	50	v = ti_clk_ll_ops->clk_readl(&ad->idlest_reg);
3cf467a9 K	51
	52	if ((v & ad->idlest_mask) == state)
	53	return r;
	54
6c0afb50	55	v = ti_clk_ll_ops->clk_readl(&ad->control_reg);
3cf467a9 K	56	v &= ~ad->enable_mask;
3cf467a9 K	57	v \|= APLL_FORCE_LOCK << __ffs(ad->enable_mask);
6c0afb50	58	ti_clk_ll_ops->clk_writel(v, &ad->control_reg);
3cf467a9 K	59
	60	state <<= __ffs(ad->idlest_mask);
	61
	62	while (1) {
6c0afb50	63	v = ti_clk_ll_ops->clk_readl(&ad->idlest_reg);
3cf467a9 K	64	if ((v & ad->idlest_mask) == state)
	65	break;
	66	if (i > MAX_APLL_WAIT_TRIES)
	67	break;
	68	i++;
	69	udelay(1);
	70	}
	71
	72	if (i == MAX_APLL_WAIT_TRIES) {
	73	pr_warn("clock: %s failed transition to '%s'\n",
	74	clk_name, (state) ? "locked" : "bypassed");
8d2f9e8e JL	75	r = -EBUSY;
8d2f9e8e JL	76	} else
3cf467a9 K	77	pr_debug("clock: %s transition to '%s' in %d loops\n",
	78	clk_name, (state) ? "locked" : "bypassed", i);
	79
3cf467a9 K	80	return r;
	81	}
	82
	83	static void dra7_apll_disable(struct clk_hw *hw)
	84	{
	85	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
	86	struct dpll_data *ad;
	87	u8 state = 1;
	88	u32 v;
	89
	90	ad = clk->dpll_data;
	91
	92	state <<= __ffs(ad->idlest_mask);
	93
6c0afb50	94	v = ti_clk_ll_ops->clk_readl(&ad->control_reg);
3cf467a9 K	95	v &= ~ad->enable_mask;
3cf467a9 K	96	v \|= APLL_AUTO_IDLE << __ffs(ad->enable_mask);
6c0afb50	97	ti_clk_ll_ops->clk_writel(v, &ad->control_reg);
3cf467a9 K	98	}
	99
	100	static int dra7_apll_is_enabled(struct clk_hw *hw)
	101	{
	102	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
	103	struct dpll_data *ad;
	104	u32 v;
	105
	106	ad = clk->dpll_data;
	107
6c0afb50	108	v = ti_clk_ll_ops->clk_readl(&ad->control_reg);
3cf467a9 K	109	v &= ad->enable_mask;
	110
	111	v >>= __ffs(ad->enable_mask);
	112
	113	return v == APLL_AUTO_IDLE ? 0 : 1;
	114	}
	115
	116	static u8 dra7_init_apll_parent(struct clk_hw *hw)
	117	{
	118	return 0;
	119	}
	120
	121	static const struct clk_ops apll_ck_ops = {
	122	.enable = &dra7_apll_enable,
	123	.disable = &dra7_apll_disable,
	124	.is_enabled = &dra7_apll_is_enabled,
	125	.get_parent = &dra7_init_apll_parent,
	126	};
	127
ffb009b2	128	static void __init omap_clk_register_apll(void *user,
3cf467a9 K	129	struct device_node *node)
3cf467a9 K	130	{
ffb009b2	131	struct clk_hw *hw = user;
3cf467a9 K	132	struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw);
3cf467a9 K	133	struct dpll_data *ad = clk_hw->dpll_data;
9e56a7d4	134	const char *name;
3cf467a9	135	struct clk *clk;
e0e04fc8	136	const struct clk_init_data *init = clk_hw->hw.init;
3cf467a9	137
b6f51284 TK	138	clk = of_clk_get(node, 0);
b6f51284 TK	139	if (IS_ERR(clk)) {
e665f029 RH	140	pr_debug("clk-ref for %pOFn not ready, retry\n",
e665f029 RH	141	node);
b6f51284 TK	142	if (!ti_clk_retry_init(node, hw, omap_clk_register_apll))
	143	return;
	144
	145	goto cleanup;
	146	}
3cf467a9	147
b6f51284 TK	148	ad->clk_ref = __clk_get_hw(clk);
	149
	150	clk = of_clk_get(node, 1);
	151	if (IS_ERR(clk)) {
e665f029 RH	152	pr_debug("clk-bypass for %pOFn not ready, retry\n",
e665f029 RH	153	node);
3cf467a9 K	154	if (!ti_clk_retry_init(node, hw, omap_clk_register_apll))
	155	return;
	156
	157	goto cleanup;
	158	}
	159
b6f51284 TK	160	ad->clk_bypass = __clk_get_hw(clk);
b6f51284 TK	161
9e56a7d4	162	name = ti_dt_clk_name(node);
3400d546	163	clk = of_ti_clk_register_omap_hw(node, &clk_hw->hw, name);
3cf467a9 K	164	if (!IS_ERR(clk)) {
3cf467a9 K	165	of_clk_add_provider(node, of_clk_src_simple_get, clk);
e0e04fc8 SB	166	kfree(init->parent_names);
e0e04fc8 SB	167	kfree(init);
3cf467a9 K	168	return;
	169	}
	170
	171	cleanup:
	172	kfree(clk_hw->dpll_data);
e0e04fc8 SB	173	kfree(init->parent_names);
e0e04fc8 SB	174	kfree(init);
3cf467a9 K	175	kfree(clk_hw);
	176	}
	177
	178	static void __init of_dra7_apll_setup(struct device_node *node)
	179	{
	180	struct dpll_data *ad = NULL;
	181	struct clk_hw_omap *clk_hw = NULL;
	182	struct clk_init_data *init = NULL;
	183	const char **parent_names = NULL;
6c0afb50	184	int ret;
3cf467a9 K	185
	186	ad = kzalloc(sizeof(*ad), GFP_KERNEL);
	187	clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
	188	init = kzalloc(sizeof(*init), GFP_KERNEL);
	189	if (!ad \|\| !clk_hw \|\| !init)
	190	goto cleanup;
	191
	192	clk_hw->dpll_data = ad;
	193	clk_hw->hw.init = init;
3cf467a9	194
9e56a7d4	195	init->name = ti_dt_clk_name(node);
3cf467a9 K	196	init->ops = &apll_ck_ops;
	197
	198	init->num_parents = of_clk_get_parent_count(node);
	199	if (init->num_parents < 1) {
e665f029	200	pr_err("dra7 apll %pOFn must have parent(s)\n", node);
3cf467a9 K	201	goto cleanup;
	202	}
	203
6396bb22	204	parent_names = kcalloc(init->num_parents, sizeof(char *), GFP_KERNEL);
3cf467a9 K	205	if (!parent_names)
	206	goto cleanup;
	207
9da9e761	208	of_clk_parent_fill(node, parent_names, init->num_parents);
3cf467a9 K	209
	210	init->parent_names = parent_names;
	211
6c0afb50 TK	212	ret = ti_clk_get_reg_addr(node, 0, &ad->control_reg);
6c0afb50 TK	213	ret \|= ti_clk_get_reg_addr(node, 1, &ad->idlest_reg);
3cf467a9	214
6c0afb50	215	if (ret)
3cf467a9 K	216	goto cleanup;
	217
	218	ad->idlest_mask = 0x1;
	219	ad->enable_mask = 0x3;
	220
	221	omap_clk_register_apll(&clk_hw->hw, node);
	222	return;
	223
	224	cleanup:
	225	kfree(parent_names);
	226	kfree(ad);
	227	kfree(clk_hw);
	228	kfree(init);
	229	}
	230	CLK_OF_DECLARE(dra7_apll_clock, "ti,dra7-apll-clock", of_dra7_apll_setup);
4d008589 TK	231
	232	#define OMAP2_EN_APLL_LOCKED 0x3
	233	#define OMAP2_EN_APLL_STOPPED 0x0
	234
	235	static int omap2_apll_is_enabled(struct clk_hw *hw)
	236	{
	237	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
	238	struct dpll_data *ad = clk->dpll_data;
	239	u32 v;
	240
6c0afb50	241	v = ti_clk_ll_ops->clk_readl(&ad->control_reg);
4d008589 TK	242	v &= ad->enable_mask;
	243
	244	v >>= __ffs(ad->enable_mask);
	245
	246	return v == OMAP2_EN_APLL_LOCKED ? 1 : 0;
	247	}
	248
	249	static unsigned long omap2_apll_recalc(struct clk_hw *hw,
	250	unsigned long parent_rate)
	251	{
	252	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
	253
	254	if (omap2_apll_is_enabled(hw))
	255	return clk->fixed_rate;
	256
	257	return 0;
	258	}
	259
	260	static int omap2_apll_enable(struct clk_hw *hw)
	261	{
	262	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
	263	struct dpll_data *ad = clk->dpll_data;
	264	u32 v;
	265	int i = 0;
	266
6c0afb50	267	v = ti_clk_ll_ops->clk_readl(&ad->control_reg);
4d008589 TK	268	v &= ~ad->enable_mask;
4d008589 TK	269	v \|= OMAP2_EN_APLL_LOCKED << __ffs(ad->enable_mask);
6c0afb50	270	ti_clk_ll_ops->clk_writel(v, &ad->control_reg);
4d008589 TK	271
4d008589 TK	272	while (1) {
6c0afb50	273	v = ti_clk_ll_ops->clk_readl(&ad->idlest_reg);
4d008589 TK	274	if (v & ad->idlest_mask)
	275	break;
	276	if (i > MAX_APLL_WAIT_TRIES)
	277	break;
	278	i++;
	279	udelay(1);
	280	}
	281
	282	if (i == MAX_APLL_WAIT_TRIES) {
	283	pr_warn("%s failed to transition to locked\n",
836ee0f7	284	clk_hw_get_name(&clk->hw));
4d008589 TK	285	return -EBUSY;
	286	}
	287
	288	return 0;
	289	}
	290
	291	static void omap2_apll_disable(struct clk_hw *hw)
	292	{
	293	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
	294	struct dpll_data *ad = clk->dpll_data;
	295	u32 v;
	296
6c0afb50	297	v = ti_clk_ll_ops->clk_readl(&ad->control_reg);
4d008589 TK	298	v &= ~ad->enable_mask;
4d008589 TK	299	v \|= OMAP2_EN_APLL_STOPPED << __ffs(ad->enable_mask);
6c0afb50	300	ti_clk_ll_ops->clk_writel(v, &ad->control_reg);
4d008589 TK	301	}
4d008589 TK	302
7cc566a8	303	static const struct clk_ops omap2_apll_ops = {
4d008589 TK	304	.enable = &omap2_apll_enable,
	305	.disable = &omap2_apll_disable,
	306	.is_enabled = &omap2_apll_is_enabled,
	307	.recalc_rate = &omap2_apll_recalc,
	308	};
	309
	310	static void omap2_apll_set_autoidle(struct clk_hw_omap *clk, u32 val)
	311	{
	312	struct dpll_data *ad = clk->dpll_data;
	313	u32 v;
	314
6c0afb50	315	v = ti_clk_ll_ops->clk_readl(&ad->autoidle_reg);
4d008589 TK	316	v &= ~ad->autoidle_mask;
4d008589 TK	317	v \|= val << __ffs(ad->autoidle_mask);
6c0afb50	318	ti_clk_ll_ops->clk_writel(v, &ad->control_reg);
4d008589 TK	319	}
	320
	321	#define OMAP2_APLL_AUTOIDLE_LOW_POWER_STOP 0x3
	322	#define OMAP2_APLL_AUTOIDLE_DISABLE 0x0
	323
	324	static void omap2_apll_allow_idle(struct clk_hw_omap *clk)
	325	{
	326	omap2_apll_set_autoidle(clk, OMAP2_APLL_AUTOIDLE_LOW_POWER_STOP);
	327	}
	328
	329	static void omap2_apll_deny_idle(struct clk_hw_omap *clk)
	330	{
	331	omap2_apll_set_autoidle(clk, OMAP2_APLL_AUTOIDLE_DISABLE);
	332	}
	333
d687767a	334	static const struct clk_hw_omap_ops omap2_apll_hwops = {
4d008589 TK	335	.allow_idle = &omap2_apll_allow_idle,
	336	.deny_idle = &omap2_apll_deny_idle,
	337	};
	338
	339	static void __init of_omap2_apll_setup(struct device_node *node)
	340	{
	341	struct dpll_data *ad = NULL;
	342	struct clk_hw_omap *clk_hw = NULL;
	343	struct clk_init_data *init = NULL;
9e56a7d4	344	const char *name;
4d008589 TK	345	struct clk *clk;
	346	const char *parent_name;
	347	u32 val;
6c0afb50	348	int ret;
4d008589	349
6c7ee890	350	ad = kzalloc(sizeof(*ad), GFP_KERNEL);
4d008589 TK	351	clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
	352	init = kzalloc(sizeof(*init), GFP_KERNEL);
	353
	354	if (!ad \|\| !clk_hw \|\| !init)
	355	goto cleanup;
	356
	357	clk_hw->dpll_data = ad;
	358	clk_hw->hw.init = init;
	359	init->ops = &omap2_apll_ops;
9e56a7d4 TL	360	name = ti_dt_clk_name(node);
9e56a7d4 TL	361	init->name = name;
4d008589 TK	362	clk_hw->ops = &omap2_apll_hwops;
	363
	364	init->num_parents = of_clk_get_parent_count(node);
	365	if (init->num_parents != 1) {
e665f029	366	pr_err("%pOFn must have one parent\n", node);
4d008589 TK	367	goto cleanup;
	368	}
	369
	370	parent_name = of_clk_get_parent_name(node, 0);
	371	init->parent_names = &parent_name;
	372
	373	if (of_property_read_u32(node, "ti,clock-frequency", &val)) {
e665f029	374	pr_err("%pOFn missing clock-frequency\n", node);
4d008589 TK	375	goto cleanup;
	376	}
	377	clk_hw->fixed_rate = val;
	378
	379	if (of_property_read_u32(node, "ti,bit-shift", &val)) {
e665f029	380	pr_err("%pOFn missing bit-shift\n", node);
4d008589 TK	381	goto cleanup;
	382	}
	383
	384	clk_hw->enable_bit = val;
	385	ad->enable_mask = 0x3 << val;
	386	ad->autoidle_mask = 0x3 << val;
	387
	388	if (of_property_read_u32(node, "ti,idlest-shift", &val)) {
e665f029	389	pr_err("%pOFn missing idlest-shift\n", node);
4d008589 TK	390	goto cleanup;
	391	}
	392
	393	ad->idlest_mask = 1 << val;
	394
6c0afb50 TK	395	ret = ti_clk_get_reg_addr(node, 0, &ad->control_reg);
	396	ret \|= ti_clk_get_reg_addr(node, 1, &ad->autoidle_reg);
	397	ret \|= ti_clk_get_reg_addr(node, 2, &ad->idlest_reg);
4d008589	398
6c0afb50	399	if (ret)
4d008589 TK	400	goto cleanup;
4d008589 TK	401
9e56a7d4	402	name = ti_dt_clk_name(node);
3400d546	403	clk = of_ti_clk_register_omap_hw(node, &clk_hw->hw, name);
4d008589 TK	404	if (!IS_ERR(clk)) {
	405	of_clk_add_provider(node, of_clk_src_simple_get, clk);
	406	kfree(init);
	407	return;
	408	}
	409	cleanup:
	410	kfree(ad);
	411	kfree(clk_hw);
	412	kfree(init);
	413	}
	414	CLK_OF_DECLARE(omap2_apll_clock, "ti,omap2-apll-clock",
	415	of_omap2_apll_setup);