Commit | Line | Data |
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c1d1939c | 1 | /* |
8f8f484b PG |
2 | * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License | |
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
15 | */ | |
16 | ||
17 | #ifndef __TEGRA_CLK_H | |
18 | #define __TEGRA_CLK_H | |
19 | ||
20 | #include <linux/clk-provider.h> | |
21 | #include <linux/clkdev.h> | |
22 | ||
23 | /** | |
24 | * struct tegra_clk_sync_source - external clock source from codec | |
25 | * | |
26 | * @hw: handle between common and hardware-specific interfaces | |
27 | * @rate: input frequency from source | |
28 | * @max_rate: max rate allowed | |
29 | */ | |
30 | struct tegra_clk_sync_source { | |
31 | struct clk_hw hw; | |
32 | unsigned long rate; | |
33 | unsigned long max_rate; | |
34 | }; | |
35 | ||
36 | #define to_clk_sync_source(_hw) \ | |
37 | container_of(_hw, struct tegra_clk_sync_source, hw) | |
38 | ||
39 | extern const struct clk_ops tegra_clk_sync_source_ops; | |
343a607c PDS |
40 | extern int *periph_clk_enb_refcnt; |
41 | ||
8f8f484b PG |
42 | struct clk *tegra_clk_register_sync_source(const char *name, |
43 | unsigned long fixed_rate, unsigned long max_rate); | |
44 | ||
45 | /** | |
46 | * struct tegra_clk_frac_div - fractional divider clock | |
47 | * | |
48 | * @hw: handle between common and hardware-specific interfaces | |
49 | * @reg: register containing divider | |
50 | * @flags: hardware-specific flags | |
51 | * @shift: shift to the divider bit field | |
52 | * @width: width of the divider bit field | |
53 | * @frac_width: width of the fractional bit field | |
54 | * @lock: register lock | |
55 | * | |
56 | * Flags: | |
57 | * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value. | |
58 | * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this | |
59 | * flag indicates that this divider is for fixed rate PLL. | |
60 | * TEGRA_DIVIDER_INT - Some modules can not cope with the duty cycle when | |
61 | * fraction bit is set. This flags indicates to calculate divider for which | |
62 | * fracton bit will be zero. | |
63 | * TEGRA_DIVIDER_UART - UART module divider has additional enable bit which is | |
64 | * set when divider value is not 0. This flags indicates that the divider | |
65 | * is for UART module. | |
66 | */ | |
67 | struct tegra_clk_frac_div { | |
68 | struct clk_hw hw; | |
69 | void __iomem *reg; | |
70 | u8 flags; | |
71 | u8 shift; | |
72 | u8 width; | |
73 | u8 frac_width; | |
74 | spinlock_t *lock; | |
75 | }; | |
76 | ||
77 | #define to_clk_frac_div(_hw) container_of(_hw, struct tegra_clk_frac_div, hw) | |
78 | ||
79 | #define TEGRA_DIVIDER_ROUND_UP BIT(0) | |
80 | #define TEGRA_DIVIDER_FIXED BIT(1) | |
81 | #define TEGRA_DIVIDER_INT BIT(2) | |
82 | #define TEGRA_DIVIDER_UART BIT(3) | |
83 | ||
84 | extern const struct clk_ops tegra_clk_frac_div_ops; | |
85 | struct clk *tegra_clk_register_divider(const char *name, | |
86 | const char *parent_name, void __iomem *reg, | |
87 | unsigned long flags, u8 clk_divider_flags, u8 shift, u8 width, | |
88 | u8 frac_width, spinlock_t *lock); | |
4f4f85fa TR |
89 | struct clk *tegra_clk_register_mc(const char *name, const char *parent_name, |
90 | void __iomem *reg, spinlock_t *lock); | |
8f8f484b PG |
91 | |
92 | /* | |
93 | * Tegra PLL: | |
94 | * | |
95 | * In general, there are 3 requirements for each PLL | |
96 | * that SW needs to be comply with. | |
97 | * (1) Input frequency range (REF). | |
98 | * (2) Comparison frequency range (CF). CF = REF/DIVM. | |
99 | * (3) VCO frequency range (VCO). VCO = CF * DIVN. | |
100 | * | |
101 | * The final PLL output frequency (FO) = VCO >> DIVP. | |
102 | */ | |
103 | ||
104 | /** | |
105 | * struct tegra_clk_pll_freq_table - PLL frequecy table | |
106 | * | |
107 | * @input_rate: input rate from source | |
108 | * @output_rate: output rate from PLL for the input rate | |
109 | * @n: feedback divider | |
110 | * @m: input divider | |
111 | * @p: post divider | |
112 | * @cpcon: charge pump current | |
d907f4b4 | 113 | * @sdm_data: fraction divider setting (0 = disabled) |
8f8f484b PG |
114 | */ |
115 | struct tegra_clk_pll_freq_table { | |
116 | unsigned long input_rate; | |
117 | unsigned long output_rate; | |
d907f4b4 | 118 | u32 n; |
8f8f484b PG |
119 | u16 m; |
120 | u8 p; | |
121 | u8 cpcon; | |
d907f4b4 | 122 | u16 sdm_data; |
8f8f484b PG |
123 | }; |
124 | ||
0b6525ac PDS |
125 | /** |
126 | * struct pdiv_map - map post divider to hw value | |
127 | * | |
128 | * @pdiv: post divider | |
129 | * @hw_val: value to be written to the PLL hw | |
130 | */ | |
131 | struct pdiv_map { | |
132 | u8 pdiv; | |
133 | u8 hw_val; | |
134 | }; | |
135 | ||
aa6fefde PDS |
136 | /** |
137 | * struct div_nmp - offset and width of m,n and p fields | |
138 | * | |
139 | * @divn_shift: shift to the feedback divider bit field | |
140 | * @divn_width: width of the feedback divider bit field | |
141 | * @divm_shift: shift to the input divider bit field | |
142 | * @divm_width: width of the input divider bit field | |
143 | * @divp_shift: shift to the post divider bit field | |
144 | * @divp_width: width of the post divider bit field | |
7b781c72 PDS |
145 | * @override_divn_shift: shift to the feedback divider bitfield in override reg |
146 | * @override_divm_shift: shift to the input divider bitfield in override reg | |
147 | * @override_divp_shift: shift to the post divider bitfield in override reg | |
aa6fefde PDS |
148 | */ |
149 | struct div_nmp { | |
150 | u8 divn_shift; | |
151 | u8 divn_width; | |
152 | u8 divm_shift; | |
153 | u8 divm_width; | |
154 | u8 divp_shift; | |
155 | u8 divp_width; | |
7b781c72 PDS |
156 | u8 override_divn_shift; |
157 | u8 override_divm_shift; | |
158 | u8 override_divp_shift; | |
aa6fefde PDS |
159 | }; |
160 | ||
56fd27b3 BH |
161 | #define MAX_PLL_MISC_REG_COUNT 6 |
162 | ||
8f8f484b | 163 | /** |
db592c4e | 164 | * struct tegra_clk_pll_params - PLL parameters |
8f8f484b PG |
165 | * |
166 | * @input_min: Minimum input frequency | |
167 | * @input_max: Maximum input frequency | |
168 | * @cf_min: Minimum comparison frequency | |
169 | * @cf_max: Maximum comparison frequency | |
170 | * @vco_min: Minimum VCO frequency | |
171 | * @vco_max: Maximum VCO frequency | |
172 | * @base_reg: PLL base reg offset | |
173 | * @misc_reg: PLL misc reg offset | |
174 | * @lock_reg: PLL lock reg offset | |
db592c4e | 175 | * @lock_mask: Bitmask for PLL lock status |
8f8f484b | 176 | * @lock_enable_bit_idx: Bit index to enable PLL lock |
db592c4e TR |
177 | * @iddq_reg: PLL IDDQ register offset |
178 | * @iddq_bit_idx: Bit index to enable PLL IDDQ | |
fde207eb BH |
179 | * @reset_reg: Register offset of where RESET bit is |
180 | * @reset_bit_idx: Shift of reset bit in reset_reg | |
d907f4b4 RK |
181 | * @sdm_din_reg: Register offset where SDM settings are |
182 | * @sdm_din_mask: Mask of SDM divider bits | |
183 | * @sdm_ctrl_reg: Register offset where SDM enable is | |
184 | * @sdm_ctrl_en_mask: Mask of SDM enable bit | |
db592c4e TR |
185 | * @aux_reg: AUX register offset |
186 | * @dyn_ramp_reg: Dynamic ramp control register offset | |
187 | * @ext_misc_reg: Miscellaneous control register offsets | |
188 | * @pmc_divnm_reg: n, m divider PMC override register offset (PLLM) | |
189 | * @pmc_divp_reg: p divider PMC override register offset (PLLM) | |
190 | * @flags: PLL flags | |
191 | * @stepa_shift: Dynamic ramp step A field shift | |
192 | * @stepb_shift: Dynamic ramp step B field shift | |
8f8f484b | 193 | * @lock_delay: Delay in us if PLL lock is not used |
db592c4e TR |
194 | * @max_p: maximum value for the p divider |
195 | * @pdiv_tohw: mapping of p divider to register values | |
196 | * @div_nmp: offsets and widths on n, m and p fields | |
fdc1fead RK |
197 | * @freq_table: array of frequencies supported by PLL |
198 | * @fixed_rate: PLL rate if it is fixed | |
407254da RK |
199 | * @mdiv_default: Default value for fixed mdiv for this PLL |
200 | * @round_p_to_pdiv: Callback used to round p to the closed pdiv | |
d907f4b4 RK |
201 | * @set_gain: Callback to adjust N div for SDM enabled |
202 | * PLL's based on fractional divider value. | |
407254da RK |
203 | * @calc_rate: Callback used to change how out of table |
204 | * rates (dividers and multipler) are calculated. | |
fdc1fead RK |
205 | * |
206 | * Flags: | |
207 | * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for | |
208 | * PLL locking. If not set it will use lock_delay value to wait. | |
209 | * TEGRA_PLL_HAS_CPCON - This flag indicates that CPCON value needs | |
210 | * to be programmed to change output frequency of the PLL. | |
211 | * TEGRA_PLL_SET_LFCON - This flag indicates that LFCON value needs | |
212 | * to be programmed to change output frequency of the PLL. | |
213 | * TEGRA_PLL_SET_DCCON - This flag indicates that DCCON value needs | |
214 | * to be programmed to change output frequency of the PLL. | |
215 | * TEGRA_PLLU - PLLU has inverted post divider. This flags indicated | |
216 | * that it is PLLU and invert post divider value. | |
217 | * TEGRA_PLLM - PLLM has additional override settings in PMC. This | |
218 | * flag indicates that it is PLLM and use override settings. | |
219 | * TEGRA_PLL_FIXED - We are not supposed to change output frequency | |
220 | * of some plls. | |
221 | * TEGRA_PLLE_CONFIGURE - Configure PLLE when enabling. | |
222 | * TEGRA_PLL_LOCK_MISC - Lock bit is in the misc register instead of the | |
223 | * base register. | |
224 | * TEGRA_PLL_BYPASS - PLL has bypass bit | |
225 | * TEGRA_PLL_HAS_LOCK_ENABLE - PLL has bit to enable lock monitoring | |
407254da RK |
226 | * TEGRA_MDIV_NEW - Switch to new method for calculating fixed mdiv |
227 | * it may be more accurate (especially if SDM present) | |
8f8f484b PG |
228 | */ |
229 | struct tegra_clk_pll_params { | |
230 | unsigned long input_min; | |
231 | unsigned long input_max; | |
232 | unsigned long cf_min; | |
233 | unsigned long cf_max; | |
234 | unsigned long vco_min; | |
235 | unsigned long vco_max; | |
236 | ||
237 | u32 base_reg; | |
238 | u32 misc_reg; | |
239 | u32 lock_reg; | |
3e72771e | 240 | u32 lock_mask; |
8f8f484b | 241 | u32 lock_enable_bit_idx; |
c1d1939c PDS |
242 | u32 iddq_reg; |
243 | u32 iddq_bit_idx; | |
fde207eb BH |
244 | u32 reset_reg; |
245 | u32 reset_bit_idx; | |
d907f4b4 RK |
246 | u32 sdm_din_reg; |
247 | u32 sdm_din_mask; | |
248 | u32 sdm_ctrl_reg; | |
249 | u32 sdm_ctrl_en_mask; | |
c1d1939c PDS |
250 | u32 aux_reg; |
251 | u32 dyn_ramp_reg; | |
56fd27b3 | 252 | u32 ext_misc_reg[MAX_PLL_MISC_REG_COUNT]; |
7b781c72 PDS |
253 | u32 pmc_divnm_reg; |
254 | u32 pmc_divp_reg; | |
ebe142b2 | 255 | u32 flags; |
c1d1939c PDS |
256 | int stepa_shift; |
257 | int stepb_shift; | |
8f8f484b | 258 | int lock_delay; |
0b6525ac | 259 | int max_p; |
385f9adf | 260 | const struct pdiv_map *pdiv_tohw; |
aa6fefde | 261 | struct div_nmp *div_nmp; |
ebe142b2 PDS |
262 | struct tegra_clk_pll_freq_table *freq_table; |
263 | unsigned long fixed_rate; | |
407254da RK |
264 | u16 mdiv_default; |
265 | u32 (*round_p_to_pdiv)(u32 p, u32 *pdiv); | |
d907f4b4 | 266 | void (*set_gain)(struct tegra_clk_pll_freq_table *cfg); |
407254da RK |
267 | int (*calc_rate)(struct clk_hw *hw, |
268 | struct tegra_clk_pll_freq_table *cfg, | |
269 | unsigned long rate, unsigned long parent_rate); | |
8f8f484b PG |
270 | }; |
271 | ||
fdc1fead RK |
272 | #define TEGRA_PLL_USE_LOCK BIT(0) |
273 | #define TEGRA_PLL_HAS_CPCON BIT(1) | |
274 | #define TEGRA_PLL_SET_LFCON BIT(2) | |
275 | #define TEGRA_PLL_SET_DCCON BIT(3) | |
276 | #define TEGRA_PLLU BIT(4) | |
277 | #define TEGRA_PLLM BIT(5) | |
278 | #define TEGRA_PLL_FIXED BIT(6) | |
279 | #define TEGRA_PLLE_CONFIGURE BIT(7) | |
280 | #define TEGRA_PLL_LOCK_MISC BIT(8) | |
281 | #define TEGRA_PLL_BYPASS BIT(9) | |
282 | #define TEGRA_PLL_HAS_LOCK_ENABLE BIT(10) | |
407254da | 283 | #define TEGRA_MDIV_NEW BIT(11) |
fdc1fead | 284 | |
8f8f484b PG |
285 | /** |
286 | * struct tegra_clk_pll - Tegra PLL clock | |
287 | * | |
288 | * @hw: handle between common and hardware-specifix interfaces | |
289 | * @clk_base: address of CAR controller | |
290 | * @pmc: address of PMC, required to read override bits | |
8f8f484b | 291 | * @lock: register lock |
fdc1fead | 292 | * @params: PLL parameters |
8f8f484b PG |
293 | */ |
294 | struct tegra_clk_pll { | |
295 | struct clk_hw hw; | |
296 | void __iomem *clk_base; | |
297 | void __iomem *pmc; | |
8f8f484b | 298 | spinlock_t *lock; |
8f8f484b PG |
299 | struct tegra_clk_pll_params *params; |
300 | }; | |
301 | ||
302 | #define to_clk_pll(_hw) container_of(_hw, struct tegra_clk_pll, hw) | |
303 | ||
88d909be RK |
304 | /** |
305 | * struct tegra_audio_clk_info - Tegra Audio Clk Information | |
306 | * | |
307 | * @name: name for the audio pll | |
308 | * @pll_params: pll_params for audio pll | |
309 | * @clk_id: clk_ids for the audio pll | |
310 | * @parent: name of the parent of the audio pll | |
311 | */ | |
312 | struct tegra_audio_clk_info { | |
313 | char *name; | |
314 | struct tegra_clk_pll_params *pll_params; | |
315 | int clk_id; | |
316 | char *parent; | |
317 | }; | |
318 | ||
8f8f484b PG |
319 | extern const struct clk_ops tegra_clk_pll_ops; |
320 | extern const struct clk_ops tegra_clk_plle_ops; | |
321 | struct clk *tegra_clk_register_pll(const char *name, const char *parent_name, | |
322 | void __iomem *clk_base, void __iomem *pmc, | |
ebe142b2 PDS |
323 | unsigned long flags, struct tegra_clk_pll_params *pll_params, |
324 | spinlock_t *lock); | |
c1d1939c | 325 | |
8f8f484b PG |
326 | struct clk *tegra_clk_register_plle(const char *name, const char *parent_name, |
327 | void __iomem *clk_base, void __iomem *pmc, | |
ebe142b2 PDS |
328 | unsigned long flags, struct tegra_clk_pll_params *pll_params, |
329 | spinlock_t *lock); | |
8f8f484b | 330 | |
c1d1939c PDS |
331 | struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name, |
332 | void __iomem *clk_base, void __iomem *pmc, | |
ebe142b2 | 333 | unsigned long flags, |
c1d1939c | 334 | struct tegra_clk_pll_params *pll_params, |
c1d1939c PDS |
335 | spinlock_t *lock); |
336 | ||
dd322f04 RK |
337 | struct clk *tegra_clk_register_pllxc_tegra210(const char *name, |
338 | const char *parent_name, void __iomem *clk_base, | |
339 | void __iomem *pmc, unsigned long flags, | |
340 | struct tegra_clk_pll_params *pll_params, | |
341 | spinlock_t *lock); | |
342 | ||
c1d1939c PDS |
343 | struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name, |
344 | void __iomem *clk_base, void __iomem *pmc, | |
ebe142b2 | 345 | unsigned long flags, |
c1d1939c | 346 | struct tegra_clk_pll_params *pll_params, |
c1d1939c PDS |
347 | spinlock_t *lock); |
348 | ||
349 | struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name, | |
350 | void __iomem *clk_base, void __iomem *pmc, | |
ebe142b2 | 351 | unsigned long flags, |
c1d1939c | 352 | struct tegra_clk_pll_params *pll_params, |
c1d1939c PDS |
353 | spinlock_t *lock); |
354 | ||
355 | struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name, | |
356 | void __iomem *clk_base, void __iomem *pmc, | |
ebe142b2 | 357 | unsigned long flags, |
c1d1939c | 358 | struct tegra_clk_pll_params *pll_params, |
c1d1939c PDS |
359 | spinlock_t *lock, unsigned long parent_rate); |
360 | ||
361 | struct clk *tegra_clk_register_plle_tegra114(const char *name, | |
362 | const char *parent_name, | |
363 | void __iomem *clk_base, unsigned long flags, | |
c1d1939c | 364 | struct tegra_clk_pll_params *pll_params, |
c1d1939c PDS |
365 | spinlock_t *lock); |
366 | ||
dd322f04 RK |
367 | struct clk *tegra_clk_register_plle_tegra210(const char *name, |
368 | const char *parent_name, | |
369 | void __iomem *clk_base, unsigned long flags, | |
370 | struct tegra_clk_pll_params *pll_params, | |
371 | spinlock_t *lock); | |
372 | ||
373 | struct clk *tegra_clk_register_pllc_tegra210(const char *name, | |
374 | const char *parent_name, void __iomem *clk_base, | |
375 | void __iomem *pmc, unsigned long flags, | |
376 | struct tegra_clk_pll_params *pll_params, | |
377 | spinlock_t *lock); | |
378 | ||
379 | struct clk *tegra_clk_register_pllss_tegra210(const char *name, | |
380 | const char *parent_name, void __iomem *clk_base, | |
381 | unsigned long flags, | |
382 | struct tegra_clk_pll_params *pll_params, | |
383 | spinlock_t *lock); | |
384 | ||
798e910b PDS |
385 | struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name, |
386 | void __iomem *clk_base, unsigned long flags, | |
387 | struct tegra_clk_pll_params *pll_params, | |
388 | spinlock_t *lock); | |
389 | ||
8f8f484b PG |
390 | /** |
391 | * struct tegra_clk_pll_out - PLL divider down clock | |
392 | * | |
393 | * @hw: handle between common and hardware-specific interfaces | |
394 | * @reg: register containing the PLL divider | |
395 | * @enb_bit_idx: bit to enable/disable PLL divider | |
396 | * @rst_bit_idx: bit to reset PLL divider | |
397 | * @lock: register lock | |
398 | * @flags: hardware-specific flags | |
399 | */ | |
400 | struct tegra_clk_pll_out { | |
401 | struct clk_hw hw; | |
402 | void __iomem *reg; | |
403 | u8 enb_bit_idx; | |
404 | u8 rst_bit_idx; | |
405 | spinlock_t *lock; | |
406 | u8 flags; | |
407 | }; | |
408 | ||
409 | #define to_clk_pll_out(_hw) container_of(_hw, struct tegra_clk_pll_out, hw) | |
410 | ||
411 | extern const struct clk_ops tegra_clk_pll_out_ops; | |
412 | struct clk *tegra_clk_register_pll_out(const char *name, | |
413 | const char *parent_name, void __iomem *reg, u8 enb_bit_idx, | |
414 | u8 rst_bit_idx, unsigned long flags, u8 pll_div_flags, | |
415 | spinlock_t *lock); | |
416 | ||
417 | /** | |
418 | * struct tegra_clk_periph_regs - Registers controlling peripheral clock | |
419 | * | |
420 | * @enb_reg: read the enable status | |
421 | * @enb_set_reg: write 1 to enable clock | |
422 | * @enb_clr_reg: write 1 to disable clock | |
423 | * @rst_reg: read the reset status | |
424 | * @rst_set_reg: write 1 to assert the reset of peripheral | |
425 | * @rst_clr_reg: write 1 to deassert the reset of peripheral | |
426 | */ | |
427 | struct tegra_clk_periph_regs { | |
428 | u32 enb_reg; | |
429 | u32 enb_set_reg; | |
430 | u32 enb_clr_reg; | |
431 | u32 rst_reg; | |
432 | u32 rst_set_reg; | |
433 | u32 rst_clr_reg; | |
434 | }; | |
435 | ||
436 | /** | |
437 | * struct tegra_clk_periph_gate - peripheral gate clock | |
438 | * | |
439 | * @magic: magic number to validate type | |
440 | * @hw: handle between common and hardware-specific interfaces | |
441 | * @clk_base: address of CAR controller | |
442 | * @regs: Registers to control the peripheral | |
443 | * @flags: hardware-specific flags | |
444 | * @clk_num: Clock number | |
445 | * @enable_refcnt: array to maintain reference count of the clock | |
446 | * | |
447 | * Flags: | |
448 | * TEGRA_PERIPH_NO_RESET - This flag indicates that reset is not allowed | |
449 | * for this module. | |
450 | * TEGRA_PERIPH_MANUAL_RESET - This flag indicates not to reset module | |
451 | * after clock enable and driver for the module is responsible for | |
452 | * doing reset. | |
453 | * TEGRA_PERIPH_ON_APB - If peripheral is in the APB bus then read the | |
454 | * bus to flush the write operation in apb bus. This flag indicates | |
455 | * that this peripheral is in apb bus. | |
fdcccbd8 | 456 | * TEGRA_PERIPH_WAR_1005168 - Apply workaround for Tegra114 MSENC bug |
8f8f484b PG |
457 | */ |
458 | struct tegra_clk_periph_gate { | |
459 | u32 magic; | |
460 | struct clk_hw hw; | |
461 | void __iomem *clk_base; | |
462 | u8 flags; | |
463 | int clk_num; | |
464 | int *enable_refcnt; | |
465 | struct tegra_clk_periph_regs *regs; | |
466 | }; | |
467 | ||
468 | #define to_clk_periph_gate(_hw) \ | |
469 | container_of(_hw, struct tegra_clk_periph_gate, hw) | |
470 | ||
471 | #define TEGRA_CLK_PERIPH_GATE_MAGIC 0x17760309 | |
472 | ||
473 | #define TEGRA_PERIPH_NO_RESET BIT(0) | |
474 | #define TEGRA_PERIPH_MANUAL_RESET BIT(1) | |
475 | #define TEGRA_PERIPH_ON_APB BIT(2) | |
fdcccbd8 | 476 | #define TEGRA_PERIPH_WAR_1005168 BIT(3) |
5bb9d267 | 477 | #define TEGRA_PERIPH_NO_DIV BIT(4) |
b29f9e92 | 478 | #define TEGRA_PERIPH_NO_GATE BIT(5) |
8f8f484b | 479 | |
8f8f484b PG |
480 | extern const struct clk_ops tegra_clk_periph_gate_ops; |
481 | struct clk *tegra_clk_register_periph_gate(const char *name, | |
482 | const char *parent_name, u8 gate_flags, void __iomem *clk_base, | |
d5ff89a8 | 483 | unsigned long flags, int clk_num, int *enable_refcnt); |
8f8f484b PG |
484 | |
485 | /** | |
486 | * struct clk-periph - peripheral clock | |
487 | * | |
488 | * @magic: magic number to validate type | |
489 | * @hw: handle between common and hardware-specific interfaces | |
490 | * @mux: mux clock | |
491 | * @divider: divider clock | |
492 | * @gate: gate clock | |
493 | * @mux_ops: mux clock ops | |
494 | * @div_ops: divider clock ops | |
495 | * @gate_ops: gate clock ops | |
496 | */ | |
497 | struct tegra_clk_periph { | |
498 | u32 magic; | |
499 | struct clk_hw hw; | |
500 | struct clk_mux mux; | |
501 | struct tegra_clk_frac_div divider; | |
502 | struct tegra_clk_periph_gate gate; | |
503 | ||
504 | const struct clk_ops *mux_ops; | |
505 | const struct clk_ops *div_ops; | |
506 | const struct clk_ops *gate_ops; | |
507 | }; | |
508 | ||
509 | #define to_clk_periph(_hw) container_of(_hw, struct tegra_clk_periph, hw) | |
510 | ||
511 | #define TEGRA_CLK_PERIPH_MAGIC 0x18221223 | |
512 | ||
513 | extern const struct clk_ops tegra_clk_periph_ops; | |
514 | struct clk *tegra_clk_register_periph(const char *name, | |
515 | const char **parent_names, int num_parents, | |
516 | struct tegra_clk_periph *periph, void __iomem *clk_base, | |
a26a0298 | 517 | u32 offset, unsigned long flags); |
8f8f484b PG |
518 | struct clk *tegra_clk_register_periph_nodiv(const char *name, |
519 | const char **parent_names, int num_parents, | |
520 | struct tegra_clk_periph *periph, void __iomem *clk_base, | |
521 | u32 offset); | |
522 | ||
ce4f3313 | 523 | #define TEGRA_CLK_PERIPH(_mux_shift, _mux_mask, _mux_flags, \ |
8f8f484b | 524 | _div_shift, _div_width, _div_frac_width, \ |
343a607c | 525 | _div_flags, _clk_num,\ |
bc44275b | 526 | _gate_flags, _table, _lock) \ |
8f8f484b PG |
527 | { \ |
528 | .mux = { \ | |
529 | .flags = _mux_flags, \ | |
530 | .shift = _mux_shift, \ | |
ce4f3313 PDS |
531 | .mask = _mux_mask, \ |
532 | .table = _table, \ | |
bc44275b | 533 | .lock = _lock, \ |
8f8f484b PG |
534 | }, \ |
535 | .divider = { \ | |
536 | .flags = _div_flags, \ | |
537 | .shift = _div_shift, \ | |
538 | .width = _div_width, \ | |
539 | .frac_width = _div_frac_width, \ | |
bc44275b | 540 | .lock = _lock, \ |
8f8f484b PG |
541 | }, \ |
542 | .gate = { \ | |
543 | .flags = _gate_flags, \ | |
544 | .clk_num = _clk_num, \ | |
8f8f484b PG |
545 | }, \ |
546 | .mux_ops = &clk_mux_ops, \ | |
547 | .div_ops = &tegra_clk_frac_div_ops, \ | |
548 | .gate_ops = &tegra_clk_periph_gate_ops, \ | |
549 | } | |
550 | ||
551 | struct tegra_periph_init_data { | |
552 | const char *name; | |
553 | int clk_id; | |
76ebc134 PDS |
554 | union { |
555 | const char **parent_names; | |
556 | const char *parent_name; | |
557 | } p; | |
8f8f484b PG |
558 | int num_parents; |
559 | struct tegra_clk_periph periph; | |
560 | u32 offset; | |
561 | const char *con_id; | |
562 | const char *dev_id; | |
a26a0298 | 563 | unsigned long flags; |
8f8f484b PG |
564 | }; |
565 | ||
ce4f3313 PDS |
566 | #define TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\ |
567 | _mux_shift, _mux_mask, _mux_flags, _div_shift, \ | |
d5ff89a8 | 568 | _div_width, _div_frac_width, _div_flags, \ |
343a607c | 569 | _clk_num, _gate_flags, _clk_id, _table, \ |
bc44275b | 570 | _flags, _lock) \ |
8f8f484b PG |
571 | { \ |
572 | .name = _name, \ | |
573 | .clk_id = _clk_id, \ | |
76ebc134 | 574 | .p.parent_names = _parent_names, \ |
8f8f484b | 575 | .num_parents = ARRAY_SIZE(_parent_names), \ |
ce4f3313 | 576 | .periph = TEGRA_CLK_PERIPH(_mux_shift, _mux_mask, \ |
8f8f484b PG |
577 | _mux_flags, _div_shift, \ |
578 | _div_width, _div_frac_width, \ | |
579 | _div_flags, _clk_num, \ | |
bc44275b | 580 | _gate_flags, _table, _lock), \ |
8f8f484b PG |
581 | .offset = _offset, \ |
582 | .con_id = _con_id, \ | |
583 | .dev_id = _dev_id, \ | |
a26a0298 | 584 | .flags = _flags \ |
8f8f484b PG |
585 | } |
586 | ||
ce4f3313 PDS |
587 | #define TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parent_names, _offset,\ |
588 | _mux_shift, _mux_width, _mux_flags, _div_shift, \ | |
d5ff89a8 | 589 | _div_width, _div_frac_width, _div_flags, \ |
343a607c | 590 | _clk_num, _gate_flags, _clk_id) \ |
ce4f3313 PDS |
591 | TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\ |
592 | _mux_shift, BIT(_mux_width) - 1, _mux_flags, \ | |
593 | _div_shift, _div_width, _div_frac_width, _div_flags, \ | |
343a607c | 594 | _clk_num, _gate_flags, _clk_id,\ |
bc44275b | 595 | NULL, 0, NULL) |
ce4f3313 | 596 | |
8f8f484b PG |
597 | /** |
598 | * struct clk_super_mux - super clock | |
599 | * | |
600 | * @hw: handle between common and hardware-specific interfaces | |
601 | * @reg: register controlling multiplexer | |
602 | * @width: width of the multiplexer bit field | |
603 | * @flags: hardware-specific flags | |
604 | * @div2_index: bit controlling divide-by-2 | |
605 | * @pllx_index: PLLX index in the parent list | |
606 | * @lock: register lock | |
607 | * | |
608 | * Flags: | |
609 | * TEGRA_DIVIDER_2 - LP cluster has additional divider. This flag indicates | |
610 | * that this is LP cluster clock. | |
611 | */ | |
612 | struct tegra_clk_super_mux { | |
613 | struct clk_hw hw; | |
614 | void __iomem *reg; | |
615 | u8 width; | |
616 | u8 flags; | |
617 | u8 div2_index; | |
618 | u8 pllx_index; | |
619 | spinlock_t *lock; | |
620 | }; | |
621 | ||
622 | #define to_clk_super_mux(_hw) container_of(_hw, struct tegra_clk_super_mux, hw) | |
623 | ||
624 | #define TEGRA_DIVIDER_2 BIT(0) | |
625 | ||
626 | extern const struct clk_ops tegra_clk_super_ops; | |
627 | struct clk *tegra_clk_register_super_mux(const char *name, | |
628 | const char **parent_names, u8 num_parents, | |
629 | unsigned long flags, void __iomem *reg, u8 clk_super_flags, | |
630 | u8 width, u8 pllx_index, u8 div2_index, spinlock_t *lock); | |
631 | ||
632 | /** | |
8106462f | 633 | * struct clk_init_table - clock initialization table |
8f8f484b PG |
634 | * @clk_id: clock id as mentioned in device tree bindings |
635 | * @parent_id: parent clock id as mentioned in device tree bindings | |
636 | * @rate: rate to set | |
637 | * @state: enable/disable | |
638 | */ | |
639 | struct tegra_clk_init_table { | |
640 | unsigned int clk_id; | |
641 | unsigned int parent_id; | |
642 | unsigned long rate; | |
643 | int state; | |
644 | }; | |
645 | ||
646 | /** | |
647 | * struct clk_duplicate - duplicate clocks | |
648 | * @clk_id: clock id as mentioned in device tree bindings | |
649 | * @lookup: duplicate lookup entry for the clock | |
650 | */ | |
651 | struct tegra_clk_duplicate { | |
652 | int clk_id; | |
653 | struct clk_lookup lookup; | |
654 | }; | |
655 | ||
656 | #define TEGRA_CLK_DUPLICATE(_clk_id, _dev, _con) \ | |
657 | { \ | |
658 | .clk_id = _clk_id, \ | |
659 | .lookup = { \ | |
660 | .dev_id = _dev, \ | |
661 | .con_id = _con, \ | |
662 | }, \ | |
663 | } | |
664 | ||
b8700d50 PDS |
665 | struct tegra_clk { |
666 | int dt_id; | |
667 | bool present; | |
668 | }; | |
669 | ||
73d37e4c PDS |
670 | struct tegra_devclk { |
671 | int dt_id; | |
672 | char *dev_id; | |
673 | char *con_id; | |
674 | }; | |
66b6f3d0 MP |
675 | |
676 | void tegra_init_special_resets(unsigned int num, int (*assert)(unsigned long), | |
677 | int (*deassert)(unsigned long)); | |
73d37e4c | 678 | |
8f8f484b PG |
679 | void tegra_init_from_table(struct tegra_clk_init_table *tbl, |
680 | struct clk *clks[], int clk_max); | |
681 | ||
682 | void tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list, | |
683 | struct clk *clks[], int clk_max); | |
684 | ||
d5ff89a8 | 685 | struct tegra_clk_periph_regs *get_reg_bank(int clkid); |
6d5b988e | 686 | struct clk **tegra_clk_init(void __iomem *clk_base, int num, int periph_banks); |
343a607c | 687 | |
b8700d50 PDS |
688 | struct clk **tegra_lookup_dt_id(int clk_id, struct tegra_clk *tegra_clk); |
689 | ||
343a607c | 690 | void tegra_add_of_provider(struct device_node *np); |
73d37e4c | 691 | void tegra_register_devclks(struct tegra_devclk *dev_clks, int num); |
d5ff89a8 | 692 | |
6609dbe4 PDS |
693 | void tegra_audio_clk_init(void __iomem *clk_base, |
694 | void __iomem *pmc_base, struct tegra_clk *tegra_clks, | |
88d909be RK |
695 | struct tegra_audio_clk_info *audio_info, |
696 | unsigned int num_plls); | |
6609dbe4 | 697 | |
76ebc134 PDS |
698 | void tegra_periph_clk_init(void __iomem *clk_base, void __iomem *pmc_base, |
699 | struct tegra_clk *tegra_clks, | |
700 | struct tegra_clk_pll_params *pll_params); | |
701 | ||
de4f30fd PDS |
702 | void tegra_pmc_clk_init(void __iomem *pmc_base, struct tegra_clk *tegra_clks); |
703 | void tegra_fixed_clk_init(struct tegra_clk *tegra_clks); | |
63cc5a4d TR |
704 | int tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks, |
705 | unsigned long *input_freqs, unsigned int num, | |
706 | unsigned int clk_m_div, unsigned long *osc_freq, | |
707 | unsigned long *pll_ref_freq); | |
a7c8485a PDS |
708 | void tegra_super_clk_gen4_init(void __iomem *clk_base, |
709 | void __iomem *pmc_base, struct tegra_clk *tegra_clks, | |
710 | struct tegra_clk_pll_params *pll_params); | |
de4f30fd | 711 | |
31b52ba4 | 712 | #ifdef CONFIG_TEGRA_CLK_EMC |
2db04f16 MP |
713 | struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np, |
714 | spinlock_t *lock); | |
31b52ba4 TR |
715 | #else |
716 | static inline struct clk *tegra_clk_register_emc(void __iomem *base, | |
717 | struct device_node *np, | |
718 | spinlock_t *lock) | |
719 | { | |
720 | return NULL; | |
721 | } | |
722 | #endif | |
2db04f16 | 723 | |
25c9ded6 PW |
724 | void tegra114_clock_tune_cpu_trimmers_high(void); |
725 | void tegra114_clock_tune_cpu_trimmers_low(void); | |
726 | void tegra114_clock_tune_cpu_trimmers_init(void); | |
1c472d8e PW |
727 | void tegra114_clock_assert_dfll_dvco_reset(void); |
728 | void tegra114_clock_deassert_dfll_dvco_reset(void); | |
25c9ded6 | 729 | |
441f199a SW |
730 | typedef void (*tegra_clk_apply_init_table_func)(void); |
731 | extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table; | |
6583a630 | 732 | int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll); |
407254da | 733 | u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate); |
441f199a | 734 | |
8f8f484b | 735 | #endif /* TEGRA_CLK_H */ |