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clk: tegra: Format tables consistently
[linux-2.6-block.git] / drivers / clk / tegra / clk-tegra30.c
CommitLineData
b08e8c0e
PG		 1/*
2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/io.h>
18#include <linux/delay.h>
b08e8c0e
PG		 19#include <linux/clk-provider.h>
20#include <linux/clkdev.h>
21#include <linux/of.h>
22#include <linux/of_address.h>
23#include <linux/clk/tegra.h>
306a7f91 24
7232398a 25#include <soc/tegra/pmc.h>
306a7f91 26
1bf40915 27#include <dt-bindings/clock/tegra30-car.h>
306a7f91 28
b08e8c0e 29#include "clk.h"
1bf40915 30#include "clk-id.h"
b08e8c0e 31
b08e8c0e
PG		 32#define OSC_CTRL 0x50
33#define OSC_CTRL_OSC_FREQ_MASK (0xF<<28)
34#define OSC_CTRL_OSC_FREQ_13MHZ (0X0<<28)
35#define OSC_CTRL_OSC_FREQ_19_2MHZ (0X4<<28)
36#define OSC_CTRL_OSC_FREQ_12MHZ (0X8<<28)
37#define OSC_CTRL_OSC_FREQ_26MHZ (0XC<<28)
38#define OSC_CTRL_OSC_FREQ_16_8MHZ (0X1<<28)
39#define OSC_CTRL_OSC_FREQ_38_4MHZ (0X5<<28)
40#define OSC_CTRL_OSC_FREQ_48MHZ (0X9<<28)
41#define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
42
43#define OSC_CTRL_PLL_REF_DIV_MASK (3<<26)
44#define OSC_CTRL_PLL_REF_DIV_1 (0<<26)
45#define OSC_CTRL_PLL_REF_DIV_2 (1<<26)
46#define OSC_CTRL_PLL_REF_DIV_4 (2<<26)
47
48#define OSC_FREQ_DET 0x58
49#define OSC_FREQ_DET_TRIG BIT(31)
50
51#define OSC_FREQ_DET_STATUS 0x5c
52#define OSC_FREQ_DET_BUSY BIT(31)
53#define OSC_FREQ_DET_CNT_MASK 0xffff
54
55#define CCLKG_BURST_POLICY 0x368
56#define SUPER_CCLKG_DIVIDER 0x36c
57#define CCLKLP_BURST_POLICY 0x370
58#define SUPER_CCLKLP_DIVIDER 0x374
59#define SCLK_BURST_POLICY 0x028
60#define SUPER_SCLK_DIVIDER 0x02c
61
62#define SYSTEM_CLK_RATE 0x030
63
d5ff89a8
PDS		 64#define TEGRA30_CLK_PERIPH_BANKS 5
65
b08e8c0e
PG		 66#define PLLC_BASE 0x80
67#define PLLC_MISC 0x8c
68#define PLLM_BASE 0x90
69#define PLLM_MISC 0x9c
70#define PLLP_BASE 0xa0
71#define PLLP_MISC 0xac
72#define PLLX_BASE 0xe0
73#define PLLX_MISC 0xe4
74#define PLLD_BASE 0xd0
75#define PLLD_MISC 0xdc
76#define PLLD2_BASE 0x4b8
77#define PLLD2_MISC 0x4bc
78#define PLLE_BASE 0xe8
79#define PLLE_MISC 0xec
80#define PLLA_BASE 0xb0
81#define PLLA_MISC 0xbc
82#define PLLU_BASE 0xc0
83#define PLLU_MISC 0xcc
84
85#define PLL_MISC_LOCK_ENABLE 18
86#define PLLDU_MISC_LOCK_ENABLE 22
87#define PLLE_MISC_LOCK_ENABLE 9
88
3e72771e
PDS		 89#define PLL_BASE_LOCK BIT(27)
90#define PLLE_MISC_LOCK BIT(11)
b08e8c0e
PG		 91
92#define PLLE_AUX 0x48c
93#define PLLC_OUT 0x84
94#define PLLM_OUT 0x94
95#define PLLP_OUTA 0xa4
96#define PLLP_OUTB 0xa8
97#define PLLA_OUT 0xb4
98
99#define AUDIO_SYNC_CLK_I2S0 0x4a0
100#define AUDIO_SYNC_CLK_I2S1 0x4a4
101#define AUDIO_SYNC_CLK_I2S2 0x4a8
102#define AUDIO_SYNC_CLK_I2S3 0x4ac
103#define AUDIO_SYNC_CLK_I2S4 0x4b0
104#define AUDIO_SYNC_CLK_SPDIF 0x4b4
105
b08e8c0e 106#define CLK_SOURCE_SPDIF_OUT 0x108
c04bf559 107#define CLK_SOURCE_PWM 0x110
b08e8c0e
PG		 108#define CLK_SOURCE_D_AUDIO 0x3d0
109#define CLK_SOURCE_DAM0 0x3d8
110#define CLK_SOURCE_DAM1 0x3dc
111#define CLK_SOURCE_DAM2 0x3e0
b08e8c0e
PG		 112#define CLK_SOURCE_3D2 0x3b0
113#define CLK_SOURCE_2D 0x15c
b08e8c0e 114#define CLK_SOURCE_HDMI 0x18c
b08e8c0e 115#define CLK_SOURCE_DSIB 0xd0
b08e8c0e 116#define CLK_SOURCE_SE 0x42c
b08e8c0e
PG		 117#define CLK_SOURCE_EMC 0x19c
118
119#define AUDIO_SYNC_DOUBLER 0x49c
120
b08e8c0e
PG		 121#define UTMIP_PLL_CFG2 0x488
122#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6)
123#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
124#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
125#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
126#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
127
128#define UTMIP_PLL_CFG1 0x484
129#define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6)
130#define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
131#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
132#define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
133#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
134
135/* Tegra CPU clock and reset control regs */
136#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c
137#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340
138#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344
139#define TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c
140#define TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470
141
142#define CPU_CLOCK(cpu) (0x1 << (8 + cpu))
143#define CPU_RESET(cpu) (0x1111ul << (cpu))
144
145#define CLK_RESET_CCLK_BURST 0x20
146#define CLK_RESET_CCLK_DIVIDER 0x24
147#define CLK_RESET_PLLX_BASE 0xe0
148#define CLK_RESET_PLLX_MISC 0xe4
149
150#define CLK_RESET_SOURCE_CSITE 0x1d4
151
152#define CLK_RESET_CCLK_BURST_POLICY_SHIFT 28
153#define CLK_RESET_CCLK_RUN_POLICY_SHIFT 4
154#define CLK_RESET_CCLK_IDLE_POLICY_SHIFT 0
155#define CLK_RESET_CCLK_IDLE_POLICY 1
156#define CLK_RESET_CCLK_RUN_POLICY 2
157#define CLK_RESET_CCLK_BURST_POLICY_PLLX 8
158
c09e32bb
PDS		 159/* PLLM override registers */
160#define PMC_PLLM_WB0_OVERRIDE 0x1dc
161
b08e8c0e
PG		 162#ifdef CONFIG_PM_SLEEP
163static struct cpu_clk_suspend_context {
164 u32 pllx_misc;
165 u32 pllx_base;
166
167 u32 cpu_burst;
168 u32 clk_csite_src;
169 u32 cclk_divider;
170} tegra30_cpu_clk_sctx;
171#endif
172
b08e8c0e
PG		 173static void __iomem *clk_base;
174static void __iomem *pmc_base;
175static unsigned long input_freq;
176
b08e8c0e
PG		 177static DEFINE_SPINLOCK(cml_lock);
178static DEFINE_SPINLOCK(pll_d_lock);
4f4f85fa 179static DEFINE_SPINLOCK(emc_lock);
b08e8c0e 180
1bf40915 181#define TEGRA_INIT_DATA_MUX(_name, _parents, _offset, \
d5ff89a8 182 _clk_num, _gate_flags, _clk_id) \
1bf40915 183 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
d5ff89a8 184 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
343a607c 185 _clk_num, _gate_flags, _clk_id)
b08e8c0e 186
1bf40915 187#define TEGRA_INIT_DATA_MUX8(_name, _parents, _offset, \
d5ff89a8 188 _clk_num, _gate_flags, _clk_id) \
1bf40915 189 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
d5ff89a8 190 29, 3, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
343a607c 191 _clk_num, _gate_flags, _clk_id)
b08e8c0e 192
1bf40915 193#define TEGRA_INIT_DATA_INT(_name, _parents, _offset, \
d5ff89a8 194 _clk_num, _gate_flags, _clk_id) \
1bf40915 195 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
252d0d2b 196 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_INT | \
d5ff89a8 197 TEGRA_DIVIDER_ROUND_UP, _clk_num, \
343a607c 198 _gate_flags, _clk_id)
b08e8c0e 199
1bf40915 200#define TEGRA_INIT_DATA_NODIV(_name, _parents, _offset, \
d5ff89a8 201 _mux_shift, _mux_width, _clk_num, \
b08e8c0e 202 _gate_flags, _clk_id) \
1bf40915 203 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
d5ff89a8 204 _mux_shift, _mux_width, 0, 0, 0, 0, 0,\
343a607c 205 _clk_num, _gate_flags, \
b08e8c0e
PG		 206 _clk_id)
207
343a607c 208static struct clk **clks;
b08e8c0e
PG		 209
210/*
211 * Structure defining the fields for USB UTMI clocks Parameters.
212 */
213struct utmi_clk_param {
214 /* Oscillator Frequency in KHz */
215 u32 osc_frequency;
216 /* UTMIP PLL Enable Delay Count */
217 u8 enable_delay_count;
218 /* UTMIP PLL Stable count */
219 u8 stable_count;
220 /* UTMIP PLL Active delay count */
221 u8 active_delay_count;
222 /* UTMIP PLL Xtal frequency count */
223 u8 xtal_freq_count;
224};
225
226static const struct utmi_clk_param utmi_parameters[] = {
8d99704f
TR		 227 {
228 .osc_frequency = 13000000, .enable_delay_count = 0x02,
229 .stable_count = 0x33, .active_delay_count = 0x05,
230 .xtal_freq_count = 0x7f
231 }, {
232 .osc_frequency = 19200000, .enable_delay_count = 0x03,
233 .stable_count = 0x4b, .active_delay_count = 0x06,
234 .xtal_freq_count = 0xbb
235 }, {
236 .osc_frequency = 12000000, .enable_delay_count = 0x02,
237 .stable_count = 0x2f, .active_delay_count = 0x04,
238 .xtal_freq_count = 0x76
239 }, {
240 .osc_frequency = 26000000, .enable_delay_count = 0x04,
241 .stable_count = 0x66, .active_delay_count = 0x09,
242 .xtal_freq_count = 0xfe
243 }, {
244 .osc_frequency = 16800000, .enable_delay_count = 0x03,
245 .stable_count = 0x41, .active_delay_count = 0x0a,
246 .xtal_freq_count = 0xa4
247 },
b08e8c0e
PG		 248};
249
250static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
8d99704f
TR		 251 { 12000000, 1040000000, 520, 6, 0, 8 },
252 { 13000000, 1040000000, 480, 6, 0, 8 },
253 { 16800000, 1040000000, 495, 8, 0, 8 }, /* actual: 1039.5 MHz */
254 { 19200000, 1040000000, 325, 6, 0, 6 },
255 { 26000000, 1040000000, 520, 13, 0, 8 },
256 { 12000000, 832000000, 416, 6, 0, 8 },
257 { 13000000, 832000000, 832, 13, 0, 8 },
258 { 16800000, 832000000, 396, 8, 0, 8 }, /* actual: 831.6 MHz */
259 { 19200000, 832000000, 260, 6, 0, 8 },
260 { 26000000, 832000000, 416, 13, 0, 8 },
261 { 12000000, 624000000, 624, 12, 0, 8 },
262 { 13000000, 624000000, 624, 13, 0, 8 },
263 { 16800000, 600000000, 520, 14, 0, 8 },
264 { 19200000, 624000000, 520, 16, 0, 8 },
265 { 26000000, 624000000, 624, 26, 0, 8 },
266 { 12000000, 600000000, 600, 12, 0, 8 },
267 { 13000000, 600000000, 600, 13, 0, 8 },
268 { 16800000, 600000000, 500, 14, 0, 8 },
269 { 19200000, 600000000, 375, 12, 0, 6 },
270 { 26000000, 600000000, 600, 26, 0, 8 },
271 { 12000000, 520000000, 520, 12, 0, 8 },
272 { 13000000, 520000000, 520, 13, 0, 8 },
273 { 16800000, 520000000, 495, 16, 0, 8 }, /* actual: 519.75 MHz */
274 { 19200000, 520000000, 325, 12, 0, 6 },
275 { 26000000, 520000000, 520, 26, 0, 8 },
276 { 12000000, 416000000, 416, 12, 0, 8 },
277 { 13000000, 416000000, 416, 13, 0, 8 },
278 { 16800000, 416000000, 396, 16, 0, 8 }, /* actual: 415.8 MHz */
279 { 19200000, 416000000, 260, 12, 0, 6 },
280 { 26000000, 416000000, 416, 26, 0, 8 },
281 { 0, 0, 0, 0, 0, 0 },
b08e8c0e
PG		 282};
283
284static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
8d99704f
TR		 285 { 12000000, 666000000, 666, 12, 0, 8 },
286 { 13000000, 666000000, 666, 13, 0, 8 },
287 { 16800000, 666000000, 555, 14, 0, 8 },
288 { 19200000, 666000000, 555, 16, 0, 8 },
289 { 26000000, 666000000, 666, 26, 0, 8 },
290 { 12000000, 600000000, 600, 12, 0, 8 },
291 { 13000000, 600000000, 600, 13, 0, 8 },
292 { 16800000, 600000000, 500, 14, 0, 8 },
293 { 19200000, 600000000, 375, 12, 0, 6 },
294 { 26000000, 600000000, 600, 26, 0, 8 },
295 { 0, 0, 0, 0, 0, 0 },
b08e8c0e
PG		 296};
297
298static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
8d99704f
TR		 299 { 12000000, 216000000, 432, 12, 1, 8 },
300 { 13000000, 216000000, 432, 13, 1, 8 },
301 { 16800000, 216000000, 360, 14, 1, 8 },
302 { 19200000, 216000000, 360, 16, 1, 8 },
303 { 26000000, 216000000, 432, 26, 1, 8 },
304 { 0, 0, 0, 0, 0, 0 },
b08e8c0e
PG		 305};
306
307static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
8d99704f
TR		 308 { 9600000, 564480000, 294, 5, 0, 4 },
309 { 9600000, 552960000, 288, 5, 0, 4 },
310 { 9600000, 24000000, 5, 2, 0, 1 },
311 { 28800000, 56448000, 49, 25, 0, 1 },
312 { 28800000, 73728000, 64, 25, 0, 1 },
313 { 28800000, 24000000, 5, 6, 0, 1 },
314 { 0, 0, 0, 0, 0, 0 },
b08e8c0e
PG		 315};
316
317static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
8d99704f
TR		 318 { 12000000, 216000000, 216, 12, 0, 4 },
319 { 13000000, 216000000, 216, 13, 0, 4 },
320 { 16800000, 216000000, 180, 14, 0, 4 },
321 { 19200000, 216000000, 180, 16, 0, 4 },
322 { 26000000, 216000000, 216, 26, 0, 4 },
323 { 12000000, 594000000, 594, 12, 0, 8 },
324 { 13000000, 594000000, 594, 13, 0, 8 },
325 { 16800000, 594000000, 495, 14, 0, 8 },
326 { 19200000, 594000000, 495, 16, 0, 8 },
327 { 26000000, 594000000, 594, 26, 0, 8 },
328 { 12000000, 1000000000, 1000, 12, 0, 12 },
329 { 13000000, 1000000000, 1000, 13, 0, 12 },
330 { 19200000, 1000000000, 625, 12, 0, 8 },
331 { 26000000, 1000000000, 1000, 26, 0, 12 },
332 { 0, 0, 0, 0, 0, 0 },
b08e8c0e
PG		 333};
334
0b6525ac
PDS		 335static struct pdiv_map pllu_p[] = {
336 { .pdiv = 1, .hw_val = 1 },
337 { .pdiv = 2, .hw_val = 0 },
338 { .pdiv = 0, .hw_val = 0 },
339};
340
b08e8c0e 341static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
8d99704f
TR		 342 { 12000000, 480000000, 960, 12, 0, 12 },
343 { 13000000, 480000000, 960, 13, 0, 12 },
344 { 16800000, 480000000, 400, 7, 0, 5 },
345 { 19200000, 480000000, 200, 4, 0, 3 },
346 { 26000000, 480000000, 960, 26, 0, 12 },
347 { 0, 0, 0, 0, 0, 0 },
b08e8c0e
PG		 348};
349
350static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
351 /* 1.7 GHz */
8d99704f
TR		 352 { 12000000, 1700000000, 850, 6, 0, 8 },
353 { 13000000, 1700000000, 915, 7, 0, 8 }, /* actual: 1699.2 MHz */
354 { 16800000, 1700000000, 708, 7, 0, 8 }, /* actual: 1699.2 MHz */
355 { 19200000, 1700000000, 885, 10, 0, 8 }, /* actual: 1699.2 MHz */
356 { 26000000, 1700000000, 850, 13, 0, 8 },
b08e8c0e 357 /* 1.6 GHz */
8d99704f
TR		 358 { 12000000, 1600000000, 800, 6, 0, 8 },
359 { 13000000, 1600000000, 738, 6, 0, 8 }, /* actual: 1599.0 MHz */
360 { 16800000, 1600000000, 857, 9, 0, 8 }, /* actual: 1599.7 MHz */
361 { 19200000, 1600000000, 500, 6, 0, 8 },
362 { 26000000, 1600000000, 800, 13, 0, 8 },
b08e8c0e 363 /* 1.5 GHz */
8d99704f
TR		 364 { 12000000, 1500000000, 750, 6, 0, 8 },
365 { 13000000, 1500000000, 923, 8, 0, 8 }, /* actual: 1499.8 MHz */
366 { 16800000, 1500000000, 625, 7, 0, 8 },
367 { 19200000, 1500000000, 625, 8, 0, 8 },
368 { 26000000, 1500000000, 750, 13, 0, 8 },
b08e8c0e 369 /* 1.4 GHz */
8d99704f
TR		 370 { 12000000, 1400000000, 700, 6, 0, 8 },
371 { 13000000, 1400000000, 969, 9, 0, 8 }, /* actual: 1399.7 MHz */
372 { 16800000, 1400000000, 1000, 12, 0, 8 },
373 { 19200000, 1400000000, 875, 12, 0, 8 },
374 { 26000000, 1400000000, 700, 13, 0, 8 },
b08e8c0e 375 /* 1.3 GHz */
8d99704f
TR		 376 { 12000000, 1300000000, 975, 9, 0, 8 },
377 { 13000000, 1300000000, 1000, 10, 0, 8 },
378 { 16800000, 1300000000, 928, 12, 0, 8 }, /* actual: 1299.2 MHz */
379 { 19200000, 1300000000, 812, 12, 0, 8 }, /* actual: 1299.2 MHz */
380 { 26000000, 1300000000, 650, 13, 0, 8 },
b08e8c0e 381 /* 1.2 GHz */
8d99704f
TR		 382 { 12000000, 1200000000, 1000, 10, 0, 8 },
383 { 13000000, 1200000000, 923, 10, 0, 8 }, /* actual: 1199.9 MHz */
384 { 16800000, 1200000000, 1000, 14, 0, 8 },
385 { 19200000, 1200000000, 1000, 16, 0, 8 },
386 { 26000000, 1200000000, 600, 13, 0, 8 },
b08e8c0e 387 /* 1.1 GHz */
8d99704f
TR		 388 { 12000000, 1100000000, 825, 9, 0, 8 },
389 { 13000000, 1100000000, 846, 10, 0, 8 }, /* actual: 1099.8 MHz */
390 { 16800000, 1100000000, 982, 15, 0, 8 }, /* actual: 1099.8 MHz */
391 { 19200000, 1100000000, 859, 15, 0, 8 }, /* actual: 1099.5 MHz */
392 { 26000000, 1100000000, 550, 13, 0, 8 },
b08e8c0e 393 /* 1 GHz */
8d99704f
TR		 394 { 12000000, 1000000000, 1000, 12, 0, 8 },
395 { 13000000, 1000000000, 1000, 13, 0, 8 },
396 { 16800000, 1000000000, 833, 14, 0, 8 }, /* actual: 999.6 MHz */
397 { 19200000, 1000000000, 625, 12, 0, 8 },
398 { 26000000, 1000000000, 1000, 26, 0, 8 },
399 { 0, 0, 0, 0, 0, 0 },
b08e8c0e
PG		 400};
401
402static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
403 /* PLLE special case: use cpcon field to store cml divider value */
8d99704f
TR		 404 { 12000000, 100000000, 150, 1, 18, 11 },
405 { 216000000, 100000000, 200, 18, 24, 13 },
406 { 0, 0, 0, 0, 0, 0 },
b08e8c0e
PG		 407};
408
409/* PLL parameters */
410static struct tegra_clk_pll_params pll_c_params = {
411 .input_min = 2000000,
412 .input_max = 31000000,
413 .cf_min = 1000000,
414 .cf_max = 6000000,
415 .vco_min = 20000000,
416 .vco_max = 1400000000,
417 .base_reg = PLLC_BASE,
418 .misc_reg = PLLC_MISC,
3e72771e 419 .lock_mask = PLL_BASE_LOCK,
b08e8c0e
PG		 420 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
421 .lock_delay = 300,
ebe142b2
PDS		 422 .freq_table = pll_c_freq_table,
423 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK,
b08e8c0e
PG		 424};
425
c09e32bb
PDS		 426static struct div_nmp pllm_nmp = {
427 .divn_shift = 8,
428 .divn_width = 10,
429 .override_divn_shift = 5,
430 .divm_shift = 0,
431 .divm_width = 5,
432 .override_divm_shift = 0,
433 .divp_shift = 20,
434 .divp_width = 3,
435 .override_divp_shift = 15,
436};
437
b08e8c0e
PG		 438static struct tegra_clk_pll_params pll_m_params = {
439 .input_min = 2000000,
440 .input_max = 31000000,
441 .cf_min = 1000000,
442 .cf_max = 6000000,
443 .vco_min = 20000000,
444 .vco_max = 1200000000,
445 .base_reg = PLLM_BASE,
446 .misc_reg = PLLM_MISC,
3e72771e 447 .lock_mask = PLL_BASE_LOCK,
b08e8c0e
PG		 448 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
449 .lock_delay = 300,
c09e32bb
PDS		 450 .div_nmp = &pllm_nmp,
451 .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
452 .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE,
ebe142b2
PDS		 453 .freq_table = pll_m_freq_table,
454 .flags = TEGRA_PLLM | TEGRA_PLL_HAS_CPCON |
455 TEGRA_PLL_SET_DCCON | TEGRA_PLL_USE_LOCK,
b08e8c0e
PG		 456};
457
458static struct tegra_clk_pll_params pll_p_params = {
459 .input_min = 2000000,
460 .input_max = 31000000,
461 .cf_min = 1000000,
462 .cf_max = 6000000,
463 .vco_min = 20000000,
464 .vco_max = 1400000000,
465 .base_reg = PLLP_BASE,
466 .misc_reg = PLLP_MISC,
3e72771e 467 .lock_mask = PLL_BASE_LOCK,
b08e8c0e
PG		 468 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
469 .lock_delay = 300,
ebe142b2
PDS		 470 .freq_table = pll_p_freq_table,
471 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK,
472 .fixed_rate = 408000000,
b08e8c0e
PG		 473};
474
475static struct tegra_clk_pll_params pll_a_params = {
476 .input_min = 2000000,
477 .input_max = 31000000,
478 .cf_min = 1000000,
479 .cf_max = 6000000,
480 .vco_min = 20000000,
481 .vco_max = 1400000000,
482 .base_reg = PLLA_BASE,
483 .misc_reg = PLLA_MISC,
3e72771e 484 .lock_mask = PLL_BASE_LOCK,
b08e8c0e
PG		 485 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
486 .lock_delay = 300,
ebe142b2
PDS		 487 .freq_table = pll_a_freq_table,
488 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK,
b08e8c0e
PG		 489};
490
491static struct tegra_clk_pll_params pll_d_params = {
492 .input_min = 2000000,
493 .input_max = 40000000,
494 .cf_min = 1000000,
495 .cf_max = 6000000,
496 .vco_min = 40000000,
497 .vco_max = 1000000000,
498 .base_reg = PLLD_BASE,
499 .misc_reg = PLLD_MISC,
3e72771e 500 .lock_mask = PLL_BASE_LOCK,
b08e8c0e
PG		 501 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
502 .lock_delay = 1000,
ebe142b2
PDS		 503 .freq_table = pll_d_freq_table,
504 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
505 TEGRA_PLL_USE_LOCK,
b08e8c0e
PG		 506};
507
508static struct tegra_clk_pll_params pll_d2_params = {
509 .input_min = 2000000,
510 .input_max = 40000000,
511 .cf_min = 1000000,
512 .cf_max = 6000000,
513 .vco_min = 40000000,
514 .vco_max = 1000000000,
515 .base_reg = PLLD2_BASE,
516 .misc_reg = PLLD2_MISC,
3e72771e 517 .lock_mask = PLL_BASE_LOCK,
b08e8c0e
PG		 518 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
519 .lock_delay = 1000,
ebe142b2
PDS		 520 .freq_table = pll_d_freq_table,
521 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
522 TEGRA_PLL_USE_LOCK,
b08e8c0e
PG		 523};
524
525static struct tegra_clk_pll_params pll_u_params = {
526 .input_min = 2000000,
527 .input_max = 40000000,
528 .cf_min = 1000000,
529 .cf_max = 6000000,
530 .vco_min = 48000000,
531 .vco_max = 960000000,
532 .base_reg = PLLU_BASE,
533 .misc_reg = PLLU_MISC,
3e72771e 534 .lock_mask = PLL_BASE_LOCK,
b08e8c0e
PG		 535 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
536 .lock_delay = 1000,
0b6525ac 537 .pdiv_tohw = pllu_p,
ebe142b2
PDS		 538 .freq_table = pll_u_freq_table,
539 .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON,
b08e8c0e
PG		 540};
541
542static struct tegra_clk_pll_params pll_x_params = {
543 .input_min = 2000000,
544 .input_max = 31000000,
545 .cf_min = 1000000,
546 .cf_max = 6000000,
547 .vco_min = 20000000,
548 .vco_max = 1700000000,
549 .base_reg = PLLX_BASE,
550 .misc_reg = PLLX_MISC,
3e72771e 551 .lock_mask = PLL_BASE_LOCK,
b08e8c0e
PG		 552 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
553 .lock_delay = 300,
ebe142b2
PDS		 554 .freq_table = pll_x_freq_table,
555 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_DCCON |
556 TEGRA_PLL_USE_LOCK,
b08e8c0e
PG		 557};
558
559static struct tegra_clk_pll_params pll_e_params = {
560 .input_min = 12000000,
561 .input_max = 216000000,
562 .cf_min = 12000000,
563 .cf_max = 12000000,
564 .vco_min = 1200000000,
565 .vco_max = 2400000000U,
566 .base_reg = PLLE_BASE,
567 .misc_reg = PLLE_MISC,
3e72771e 568 .lock_mask = PLLE_MISC_LOCK,
b08e8c0e
PG		 569 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
570 .lock_delay = 300,
ebe142b2
PDS		 571 .freq_table = pll_e_freq_table,
572 .flags = TEGRA_PLLE_CONFIGURE | TEGRA_PLL_FIXED,
573 .fixed_rate = 100000000,
b08e8c0e
PG		 574};
575
1bf40915 576static unsigned long tegra30_input_freq[] = {
8d99704f
TR		 577 [ 0] = 13000000,
578 [ 1] = 16800000,
579 [ 4] = 19200000,
580 [ 5] = 38400000,
581 [ 8] = 12000000,
582 [ 9] = 48000000,
c4947e36 583 [12] = 26000000,
1bf40915 584};
b08e8c0e 585
1bf40915
PDS		 586static struct tegra_devclk devclks[] __initdata = {
587 { .con_id = "pll_c", .dt_id = TEGRA30_CLK_PLL_C },
588 { .con_id = "pll_c_out1", .dt_id = TEGRA30_CLK_PLL_C_OUT1 },
589 { .con_id = "pll_p", .dt_id = TEGRA30_CLK_PLL_P },
590 { .con_id = "pll_p_out1", .dt_id = TEGRA30_CLK_PLL_P_OUT1 },
591 { .con_id = "pll_p_out2", .dt_id = TEGRA30_CLK_PLL_P_OUT2 },
592 { .con_id = "pll_p_out3", .dt_id = TEGRA30_CLK_PLL_P_OUT3 },
593 { .con_id = "pll_p_out4", .dt_id = TEGRA30_CLK_PLL_P_OUT4 },
594 { .con_id = "pll_m", .dt_id = TEGRA30_CLK_PLL_M },
595 { .con_id = "pll_m_out1", .dt_id = TEGRA30_CLK_PLL_M_OUT1 },
596 { .con_id = "pll_x", .dt_id = TEGRA30_CLK_PLL_X },
597 { .con_id = "pll_x_out0", .dt_id = TEGRA30_CLK_PLL_X_OUT0 },
598 { .con_id = "pll_u", .dt_id = TEGRA30_CLK_PLL_U },
599 { .con_id = "pll_d", .dt_id = TEGRA30_CLK_PLL_D },
600 { .con_id = "pll_d_out0", .dt_id = TEGRA30_CLK_PLL_D_OUT0 },
601 { .con_id = "pll_d2", .dt_id = TEGRA30_CLK_PLL_D2 },
602 { .con_id = "pll_d2_out0", .dt_id = TEGRA30_CLK_PLL_D2_OUT0 },
603 { .con_id = "pll_a", .dt_id = TEGRA30_CLK_PLL_A },
604 { .con_id = "pll_a_out0", .dt_id = TEGRA30_CLK_PLL_A_OUT0 },
605 { .con_id = "pll_e", .dt_id = TEGRA30_CLK_PLL_E },
606 { .con_id = "spdif_in_sync", .dt_id = TEGRA30_CLK_SPDIF_IN_SYNC },
607 { .con_id = "i2s0_sync", .dt_id = TEGRA30_CLK_I2S0_SYNC },
608 { .con_id = "i2s1_sync", .dt_id = TEGRA30_CLK_I2S1_SYNC },
609 { .con_id = "i2s2_sync", .dt_id = TEGRA30_CLK_I2S2_SYNC },
610 { .con_id = "i2s3_sync", .dt_id = TEGRA30_CLK_I2S3_SYNC },
611 { .con_id = "i2s4_sync", .dt_id = TEGRA30_CLK_I2S4_SYNC },
612 { .con_id = "vimclk_sync", .dt_id = TEGRA30_CLK_VIMCLK_SYNC },
613 { .con_id = "audio0", .dt_id = TEGRA30_CLK_AUDIO0 },
614 { .con_id = "audio1", .dt_id = TEGRA30_CLK_AUDIO1 },
615 { .con_id = "audio2", .dt_id = TEGRA30_CLK_AUDIO2 },
616 { .con_id = "audio3", .dt_id = TEGRA30_CLK_AUDIO3 },
617 { .con_id = "audio4", .dt_id = TEGRA30_CLK_AUDIO4 },
618 { .con_id = "spdif", .dt_id = TEGRA30_CLK_SPDIF },
619 { .con_id = "audio0_2x", .dt_id = TEGRA30_CLK_AUDIO0_2X },
620 { .con_id = "audio1_2x", .dt_id = TEGRA30_CLK_AUDIO1_2X },
621 { .con_id = "audio2_2x", .dt_id = TEGRA30_CLK_AUDIO2_2X },
622 { .con_id = "audio3_2x", .dt_id = TEGRA30_CLK_AUDIO3_2X },
623 { .con_id = "audio4_2x", .dt_id = TEGRA30_CLK_AUDIO4_2X },
624 { .con_id = "spdif_2x", .dt_id = TEGRA30_CLK_SPDIF_2X },
625 { .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA30_CLK_EXTERN1 },
626 { .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA30_CLK_EXTERN2 },
627 { .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA30_CLK_EXTERN3 },
628 { .con_id = "blink", .dt_id = TEGRA30_CLK_BLINK },
629 { .con_id = "cclk_g", .dt_id = TEGRA30_CLK_CCLK_G },
630 { .con_id = "cclk_lp", .dt_id = TEGRA30_CLK_CCLK_LP },
631 { .con_id = "sclk", .dt_id = TEGRA30_CLK_SCLK },
632 { .con_id = "hclk", .dt_id = TEGRA30_CLK_HCLK },
633 { .con_id = "pclk", .dt_id = TEGRA30_CLK_PCLK },
634 { .con_id = "twd", .dt_id = TEGRA30_CLK_TWD },
635 { .con_id = "emc", .dt_id = TEGRA30_CLK_EMC },
636 { .con_id = "clk_32k", .dt_id = TEGRA30_CLK_CLK_32K },
637 { .con_id = "clk_m_div2", .dt_id = TEGRA30_CLK_CLK_M_DIV2 },
638 { .con_id = "clk_m_div4", .dt_id = TEGRA30_CLK_CLK_M_DIV4 },
639 { .con_id = "cml0", .dt_id = TEGRA30_CLK_CML0 },
640 { .con_id = "cml1", .dt_id = TEGRA30_CLK_CML1 },
641 { .con_id = "clk_m", .dt_id = TEGRA30_CLK_CLK_M },
642 { .con_id = "pll_ref", .dt_id = TEGRA30_CLK_PLL_REF },
643 { .con_id = "csus", .dev_id = "tengra_camera", .dt_id = TEGRA30_CLK_CSUS },
644 { .con_id = "vcp", .dev_id = "tegra-avp", .dt_id = TEGRA30_CLK_VCP },
645 { .con_id = "bsea", .dev_id = "tegra-avp", .dt_id = TEGRA30_CLK_BSEA },
646 { .con_id = "bsev", .dev_id = "tegra-aes", .dt_id = TEGRA30_CLK_BSEV },
647 { .con_id = "dsia", .dev_id = "tegradc.0", .dt_id = TEGRA30_CLK_DSIA },
648 { .con_id = "csi", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_CSI },
649 { .con_id = "isp", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_ISP },
650 { .con_id = "pcie", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_PCIE },
651 { .con_id = "afi", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_AFI },
5ab5d404 652 { .con_id = "fuse", .dt_id = TEGRA30_CLK_FUSE },
1bf40915
PDS		 653 { .con_id = "fuse_burn", .dev_id = "fuse-tegra", .dt_id = TEGRA30_CLK_FUSE_BURN },
654 { .con_id = "apbif", .dev_id = "tegra30-ahub", .dt_id = TEGRA30_CLK_APBIF },
655 { .con_id = "hda2hdmi", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA2HDMI },
12cf33c0
TR		 656 { .dev_id = "tegra-apbdma", .dt_id = TEGRA30_CLK_APBDMA },
657 { .dev_id = "rtc-tegra", .dt_id = TEGRA30_CLK_RTC },
658 { .dev_id = "timer", .dt_id = TEGRA30_CLK_TIMER },
659 { .dev_id = "tegra-kbc", .dt_id = TEGRA30_CLK_KBC },
660 { .dev_id = "fsl-tegra-udc", .dt_id = TEGRA30_CLK_USBD },
661 { .dev_id = "tegra-ehci.1", .dt_id = TEGRA30_CLK_USB2 },
662 { .dev_id = "tegra-ehci.2", .dt_id = TEGRA30_CLK_USB2 },
663 { .dev_id = "kfuse-tegra", .dt_id = TEGRA30_CLK_KFUSE },
664 { .dev_id = "tegra_sata_cold", .dt_id = TEGRA30_CLK_SATA_COLD },
665 { .dev_id = "dtv", .dt_id = TEGRA30_CLK_DTV },
1bf40915
PDS		 666 { .dev_id = "tegra30-i2s.0", .dt_id = TEGRA30_CLK_I2S0 },
667 { .dev_id = "tegra30-i2s.1", .dt_id = TEGRA30_CLK_I2S1 },
668 { .dev_id = "tegra30-i2s.2", .dt_id = TEGRA30_CLK_I2S2 },
669 { .dev_id = "tegra30-i2s.3", .dt_id = TEGRA30_CLK_I2S3 },
670 { .dev_id = "tegra30-i2s.4", .dt_id = TEGRA30_CLK_I2S4 },
671 { .con_id = "spdif_out", .dev_id = "tegra30-spdif", .dt_id = TEGRA30_CLK_SPDIF_OUT },
672 { .con_id = "spdif_in", .dev_id = "tegra30-spdif", .dt_id = TEGRA30_CLK_SPDIF_IN },
673 { .con_id = "d_audio", .dev_id = "tegra30-ahub", .dt_id = TEGRA30_CLK_D_AUDIO },
674 { .dev_id = "tegra30-dam.0", .dt_id = TEGRA30_CLK_DAM0 },
675 { .dev_id = "tegra30-dam.1", .dt_id = TEGRA30_CLK_DAM1 },
676 { .dev_id = "tegra30-dam.2", .dt_id = TEGRA30_CLK_DAM2 },
677 { .con_id = "hda", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA },
36b7be6d 678 { .con_id = "hda2codec_2x", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA2CODEC_2X },
1bf40915
PDS		 679 { .dev_id = "spi_tegra.0", .dt_id = TEGRA30_CLK_SBC1 },
680 { .dev_id = "spi_tegra.1", .dt_id = TEGRA30_CLK_SBC2 },
681 { .dev_id = "spi_tegra.2", .dt_id = TEGRA30_CLK_SBC3 },
682 { .dev_id = "spi_tegra.3", .dt_id = TEGRA30_CLK_SBC4 },
683 { .dev_id = "spi_tegra.4", .dt_id = TEGRA30_CLK_SBC5 },
684 { .dev_id = "spi_tegra.5", .dt_id = TEGRA30_CLK_SBC6 },
685 { .dev_id = "tegra_sata_oob", .dt_id = TEGRA30_CLK_SATA_OOB },
686 { .dev_id = "tegra_sata", .dt_id = TEGRA30_CLK_SATA },
687 { .dev_id = "tegra_nand", .dt_id = TEGRA30_CLK_NDFLASH },
688 { .dev_id = "tegra_nand_speed", .dt_id = TEGRA30_CLK_NDSPEED },
689 { .dev_id = "vfir", .dt_id = TEGRA30_CLK_VFIR },
690 { .dev_id = "csite", .dt_id = TEGRA30_CLK_CSITE },
691 { .dev_id = "la", .dt_id = TEGRA30_CLK_LA },
692 { .dev_id = "tegra_w1", .dt_id = TEGRA30_CLK_OWR },
693 { .dev_id = "mipi", .dt_id = TEGRA30_CLK_MIPI },
694 { .dev_id = "tegra-tsensor", .dt_id = TEGRA30_CLK_TSENSOR },
695 { .dev_id = "i2cslow", .dt_id = TEGRA30_CLK_I2CSLOW },
696 { .dev_id = "vde", .dt_id = TEGRA30_CLK_VDE },
697 { .con_id = "vi", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_VI },
698 { .dev_id = "epp", .dt_id = TEGRA30_CLK_EPP },
699 { .dev_id = "mpe", .dt_id = TEGRA30_CLK_MPE },
700 { .dev_id = "host1x", .dt_id = TEGRA30_CLK_HOST1X },
701 { .dev_id = "3d", .dt_id = TEGRA30_CLK_GR3D },
702 { .dev_id = "3d2", .dt_id = TEGRA30_CLK_GR3D2 },
703 { .dev_id = "2d", .dt_id = TEGRA30_CLK_GR2D },
704 { .dev_id = "se", .dt_id = TEGRA30_CLK_SE },
705 { .dev_id = "mselect", .dt_id = TEGRA30_CLK_MSELECT },
706 { .dev_id = "tegra-nor", .dt_id = TEGRA30_CLK_NOR },
707 { .dev_id = "sdhci-tegra.0", .dt_id = TEGRA30_CLK_SDMMC1 },
708 { .dev_id = "sdhci-tegra.1", .dt_id = TEGRA30_CLK_SDMMC2 },
709 { .dev_id = "sdhci-tegra.2", .dt_id = TEGRA30_CLK_SDMMC3 },
710 { .dev_id = "sdhci-tegra.3", .dt_id = TEGRA30_CLK_SDMMC4 },
711 { .dev_id = "cve", .dt_id = TEGRA30_CLK_CVE },
712 { .dev_id = "tvo", .dt_id = TEGRA30_CLK_TVO },
713 { .dev_id = "tvdac", .dt_id = TEGRA30_CLK_TVDAC },
714 { .dev_id = "actmon", .dt_id = TEGRA30_CLK_ACTMON },
715 { .con_id = "vi_sensor", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_VI_SENSOR },
716 { .con_id = "div-clk", .dev_id = "tegra-i2c.0", .dt_id = TEGRA30_CLK_I2C1 },
717 { .con_id = "div-clk", .dev_id = "tegra-i2c.1", .dt_id = TEGRA30_CLK_I2C2 },
718 { .con_id = "div-clk", .dev_id = "tegra-i2c.2", .dt_id = TEGRA30_CLK_I2C3 },
719 { .con_id = "div-clk", .dev_id = "tegra-i2c.3", .dt_id = TEGRA30_CLK_I2C4 },
720 { .con_id = "div-clk", .dev_id = "tegra-i2c.4", .dt_id = TEGRA30_CLK_I2C5 },
721 { .dev_id = "tegra_uart.0", .dt_id = TEGRA30_CLK_UARTA },
722 { .dev_id = "tegra_uart.1", .dt_id = TEGRA30_CLK_UARTB },
723 { .dev_id = "tegra_uart.2", .dt_id = TEGRA30_CLK_UARTC },
724 { .dev_id = "tegra_uart.3", .dt_id = TEGRA30_CLK_UARTD },
725 { .dev_id = "tegra_uart.4", .dt_id = TEGRA30_CLK_UARTE },
726 { .dev_id = "hdmi", .dt_id = TEGRA30_CLK_HDMI },
727 { .dev_id = "extern1", .dt_id = TEGRA30_CLK_EXTERN1 },
728 { .dev_id = "extern2", .dt_id = TEGRA30_CLK_EXTERN2 },
729 { .dev_id = "extern3", .dt_id = TEGRA30_CLK_EXTERN3 },
730 { .dev_id = "pwm", .dt_id = TEGRA30_CLK_PWM },
731 { .dev_id = "tegradc.0", .dt_id = TEGRA30_CLK_DISP1 },
732 { .dev_id = "tegradc.1", .dt_id = TEGRA30_CLK_DISP2 },
733 { .dev_id = "tegradc.1", .dt_id = TEGRA30_CLK_DSIB },
734};
735
736static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = {
737 [tegra_clk_clk_32k] = { .dt_id = TEGRA30_CLK_CLK_32K, .present = true },
738 [tegra_clk_clk_m] = { .dt_id = TEGRA30_CLK_CLK_M, .present = true },
739 [tegra_clk_clk_m_div2] = { .dt_id = TEGRA30_CLK_CLK_M_DIV2, .present = true },
740 [tegra_clk_clk_m_div4] = { .dt_id = TEGRA30_CLK_CLK_M_DIV4, .present = true },
741 [tegra_clk_pll_ref] = { .dt_id = TEGRA30_CLK_PLL_REF, .present = true },
742 [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA30_CLK_SPDIF_IN_SYNC, .present = true },
743 [tegra_clk_i2s0_sync] = { .dt_id = TEGRA30_CLK_I2S0_SYNC, .present = true },
744 [tegra_clk_i2s1_sync] = { .dt_id = TEGRA30_CLK_I2S1_SYNC, .present = true },
745 [tegra_clk_i2s2_sync] = { .dt_id = TEGRA30_CLK_I2S2_SYNC, .present = true },
746 [tegra_clk_i2s3_sync] = { .dt_id = TEGRA30_CLK_I2S3_SYNC, .present = true },
747 [tegra_clk_i2s4_sync] = { .dt_id = TEGRA30_CLK_I2S4_SYNC, .present = true },
748 [tegra_clk_vimclk_sync] = { .dt_id = TEGRA30_CLK_VIMCLK_SYNC, .present = true },
749 [tegra_clk_audio0] = { .dt_id = TEGRA30_CLK_AUDIO0, .present = true },
750 [tegra_clk_audio1] = { .dt_id = TEGRA30_CLK_AUDIO1, .present = true },
751 [tegra_clk_audio2] = { .dt_id = TEGRA30_CLK_AUDIO2, .present = true },
752 [tegra_clk_audio3] = { .dt_id = TEGRA30_CLK_AUDIO3, .present = true },
753 [tegra_clk_audio4] = { .dt_id = TEGRA30_CLK_AUDIO4, .present = true },
754 [tegra_clk_spdif] = { .dt_id = TEGRA30_CLK_SPDIF, .present = true },
755 [tegra_clk_audio0_mux] = { .dt_id = TEGRA30_CLK_AUDIO0_MUX, .present = true },
756 [tegra_clk_audio1_mux] = { .dt_id = TEGRA30_CLK_AUDIO1_MUX, .present = true },
757 [tegra_clk_audio2_mux] = { .dt_id = TEGRA30_CLK_AUDIO2_MUX, .present = true },
758 [tegra_clk_audio3_mux] = { .dt_id = TEGRA30_CLK_AUDIO3_MUX, .present = true },
759 [tegra_clk_audio4_mux] = { .dt_id = TEGRA30_CLK_AUDIO4_MUX, .present = true },
760 [tegra_clk_spdif_mux] = { .dt_id = TEGRA30_CLK_SPDIF_MUX, .present = true },
761 [tegra_clk_audio0_2x] = { .dt_id = TEGRA30_CLK_AUDIO0_2X, .present = true },
762 [tegra_clk_audio1_2x] = { .dt_id = TEGRA30_CLK_AUDIO1_2X, .present = true },
763 [tegra_clk_audio2_2x] = { .dt_id = TEGRA30_CLK_AUDIO2_2X, .present = true },
764 [tegra_clk_audio3_2x] = { .dt_id = TEGRA30_CLK_AUDIO3_2X, .present = true },
765 [tegra_clk_audio4_2x] = { .dt_id = TEGRA30_CLK_AUDIO4_2X, .present = true },
766 [tegra_clk_spdif_2x] = { .dt_id = TEGRA30_CLK_SPDIF_2X, .present = true },
767 [tegra_clk_clk_out_1] = { .dt_id = TEGRA30_CLK_CLK_OUT_1, .present = true },
768 [tegra_clk_clk_out_2] = { .dt_id = TEGRA30_CLK_CLK_OUT_2, .present = true },
769 [tegra_clk_clk_out_3] = { .dt_id = TEGRA30_CLK_CLK_OUT_3, .present = true },
770 [tegra_clk_blink] = { .dt_id = TEGRA30_CLK_BLINK, .present = true },
771 [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA30_CLK_CLK_OUT_1_MUX, .present = true },
772 [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA30_CLK_CLK_OUT_2_MUX, .present = true },
773 [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA30_CLK_CLK_OUT_3_MUX, .present = true },
774 [tegra_clk_hclk] = { .dt_id = TEGRA30_CLK_HCLK, .present = true },
775 [tegra_clk_pclk] = { .dt_id = TEGRA30_CLK_PCLK, .present = true },
776 [tegra_clk_i2s0] = { .dt_id = TEGRA30_CLK_I2S0, .present = true },
777 [tegra_clk_i2s1] = { .dt_id = TEGRA30_CLK_I2S1, .present = true },
778 [tegra_clk_i2s2] = { .dt_id = TEGRA30_CLK_I2S2, .present = true },
779 [tegra_clk_i2s3] = { .dt_id = TEGRA30_CLK_I2S3, .present = true },
780 [tegra_clk_i2s4] = { .dt_id = TEGRA30_CLK_I2S4, .present = true },
781 [tegra_clk_spdif_in] = { .dt_id = TEGRA30_CLK_SPDIF_IN, .present = true },
782 [tegra_clk_hda] = { .dt_id = TEGRA30_CLK_HDA, .present = true },
783 [tegra_clk_hda2codec_2x] = { .dt_id = TEGRA30_CLK_HDA2CODEC_2X, .present = true },
784 [tegra_clk_sbc1] = { .dt_id = TEGRA30_CLK_SBC1, .present = true },
785 [tegra_clk_sbc2] = { .dt_id = TEGRA30_CLK_SBC2, .present = true },
786 [tegra_clk_sbc3] = { .dt_id = TEGRA30_CLK_SBC3, .present = true },
787 [tegra_clk_sbc4] = { .dt_id = TEGRA30_CLK_SBC4, .present = true },
788 [tegra_clk_sbc5] = { .dt_id = TEGRA30_CLK_SBC5, .present = true },
789 [tegra_clk_sbc6] = { .dt_id = TEGRA30_CLK_SBC6, .present = true },
790 [tegra_clk_ndflash] = { .dt_id = TEGRA30_CLK_NDFLASH, .present = true },
791 [tegra_clk_ndspeed] = { .dt_id = TEGRA30_CLK_NDSPEED, .present = true },
792 [tegra_clk_vfir] = { .dt_id = TEGRA30_CLK_VFIR, .present = true },
793 [tegra_clk_la] = { .dt_id = TEGRA30_CLK_LA, .present = true },
794 [tegra_clk_csite] = { .dt_id = TEGRA30_CLK_CSITE, .present = true },
795 [tegra_clk_owr] = { .dt_id = TEGRA30_CLK_OWR, .present = true },
796 [tegra_clk_mipi] = { .dt_id = TEGRA30_CLK_MIPI, .present = true },
797 [tegra_clk_tsensor] = { .dt_id = TEGRA30_CLK_TSENSOR, .present = true },
798 [tegra_clk_i2cslow] = { .dt_id = TEGRA30_CLK_I2CSLOW, .present = true },
799 [tegra_clk_vde] = { .dt_id = TEGRA30_CLK_VDE, .present = true },
800 [tegra_clk_vi] = { .dt_id = TEGRA30_CLK_VI, .present = true },
801 [tegra_clk_epp] = { .dt_id = TEGRA30_CLK_EPP, .present = true },
802 [tegra_clk_mpe] = { .dt_id = TEGRA30_CLK_MPE, .present = true },
803 [tegra_clk_host1x] = { .dt_id = TEGRA30_CLK_HOST1X, .present = true },
804 [tegra_clk_gr2d] = { .dt_id = TEGRA30_CLK_GR2D, .present = true },
805 [tegra_clk_gr3d] = { .dt_id = TEGRA30_CLK_GR3D, .present = true },
806 [tegra_clk_mselect] = { .dt_id = TEGRA30_CLK_MSELECT, .present = true },
807 [tegra_clk_nor] = { .dt_id = TEGRA30_CLK_NOR, .present = true },
808 [tegra_clk_sdmmc1] = { .dt_id = TEGRA30_CLK_SDMMC1, .present = true },
809 [tegra_clk_sdmmc2] = { .dt_id = TEGRA30_CLK_SDMMC2, .present = true },
810 [tegra_clk_sdmmc3] = { .dt_id = TEGRA30_CLK_SDMMC3, .present = true },
811 [tegra_clk_sdmmc4] = { .dt_id = TEGRA30_CLK_SDMMC4, .present = true },
812 [tegra_clk_cve] = { .dt_id = TEGRA30_CLK_CVE, .present = true },
813 [tegra_clk_tvo] = { .dt_id = TEGRA30_CLK_TVO, .present = true },
814 [tegra_clk_tvdac] = { .dt_id = TEGRA30_CLK_TVDAC, .present = true },
815 [tegra_clk_actmon] = { .dt_id = TEGRA30_CLK_ACTMON, .present = true },
816 [tegra_clk_vi_sensor] = { .dt_id = TEGRA30_CLK_VI_SENSOR, .present = true },
817 [tegra_clk_i2c1] = { .dt_id = TEGRA30_CLK_I2C1, .present = true },
818 [tegra_clk_i2c2] = { .dt_id = TEGRA30_CLK_I2C2, .present = true },
819 [tegra_clk_i2c3] = { .dt_id = TEGRA30_CLK_I2C3, .present = true },
820 [tegra_clk_i2c4] = { .dt_id = TEGRA30_CLK_I2C4, .present = true },
821 [tegra_clk_i2c5] = { .dt_id = TEGRA30_CLK_I2C5, .present = true },
822 [tegra_clk_uarta] = { .dt_id = TEGRA30_CLK_UARTA, .present = true },
823 [tegra_clk_uartb] = { .dt_id = TEGRA30_CLK_UARTB, .present = true },
824 [tegra_clk_uartc] = { .dt_id = TEGRA30_CLK_UARTC, .present = true },
825 [tegra_clk_uartd] = { .dt_id = TEGRA30_CLK_UARTD, .present = true },
826 [tegra_clk_uarte] = { .dt_id = TEGRA30_CLK_UARTE, .present = true },
827 [tegra_clk_extern1] = { .dt_id = TEGRA30_CLK_EXTERN1, .present = true },
828 [tegra_clk_extern2] = { .dt_id = TEGRA30_CLK_EXTERN2, .present = true },
829 [tegra_clk_extern3] = { .dt_id = TEGRA30_CLK_EXTERN3, .present = true },
1bf40915
PDS		 830 [tegra_clk_disp1] = { .dt_id = TEGRA30_CLK_DISP1, .present = true },
831 [tegra_clk_disp2] = { .dt_id = TEGRA30_CLK_DISP2, .present = true },
832 [tegra_clk_apbdma] = { .dt_id = TEGRA30_CLK_APBDMA, .present = true },
833 [tegra_clk_rtc] = { .dt_id = TEGRA30_CLK_RTC, .present = true },
834 [tegra_clk_timer] = { .dt_id = TEGRA30_CLK_TIMER, .present = true },
835 [tegra_clk_kbc] = { .dt_id = TEGRA30_CLK_KBC, .present = true },
836 [tegra_clk_csus] = { .dt_id = TEGRA30_CLK_CSUS, .present = true },
837 [tegra_clk_vcp] = { .dt_id = TEGRA30_CLK_VCP, .present = true },
838 [tegra_clk_bsea] = { .dt_id = TEGRA30_CLK_BSEA, .present = true },
839 [tegra_clk_bsev] = { .dt_id = TEGRA30_CLK_BSEV, .present = true },
840 [tegra_clk_usbd] = { .dt_id = TEGRA30_CLK_USBD, .present = true },
841 [tegra_clk_usb2] = { .dt_id = TEGRA30_CLK_USB2, .present = true },
842 [tegra_clk_usb3] = { .dt_id = TEGRA30_CLK_USB3, .present = true },
843 [tegra_clk_csi] = { .dt_id = TEGRA30_CLK_CSI, .present = true },
844 [tegra_clk_isp] = { .dt_id = TEGRA30_CLK_ISP, .present = true },
845 [tegra_clk_kfuse] = { .dt_id = TEGRA30_CLK_KFUSE, .present = true },
846 [tegra_clk_fuse] = { .dt_id = TEGRA30_CLK_FUSE, .present = true },
847 [tegra_clk_fuse_burn] = { .dt_id = TEGRA30_CLK_FUSE_BURN, .present = true },
848 [tegra_clk_apbif] = { .dt_id = TEGRA30_CLK_APBIF, .present = true },
849 [tegra_clk_hda2hdmi] = { .dt_id = TEGRA30_CLK_HDA2HDMI, .present = true },
850 [tegra_clk_sata_cold] = { .dt_id = TEGRA30_CLK_SATA_COLD, .present = true },
851 [tegra_clk_sata_oob] = { .dt_id = TEGRA30_CLK_SATA_OOB, .present = true },
852 [tegra_clk_sata] = { .dt_id = TEGRA30_CLK_SATA, .present = true },
853 [tegra_clk_dtv] = { .dt_id = TEGRA30_CLK_DTV, .present = true },
854 [tegra_clk_pll_p] = { .dt_id = TEGRA30_CLK_PLL_P, .present = true },
855 [tegra_clk_pll_p_out1] = { .dt_id = TEGRA30_CLK_PLL_P_OUT1, .present = true },
856 [tegra_clk_pll_p_out2] = { .dt_id = TEGRA30_CLK_PLL_P_OUT2, .present = true },
857 [tegra_clk_pll_p_out3] = { .dt_id = TEGRA30_CLK_PLL_P_OUT3, .present = true },
858 [tegra_clk_pll_p_out4] = { .dt_id = TEGRA30_CLK_PLL_P_OUT4, .present = true },
859 [tegra_clk_pll_a] = { .dt_id = TEGRA30_CLK_PLL_A, .present = true },
860 [tegra_clk_pll_a_out0] = { .dt_id = TEGRA30_CLK_PLL_A_OUT0, .present = true },
1bf40915 861};
b08e8c0e
PG		 862
863static void tegra30_utmi_param_configure(void)
864{
e52d7c04 865 unsigned int i;
b08e8c0e 866 u32 reg;
b08e8c0e
PG		 867
868 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
869 if (input_freq == utmi_parameters[i].osc_frequency)
870 break;
871 }
872
873 if (i >= ARRAY_SIZE(utmi_parameters)) {
874 pr_err("%s: Unexpected input rate %lu\n", __func__, input_freq);
875 return;
876 }
877
878 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
879
880 /* Program UTMIP PLL stable and active counts */
881 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
882 reg |= UTMIP_PLL_CFG2_STABLE_COUNT(
883 utmi_parameters[i].stable_count);
884
885 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
886
887 reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(
888 utmi_parameters[i].active_delay_count);
889
890 /* Remove power downs from UTMIP PLL control bits */
891 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
892 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
893 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
894
895 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
896
897 /* Program UTMIP PLL delay and oscillator frequency counts */
898 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
899 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
900
901 reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(
902 utmi_parameters[i].enable_delay_count);
903
904 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
905 reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(
906 utmi_parameters[i].xtal_freq_count);
907
908 /* Remove power downs from UTMIP PLL control bits */
909 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
910 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
911 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
912
913 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
914}
915
8d99704f 916static const char *pll_e_parents[] = { "pll_ref", "pll_p" };
b08e8c0e
PG		 917
918static void __init tegra30_pll_init(void)
919{
920 struct clk *clk;
921
922 /* PLLC */
923 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0,
e52d7c04 924 &pll_c_params, NULL);
1bf40915 925 clks[TEGRA30_CLK_PLL_C] = clk;
b08e8c0e
PG		 926
927 /* PLLC_OUT1 */
928 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
929 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
930 8, 8, 1, NULL);
931 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
932 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT,
933 0, NULL);
1bf40915 934 clks[TEGRA30_CLK_PLL_C_OUT1] = clk;
b08e8c0e
PG		 935
936 /* PLLM */
937 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, pmc_base,
ebe142b2
PDS		 938 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
939 &pll_m_params, NULL);
1bf40915 940 clks[TEGRA30_CLK_PLL_M] = clk;
b08e8c0e
PG		 941
942 /* PLLM_OUT1 */
943 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
944 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
945 8, 8, 1, NULL);
946 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
947 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
948 CLK_SET_RATE_PARENT, 0, NULL);
1bf40915 949 clks[TEGRA30_CLK_PLL_M_OUT1] = clk;
b08e8c0e
PG		 950
951 /* PLLX */
952 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, pmc_base, 0,
ebe142b2 953 &pll_x_params, NULL);
1bf40915 954 clks[TEGRA30_CLK_PLL_X] = clk;
b08e8c0e
PG		 955
956 /* PLLX_OUT0 */
957 clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x",
958 CLK_SET_RATE_PARENT, 1, 2);
1bf40915 959 clks[TEGRA30_CLK_PLL_X_OUT0] = clk;
b08e8c0e
PG		 960
961 /* PLLU */
962 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc_base, 0,
ebe142b2 963 &pll_u_params, NULL);
1bf40915 964 clks[TEGRA30_CLK_PLL_U] = clk;
b08e8c0e
PG		 965
966 tegra30_utmi_param_configure();
967
968 /* PLLD */
969 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc_base, 0,
ebe142b2 970 &pll_d_params, &pll_d_lock);
1bf40915 971 clks[TEGRA30_CLK_PLL_D] = clk;
b08e8c0e
PG		 972
973 /* PLLD_OUT0 */
974 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
975 CLK_SET_RATE_PARENT, 1, 2);
1bf40915 976 clks[TEGRA30_CLK_PLL_D_OUT0] = clk;
b08e8c0e
PG		 977
978 /* PLLD2 */
979 clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc_base, 0,
ebe142b2 980 &pll_d2_params, NULL);
1bf40915 981 clks[TEGRA30_CLK_PLL_D2] = clk;
b08e8c0e
PG		 982
983 /* PLLD2_OUT0 */
984 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
985 CLK_SET_RATE_PARENT, 1, 2);
1bf40915 986 clks[TEGRA30_CLK_PLL_D2_OUT0] = clk;
b08e8c0e
PG		 987
988 /* PLLE */
989 clk = clk_register_mux(NULL, "pll_e_mux", pll_e_parents,
819c1de3
JH		 990 ARRAY_SIZE(pll_e_parents),
991 CLK_SET_RATE_NO_REPARENT,
b08e8c0e
PG		 992 clk_base + PLLE_AUX, 2, 1, 0, NULL);
993 clk = tegra_clk_register_plle("pll_e", "pll_e_mux", clk_base, pmc_base,
ebe142b2 994 CLK_GET_RATE_NOCACHE, &pll_e_params, NULL);
1bf40915 995 clks[TEGRA30_CLK_PLL_E] = clk;
b08e8c0e
PG		 996}
997
b4c154a3
PDS		 998static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
999 "pll_p_cclkg", "pll_p_out4_cclkg",
1000 "pll_p_out3_cclkg", "unused", "pll_x" };
1001static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
1002 "pll_p_cclklp", "pll_p_out4_cclklp",
1003 "pll_p_out3_cclklp", "unused", "pll_x",
1004 "pll_x_out0" };
1005static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
1006 "pll_p_out3", "pll_p_out2", "unused",
1007 "clk_32k", "pll_m_out1" };
b08e8c0e
PG		 1008
1009static void __init tegra30_super_clk_init(void)
1010{
1011 struct clk *clk;
1012
1013 /*
1014 * Clock input to cclk_g divided from pll_p using
1015 * U71 divider of cclk_g.
1016 */
1017 clk = tegra_clk_register_divider("pll_p_cclkg", "pll_p",
1018 clk_base + SUPER_CCLKG_DIVIDER, 0,
1019 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1020 clk_register_clkdev(clk, "pll_p_cclkg", NULL);
1021
1022 /*
1023 * Clock input to cclk_g divided from pll_p_out3 using
1024 * U71 divider of cclk_g.
1025 */
1026 clk = tegra_clk_register_divider("pll_p_out3_cclkg", "pll_p_out3",
1027 clk_base + SUPER_CCLKG_DIVIDER, 0,
1028 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1029 clk_register_clkdev(clk, "pll_p_out3_cclkg", NULL);
1030
1031 /*
1032 * Clock input to cclk_g divided from pll_p_out4 using
1033 * U71 divider of cclk_g.
1034 */
1035 clk = tegra_clk_register_divider("pll_p_out4_cclkg", "pll_p_out4",
1036 clk_base + SUPER_CCLKG_DIVIDER, 0,
1037 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1038 clk_register_clkdev(clk, "pll_p_out4_cclkg", NULL);
1039
1040 /* CCLKG */
1041 clk = tegra_clk_register_super_mux("cclk_g", cclk_g_parents,
1042 ARRAY_SIZE(cclk_g_parents),
1043 CLK_SET_RATE_PARENT,
1044 clk_base + CCLKG_BURST_POLICY,
1045 0, 4, 0, 0, NULL);
1bf40915 1046 clks[TEGRA30_CLK_CCLK_G] = clk;
b08e8c0e
PG		 1047
1048 /*
1049 * Clock input to cclk_lp divided from pll_p using
1050 * U71 divider of cclk_lp.
1051 */
1052 clk = tegra_clk_register_divider("pll_p_cclklp", "pll_p",
1053 clk_base + SUPER_CCLKLP_DIVIDER, 0,
1054 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1055 clk_register_clkdev(clk, "pll_p_cclklp", NULL);
1056
1057 /*
1058 * Clock input to cclk_lp divided from pll_p_out3 using
1059 * U71 divider of cclk_lp.
1060 */
1061 clk = tegra_clk_register_divider("pll_p_out3_cclklp", "pll_p_out3",
1062 clk_base + SUPER_CCLKG_DIVIDER, 0,
1063 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1064 clk_register_clkdev(clk, "pll_p_out3_cclklp", NULL);
1065
1066 /*
1067 * Clock input to cclk_lp divided from pll_p_out4 using
1068 * U71 divider of cclk_lp.
1069 */
1070 clk = tegra_clk_register_divider("pll_p_out4_cclklp", "pll_p_out4",
1071 clk_base + SUPER_CCLKLP_DIVIDER, 0,
1072 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1073 clk_register_clkdev(clk, "pll_p_out4_cclklp", NULL);
1074
1075 /* CCLKLP */
1076 clk = tegra_clk_register_super_mux("cclk_lp", cclk_lp_parents,
1077 ARRAY_SIZE(cclk_lp_parents),
1078 CLK_SET_RATE_PARENT,
1079 clk_base + CCLKLP_BURST_POLICY,
1080 TEGRA_DIVIDER_2, 4, 8, 9,
1081 NULL);
1bf40915 1082 clks[TEGRA30_CLK_CCLK_LP] = clk;
b08e8c0e
PG		 1083
1084 /* SCLK */
1085 clk = tegra_clk_register_super_mux("sclk", sclk_parents,
1086 ARRAY_SIZE(sclk_parents),
1087 CLK_SET_RATE_PARENT,
1088 clk_base + SCLK_BURST_POLICY,
1089 0, 4, 0, 0, NULL);
1bf40915 1090 clks[TEGRA30_CLK_SCLK] = clk;
b08e8c0e
PG		 1091
1092 /* twd */
1093 clk = clk_register_fixed_factor(NULL, "twd", "cclk_g",
1094 CLK_SET_RATE_PARENT, 1, 2);
1bf40915
PDS		 1095 clks[TEGRA30_CLK_TWD] = clk;
1096
1097 tegra_super_clk_gen4_init(clk_base, pmc_base, tegra30_clks, NULL);
b08e8c0e
PG		 1098}
1099
1100static const char *mux_pllacp_clkm[] = { "pll_a_out0", "unused", "pll_p",
1101 "clk_m" };
1102static const char *mux_pllpcm_clkm[] = { "pll_p", "pll_c", "pll_m", "clk_m" };
1103static const char *mux_pllmcp_clkm[] = { "pll_m", "pll_c", "pll_p", "clk_m" };
b08e8c0e
PG		 1104static const char *spdif_out_parents[] = { "pll_a_out0", "spdif_2x", "pll_p",
1105 "clk_m" };
b08e8c0e 1106static const char *mux_pllmcpa[] = { "pll_m", "pll_c", "pll_p", "pll_a_out0" };
b08e8c0e
PG		 1107static const char *mux_pllpmdacd2_clkm[] = { "pll_p", "pll_m", "pll_d_out0",
1108 "pll_a_out0", "pll_c",
1109 "pll_d2_out0", "clk_m" };
b08e8c0e
PG		 1110static const char *mux_plld_out0_plld2_out0[] = { "pll_d_out0",
1111 "pll_d2_out0" };
c04bf559 1112static const char *pwm_parents[] = { "pll_p", "pll_c", "clk_32k", "clk_m" };
b08e8c0e
PG		 1113
1114static struct tegra_periph_init_data tegra_periph_clk_list[] = {
1bf40915
PDS		 1115 TEGRA_INIT_DATA_MUX("spdif_out", spdif_out_parents, CLK_SOURCE_SPDIF_OUT, 10, TEGRA_PERIPH_ON_APB, TEGRA30_CLK_SPDIF_OUT),
1116 TEGRA_INIT_DATA_MUX("d_audio", mux_pllacp_clkm, CLK_SOURCE_D_AUDIO, 106, 0, TEGRA30_CLK_D_AUDIO),
1117 TEGRA_INIT_DATA_MUX("dam0", mux_pllacp_clkm, CLK_SOURCE_DAM0, 108, 0, TEGRA30_CLK_DAM0),
1118 TEGRA_INIT_DATA_MUX("dam1", mux_pllacp_clkm, CLK_SOURCE_DAM1, 109, 0, TEGRA30_CLK_DAM1),
1119 TEGRA_INIT_DATA_MUX("dam2", mux_pllacp_clkm, CLK_SOURCE_DAM2, 110, 0, TEGRA30_CLK_DAM2),
1120 TEGRA_INIT_DATA_INT("3d2", mux_pllmcpa, CLK_SOURCE_3D2, 98, TEGRA_PERIPH_MANUAL_RESET, TEGRA30_CLK_GR3D2),
1121 TEGRA_INIT_DATA_INT("se", mux_pllpcm_clkm, CLK_SOURCE_SE, 127, 0, TEGRA30_CLK_SE),
1122 TEGRA_INIT_DATA_MUX8("hdmi", mux_pllpmdacd2_clkm, CLK_SOURCE_HDMI, 51, 0, TEGRA30_CLK_HDMI),
c04bf559 1123 TEGRA_INIT_DATA("pwm", NULL, NULL, pwm_parents, CLK_SOURCE_PWM, 28, 2, 0, 0, 8, 1, 0, 17, TEGRA_PERIPH_ON_APB, TEGRA30_CLK_PWM),
b08e8c0e
PG		 1124};
1125
1126static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = {
1bf40915 1127 TEGRA_INIT_DATA_NODIV("dsib", mux_plld_out0_plld2_out0, CLK_SOURCE_DSIB, 25, 1, 82, 0, TEGRA30_CLK_DSIB),
b08e8c0e
PG		 1128};
1129
1130static void __init tegra30_periph_clk_init(void)
1131{
1132 struct tegra_periph_init_data *data;
1133 struct clk *clk;
e52d7c04 1134 unsigned int i;
b08e8c0e 1135
b08e8c0e
PG		 1136 /* dsia */
1137 clk = tegra_clk_register_periph_gate("dsia", "pll_d_out0", 0, clk_base,
d5ff89a8 1138 0, 48, periph_clk_enb_refcnt);
1bf40915 1139 clks[TEGRA30_CLK_DSIA] = clk;
b08e8c0e
PG		 1140
1141 /* pcie */
1142 clk = tegra_clk_register_periph_gate("pcie", "clk_m", 0, clk_base, 0,
d5ff89a8 1143 70, periph_clk_enb_refcnt);
1bf40915 1144 clks[TEGRA30_CLK_PCIE] = clk;
b08e8c0e
PG		 1145
1146 /* afi */
1147 clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72,
d5ff89a8 1148 periph_clk_enb_refcnt);
1bf40915 1149 clks[TEGRA30_CLK_AFI] = clk;
b08e8c0e 1150
b08e8c0e
PG		 1151 /* emc */
1152 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
819c1de3
JH		 1153 ARRAY_SIZE(mux_pllmcp_clkm),
1154 CLK_SET_RATE_NO_REPARENT,
b08e8c0e 1155 clk_base + CLK_SOURCE_EMC,
4f4f85fa 1156 30, 2, 0, &emc_lock);
b08e8c0e 1157 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0,
d5ff89a8 1158 57, periph_clk_enb_refcnt);
1bf40915
PDS		 1159 clks[TEGRA30_CLK_EMC] = clk;
1160
4f4f85fa
TR		 1161 clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,
1162 &emc_lock);
1163 clks[TEGRA30_CLK_MC] = clk;
1164
1bf40915
PDS		 1165 /* cml0 */
1166 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
1167 0, 0, &cml_lock);
1168 clks[TEGRA30_CLK_CML0] = clk;
1169
1170 /* cml1 */
1171 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,
1172 1, 0, &cml_lock);
1173 clks[TEGRA30_CLK_CML1] = clk;
b08e8c0e 1174
b08e8c0e
PG		 1175 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
1176 data = &tegra_periph_clk_list[i];
76ebc134 1177 clk = tegra_clk_register_periph(data->name, data->p.parent_names,
b08e8c0e 1178 data->num_parents, &data->periph,
a26a0298 1179 clk_base, data->offset, data->flags);
b08e8c0e
PG		 1180 clks[data->clk_id] = clk;
1181 }
1182
1183 for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) {
1184 data = &tegra_periph_nodiv_clk_list[i];
1185 clk = tegra_clk_register_periph_nodiv(data->name,
76ebc134 1186 data->p.parent_names,
b08e8c0e
PG		 1187 data->num_parents, &data->periph,
1188 clk_base, data->offset);
b08e8c0e
PG		 1189 clks[data->clk_id] = clk;
1190 }
b08e8c0e 1191
1bf40915 1192 tegra_periph_clk_init(clk_base, pmc_base, tegra30_clks, &pll_p_params);
b08e8c0e
PG		 1193}
1194
1195/* Tegra30 CPU clock and reset control functions */
1196static void tegra30_wait_cpu_in_reset(u32 cpu)
1197{
1198 unsigned int reg;
1199
1200 do {
1201 reg = readl(clk_base +
1202 TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
1203 cpu_relax();
1204 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */
1205
1206 return;
1207}
1208
1209static void tegra30_put_cpu_in_reset(u32 cpu)
1210{
1211 writel(CPU_RESET(cpu),
1212 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
1213 dmb();
1214}
1215
1216static void tegra30_cpu_out_of_reset(u32 cpu)
1217{
1218 writel(CPU_RESET(cpu),
1219 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
1220 wmb();
1221}
1222
b08e8c0e
PG		 1223static void tegra30_enable_cpu_clock(u32 cpu)
1224{
1225 unsigned int reg;
1226
1227 writel(CPU_CLOCK(cpu),
1228 clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
1229 reg = readl(clk_base +
1230 TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
1231}
1232
1233static void tegra30_disable_cpu_clock(u32 cpu)
1234{
b08e8c0e
PG		 1235 unsigned int reg;
1236
1237 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1238 writel(reg | CPU_CLOCK(cpu),
1239 clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1240}
1241
1242#ifdef CONFIG_PM_SLEEP
1243static bool tegra30_cpu_rail_off_ready(void)
1244{
1245 unsigned int cpu_rst_status;
1246 int cpu_pwr_status;
1247
1248 cpu_rst_status = readl(clk_base +
1249 TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
1250 cpu_pwr_status = tegra_powergate_is_powered(TEGRA_POWERGATE_CPU1) ||
1251 tegra_powergate_is_powered(TEGRA_POWERGATE_CPU2) ||
1252 tegra_powergate_is_powered(TEGRA_POWERGATE_CPU3);
1253
1254 if (((cpu_rst_status & 0xE) != 0xE) || cpu_pwr_status)
1255 return false;
1256
1257 return true;
1258}
1259
1260static void tegra30_cpu_clock_suspend(void)
1261{
1262 /* switch coresite to clk_m, save off original source */
1263 tegra30_cpu_clk_sctx.clk_csite_src =
1264 readl(clk_base + CLK_RESET_SOURCE_CSITE);
e52d7c04 1265 writel(3 << 30, clk_base + CLK_RESET_SOURCE_CSITE);
b08e8c0e
PG		 1266
1267 tegra30_cpu_clk_sctx.cpu_burst =
1268 readl(clk_base + CLK_RESET_CCLK_BURST);
1269 tegra30_cpu_clk_sctx.pllx_base =
1270 readl(clk_base + CLK_RESET_PLLX_BASE);
1271 tegra30_cpu_clk_sctx.pllx_misc =
1272 readl(clk_base + CLK_RESET_PLLX_MISC);
1273 tegra30_cpu_clk_sctx.cclk_divider =
1274 readl(clk_base + CLK_RESET_CCLK_DIVIDER);
1275}
1276
1277static void tegra30_cpu_clock_resume(void)
1278{
1279 unsigned int reg, policy;
1280
1281 /* Is CPU complex already running on PLLX? */
1282 reg = readl(clk_base + CLK_RESET_CCLK_BURST);
1283 policy = (reg >> CLK_RESET_CCLK_BURST_POLICY_SHIFT) & 0xF;
1284
1285 if (policy == CLK_RESET_CCLK_IDLE_POLICY)
1286 reg = (reg >> CLK_RESET_CCLK_IDLE_POLICY_SHIFT) & 0xF;
1287 else if (policy == CLK_RESET_CCLK_RUN_POLICY)
1288 reg = (reg >> CLK_RESET_CCLK_RUN_POLICY_SHIFT) & 0xF;
1289 else
1290 BUG();
1291
1292 if (reg != CLK_RESET_CCLK_BURST_POLICY_PLLX) {
1293 /* restore PLLX settings if CPU is on different PLL */
1294 writel(tegra30_cpu_clk_sctx.pllx_misc,
1295 clk_base + CLK_RESET_PLLX_MISC);
1296 writel(tegra30_cpu_clk_sctx.pllx_base,
1297 clk_base + CLK_RESET_PLLX_BASE);
1298
1299 /* wait for PLL stabilization if PLLX was enabled */
1300 if (tegra30_cpu_clk_sctx.pllx_base & (1 << 30))
1301 udelay(300);
1302 }
1303
1304 /*
1305 * Restore original burst policy setting for calls resulting from CPU
1306 * LP2 in idle or system suspend.
1307 */
1308 writel(tegra30_cpu_clk_sctx.cclk_divider,
1309 clk_base + CLK_RESET_CCLK_DIVIDER);
1310 writel(tegra30_cpu_clk_sctx.cpu_burst,
1311 clk_base + CLK_RESET_CCLK_BURST);
1312
1313 writel(tegra30_cpu_clk_sctx.clk_csite_src,
1314 clk_base + CLK_RESET_SOURCE_CSITE);
1315}
1316#endif
1317
1318static struct tegra_cpu_car_ops tegra30_cpu_car_ops = {
1319 .wait_for_reset = tegra30_wait_cpu_in_reset,
1320 .put_in_reset = tegra30_put_cpu_in_reset,
1321 .out_of_reset = tegra30_cpu_out_of_reset,
1322 .enable_clock = tegra30_enable_cpu_clock,
1323 .disable_clock = tegra30_disable_cpu_clock,
1324#ifdef CONFIG_PM_SLEEP
1325 .rail_off_ready = tegra30_cpu_rail_off_ready,
1326 .suspend = tegra30_cpu_clock_suspend,
1327 .resume = tegra30_cpu_clock_resume,
1328#endif
1329};
1330
4c3b2404 1331static struct tegra_clk_init_table init_table[] __initdata = {
8d99704f
TR		 1332 { TEGRA30_CLK_UARTA, TEGRA30_CLK_PLL_P, 408000000, 0 },
1333 { TEGRA30_CLK_UARTB, TEGRA30_CLK_PLL_P, 408000000, 0 },
1334 { TEGRA30_CLK_UARTC, TEGRA30_CLK_PLL_P, 408000000, 0 },
1335 { TEGRA30_CLK_UARTD, TEGRA30_CLK_PLL_P, 408000000, 0 },
1336 { TEGRA30_CLK_UARTE, TEGRA30_CLK_PLL_P, 408000000, 0 },
1337 { TEGRA30_CLK_PLL_A, TEGRA30_CLK_CLK_MAX, 564480000, 1 },
1338 { TEGRA30_CLK_PLL_A_OUT0, TEGRA30_CLK_CLK_MAX, 11289600, 1 },
1339 { TEGRA30_CLK_EXTERN1, TEGRA30_CLK_PLL_A_OUT0, 0, 1 },
1340 { TEGRA30_CLK_CLK_OUT_1_MUX, TEGRA30_CLK_EXTERN1, 0, 0 },
1341 { TEGRA30_CLK_CLK_OUT_1, TEGRA30_CLK_CLK_MAX, 0, 1 },
1342 { TEGRA30_CLK_BLINK, TEGRA30_CLK_CLK_MAX, 0, 1 },
1343 { TEGRA30_CLK_I2S0, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
1344 { TEGRA30_CLK_I2S1, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
1345 { TEGRA30_CLK_I2S2, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
1346 { TEGRA30_CLK_I2S3, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
1347 { TEGRA30_CLK_I2S4, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
1348 { TEGRA30_CLK_SDMMC1, TEGRA30_CLK_PLL_P, 48000000, 0 },
1349 { TEGRA30_CLK_SDMMC2, TEGRA30_CLK_PLL_P, 48000000, 0 },
1350 { TEGRA30_CLK_SDMMC3, TEGRA30_CLK_PLL_P, 48000000, 0 },
1351 { TEGRA30_CLK_PLL_M, TEGRA30_CLK_CLK_MAX, 0, 1 },
1352 { TEGRA30_CLK_PCLK, TEGRA30_CLK_CLK_MAX, 0, 1 },
1353 { TEGRA30_CLK_CSITE, TEGRA30_CLK_CLK_MAX, 0, 1 },
1354 { TEGRA30_CLK_EMC, TEGRA30_CLK_CLK_MAX, 0, 1 },
1355 { TEGRA30_CLK_MSELECT, TEGRA30_CLK_CLK_MAX, 0, 1 },
1356 { TEGRA30_CLK_SBC1, TEGRA30_CLK_PLL_P, 100000000, 0 },
1357 { TEGRA30_CLK_SBC2, TEGRA30_CLK_PLL_P, 100000000, 0 },
1358 { TEGRA30_CLK_SBC3, TEGRA30_CLK_PLL_P, 100000000, 0 },
1359 { TEGRA30_CLK_SBC4, TEGRA30_CLK_PLL_P, 100000000, 0 },
1360 { TEGRA30_CLK_SBC5, TEGRA30_CLK_PLL_P, 100000000, 0 },
1361 { TEGRA30_CLK_SBC6, TEGRA30_CLK_PLL_P, 100000000, 0 },
1362 { TEGRA30_CLK_HOST1X, TEGRA30_CLK_PLL_C, 150000000, 0 },
1363 { TEGRA30_CLK_DISP1, TEGRA30_CLK_PLL_P, 600000000, 0 },
1364 { TEGRA30_CLK_DISP2, TEGRA30_CLK_PLL_P, 600000000, 0 },
1365 { TEGRA30_CLK_TWD, TEGRA30_CLK_CLK_MAX, 0, 1 },
1366 { TEGRA30_CLK_GR2D, TEGRA30_CLK_PLL_C, 300000000, 0 },
1367 { TEGRA30_CLK_GR3D, TEGRA30_CLK_PLL_C, 300000000, 0 },
1368 { TEGRA30_CLK_GR3D2, TEGRA30_CLK_PLL_C, 300000000, 0 },
1369 /* must be the last entry */
1370 { TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0 },
b08e8c0e
PG		 1371};
1372
441f199a
SW		 1373static void __init tegra30_clock_apply_init_table(void)
1374{
1bf40915 1375 tegra_init_from_table(init_table, clks, TEGRA30_CLK_CLK_MAX);
441f199a
SW		 1376}
1377
b08e8c0e
PG		 1378/*
1379 * Some clocks may be used by different drivers depending on the board
1380 * configuration. List those here to register them twice in the clock lookup
1381 * table under two names.
1382 */
1383static struct tegra_clk_duplicate tegra_clk_duplicates[] = {
1bf40915
PDS		 1384 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_USBD, "utmip-pad", NULL),
1385 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_USBD, "tegra-ehci.0", NULL),
1386 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_USBD, "tegra-otg", NULL),
1387 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEV, "tegra-avp", "bsev"),
1388 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEV, "nvavp", "bsev"),
1389 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_VDE, "tegra-aes", "vde"),
1390 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEA, "tegra-aes", "bsea"),
1391 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEA, "nvavp", "bsea"),
1392 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CML1, "tegra_sata_cml", NULL),
1393 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CML0, "tegra_pcie", "cml"),
1bf40915 1394 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_VCP, "nvavp", "vcp"),
8d99704f
TR		 1395 /* must be the last entry */
1396 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CLK_MAX, NULL, NULL),
b08e8c0e
PG		 1397};
1398
1399static const struct of_device_id pmc_match[] __initconst = {
1400 { .compatible = "nvidia,tegra30-pmc" },
e52d7c04 1401 { },
b08e8c0e
PG		 1402};
1403
88d909be
RK		 1404static struct tegra_audio_clk_info tegra30_audio_plls[] = {
1405 { "pll_a", &pll_a_params, tegra_clk_pll_a, "pll_p_out1" },
1406};
1407
061cec92 1408static void __init tegra30_clock_init(struct device_node *np)
b08e8c0e
PG		 1409{
1410 struct device_node *node;
b08e8c0e
PG		 1411
1412 clk_base = of_iomap(np, 0);
1413 if (!clk_base) {
1414 pr_err("ioremap tegra30 CAR failed\n");
1415 return;
1416 }
1417
1418 node = of_find_matching_node(NULL, pmc_match);
1419 if (!node) {
1420 pr_err("Failed to find pmc node\n");
1421 BUG();
1422 }
1423
1424 pmc_base = of_iomap(node, 0);
1425 if (!pmc_base) {
1426 pr_err("Can't map pmc registers\n");
1427 BUG();
1428 }
1429
6d5b988e
SW		 1430 clks = tegra_clk_init(clk_base, TEGRA30_CLK_CLK_MAX,
1431 TEGRA30_CLK_PERIPH_BANKS);
343a607c 1432 if (!clks)
d5ff89a8
PDS		 1433 return;
1434
1bf40915 1435 if (tegra_osc_clk_init(clk_base, tegra30_clks, tegra30_input_freq,
63cc5a4d
TR		 1436 ARRAY_SIZE(tegra30_input_freq), 1, &input_freq,
1437 NULL) < 0)
1bf40915
PDS		 1438 return;
1439
1bf40915 1440 tegra_fixed_clk_init(tegra30_clks);
b08e8c0e
PG		 1441 tegra30_pll_init();
1442 tegra30_super_clk_init();
1443 tegra30_periph_clk_init();
88d909be
RK		 1444 tegra_audio_clk_init(clk_base, pmc_base, tegra30_clks,
1445 tegra30_audio_plls,
1446 ARRAY_SIZE(tegra30_audio_plls));
1bf40915 1447 tegra_pmc_clk_init(pmc_base, tegra30_clks);
b08e8c0e 1448
1bf40915 1449 tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA30_CLK_CLK_MAX);
b08e8c0e 1450
343a607c 1451 tegra_add_of_provider(np);
1bf40915 1452 tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
b08e8c0e 1453
441f199a 1454 tegra_clk_apply_init_table = tegra30_clock_apply_init_table;
b08e8c0e
PG		 1455
1456 tegra_cpu_car_ops = &tegra30_cpu_car_ops;
1457}
061cec92 1458CLK_OF_DECLARE(tegra30, "nvidia,tegra30-car", tegra30_clock_init);
Linux 6.x block layer and io_uring tree(s)