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9952f691 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
6b301a05 RK |
2 | /* |
3 | * Copyright (c) 2012-2014 NVIDIA CORPORATION. All rights reserved. | |
6b301a05 RK |
4 | */ |
5 | ||
6 | #include <linux/io.h> | |
7 | #include <linux/clk.h> | |
8 | #include <linux/clk-provider.h> | |
9 | #include <linux/clkdev.h> | |
10 | #include <linux/of.h> | |
11 | #include <linux/of_address.h> | |
535f296d | 12 | #include <linux/syscore_ops.h> |
6b301a05 RK |
13 | #include <linux/delay.h> |
14 | #include <linux/export.h> | |
e403d005 | 15 | #include <linux/mutex.h> |
6b301a05 RK |
16 | #include <linux/clk/tegra.h> |
17 | #include <dt-bindings/clock/tegra210-car.h> | |
68d724ce | 18 | #include <dt-bindings/reset/tegra210-car.h> |
c8da78e8 | 19 | #include <linux/sizes.h> |
e403d005 | 20 | #include <soc/tegra/pmc.h> |
6b301a05 RK |
21 | |
22 | #include "clk.h" | |
23 | #include "clk-id.h" | |
24 | ||
25 | /* | |
26 | * TEGRA210_CAR_BANK_COUNT: the number of peripheral clock register | |
27 | * banks present in the Tegra210 CAR IP block. The banks are | |
28 | * identified by single letters, e.g.: L, H, U, V, W, X, Y. See | |
29 | * periph_regs[] in drivers/clk/tegra/clk.c | |
30 | */ | |
31 | #define TEGRA210_CAR_BANK_COUNT 7 | |
32 | ||
33 | #define CLK_SOURCE_CSITE 0x1d4 | |
34 | #define CLK_SOURCE_EMC 0x19c | |
bc2e4d29 | 35 | #define CLK_SOURCE_SOR1 0x410 |
05308d7e | 36 | #define CLK_SOURCE_SOR0 0x414 |
89e423c3 | 37 | #define CLK_SOURCE_LA 0x1f8 |
c76a69e4 PDS |
38 | #define CLK_SOURCE_SDMMC2 0x154 |
39 | #define CLK_SOURCE_SDMMC4 0x164 | |
a3cba697 | 40 | #define CLK_SOURCE_EMC_DLL 0x664 |
6b301a05 RK |
41 | |
42 | #define PLLC_BASE 0x80 | |
43 | #define PLLC_OUT 0x84 | |
44 | #define PLLC_MISC0 0x88 | |
45 | #define PLLC_MISC1 0x8c | |
46 | #define PLLC_MISC2 0x5d0 | |
47 | #define PLLC_MISC3 0x5d4 | |
48 | ||
49 | #define PLLC2_BASE 0x4e8 | |
50 | #define PLLC2_MISC0 0x4ec | |
51 | #define PLLC2_MISC1 0x4f0 | |
52 | #define PLLC2_MISC2 0x4f4 | |
53 | #define PLLC2_MISC3 0x4f8 | |
54 | ||
55 | #define PLLC3_BASE 0x4fc | |
56 | #define PLLC3_MISC0 0x500 | |
57 | #define PLLC3_MISC1 0x504 | |
58 | #define PLLC3_MISC2 0x508 | |
59 | #define PLLC3_MISC3 0x50c | |
60 | ||
61 | #define PLLM_BASE 0x90 | |
6b301a05 | 62 | #define PLLM_MISC1 0x98 |
474f2ba2 | 63 | #define PLLM_MISC2 0x9c |
6b301a05 RK |
64 | #define PLLP_BASE 0xa0 |
65 | #define PLLP_MISC0 0xac | |
66 | #define PLLP_MISC1 0x680 | |
67 | #define PLLA_BASE 0xb0 | |
68 | #define PLLA_MISC0 0xbc | |
69 | #define PLLA_MISC1 0xb8 | |
70 | #define PLLA_MISC2 0x5d8 | |
71 | #define PLLD_BASE 0xd0 | |
72 | #define PLLD_MISC0 0xdc | |
73 | #define PLLD_MISC1 0xd8 | |
74 | #define PLLU_BASE 0xc0 | |
75 | #define PLLU_OUTA 0xc4 | |
76 | #define PLLU_MISC0 0xcc | |
77 | #define PLLU_MISC1 0xc8 | |
78 | #define PLLX_BASE 0xe0 | |
79 | #define PLLX_MISC0 0xe4 | |
80 | #define PLLX_MISC1 0x510 | |
81 | #define PLLX_MISC2 0x514 | |
82 | #define PLLX_MISC3 0x518 | |
83 | #define PLLX_MISC4 0x5f0 | |
84 | #define PLLX_MISC5 0x5f4 | |
85 | #define PLLE_BASE 0xe8 | |
86 | #define PLLE_MISC0 0xec | |
87 | #define PLLD2_BASE 0x4b8 | |
88 | #define PLLD2_MISC0 0x4bc | |
89 | #define PLLD2_MISC1 0x570 | |
90 | #define PLLD2_MISC2 0x574 | |
91 | #define PLLD2_MISC3 0x578 | |
92 | #define PLLE_AUX 0x48c | |
93 | #define PLLRE_BASE 0x4c4 | |
94 | #define PLLRE_MISC0 0x4c8 | |
926655f9 | 95 | #define PLLRE_OUT1 0x4cc |
6b301a05 RK |
96 | #define PLLDP_BASE 0x590 |
97 | #define PLLDP_MISC 0x594 | |
98 | ||
99 | #define PLLC4_BASE 0x5a4 | |
100 | #define PLLC4_MISC0 0x5a8 | |
101 | #define PLLC4_OUT 0x5e4 | |
102 | #define PLLMB_BASE 0x5e8 | |
474f2ba2 | 103 | #define PLLMB_MISC1 0x5ec |
6b301a05 RK |
104 | #define PLLA1_BASE 0x6a4 |
105 | #define PLLA1_MISC0 0x6a8 | |
106 | #define PLLA1_MISC1 0x6ac | |
107 | #define PLLA1_MISC2 0x6b0 | |
108 | #define PLLA1_MISC3 0x6b4 | |
109 | ||
110 | #define PLLU_IDDQ_BIT 31 | |
111 | #define PLLCX_IDDQ_BIT 27 | |
112 | #define PLLRE_IDDQ_BIT 24 | |
113 | #define PLLA_IDDQ_BIT 25 | |
114 | #define PLLD_IDDQ_BIT 20 | |
115 | #define PLLSS_IDDQ_BIT 18 | |
116 | #define PLLM_IDDQ_BIT 5 | |
117 | #define PLLMB_IDDQ_BIT 17 | |
118 | #define PLLXP_IDDQ_BIT 3 | |
119 | ||
120 | #define PLLCX_RESET_BIT 30 | |
121 | ||
122 | #define PLL_BASE_LOCK BIT(27) | |
123 | #define PLLCX_BASE_LOCK BIT(26) | |
124 | #define PLLE_MISC_LOCK BIT(11) | |
125 | #define PLLRE_MISC_LOCK BIT(27) | |
126 | ||
127 | #define PLL_MISC_LOCK_ENABLE 18 | |
128 | #define PLLC_MISC_LOCK_ENABLE 24 | |
129 | #define PLLDU_MISC_LOCK_ENABLE 22 | |
130 | #define PLLU_MISC_LOCK_ENABLE 29 | |
131 | #define PLLE_MISC_LOCK_ENABLE 9 | |
132 | #define PLLRE_MISC_LOCK_ENABLE 30 | |
133 | #define PLLSS_MISC_LOCK_ENABLE 30 | |
134 | #define PLLP_MISC_LOCK_ENABLE 18 | |
135 | #define PLLM_MISC_LOCK_ENABLE 4 | |
136 | #define PLLMB_MISC_LOCK_ENABLE 16 | |
137 | #define PLLA_MISC_LOCK_ENABLE 28 | |
138 | #define PLLU_MISC_LOCK_ENABLE 29 | |
139 | #define PLLD_MISC_LOCK_ENABLE 18 | |
140 | ||
141 | #define PLLA_SDM_DIN_MASK 0xffff | |
142 | #define PLLA_SDM_EN_MASK BIT(26) | |
143 | ||
144 | #define PLLD_SDM_EN_MASK BIT(16) | |
145 | ||
146 | #define PLLD2_SDM_EN_MASK BIT(31) | |
030999fe | 147 | #define PLLD2_SSC_EN_MASK 0 |
6b301a05 RK |
148 | |
149 | #define PLLDP_SS_CFG 0x598 | |
150 | #define PLLDP_SDM_EN_MASK BIT(31) | |
151 | #define PLLDP_SSC_EN_MASK BIT(30) | |
152 | #define PLLDP_SS_CTRL1 0x59c | |
153 | #define PLLDP_SS_CTRL2 0x5a0 | |
154 | ||
155 | #define PMC_PLLM_WB0_OVERRIDE 0x1dc | |
156 | #define PMC_PLLM_WB0_OVERRIDE_2 0x2b0 | |
157 | ||
e745f992 PDS |
158 | #define UTMIP_PLL_CFG2 0x488 |
159 | #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6) | |
160 | #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18) | |
161 | #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0) | |
162 | #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP BIT(1) | |
163 | #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2) | |
164 | #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP BIT(3) | |
165 | #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4) | |
166 | #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP BIT(5) | |
167 | #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN BIT(24) | |
168 | #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP BIT(25) | |
169 | ||
170 | #define UTMIP_PLL_CFG1 0x484 | |
171 | #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27) | |
172 | #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0) | |
173 | #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17) | |
174 | #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16) | |
175 | #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15) | |
176 | #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14) | |
177 | #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12) | |
178 | ||
3358d2d9 AB |
179 | #define SATA_PLL_CFG0 0x490 |
180 | #define SATA_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0) | |
181 | #define SATA_PLL_CFG0_PADPLL_USE_LOCKDET BIT(2) | |
59af78d7 PDS |
182 | #define SATA_PLL_CFG0_SATA_SEQ_IN_SWCTL BIT(4) |
183 | #define SATA_PLL_CFG0_SATA_SEQ_RESET_INPUT_VALUE BIT(5) | |
184 | #define SATA_PLL_CFG0_SATA_SEQ_LANE_PD_INPUT_VALUE BIT(6) | |
185 | #define SATA_PLL_CFG0_SATA_SEQ_PADPLL_PD_INPUT_VALUE BIT(7) | |
186 | ||
3358d2d9 AB |
187 | #define SATA_PLL_CFG0_PADPLL_SLEEP_IDDQ BIT(13) |
188 | #define SATA_PLL_CFG0_SEQ_ENABLE BIT(24) | |
189 | ||
190 | #define XUSBIO_PLL_CFG0 0x51c | |
191 | #define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0) | |
192 | #define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL BIT(2) | |
193 | #define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET BIT(6) | |
194 | #define XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ BIT(13) | |
195 | #define XUSBIO_PLL_CFG0_SEQ_ENABLE BIT(24) | |
196 | ||
6b301a05 RK |
197 | #define UTMIPLL_HW_PWRDN_CFG0 0x52c |
198 | #define UTMIPLL_HW_PWRDN_CFG0_UTMIPLL_LOCK BIT(31) | |
199 | #define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE BIT(25) | |
200 | #define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24) | |
201 | #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE BIT(7) | |
202 | #define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET BIT(6) | |
203 | #define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5) | |
204 | #define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL BIT(4) | |
205 | #define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2) | |
206 | #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1) | |
207 | #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0) | |
208 | ||
209 | #define PLLU_HW_PWRDN_CFG0 0x530 | |
210 | #define PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE BIT(28) | |
211 | #define PLLU_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24) | |
212 | #define PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT BIT(7) | |
213 | #define PLLU_HW_PWRDN_CFG0_USE_LOCKDET BIT(6) | |
214 | #define PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2) | |
215 | #define PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL BIT(0) | |
216 | ||
217 | #define XUSB_PLL_CFG0 0x534 | |
218 | #define XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY 0x3ff | |
219 | #define XUSB_PLL_CFG0_PLLU_LOCK_DLY_MASK (0x3ff << 14) | |
220 | ||
221 | #define SPARE_REG0 0x55c | |
222 | #define CLK_M_DIVISOR_SHIFT 2 | |
223 | #define CLK_M_DIVISOR_MASK 0x3 | |
224 | ||
535f296d SK |
225 | #define CLK_MASK_ARM 0x44 |
226 | #define MISC_CLK_ENB 0x48 | |
227 | ||
68d724ce PDS |
228 | #define RST_DFLL_DVCO 0x2f4 |
229 | #define DVFS_DFLL_RESET_SHIFT 0 | |
230 | ||
a3cba697 JL |
231 | #define CLK_RST_CONTROLLER_CLK_OUT_ENB_X_SET 0x284 |
232 | #define CLK_RST_CONTROLLER_CLK_OUT_ENB_X_CLR 0x288 | |
233 | #define CLK_OUT_ENB_X_CLK_ENB_EMC_DLL BIT(14) | |
234 | ||
68d724ce PDS |
235 | #define CLK_RST_CONTROLLER_RST_DEV_Y_SET 0x2a8 |
236 | #define CLK_RST_CONTROLLER_RST_DEV_Y_CLR 0x2ac | |
535f296d | 237 | #define CPU_SOFTRST_CTRL 0x380 |
68d724ce | 238 | |
e403d005 PDS |
239 | #define LVL2_CLK_GATE_OVRA 0xf8 |
240 | #define LVL2_CLK_GATE_OVRC 0x3a0 | |
241 | #define LVL2_CLK_GATE_OVRD 0x3a4 | |
242 | #define LVL2_CLK_GATE_OVRE 0x554 | |
243 | ||
244 | /* I2S registers to handle during APE MBIST WAR */ | |
245 | #define TEGRA210_I2S_BASE 0x1000 | |
246 | #define TEGRA210_I2S_SIZE 0x100 | |
247 | #define TEGRA210_I2S_CTRLS 5 | |
248 | #define TEGRA210_I2S_CG 0x88 | |
249 | #define TEGRA210_I2S_CTRL 0xa0 | |
250 | ||
251 | /* DISPA registers to handle during MBIST WAR */ | |
252 | #define DC_CMD_DISPLAY_COMMAND 0xc8 | |
253 | #define DC_COM_DSC_TOP_CTL 0xcf8 | |
254 | ||
255 | /* VIC register to handle during MBIST WAR */ | |
256 | #define NV_PVIC_THI_SLCG_OVERRIDE_LOW 0x8c | |
257 | ||
258 | /* APE, DISPA and VIC base addesses needed for MBIST WAR */ | |
259 | #define TEGRA210_AHUB_BASE 0x702d0000 | |
260 | #define TEGRA210_DISPA_BASE 0x54200000 | |
261 | #define TEGRA210_VIC_BASE 0x54340000 | |
262 | ||
6b301a05 RK |
263 | /* |
264 | * SDM fractional divisor is 16-bit 2's complement signed number within | |
265 | * (-2^12 ... 2^12-1) range. Represented in PLL data structure as unsigned | |
266 | * 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used to | |
267 | * indicate that SDM is disabled. | |
268 | * | |
269 | * Effective ndiv value when SDM is enabled: ndiv + 1/2 + sdm_din/2^13 | |
270 | */ | |
271 | #define PLL_SDM_COEFF BIT(13) | |
272 | #define sdin_din_to_data(din) ((u16)((din) ? : 0xFFFFU)) | |
273 | #define sdin_data_to_din(dat) (((dat) == 0xFFFFU) ? 0 : (s16)dat) | |
a851ea2b AF |
274 | /* This macro returns ndiv effective scaled to SDM range */ |
275 | #define sdin_get_n_eff(cfg) ((cfg)->n * PLL_SDM_COEFF + ((cfg)->sdm_data ? \ | |
276 | (PLL_SDM_COEFF/2 + sdin_data_to_din((cfg)->sdm_data)) : 0)) | |
6b301a05 RK |
277 | |
278 | /* Tegra CPU clock and reset control regs */ | |
279 | #define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470 | |
280 | ||
281 | #ifdef CONFIG_PM_SLEEP | |
282 | static struct cpu_clk_suspend_context { | |
283 | u32 clk_csite_src; | |
284 | } tegra210_cpu_clk_sctx; | |
285 | #endif | |
286 | ||
e403d005 PDS |
287 | struct tegra210_domain_mbist_war { |
288 | void (*handle_lvl2_ovr)(struct tegra210_domain_mbist_war *mbist); | |
289 | const u32 lvl2_offset; | |
290 | const u32 lvl2_mask; | |
291 | const unsigned int num_clks; | |
292 | const unsigned int *clk_init_data; | |
293 | struct clk_bulk_data *clks; | |
294 | }; | |
295 | ||
296 | static struct clk **clks; | |
297 | ||
6b301a05 RK |
298 | static void __iomem *clk_base; |
299 | static void __iomem *pmc_base; | |
e403d005 PDS |
300 | static void __iomem *ahub_base; |
301 | static void __iomem *dispa_base; | |
302 | static void __iomem *vic_base; | |
6b301a05 RK |
303 | |
304 | static unsigned long osc_freq; | |
305 | static unsigned long pll_ref_freq; | |
306 | ||
307 | static DEFINE_SPINLOCK(pll_d_lock); | |
308 | static DEFINE_SPINLOCK(pll_e_lock); | |
309 | static DEFINE_SPINLOCK(pll_re_lock); | |
310 | static DEFINE_SPINLOCK(pll_u_lock); | |
05308d7e | 311 | static DEFINE_SPINLOCK(sor0_lock); |
bc2e4d29 | 312 | static DEFINE_SPINLOCK(sor1_lock); |
6b301a05 | 313 | static DEFINE_SPINLOCK(emc_lock); |
e403d005 | 314 | static DEFINE_MUTEX(lvl2_ovr_lock); |
6b301a05 RK |
315 | |
316 | /* possible OSC frequencies in Hz */ | |
317 | static unsigned long tegra210_input_freq[] = { | |
318 | [5] = 38400000, | |
319 | [8] = 12000000, | |
320 | }; | |
321 | ||
6b301a05 RK |
322 | #define PLL_ENABLE (1 << 30) |
323 | ||
324 | #define PLLCX_MISC1_IDDQ (1 << 27) | |
325 | #define PLLCX_MISC0_RESET (1 << 30) | |
326 | ||
327 | #define PLLCX_MISC0_DEFAULT_VALUE 0x40080000 | |
328 | #define PLLCX_MISC0_WRITE_MASK 0x400ffffb | |
329 | #define PLLCX_MISC1_DEFAULT_VALUE 0x08000000 | |
330 | #define PLLCX_MISC1_WRITE_MASK 0x08003cff | |
331 | #define PLLCX_MISC2_DEFAULT_VALUE 0x1f720f05 | |
332 | #define PLLCX_MISC2_WRITE_MASK 0xffffff17 | |
333 | #define PLLCX_MISC3_DEFAULT_VALUE 0x000000c4 | |
334 | #define PLLCX_MISC3_WRITE_MASK 0x00ffffff | |
335 | ||
336 | /* PLLA */ | |
337 | #define PLLA_BASE_IDDQ (1 << 25) | |
338 | #define PLLA_BASE_LOCK (1 << 27) | |
339 | ||
340 | #define PLLA_MISC0_LOCK_ENABLE (1 << 28) | |
341 | #define PLLA_MISC0_LOCK_OVERRIDE (1 << 27) | |
342 | ||
343 | #define PLLA_MISC2_EN_SDM (1 << 26) | |
344 | #define PLLA_MISC2_EN_DYNRAMP (1 << 25) | |
345 | ||
346 | #define PLLA_MISC0_DEFAULT_VALUE 0x12000020 | |
347 | #define PLLA_MISC0_WRITE_MASK 0x7fffffff | |
348 | #define PLLA_MISC2_DEFAULT_VALUE 0x0 | |
349 | #define PLLA_MISC2_WRITE_MASK 0x06ffffff | |
350 | ||
351 | /* PLLD */ | |
e403d005 PDS |
352 | #define PLLD_BASE_CSI_CLKSOURCE (1 << 23) |
353 | ||
6b301a05 RK |
354 | #define PLLD_MISC0_EN_SDM (1 << 16) |
355 | #define PLLD_MISC0_LOCK_OVERRIDE (1 << 17) | |
356 | #define PLLD_MISC0_LOCK_ENABLE (1 << 18) | |
357 | #define PLLD_MISC0_IDDQ (1 << 20) | |
358 | #define PLLD_MISC0_DSI_CLKENABLE (1 << 21) | |
359 | ||
360 | #define PLLD_MISC0_DEFAULT_VALUE 0x00140000 | |
361 | #define PLLD_MISC0_WRITE_MASK 0x3ff7ffff | |
362 | #define PLLD_MISC1_DEFAULT_VALUE 0x20 | |
363 | #define PLLD_MISC1_WRITE_MASK 0x00ffffff | |
364 | ||
365 | /* PLLD2 and PLLDP and PLLC4 */ | |
366 | #define PLLDSS_BASE_LOCK (1 << 27) | |
367 | #define PLLDSS_BASE_LOCK_OVERRIDE (1 << 24) | |
368 | #define PLLDSS_BASE_IDDQ (1 << 18) | |
369 | #define PLLDSS_BASE_REF_SEL_SHIFT 25 | |
370 | #define PLLDSS_BASE_REF_SEL_MASK (0x3 << PLLDSS_BASE_REF_SEL_SHIFT) | |
371 | ||
372 | #define PLLDSS_MISC0_LOCK_ENABLE (1 << 30) | |
373 | ||
374 | #define PLLDSS_MISC1_CFG_EN_SDM (1 << 31) | |
375 | #define PLLDSS_MISC1_CFG_EN_SSC (1 << 30) | |
376 | ||
377 | #define PLLD2_MISC0_DEFAULT_VALUE 0x40000020 | |
378 | #define PLLD2_MISC1_CFG_DEFAULT_VALUE 0x10000000 | |
379 | #define PLLD2_MISC2_CTRL1_DEFAULT_VALUE 0x0 | |
380 | #define PLLD2_MISC3_CTRL2_DEFAULT_VALUE 0x0 | |
381 | ||
382 | #define PLLDP_MISC0_DEFAULT_VALUE 0x40000020 | |
383 | #define PLLDP_MISC1_CFG_DEFAULT_VALUE 0xc0000000 | |
384 | #define PLLDP_MISC2_CTRL1_DEFAULT_VALUE 0xf400f0da | |
385 | #define PLLDP_MISC3_CTRL2_DEFAULT_VALUE 0x2004f400 | |
386 | ||
387 | #define PLLDSS_MISC0_WRITE_MASK 0x47ffffff | |
388 | #define PLLDSS_MISC1_CFG_WRITE_MASK 0xf8000000 | |
389 | #define PLLDSS_MISC2_CTRL1_WRITE_MASK 0xffffffff | |
390 | #define PLLDSS_MISC3_CTRL2_WRITE_MASK 0xffffffff | |
391 | ||
392 | #define PLLC4_MISC0_DEFAULT_VALUE 0x40000000 | |
393 | ||
394 | /* PLLRE */ | |
395 | #define PLLRE_MISC0_LOCK_ENABLE (1 << 30) | |
396 | #define PLLRE_MISC0_LOCK_OVERRIDE (1 << 29) | |
397 | #define PLLRE_MISC0_LOCK (1 << 27) | |
398 | #define PLLRE_MISC0_IDDQ (1 << 24) | |
399 | ||
400 | #define PLLRE_BASE_DEFAULT_VALUE 0x0 | |
401 | #define PLLRE_MISC0_DEFAULT_VALUE 0x41000000 | |
402 | ||
403 | #define PLLRE_BASE_DEFAULT_MASK 0x1c000000 | |
404 | #define PLLRE_MISC0_WRITE_MASK 0x67ffffff | |
405 | ||
406 | /* PLLX */ | |
407 | #define PLLX_USE_DYN_RAMP 1 | |
408 | #define PLLX_BASE_LOCK (1 << 27) | |
409 | ||
410 | #define PLLX_MISC0_FO_G_DISABLE (0x1 << 28) | |
411 | #define PLLX_MISC0_LOCK_ENABLE (0x1 << 18) | |
412 | ||
413 | #define PLLX_MISC2_DYNRAMP_STEPB_SHIFT 24 | |
414 | #define PLLX_MISC2_DYNRAMP_STEPB_MASK (0xFF << PLLX_MISC2_DYNRAMP_STEPB_SHIFT) | |
415 | #define PLLX_MISC2_DYNRAMP_STEPA_SHIFT 16 | |
416 | #define PLLX_MISC2_DYNRAMP_STEPA_MASK (0xFF << PLLX_MISC2_DYNRAMP_STEPA_SHIFT) | |
417 | #define PLLX_MISC2_NDIV_NEW_SHIFT 8 | |
418 | #define PLLX_MISC2_NDIV_NEW_MASK (0xFF << PLLX_MISC2_NDIV_NEW_SHIFT) | |
419 | #define PLLX_MISC2_LOCK_OVERRIDE (0x1 << 4) | |
420 | #define PLLX_MISC2_DYNRAMP_DONE (0x1 << 2) | |
421 | #define PLLX_MISC2_EN_DYNRAMP (0x1 << 0) | |
422 | ||
423 | #define PLLX_MISC3_IDDQ (0x1 << 3) | |
424 | ||
425 | #define PLLX_MISC0_DEFAULT_VALUE PLLX_MISC0_LOCK_ENABLE | |
426 | #define PLLX_MISC0_WRITE_MASK 0x10c40000 | |
427 | #define PLLX_MISC1_DEFAULT_VALUE 0x20 | |
428 | #define PLLX_MISC1_WRITE_MASK 0x00ffffff | |
429 | #define PLLX_MISC2_DEFAULT_VALUE 0x0 | |
430 | #define PLLX_MISC2_WRITE_MASK 0xffffff11 | |
431 | #define PLLX_MISC3_DEFAULT_VALUE PLLX_MISC3_IDDQ | |
432 | #define PLLX_MISC3_WRITE_MASK 0x01ff0f0f | |
433 | #define PLLX_MISC4_DEFAULT_VALUE 0x0 | |
434 | #define PLLX_MISC4_WRITE_MASK 0x8000ffff | |
435 | #define PLLX_MISC5_DEFAULT_VALUE 0x0 | |
436 | #define PLLX_MISC5_WRITE_MASK 0x0000ffff | |
437 | ||
438 | #define PLLX_HW_CTRL_CFG 0x548 | |
439 | #define PLLX_HW_CTRL_CFG_SWCTRL (0x1 << 0) | |
440 | ||
441 | /* PLLMB */ | |
442 | #define PLLMB_BASE_LOCK (1 << 27) | |
443 | ||
474f2ba2 RK |
444 | #define PLLMB_MISC1_LOCK_OVERRIDE (1 << 18) |
445 | #define PLLMB_MISC1_IDDQ (1 << 17) | |
446 | #define PLLMB_MISC1_LOCK_ENABLE (1 << 16) | |
6b301a05 | 447 | |
474f2ba2 RK |
448 | #define PLLMB_MISC1_DEFAULT_VALUE 0x00030000 |
449 | #define PLLMB_MISC1_WRITE_MASK 0x0007ffff | |
6b301a05 RK |
450 | |
451 | /* PLLP */ | |
452 | #define PLLP_BASE_OVERRIDE (1 << 28) | |
453 | #define PLLP_BASE_LOCK (1 << 27) | |
454 | ||
455 | #define PLLP_MISC0_LOCK_ENABLE (1 << 18) | |
456 | #define PLLP_MISC0_LOCK_OVERRIDE (1 << 17) | |
457 | #define PLLP_MISC0_IDDQ (1 << 3) | |
458 | ||
459 | #define PLLP_MISC1_HSIO_EN_SHIFT 29 | |
460 | #define PLLP_MISC1_HSIO_EN (1 << PLLP_MISC1_HSIO_EN_SHIFT) | |
461 | #define PLLP_MISC1_XUSB_EN_SHIFT 28 | |
462 | #define PLLP_MISC1_XUSB_EN (1 << PLLP_MISC1_XUSB_EN_SHIFT) | |
463 | ||
464 | #define PLLP_MISC0_DEFAULT_VALUE 0x00040008 | |
465 | #define PLLP_MISC1_DEFAULT_VALUE 0x0 | |
466 | ||
467 | #define PLLP_MISC0_WRITE_MASK 0xdc6000f | |
468 | #define PLLP_MISC1_WRITE_MASK 0x70ffffff | |
469 | ||
470 | /* PLLU */ | |
471 | #define PLLU_BASE_LOCK (1 << 27) | |
472 | #define PLLU_BASE_OVERRIDE (1 << 24) | |
473 | #define PLLU_BASE_CLKENABLE_USB (1 << 21) | |
474 | #define PLLU_BASE_CLKENABLE_HSIC (1 << 22) | |
475 | #define PLLU_BASE_CLKENABLE_ICUSB (1 << 23) | |
476 | #define PLLU_BASE_CLKENABLE_48M (1 << 25) | |
477 | #define PLLU_BASE_CLKENABLE_ALL (PLLU_BASE_CLKENABLE_USB |\ | |
478 | PLLU_BASE_CLKENABLE_HSIC |\ | |
479 | PLLU_BASE_CLKENABLE_ICUSB |\ | |
480 | PLLU_BASE_CLKENABLE_48M) | |
481 | ||
482 | #define PLLU_MISC0_IDDQ (1 << 31) | |
483 | #define PLLU_MISC0_LOCK_ENABLE (1 << 29) | |
484 | #define PLLU_MISC1_LOCK_OVERRIDE (1 << 0) | |
485 | ||
486 | #define PLLU_MISC0_DEFAULT_VALUE 0xa0000000 | |
487 | #define PLLU_MISC1_DEFAULT_VALUE 0x0 | |
488 | ||
489 | #define PLLU_MISC0_WRITE_MASK 0xbfffffff | |
490 | #define PLLU_MISC1_WRITE_MASK 0x00000007 | |
491 | ||
3358d2d9 AB |
492 | void tegra210_xusb_pll_hw_control_enable(void) |
493 | { | |
494 | u32 val; | |
495 | ||
496 | val = readl_relaxed(clk_base + XUSBIO_PLL_CFG0); | |
497 | val &= ~(XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL | | |
498 | XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL); | |
499 | val |= XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET | | |
500 | XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ; | |
501 | writel_relaxed(val, clk_base + XUSBIO_PLL_CFG0); | |
502 | } | |
503 | EXPORT_SYMBOL_GPL(tegra210_xusb_pll_hw_control_enable); | |
504 | ||
505 | void tegra210_xusb_pll_hw_sequence_start(void) | |
506 | { | |
507 | u32 val; | |
508 | ||
509 | val = readl_relaxed(clk_base + XUSBIO_PLL_CFG0); | |
510 | val |= XUSBIO_PLL_CFG0_SEQ_ENABLE; | |
511 | writel_relaxed(val, clk_base + XUSBIO_PLL_CFG0); | |
512 | } | |
513 | EXPORT_SYMBOL_GPL(tegra210_xusb_pll_hw_sequence_start); | |
514 | ||
515 | void tegra210_sata_pll_hw_control_enable(void) | |
516 | { | |
517 | u32 val; | |
518 | ||
519 | val = readl_relaxed(clk_base + SATA_PLL_CFG0); | |
520 | val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL; | |
521 | val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET | | |
522 | SATA_PLL_CFG0_PADPLL_SLEEP_IDDQ; | |
523 | writel_relaxed(val, clk_base + SATA_PLL_CFG0); | |
524 | } | |
525 | EXPORT_SYMBOL_GPL(tegra210_sata_pll_hw_control_enable); | |
526 | ||
527 | void tegra210_sata_pll_hw_sequence_start(void) | |
528 | { | |
529 | u32 val; | |
530 | ||
531 | val = readl_relaxed(clk_base + SATA_PLL_CFG0); | |
532 | val |= SATA_PLL_CFG0_SEQ_ENABLE; | |
533 | writel_relaxed(val, clk_base + SATA_PLL_CFG0); | |
534 | } | |
535 | EXPORT_SYMBOL_GPL(tegra210_sata_pll_hw_sequence_start); | |
536 | ||
59af78d7 PDS |
537 | void tegra210_set_sata_pll_seq_sw(bool state) |
538 | { | |
539 | u32 val; | |
540 | ||
541 | val = readl_relaxed(clk_base + SATA_PLL_CFG0); | |
542 | if (state) { | |
543 | val |= SATA_PLL_CFG0_SATA_SEQ_IN_SWCTL; | |
544 | val |= SATA_PLL_CFG0_SATA_SEQ_RESET_INPUT_VALUE; | |
545 | val |= SATA_PLL_CFG0_SATA_SEQ_LANE_PD_INPUT_VALUE; | |
546 | val |= SATA_PLL_CFG0_SATA_SEQ_PADPLL_PD_INPUT_VALUE; | |
547 | } else { | |
548 | val &= ~SATA_PLL_CFG0_SATA_SEQ_IN_SWCTL; | |
549 | val &= ~SATA_PLL_CFG0_SATA_SEQ_RESET_INPUT_VALUE; | |
550 | val &= ~SATA_PLL_CFG0_SATA_SEQ_LANE_PD_INPUT_VALUE; | |
551 | val &= ~SATA_PLL_CFG0_SATA_SEQ_PADPLL_PD_INPUT_VALUE; | |
552 | } | |
553 | writel_relaxed(val, clk_base + SATA_PLL_CFG0); | |
554 | } | |
555 | EXPORT_SYMBOL_GPL(tegra210_set_sata_pll_seq_sw); | |
556 | ||
a3cba697 JL |
557 | void tegra210_clk_emc_dll_enable(bool flag) |
558 | { | |
559 | u32 offset = flag ? CLK_RST_CONTROLLER_CLK_OUT_ENB_X_SET : | |
560 | CLK_RST_CONTROLLER_CLK_OUT_ENB_X_CLR; | |
561 | ||
562 | writel_relaxed(CLK_OUT_ENB_X_CLK_ENB_EMC_DLL, clk_base + offset); | |
563 | } | |
564 | EXPORT_SYMBOL_GPL(tegra210_clk_emc_dll_enable); | |
565 | ||
566 | void tegra210_clk_emc_dll_update_setting(u32 emc_dll_src_value) | |
567 | { | |
568 | writel_relaxed(emc_dll_src_value, clk_base + CLK_SOURCE_EMC_DLL); | |
569 | } | |
570 | EXPORT_SYMBOL_GPL(tegra210_clk_emc_dll_update_setting); | |
571 | ||
572 | void tegra210_clk_emc_update_setting(u32 emc_src_value) | |
573 | { | |
574 | writel_relaxed(emc_src_value, clk_base + CLK_SOURCE_EMC); | |
575 | } | |
576 | EXPORT_SYMBOL_GPL(tegra210_clk_emc_update_setting); | |
577 | ||
e403d005 PDS |
578 | static void tegra210_generic_mbist_war(struct tegra210_domain_mbist_war *mbist) |
579 | { | |
580 | u32 val; | |
581 | ||
582 | val = readl_relaxed(clk_base + mbist->lvl2_offset); | |
583 | writel_relaxed(val | mbist->lvl2_mask, clk_base + mbist->lvl2_offset); | |
584 | fence_udelay(1, clk_base); | |
585 | writel_relaxed(val, clk_base + mbist->lvl2_offset); | |
586 | fence_udelay(1, clk_base); | |
587 | } | |
588 | ||
589 | static void tegra210_venc_mbist_war(struct tegra210_domain_mbist_war *mbist) | |
590 | { | |
591 | u32 csi_src, ovra, ovre; | |
592 | unsigned long flags = 0; | |
593 | ||
594 | spin_lock_irqsave(&pll_d_lock, flags); | |
595 | ||
596 | csi_src = readl_relaxed(clk_base + PLLD_BASE); | |
597 | writel_relaxed(csi_src | PLLD_BASE_CSI_CLKSOURCE, clk_base + PLLD_BASE); | |
598 | fence_udelay(1, clk_base); | |
599 | ||
600 | ovra = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRA); | |
601 | writel_relaxed(ovra | BIT(15), clk_base + LVL2_CLK_GATE_OVRA); | |
602 | ovre = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRE); | |
603 | writel_relaxed(ovre | BIT(3), clk_base + LVL2_CLK_GATE_OVRE); | |
604 | fence_udelay(1, clk_base); | |
605 | ||
606 | writel_relaxed(ovra, clk_base + LVL2_CLK_GATE_OVRA); | |
607 | writel_relaxed(ovre, clk_base + LVL2_CLK_GATE_OVRE); | |
608 | writel_relaxed(csi_src, clk_base + PLLD_BASE); | |
609 | fence_udelay(1, clk_base); | |
610 | ||
611 | spin_unlock_irqrestore(&pll_d_lock, flags); | |
612 | } | |
613 | ||
614 | static void tegra210_disp_mbist_war(struct tegra210_domain_mbist_war *mbist) | |
615 | { | |
616 | u32 ovra, dsc_top_ctrl; | |
617 | ||
618 | ovra = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRA); | |
619 | writel_relaxed(ovra | BIT(1), clk_base + LVL2_CLK_GATE_OVRA); | |
620 | fence_udelay(1, clk_base); | |
621 | ||
622 | dsc_top_ctrl = readl_relaxed(dispa_base + DC_COM_DSC_TOP_CTL); | |
623 | writel_relaxed(dsc_top_ctrl | BIT(2), dispa_base + DC_COM_DSC_TOP_CTL); | |
624 | readl_relaxed(dispa_base + DC_CMD_DISPLAY_COMMAND); | |
625 | writel_relaxed(dsc_top_ctrl, dispa_base + DC_COM_DSC_TOP_CTL); | |
626 | readl_relaxed(dispa_base + DC_CMD_DISPLAY_COMMAND); | |
627 | ||
628 | writel_relaxed(ovra, clk_base + LVL2_CLK_GATE_OVRA); | |
629 | fence_udelay(1, clk_base); | |
630 | } | |
631 | ||
632 | static void tegra210_vic_mbist_war(struct tegra210_domain_mbist_war *mbist) | |
633 | { | |
634 | u32 ovre, val; | |
635 | ||
636 | ovre = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRE); | |
637 | writel_relaxed(ovre | BIT(5), clk_base + LVL2_CLK_GATE_OVRE); | |
638 | fence_udelay(1, clk_base); | |
639 | ||
640 | val = readl_relaxed(vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW); | |
641 | writel_relaxed(val | BIT(0) | GENMASK(7, 2) | BIT(24), | |
642 | vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW); | |
643 | fence_udelay(1, vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW); | |
644 | ||
645 | writel_relaxed(val, vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW); | |
646 | readl(vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW); | |
647 | ||
648 | writel_relaxed(ovre, clk_base + LVL2_CLK_GATE_OVRE); | |
649 | fence_udelay(1, clk_base); | |
650 | } | |
651 | ||
652 | static void tegra210_ape_mbist_war(struct tegra210_domain_mbist_war *mbist) | |
653 | { | |
654 | void __iomem *i2s_base; | |
655 | unsigned int i; | |
656 | u32 ovrc, ovre; | |
657 | ||
658 | ovrc = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRC); | |
659 | ovre = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRE); | |
660 | writel_relaxed(ovrc | BIT(1), clk_base + LVL2_CLK_GATE_OVRC); | |
661 | writel_relaxed(ovre | BIT(10) | BIT(11), | |
662 | clk_base + LVL2_CLK_GATE_OVRE); | |
663 | fence_udelay(1, clk_base); | |
664 | ||
665 | i2s_base = ahub_base + TEGRA210_I2S_BASE; | |
666 | ||
667 | for (i = 0; i < TEGRA210_I2S_CTRLS; i++) { | |
668 | u32 i2s_ctrl; | |
669 | ||
670 | i2s_ctrl = readl_relaxed(i2s_base + TEGRA210_I2S_CTRL); | |
671 | writel_relaxed(i2s_ctrl | BIT(10), | |
672 | i2s_base + TEGRA210_I2S_CTRL); | |
673 | writel_relaxed(0, i2s_base + TEGRA210_I2S_CG); | |
674 | readl(i2s_base + TEGRA210_I2S_CG); | |
675 | writel_relaxed(1, i2s_base + TEGRA210_I2S_CG); | |
676 | writel_relaxed(i2s_ctrl, i2s_base + TEGRA210_I2S_CTRL); | |
677 | readl(i2s_base + TEGRA210_I2S_CTRL); | |
678 | ||
679 | i2s_base += TEGRA210_I2S_SIZE; | |
680 | } | |
681 | ||
682 | writel_relaxed(ovrc, clk_base + LVL2_CLK_GATE_OVRC); | |
683 | writel_relaxed(ovre, clk_base + LVL2_CLK_GATE_OVRE); | |
684 | fence_udelay(1, clk_base); | |
685 | } | |
686 | ||
6b301a05 RK |
687 | static inline void _pll_misc_chk_default(void __iomem *base, |
688 | struct tegra_clk_pll_params *params, | |
689 | u8 misc_num, u32 default_val, u32 mask) | |
690 | { | |
691 | u32 boot_val = readl_relaxed(base + params->ext_misc_reg[misc_num]); | |
692 | ||
693 | boot_val &= mask; | |
694 | default_val &= mask; | |
695 | if (boot_val != default_val) { | |
696 | pr_warn("boot misc%d 0x%x: expected 0x%x\n", | |
697 | misc_num, boot_val, default_val); | |
698 | pr_warn(" (comparison mask = 0x%x)\n", mask); | |
699 | params->defaults_set = false; | |
700 | } | |
701 | } | |
702 | ||
703 | /* | |
704 | * PLLCX: PLLC, PLLC2, PLLC3, PLLA1 | |
705 | * Hybrid PLLs with dynamic ramp. Dynamic ramp is allowed for any transition | |
706 | * that changes NDIV only, while PLL is already locked. | |
707 | */ | |
708 | static void pllcx_check_defaults(struct tegra_clk_pll_params *params) | |
709 | { | |
710 | u32 default_val; | |
711 | ||
712 | default_val = PLLCX_MISC0_DEFAULT_VALUE & (~PLLCX_MISC0_RESET); | |
713 | _pll_misc_chk_default(clk_base, params, 0, default_val, | |
714 | PLLCX_MISC0_WRITE_MASK); | |
715 | ||
716 | default_val = PLLCX_MISC1_DEFAULT_VALUE & (~PLLCX_MISC1_IDDQ); | |
717 | _pll_misc_chk_default(clk_base, params, 1, default_val, | |
718 | PLLCX_MISC1_WRITE_MASK); | |
719 | ||
720 | default_val = PLLCX_MISC2_DEFAULT_VALUE; | |
721 | _pll_misc_chk_default(clk_base, params, 2, default_val, | |
722 | PLLCX_MISC2_WRITE_MASK); | |
723 | ||
724 | default_val = PLLCX_MISC3_DEFAULT_VALUE; | |
725 | _pll_misc_chk_default(clk_base, params, 3, default_val, | |
726 | PLLCX_MISC3_WRITE_MASK); | |
727 | } | |
728 | ||
fd360e20 JH |
729 | static void tegra210_pllcx_set_defaults(const char *name, |
730 | struct tegra_clk_pll *pllcx) | |
6b301a05 RK |
731 | { |
732 | pllcx->params->defaults_set = true; | |
733 | ||
1116d5a7 | 734 | if (readl_relaxed(clk_base + pllcx->params->base_reg) & PLL_ENABLE) { |
6b301a05 RK |
735 | /* PLL is ON: only check if defaults already set */ |
736 | pllcx_check_defaults(pllcx->params); | |
1116d5a7 JH |
737 | if (!pllcx->params->defaults_set) |
738 | pr_warn("%s already enabled. Postponing set full defaults\n", | |
739 | name); | |
6b301a05 RK |
740 | return; |
741 | } | |
742 | ||
743 | /* Defaults assert PLL reset, and set IDDQ */ | |
744 | writel_relaxed(PLLCX_MISC0_DEFAULT_VALUE, | |
745 | clk_base + pllcx->params->ext_misc_reg[0]); | |
746 | writel_relaxed(PLLCX_MISC1_DEFAULT_VALUE, | |
747 | clk_base + pllcx->params->ext_misc_reg[1]); | |
748 | writel_relaxed(PLLCX_MISC2_DEFAULT_VALUE, | |
749 | clk_base + pllcx->params->ext_misc_reg[2]); | |
750 | writel_relaxed(PLLCX_MISC3_DEFAULT_VALUE, | |
751 | clk_base + pllcx->params->ext_misc_reg[3]); | |
752 | udelay(1); | |
753 | } | |
754 | ||
fd360e20 | 755 | static void _pllc_set_defaults(struct tegra_clk_pll *pllcx) |
6b301a05 RK |
756 | { |
757 | tegra210_pllcx_set_defaults("PLL_C", pllcx); | |
758 | } | |
759 | ||
fd360e20 | 760 | static void _pllc2_set_defaults(struct tegra_clk_pll *pllcx) |
6b301a05 RK |
761 | { |
762 | tegra210_pllcx_set_defaults("PLL_C2", pllcx); | |
763 | } | |
764 | ||
fd360e20 | 765 | static void _pllc3_set_defaults(struct tegra_clk_pll *pllcx) |
6b301a05 RK |
766 | { |
767 | tegra210_pllcx_set_defaults("PLL_C3", pllcx); | |
768 | } | |
769 | ||
fd360e20 | 770 | static void _plla1_set_defaults(struct tegra_clk_pll *pllcx) |
6b301a05 RK |
771 | { |
772 | tegra210_pllcx_set_defaults("PLL_A1", pllcx); | |
773 | } | |
774 | ||
775 | /* | |
776 | * PLLA | |
777 | * PLL with dynamic ramp and fractional SDM. Dynamic ramp is not used. | |
778 | * Fractional SDM is allowed to provide exact audio rates. | |
779 | */ | |
fd360e20 | 780 | static void tegra210_plla_set_defaults(struct tegra_clk_pll *plla) |
6b301a05 RK |
781 | { |
782 | u32 mask; | |
783 | u32 val = readl_relaxed(clk_base + plla->params->base_reg); | |
784 | ||
785 | plla->params->defaults_set = true; | |
786 | ||
787 | if (val & PLL_ENABLE) { | |
788 | /* | |
789 | * PLL is ON: check if defaults already set, then set those | |
790 | * that can be updated in flight. | |
791 | */ | |
792 | if (val & PLLA_BASE_IDDQ) { | |
793 | pr_warn("PLL_A boot enabled with IDDQ set\n"); | |
794 | plla->params->defaults_set = false; | |
795 | } | |
796 | ||
797 | pr_warn("PLL_A already enabled. Postponing set full defaults\n"); | |
798 | ||
799 | val = PLLA_MISC0_DEFAULT_VALUE; /* ignore lock enable */ | |
800 | mask = PLLA_MISC0_LOCK_ENABLE | PLLA_MISC0_LOCK_OVERRIDE; | |
801 | _pll_misc_chk_default(clk_base, plla->params, 0, val, | |
802 | ~mask & PLLA_MISC0_WRITE_MASK); | |
803 | ||
804 | val = PLLA_MISC2_DEFAULT_VALUE; /* ignore all but control bit */ | |
805 | _pll_misc_chk_default(clk_base, plla->params, 2, val, | |
806 | PLLA_MISC2_EN_DYNRAMP); | |
807 | ||
808 | /* Enable lock detect */ | |
809 | val = readl_relaxed(clk_base + plla->params->ext_misc_reg[0]); | |
810 | val &= ~mask; | |
811 | val |= PLLA_MISC0_DEFAULT_VALUE & mask; | |
812 | writel_relaxed(val, clk_base + plla->params->ext_misc_reg[0]); | |
813 | udelay(1); | |
814 | ||
815 | return; | |
816 | } | |
817 | ||
818 | /* set IDDQ, enable lock detect, disable dynamic ramp and SDM */ | |
819 | val |= PLLA_BASE_IDDQ; | |
820 | writel_relaxed(val, clk_base + plla->params->base_reg); | |
821 | writel_relaxed(PLLA_MISC0_DEFAULT_VALUE, | |
822 | clk_base + plla->params->ext_misc_reg[0]); | |
823 | writel_relaxed(PLLA_MISC2_DEFAULT_VALUE, | |
824 | clk_base + plla->params->ext_misc_reg[2]); | |
825 | udelay(1); | |
826 | } | |
827 | ||
828 | /* | |
829 | * PLLD | |
830 | * PLL with fractional SDM. | |
831 | */ | |
fd360e20 | 832 | static void tegra210_plld_set_defaults(struct tegra_clk_pll *plld) |
6b301a05 RK |
833 | { |
834 | u32 val; | |
835 | u32 mask = 0xffff; | |
836 | ||
837 | plld->params->defaults_set = true; | |
838 | ||
839 | if (readl_relaxed(clk_base + plld->params->base_reg) & | |
840 | PLL_ENABLE) { | |
6b301a05 RK |
841 | |
842 | /* | |
843 | * PLL is ON: check if defaults already set, then set those | |
844 | * that can be updated in flight. | |
845 | */ | |
846 | val = PLLD_MISC1_DEFAULT_VALUE; | |
847 | _pll_misc_chk_default(clk_base, plld->params, 1, | |
848 | val, PLLD_MISC1_WRITE_MASK); | |
849 | ||
850 | /* ignore lock, DSI and SDM controls, make sure IDDQ not set */ | |
851 | val = PLLD_MISC0_DEFAULT_VALUE & (~PLLD_MISC0_IDDQ); | |
852 | mask |= PLLD_MISC0_DSI_CLKENABLE | PLLD_MISC0_LOCK_ENABLE | | |
853 | PLLD_MISC0_LOCK_OVERRIDE | PLLD_MISC0_EN_SDM; | |
854 | _pll_misc_chk_default(clk_base, plld->params, 0, val, | |
855 | ~mask & PLLD_MISC0_WRITE_MASK); | |
856 | ||
8dce89a1 PDS |
857 | if (!plld->params->defaults_set) |
858 | pr_warn("PLL_D already enabled. Postponing set full defaults\n"); | |
859 | ||
6b301a05 RK |
860 | /* Enable lock detect */ |
861 | mask = PLLD_MISC0_LOCK_ENABLE | PLLD_MISC0_LOCK_OVERRIDE; | |
862 | val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]); | |
863 | val &= ~mask; | |
864 | val |= PLLD_MISC0_DEFAULT_VALUE & mask; | |
865 | writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]); | |
866 | udelay(1); | |
867 | ||
868 | return; | |
869 | } | |
870 | ||
871 | val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]); | |
872 | val &= PLLD_MISC0_DSI_CLKENABLE; | |
873 | val |= PLLD_MISC0_DEFAULT_VALUE; | |
874 | /* set IDDQ, enable lock detect, disable SDM */ | |
875 | writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]); | |
876 | writel_relaxed(PLLD_MISC1_DEFAULT_VALUE, clk_base + | |
877 | plld->params->ext_misc_reg[1]); | |
878 | udelay(1); | |
879 | } | |
880 | ||
881 | /* | |
882 | * PLLD2, PLLDP | |
883 | * PLL with fractional SDM and Spread Spectrum (SDM is a must if SSC is used). | |
884 | */ | |
885 | static void plldss_defaults(const char *pll_name, struct tegra_clk_pll *plldss, | |
886 | u32 misc0_val, u32 misc1_val, u32 misc2_val, u32 misc3_val) | |
887 | { | |
888 | u32 default_val; | |
889 | u32 val = readl_relaxed(clk_base + plldss->params->base_reg); | |
890 | ||
891 | plldss->params->defaults_set = true; | |
892 | ||
893 | if (val & PLL_ENABLE) { | |
6b301a05 RK |
894 | |
895 | /* | |
896 | * PLL is ON: check if defaults already set, then set those | |
897 | * that can be updated in flight. | |
898 | */ | |
899 | if (val & PLLDSS_BASE_IDDQ) { | |
900 | pr_warn("plldss boot enabled with IDDQ set\n"); | |
901 | plldss->params->defaults_set = false; | |
902 | } | |
903 | ||
904 | /* ignore lock enable */ | |
905 | default_val = misc0_val; | |
906 | _pll_misc_chk_default(clk_base, plldss->params, 0, default_val, | |
907 | PLLDSS_MISC0_WRITE_MASK & | |
908 | (~PLLDSS_MISC0_LOCK_ENABLE)); | |
909 | ||
910 | /* | |
911 | * If SSC is used, check all settings, otherwise just confirm | |
912 | * that SSC is not used on boot as well. Do nothing when using | |
913 | * this function for PLLC4 that has only MISC0. | |
914 | */ | |
915 | if (plldss->params->ssc_ctrl_en_mask) { | |
916 | default_val = misc1_val; | |
917 | _pll_misc_chk_default(clk_base, plldss->params, 1, | |
918 | default_val, PLLDSS_MISC1_CFG_WRITE_MASK); | |
919 | default_val = misc2_val; | |
920 | _pll_misc_chk_default(clk_base, plldss->params, 2, | |
921 | default_val, PLLDSS_MISC2_CTRL1_WRITE_MASK); | |
922 | default_val = misc3_val; | |
923 | _pll_misc_chk_default(clk_base, plldss->params, 3, | |
924 | default_val, PLLDSS_MISC3_CTRL2_WRITE_MASK); | |
925 | } else if (plldss->params->ext_misc_reg[1]) { | |
926 | default_val = misc1_val; | |
927 | _pll_misc_chk_default(clk_base, plldss->params, 1, | |
928 | default_val, PLLDSS_MISC1_CFG_WRITE_MASK & | |
929 | (~PLLDSS_MISC1_CFG_EN_SDM)); | |
930 | } | |
931 | ||
1934ffd0 PDS |
932 | if (!plldss->params->defaults_set) |
933 | pr_warn("%s already enabled. Postponing set full defaults\n", | |
934 | pll_name); | |
935 | ||
6b301a05 RK |
936 | /* Enable lock detect */ |
937 | if (val & PLLDSS_BASE_LOCK_OVERRIDE) { | |
938 | val &= ~PLLDSS_BASE_LOCK_OVERRIDE; | |
939 | writel_relaxed(val, clk_base + | |
940 | plldss->params->base_reg); | |
941 | } | |
942 | ||
943 | val = readl_relaxed(clk_base + plldss->params->ext_misc_reg[0]); | |
944 | val &= ~PLLDSS_MISC0_LOCK_ENABLE; | |
945 | val |= misc0_val & PLLDSS_MISC0_LOCK_ENABLE; | |
946 | writel_relaxed(val, clk_base + plldss->params->ext_misc_reg[0]); | |
947 | udelay(1); | |
948 | ||
949 | return; | |
950 | } | |
951 | ||
952 | /* set IDDQ, enable lock detect, configure SDM/SSC */ | |
953 | val |= PLLDSS_BASE_IDDQ; | |
954 | val &= ~PLLDSS_BASE_LOCK_OVERRIDE; | |
955 | writel_relaxed(val, clk_base + plldss->params->base_reg); | |
956 | ||
957 | /* When using this function for PLLC4 exit here */ | |
958 | if (!plldss->params->ext_misc_reg[1]) { | |
959 | writel_relaxed(misc0_val, clk_base + | |
960 | plldss->params->ext_misc_reg[0]); | |
961 | udelay(1); | |
962 | return; | |
963 | } | |
964 | ||
965 | writel_relaxed(misc0_val, clk_base + | |
966 | plldss->params->ext_misc_reg[0]); | |
967 | /* if SSC used set by 1st enable */ | |
968 | writel_relaxed(misc1_val & (~PLLDSS_MISC1_CFG_EN_SSC), | |
969 | clk_base + plldss->params->ext_misc_reg[1]); | |
970 | writel_relaxed(misc2_val, clk_base + plldss->params->ext_misc_reg[2]); | |
971 | writel_relaxed(misc3_val, clk_base + plldss->params->ext_misc_reg[3]); | |
972 | udelay(1); | |
973 | } | |
974 | ||
fd360e20 | 975 | static void tegra210_plld2_set_defaults(struct tegra_clk_pll *plld2) |
6b301a05 RK |
976 | { |
977 | plldss_defaults("PLL_D2", plld2, PLLD2_MISC0_DEFAULT_VALUE, | |
978 | PLLD2_MISC1_CFG_DEFAULT_VALUE, | |
979 | PLLD2_MISC2_CTRL1_DEFAULT_VALUE, | |
980 | PLLD2_MISC3_CTRL2_DEFAULT_VALUE); | |
981 | } | |
982 | ||
fd360e20 | 983 | static void tegra210_plldp_set_defaults(struct tegra_clk_pll *plldp) |
6b301a05 RK |
984 | { |
985 | plldss_defaults("PLL_DP", plldp, PLLDP_MISC0_DEFAULT_VALUE, | |
986 | PLLDP_MISC1_CFG_DEFAULT_VALUE, | |
987 | PLLDP_MISC2_CTRL1_DEFAULT_VALUE, | |
988 | PLLDP_MISC3_CTRL2_DEFAULT_VALUE); | |
989 | } | |
990 | ||
991 | /* | |
992 | * PLLC4 | |
993 | * Base and misc0 layout is the same as PLLD2/PLLDP, but no SDM/SSC support. | |
994 | * VCO is exposed to the clock tree via fixed 1/3 and 1/5 dividers. | |
995 | */ | |
fd360e20 | 996 | static void tegra210_pllc4_set_defaults(struct tegra_clk_pll *pllc4) |
6b301a05 RK |
997 | { |
998 | plldss_defaults("PLL_C4", pllc4, PLLC4_MISC0_DEFAULT_VALUE, 0, 0, 0); | |
999 | } | |
1000 | ||
1001 | /* | |
1002 | * PLLRE | |
1003 | * VCO is exposed to the clock tree directly along with post-divider output | |
1004 | */ | |
fd360e20 | 1005 | static void tegra210_pllre_set_defaults(struct tegra_clk_pll *pllre) |
6b301a05 RK |
1006 | { |
1007 | u32 mask; | |
1008 | u32 val = readl_relaxed(clk_base + pllre->params->base_reg); | |
1009 | ||
1010 | pllre->params->defaults_set = true; | |
1011 | ||
1012 | if (val & PLL_ENABLE) { | |
6b301a05 RK |
1013 | /* |
1014 | * PLL is ON: check if defaults already set, then set those | |
1015 | * that can be updated in flight. | |
1016 | */ | |
1017 | val &= PLLRE_BASE_DEFAULT_MASK; | |
1018 | if (val != PLLRE_BASE_DEFAULT_VALUE) { | |
1019 | pr_warn("pllre boot base 0x%x : expected 0x%x\n", | |
1020 | val, PLLRE_BASE_DEFAULT_VALUE); | |
1021 | pr_warn("(comparison mask = 0x%x)\n", | |
1022 | PLLRE_BASE_DEFAULT_MASK); | |
1023 | pllre->params->defaults_set = false; | |
1024 | } | |
1025 | ||
1026 | /* Ignore lock enable */ | |
1027 | val = PLLRE_MISC0_DEFAULT_VALUE & (~PLLRE_MISC0_IDDQ); | |
1028 | mask = PLLRE_MISC0_LOCK_ENABLE | PLLRE_MISC0_LOCK_OVERRIDE; | |
1029 | _pll_misc_chk_default(clk_base, pllre->params, 0, val, | |
1030 | ~mask & PLLRE_MISC0_WRITE_MASK); | |
1031 | ||
c1139d20 | 1032 | /* The PLL doesn't work if it's in IDDQ. */ |
6b301a05 | 1033 | val = readl_relaxed(clk_base + pllre->params->ext_misc_reg[0]); |
c1139d20 TR |
1034 | if (val & PLLRE_MISC0_IDDQ) |
1035 | pr_warn("unexpected IDDQ bit set for enabled clock\n"); | |
1036 | ||
1037 | /* Enable lock detect */ | |
6b301a05 RK |
1038 | val &= ~mask; |
1039 | val |= PLLRE_MISC0_DEFAULT_VALUE & mask; | |
1040 | writel_relaxed(val, clk_base + pllre->params->ext_misc_reg[0]); | |
1041 | udelay(1); | |
1042 | ||
20675070 TR |
1043 | if (!pllre->params->defaults_set) |
1044 | pr_warn("PLL_RE already enabled. Postponing set full defaults\n"); | |
1045 | ||
6b301a05 RK |
1046 | return; |
1047 | } | |
1048 | ||
1049 | /* set IDDQ, enable lock detect */ | |
1050 | val &= ~PLLRE_BASE_DEFAULT_MASK; | |
1051 | val |= PLLRE_BASE_DEFAULT_VALUE & PLLRE_BASE_DEFAULT_MASK; | |
1052 | writel_relaxed(val, clk_base + pllre->params->base_reg); | |
1053 | writel_relaxed(PLLRE_MISC0_DEFAULT_VALUE, | |
1054 | clk_base + pllre->params->ext_misc_reg[0]); | |
1055 | udelay(1); | |
1056 | } | |
1057 | ||
1058 | static void pllx_get_dyn_steps(struct clk_hw *hw, u32 *step_a, u32 *step_b) | |
1059 | { | |
1060 | unsigned long input_rate; | |
1061 | ||
3dad5c5f RK |
1062 | /* cf rate */ |
1063 | if (!IS_ERR_OR_NULL(hw->clk)) | |
6b301a05 | 1064 | input_rate = clk_hw_get_rate(clk_hw_get_parent(hw)); |
3dad5c5f | 1065 | else |
6b301a05 | 1066 | input_rate = 38400000; |
3dad5c5f RK |
1067 | |
1068 | input_rate /= tegra_pll_get_fixed_mdiv(hw, input_rate); | |
6b301a05 RK |
1069 | |
1070 | switch (input_rate) { | |
1071 | case 12000000: | |
1072 | case 12800000: | |
1073 | case 13000000: | |
1074 | *step_a = 0x2B; | |
1075 | *step_b = 0x0B; | |
1076 | return; | |
1077 | case 19200000: | |
1078 | *step_a = 0x12; | |
1079 | *step_b = 0x08; | |
1080 | return; | |
1081 | case 38400000: | |
1082 | *step_a = 0x04; | |
1083 | *step_b = 0x05; | |
1084 | return; | |
1085 | default: | |
1086 | pr_err("%s: Unexpected reference rate %lu\n", | |
1087 | __func__, input_rate); | |
1088 | BUG(); | |
1089 | } | |
1090 | } | |
1091 | ||
1092 | static void pllx_check_defaults(struct tegra_clk_pll *pll) | |
1093 | { | |
1094 | u32 default_val; | |
1095 | ||
1096 | default_val = PLLX_MISC0_DEFAULT_VALUE; | |
1097 | /* ignore lock enable */ | |
1098 | _pll_misc_chk_default(clk_base, pll->params, 0, default_val, | |
1099 | PLLX_MISC0_WRITE_MASK & (~PLLX_MISC0_LOCK_ENABLE)); | |
1100 | ||
1101 | default_val = PLLX_MISC1_DEFAULT_VALUE; | |
1102 | _pll_misc_chk_default(clk_base, pll->params, 1, default_val, | |
1103 | PLLX_MISC1_WRITE_MASK); | |
1104 | ||
1105 | /* ignore all but control bit */ | |
1106 | default_val = PLLX_MISC2_DEFAULT_VALUE; | |
1107 | _pll_misc_chk_default(clk_base, pll->params, 2, | |
1108 | default_val, PLLX_MISC2_EN_DYNRAMP); | |
1109 | ||
1110 | default_val = PLLX_MISC3_DEFAULT_VALUE & (~PLLX_MISC3_IDDQ); | |
1111 | _pll_misc_chk_default(clk_base, pll->params, 3, default_val, | |
1112 | PLLX_MISC3_WRITE_MASK); | |
1113 | ||
1114 | default_val = PLLX_MISC4_DEFAULT_VALUE; | |
1115 | _pll_misc_chk_default(clk_base, pll->params, 4, default_val, | |
1116 | PLLX_MISC4_WRITE_MASK); | |
1117 | ||
1118 | default_val = PLLX_MISC5_DEFAULT_VALUE; | |
1119 | _pll_misc_chk_default(clk_base, pll->params, 5, default_val, | |
1120 | PLLX_MISC5_WRITE_MASK); | |
1121 | } | |
1122 | ||
fd360e20 | 1123 | static void tegra210_pllx_set_defaults(struct tegra_clk_pll *pllx) |
6b301a05 RK |
1124 | { |
1125 | u32 val; | |
1126 | u32 step_a, step_b; | |
1127 | ||
1128 | pllx->params->defaults_set = true; | |
1129 | ||
1130 | /* Get ready dyn ramp state machine settings */ | |
1131 | pllx_get_dyn_steps(&pllx->hw, &step_a, &step_b); | |
1132 | val = PLLX_MISC2_DEFAULT_VALUE & (~PLLX_MISC2_DYNRAMP_STEPA_MASK) & | |
1133 | (~PLLX_MISC2_DYNRAMP_STEPB_MASK); | |
1134 | val |= step_a << PLLX_MISC2_DYNRAMP_STEPA_SHIFT; | |
1135 | val |= step_b << PLLX_MISC2_DYNRAMP_STEPB_SHIFT; | |
1136 | ||
1137 | if (readl_relaxed(clk_base + pllx->params->base_reg) & PLL_ENABLE) { | |
6b301a05 RK |
1138 | |
1139 | /* | |
1140 | * PLL is ON: check if defaults already set, then set those | |
1141 | * that can be updated in flight. | |
1142 | */ | |
1143 | pllx_check_defaults(pllx); | |
1144 | ||
8dce89a1 PDS |
1145 | if (!pllx->params->defaults_set) |
1146 | pr_warn("PLL_X already enabled. Postponing set full defaults\n"); | |
6b301a05 RK |
1147 | /* Configure dyn ramp, disable lock override */ |
1148 | writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); | |
1149 | ||
1150 | /* Enable lock detect */ | |
1151 | val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[0]); | |
1152 | val &= ~PLLX_MISC0_LOCK_ENABLE; | |
1153 | val |= PLLX_MISC0_DEFAULT_VALUE & PLLX_MISC0_LOCK_ENABLE; | |
1154 | writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[0]); | |
1155 | udelay(1); | |
1156 | ||
1157 | return; | |
1158 | } | |
1159 | ||
1160 | /* Enable lock detect and CPU output */ | |
1161 | writel_relaxed(PLLX_MISC0_DEFAULT_VALUE, clk_base + | |
1162 | pllx->params->ext_misc_reg[0]); | |
1163 | ||
1164 | /* Setup */ | |
1165 | writel_relaxed(PLLX_MISC1_DEFAULT_VALUE, clk_base + | |
1166 | pllx->params->ext_misc_reg[1]); | |
1167 | ||
1168 | /* Configure dyn ramp state machine, disable lock override */ | |
1169 | writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); | |
1170 | ||
1171 | /* Set IDDQ */ | |
1172 | writel_relaxed(PLLX_MISC3_DEFAULT_VALUE, clk_base + | |
1173 | pllx->params->ext_misc_reg[3]); | |
1174 | ||
1175 | /* Disable SDM */ | |
1176 | writel_relaxed(PLLX_MISC4_DEFAULT_VALUE, clk_base + | |
1177 | pllx->params->ext_misc_reg[4]); | |
1178 | writel_relaxed(PLLX_MISC5_DEFAULT_VALUE, clk_base + | |
1179 | pllx->params->ext_misc_reg[5]); | |
1180 | udelay(1); | |
1181 | } | |
1182 | ||
1183 | /* PLLMB */ | |
fd360e20 | 1184 | static void tegra210_pllmb_set_defaults(struct tegra_clk_pll *pllmb) |
6b301a05 RK |
1185 | { |
1186 | u32 mask, val = readl_relaxed(clk_base + pllmb->params->base_reg); | |
1187 | ||
1188 | pllmb->params->defaults_set = true; | |
1189 | ||
1190 | if (val & PLL_ENABLE) { | |
6b301a05 RK |
1191 | |
1192 | /* | |
1193 | * PLL is ON: check if defaults already set, then set those | |
1194 | * that can be updated in flight. | |
1195 | */ | |
474f2ba2 RK |
1196 | val = PLLMB_MISC1_DEFAULT_VALUE & (~PLLMB_MISC1_IDDQ); |
1197 | mask = PLLMB_MISC1_LOCK_ENABLE | PLLMB_MISC1_LOCK_OVERRIDE; | |
6b301a05 | 1198 | _pll_misc_chk_default(clk_base, pllmb->params, 0, val, |
474f2ba2 | 1199 | ~mask & PLLMB_MISC1_WRITE_MASK); |
6b301a05 | 1200 | |
8dce89a1 PDS |
1201 | if (!pllmb->params->defaults_set) |
1202 | pr_warn("PLL_MB already enabled. Postponing set full defaults\n"); | |
6b301a05 RK |
1203 | /* Enable lock detect */ |
1204 | val = readl_relaxed(clk_base + pllmb->params->ext_misc_reg[0]); | |
1205 | val &= ~mask; | |
474f2ba2 | 1206 | val |= PLLMB_MISC1_DEFAULT_VALUE & mask; |
6b301a05 RK |
1207 | writel_relaxed(val, clk_base + pllmb->params->ext_misc_reg[0]); |
1208 | udelay(1); | |
1209 | ||
1210 | return; | |
1211 | } | |
1212 | ||
1213 | /* set IDDQ, enable lock detect */ | |
474f2ba2 | 1214 | writel_relaxed(PLLMB_MISC1_DEFAULT_VALUE, |
6b301a05 RK |
1215 | clk_base + pllmb->params->ext_misc_reg[0]); |
1216 | udelay(1); | |
1217 | } | |
1218 | ||
1219 | /* | |
1220 | * PLLP | |
1221 | * VCO is exposed to the clock tree directly along with post-divider output. | |
1222 | * Both VCO and post-divider output rates are fixed at 408MHz and 204MHz, | |
1223 | * respectively. | |
1224 | */ | |
1225 | static void pllp_check_defaults(struct tegra_clk_pll *pll, bool enabled) | |
1226 | { | |
1227 | u32 val, mask; | |
1228 | ||
1229 | /* Ignore lock enable (will be set), make sure not in IDDQ if enabled */ | |
1230 | val = PLLP_MISC0_DEFAULT_VALUE & (~PLLP_MISC0_IDDQ); | |
1231 | mask = PLLP_MISC0_LOCK_ENABLE | PLLP_MISC0_LOCK_OVERRIDE; | |
1232 | if (!enabled) | |
1233 | mask |= PLLP_MISC0_IDDQ; | |
1234 | _pll_misc_chk_default(clk_base, pll->params, 0, val, | |
1235 | ~mask & PLLP_MISC0_WRITE_MASK); | |
1236 | ||
1237 | /* Ignore branch controls */ | |
1238 | val = PLLP_MISC1_DEFAULT_VALUE; | |
1239 | mask = PLLP_MISC1_HSIO_EN | PLLP_MISC1_XUSB_EN; | |
1240 | _pll_misc_chk_default(clk_base, pll->params, 1, val, | |
1241 | ~mask & PLLP_MISC1_WRITE_MASK); | |
1242 | } | |
1243 | ||
fd360e20 | 1244 | static void tegra210_pllp_set_defaults(struct tegra_clk_pll *pllp) |
6b301a05 RK |
1245 | { |
1246 | u32 mask; | |
1247 | u32 val = readl_relaxed(clk_base + pllp->params->base_reg); | |
1248 | ||
1249 | pllp->params->defaults_set = true; | |
1250 | ||
1251 | if (val & PLL_ENABLE) { | |
6b301a05 RK |
1252 | |
1253 | /* | |
1254 | * PLL is ON: check if defaults already set, then set those | |
1255 | * that can be updated in flight. | |
1256 | */ | |
1257 | pllp_check_defaults(pllp, true); | |
8dce89a1 PDS |
1258 | if (!pllp->params->defaults_set) |
1259 | pr_warn("PLL_P already enabled. Postponing set full defaults\n"); | |
6b301a05 RK |
1260 | |
1261 | /* Enable lock detect */ | |
1262 | val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[0]); | |
1263 | mask = PLLP_MISC0_LOCK_ENABLE | PLLP_MISC0_LOCK_OVERRIDE; | |
1264 | val &= ~mask; | |
1265 | val |= PLLP_MISC0_DEFAULT_VALUE & mask; | |
1266 | writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[0]); | |
1267 | udelay(1); | |
1268 | ||
1269 | return; | |
1270 | } | |
1271 | ||
1272 | /* set IDDQ, enable lock detect */ | |
1273 | writel_relaxed(PLLP_MISC0_DEFAULT_VALUE, | |
1274 | clk_base + pllp->params->ext_misc_reg[0]); | |
1275 | ||
1276 | /* Preserve branch control */ | |
1277 | val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[1]); | |
1278 | mask = PLLP_MISC1_HSIO_EN | PLLP_MISC1_XUSB_EN; | |
1279 | val &= mask; | |
1280 | val |= ~mask & PLLP_MISC1_DEFAULT_VALUE; | |
1281 | writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[1]); | |
1282 | udelay(1); | |
1283 | } | |
1284 | ||
1285 | /* | |
1286 | * PLLU | |
1287 | * VCO is exposed to the clock tree directly along with post-divider output. | |
1288 | * Both VCO and post-divider output rates are fixed at 480MHz and 240MHz, | |
1289 | * respectively. | |
1290 | */ | |
e745f992 PDS |
1291 | static void pllu_check_defaults(struct tegra_clk_pll_params *params, |
1292 | bool hw_control) | |
6b301a05 RK |
1293 | { |
1294 | u32 val, mask; | |
1295 | ||
1296 | /* Ignore lock enable (will be set) and IDDQ if under h/w control */ | |
1297 | val = PLLU_MISC0_DEFAULT_VALUE & (~PLLU_MISC0_IDDQ); | |
1298 | mask = PLLU_MISC0_LOCK_ENABLE | (hw_control ? PLLU_MISC0_IDDQ : 0); | |
e745f992 | 1299 | _pll_misc_chk_default(clk_base, params, 0, val, |
6b301a05 RK |
1300 | ~mask & PLLU_MISC0_WRITE_MASK); |
1301 | ||
1302 | val = PLLU_MISC1_DEFAULT_VALUE; | |
1303 | mask = PLLU_MISC1_LOCK_OVERRIDE; | |
e745f992 | 1304 | _pll_misc_chk_default(clk_base, params, 1, val, |
6b301a05 RK |
1305 | ~mask & PLLU_MISC1_WRITE_MASK); |
1306 | } | |
1307 | ||
e745f992 | 1308 | static void tegra210_pllu_set_defaults(struct tegra_clk_pll_params *pllu) |
6b301a05 | 1309 | { |
e745f992 | 1310 | u32 val = readl_relaxed(clk_base + pllu->base_reg); |
6b301a05 | 1311 | |
e745f992 | 1312 | pllu->defaults_set = true; |
6b301a05 RK |
1313 | |
1314 | if (val & PLL_ENABLE) { | |
6b301a05 RK |
1315 | |
1316 | /* | |
1317 | * PLL is ON: check if defaults already set, then set those | |
1318 | * that can be updated in flight. | |
1319 | */ | |
1320 | pllu_check_defaults(pllu, false); | |
e745f992 | 1321 | if (!pllu->defaults_set) |
8dce89a1 | 1322 | pr_warn("PLL_U already enabled. Postponing set full defaults\n"); |
6b301a05 RK |
1323 | |
1324 | /* Enable lock detect */ | |
e745f992 | 1325 | val = readl_relaxed(clk_base + pllu->ext_misc_reg[0]); |
6b301a05 RK |
1326 | val &= ~PLLU_MISC0_LOCK_ENABLE; |
1327 | val |= PLLU_MISC0_DEFAULT_VALUE & PLLU_MISC0_LOCK_ENABLE; | |
e745f992 | 1328 | writel_relaxed(val, clk_base + pllu->ext_misc_reg[0]); |
6b301a05 | 1329 | |
e745f992 | 1330 | val = readl_relaxed(clk_base + pllu->ext_misc_reg[1]); |
6b301a05 RK |
1331 | val &= ~PLLU_MISC1_LOCK_OVERRIDE; |
1332 | val |= PLLU_MISC1_DEFAULT_VALUE & PLLU_MISC1_LOCK_OVERRIDE; | |
e745f992 | 1333 | writel_relaxed(val, clk_base + pllu->ext_misc_reg[1]); |
6b301a05 RK |
1334 | udelay(1); |
1335 | ||
1336 | return; | |
1337 | } | |
1338 | ||
1339 | /* set IDDQ, enable lock detect */ | |
1340 | writel_relaxed(PLLU_MISC0_DEFAULT_VALUE, | |
e745f992 | 1341 | clk_base + pllu->ext_misc_reg[0]); |
6b301a05 | 1342 | writel_relaxed(PLLU_MISC1_DEFAULT_VALUE, |
e745f992 | 1343 | clk_base + pllu->ext_misc_reg[1]); |
6b301a05 RK |
1344 | udelay(1); |
1345 | } | |
1346 | ||
1347 | #define mask(w) ((1 << (w)) - 1) | |
1348 | #define divm_mask(p) mask(p->params->div_nmp->divm_width) | |
1349 | #define divn_mask(p) mask(p->params->div_nmp->divn_width) | |
1350 | #define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\ | |
1351 | mask(p->params->div_nmp->divp_width)) | |
1352 | ||
1353 | #define divm_shift(p) ((p)->params->div_nmp->divm_shift) | |
1354 | #define divn_shift(p) ((p)->params->div_nmp->divn_shift) | |
1355 | #define divp_shift(p) ((p)->params->div_nmp->divp_shift) | |
1356 | ||
1357 | #define divm_mask_shifted(p) (divm_mask(p) << divm_shift(p)) | |
1358 | #define divn_mask_shifted(p) (divn_mask(p) << divn_shift(p)) | |
1359 | #define divp_mask_shifted(p) (divp_mask(p) << divp_shift(p)) | |
1360 | ||
1361 | #define PLL_LOCKDET_DELAY 2 /* Lock detection safety delays */ | |
1362 | static int tegra210_wait_for_mask(struct tegra_clk_pll *pll, | |
1363 | u32 reg, u32 mask) | |
1364 | { | |
1365 | int i; | |
1366 | u32 val = 0; | |
1367 | ||
1368 | for (i = 0; i < pll->params->lock_delay / PLL_LOCKDET_DELAY + 1; i++) { | |
1369 | udelay(PLL_LOCKDET_DELAY); | |
1370 | val = readl_relaxed(clk_base + reg); | |
1371 | if ((val & mask) == mask) { | |
1372 | udelay(PLL_LOCKDET_DELAY); | |
1373 | return 0; | |
1374 | } | |
1375 | } | |
1376 | return -ETIMEDOUT; | |
1377 | } | |
1378 | ||
1379 | static int tegra210_pllx_dyn_ramp(struct tegra_clk_pll *pllx, | |
1380 | struct tegra_clk_pll_freq_table *cfg) | |
1381 | { | |
1382 | u32 val, base, ndiv_new_mask; | |
1383 | ||
1384 | ndiv_new_mask = (divn_mask(pllx) >> pllx->params->div_nmp->divn_shift) | |
1385 | << PLLX_MISC2_NDIV_NEW_SHIFT; | |
1386 | ||
1387 | val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[2]); | |
1388 | val &= (~ndiv_new_mask); | |
1389 | val |= cfg->n << PLLX_MISC2_NDIV_NEW_SHIFT; | |
1390 | writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); | |
1391 | udelay(1); | |
1392 | ||
1393 | val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[2]); | |
1394 | val |= PLLX_MISC2_EN_DYNRAMP; | |
1395 | writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); | |
1396 | udelay(1); | |
1397 | ||
1398 | tegra210_wait_for_mask(pllx, pllx->params->ext_misc_reg[2], | |
1399 | PLLX_MISC2_DYNRAMP_DONE); | |
1400 | ||
1401 | base = readl_relaxed(clk_base + pllx->params->base_reg) & | |
1402 | (~divn_mask_shifted(pllx)); | |
1403 | base |= cfg->n << pllx->params->div_nmp->divn_shift; | |
1404 | writel_relaxed(base, clk_base + pllx->params->base_reg); | |
1405 | udelay(1); | |
1406 | ||
1407 | val &= ~PLLX_MISC2_EN_DYNRAMP; | |
1408 | writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); | |
1409 | udelay(1); | |
1410 | ||
1411 | pr_debug("%s: dynamic ramp to m = %u n = %u p = %u, Fout = %lu kHz\n", | |
1412 | __clk_get_name(pllx->hw.clk), cfg->m, cfg->n, cfg->p, | |
1413 | cfg->input_rate / cfg->m * cfg->n / | |
1414 | pllx->params->pdiv_tohw[cfg->p].pdiv / 1000); | |
1415 | ||
1416 | return 0; | |
1417 | } | |
1418 | ||
1419 | /* | |
1420 | * Common configuration for PLLs with fixed input divider policy: | |
1421 | * - always set fixed M-value based on the reference rate | |
1422 | * - always set P-value value 1:1 for output rates above VCO minimum, and | |
1423 | * choose minimum necessary P-value for output rates below VCO maximum | |
1424 | * - calculate N-value based on selected M and P | |
1425 | * - calculate SDM_DIN fractional part | |
1426 | */ | |
1427 | static int tegra210_pll_fixed_mdiv_cfg(struct clk_hw *hw, | |
1428 | struct tegra_clk_pll_freq_table *cfg, | |
1429 | unsigned long rate, unsigned long input_rate) | |
1430 | { | |
1431 | struct tegra_clk_pll *pll = to_clk_pll(hw); | |
1432 | struct tegra_clk_pll_params *params = pll->params; | |
1433 | int p; | |
1434 | unsigned long cf, p_rate; | |
1435 | u32 pdiv; | |
1436 | ||
1437 | if (!rate) | |
1438 | return -EINVAL; | |
1439 | ||
1440 | if (!(params->flags & TEGRA_PLL_VCO_OUT)) { | |
1441 | p = DIV_ROUND_UP(params->vco_min, rate); | |
1442 | p = params->round_p_to_pdiv(p, &pdiv); | |
1443 | } else { | |
1444 | p = rate >= params->vco_min ? 1 : -EINVAL; | |
1445 | } | |
1446 | ||
287980e4 | 1447 | if (p < 0) |
6b301a05 RK |
1448 | return -EINVAL; |
1449 | ||
1450 | cfg->m = tegra_pll_get_fixed_mdiv(hw, input_rate); | |
1451 | cfg->p = p; | |
1452 | ||
1453 | /* Store P as HW value, as that is what is expected */ | |
1454 | cfg->p = tegra_pll_p_div_to_hw(pll, cfg->p); | |
1455 | ||
1456 | p_rate = rate * p; | |
1457 | if (p_rate > params->vco_max) | |
1458 | p_rate = params->vco_max; | |
1459 | cf = input_rate / cfg->m; | |
1460 | cfg->n = p_rate / cf; | |
1461 | ||
1462 | cfg->sdm_data = 0; | |
ef6ed2b9 | 1463 | cfg->output_rate = input_rate; |
6b301a05 RK |
1464 | if (params->sdm_ctrl_reg) { |
1465 | unsigned long rem = p_rate - cf * cfg->n; | |
1466 | /* If ssc is enabled SDM enabled as well, even for integer n */ | |
1467 | if (rem || params->ssc_ctrl_reg) { | |
1468 | u64 s = rem * PLL_SDM_COEFF; | |
1469 | ||
1470 | do_div(s, cf); | |
1471 | s -= PLL_SDM_COEFF / 2; | |
1472 | cfg->sdm_data = sdin_din_to_data(s); | |
1473 | } | |
a851ea2b | 1474 | cfg->output_rate *= sdin_get_n_eff(cfg); |
ef6ed2b9 PDS |
1475 | cfg->output_rate /= p * cfg->m * PLL_SDM_COEFF; |
1476 | } else { | |
1477 | cfg->output_rate *= cfg->n; | |
1478 | cfg->output_rate /= p * cfg->m; | |
6b301a05 RK |
1479 | } |
1480 | ||
1481 | cfg->input_rate = input_rate; | |
6b301a05 RK |
1482 | |
1483 | return 0; | |
1484 | } | |
1485 | ||
1486 | /* | |
1487 | * clk_pll_set_gain - set gain to m, n to calculate correct VCO rate | |
1488 | * | |
1489 | * @cfg: struct tegra_clk_pll_freq_table * cfg | |
1490 | * | |
1491 | * For Normal mode: | |
1492 | * Fvco = Fref * NDIV / MDIV | |
1493 | * | |
1494 | * For fractional mode: | |
1495 | * Fvco = Fref * (NDIV + 0.5 + SDM_DIN / PLL_SDM_COEFF) / MDIV | |
1496 | */ | |
1497 | static void tegra210_clk_pll_set_gain(struct tegra_clk_pll_freq_table *cfg) | |
1498 | { | |
a851ea2b | 1499 | cfg->n = sdin_get_n_eff(cfg); |
6b301a05 RK |
1500 | cfg->m *= PLL_SDM_COEFF; |
1501 | } | |
1502 | ||
fd360e20 JH |
1503 | static unsigned long |
1504 | tegra210_clk_adjust_vco_min(struct tegra_clk_pll_params *params, | |
1505 | unsigned long parent_rate) | |
6b301a05 RK |
1506 | { |
1507 | unsigned long vco_min = params->vco_min; | |
1508 | ||
1509 | params->vco_min += DIV_ROUND_UP(parent_rate, PLL_SDM_COEFF); | |
1510 | vco_min = min(vco_min, params->vco_min); | |
1511 | ||
1512 | return vco_min; | |
1513 | } | |
1514 | ||
1515 | static struct div_nmp pllx_nmp = { | |
1516 | .divm_shift = 0, | |
1517 | .divm_width = 8, | |
1518 | .divn_shift = 8, | |
1519 | .divn_width = 8, | |
1520 | .divp_shift = 20, | |
1521 | .divp_width = 5, | |
1522 | }; | |
1523 | /* | |
1524 | * PLL post divider maps - two types: quasi-linear and exponential | |
1525 | * post divider. | |
1526 | */ | |
1527 | #define PLL_QLIN_PDIV_MAX 16 | |
1528 | static const struct pdiv_map pll_qlin_pdiv_to_hw[] = { | |
1529 | { .pdiv = 1, .hw_val = 0 }, | |
1530 | { .pdiv = 2, .hw_val = 1 }, | |
1531 | { .pdiv = 3, .hw_val = 2 }, | |
1532 | { .pdiv = 4, .hw_val = 3 }, | |
1533 | { .pdiv = 5, .hw_val = 4 }, | |
1534 | { .pdiv = 6, .hw_val = 5 }, | |
1535 | { .pdiv = 8, .hw_val = 6 }, | |
1536 | { .pdiv = 9, .hw_val = 7 }, | |
1537 | { .pdiv = 10, .hw_val = 8 }, | |
1538 | { .pdiv = 12, .hw_val = 9 }, | |
1539 | { .pdiv = 15, .hw_val = 10 }, | |
1540 | { .pdiv = 16, .hw_val = 11 }, | |
1541 | { .pdiv = 18, .hw_val = 12 }, | |
1542 | { .pdiv = 20, .hw_val = 13 }, | |
1543 | { .pdiv = 24, .hw_val = 14 }, | |
1544 | { .pdiv = 30, .hw_val = 15 }, | |
1545 | { .pdiv = 32, .hw_val = 16 }, | |
1546 | }; | |
1547 | ||
1548 | static u32 pll_qlin_p_to_pdiv(u32 p, u32 *pdiv) | |
1549 | { | |
1550 | int i; | |
1551 | ||
1552 | if (p) { | |
1553 | for (i = 0; i <= PLL_QLIN_PDIV_MAX; i++) { | |
1554 | if (p <= pll_qlin_pdiv_to_hw[i].pdiv) { | |
1555 | if (pdiv) | |
1556 | *pdiv = i; | |
1557 | return pll_qlin_pdiv_to_hw[i].pdiv; | |
1558 | } | |
1559 | } | |
1560 | } | |
1561 | ||
1562 | return -EINVAL; | |
1563 | } | |
1564 | ||
1565 | #define PLL_EXPO_PDIV_MAX 7 | |
1566 | static const struct pdiv_map pll_expo_pdiv_to_hw[] = { | |
1567 | { .pdiv = 1, .hw_val = 0 }, | |
1568 | { .pdiv = 2, .hw_val = 1 }, | |
1569 | { .pdiv = 4, .hw_val = 2 }, | |
1570 | { .pdiv = 8, .hw_val = 3 }, | |
1571 | { .pdiv = 16, .hw_val = 4 }, | |
1572 | { .pdiv = 32, .hw_val = 5 }, | |
1573 | { .pdiv = 64, .hw_val = 6 }, | |
1574 | { .pdiv = 128, .hw_val = 7 }, | |
1575 | }; | |
1576 | ||
1577 | static u32 pll_expo_p_to_pdiv(u32 p, u32 *pdiv) | |
1578 | { | |
1579 | if (p) { | |
1580 | u32 i = fls(p); | |
1581 | ||
1582 | if (i == ffs(p)) | |
1583 | i--; | |
1584 | ||
1585 | if (i <= PLL_EXPO_PDIV_MAX) { | |
1586 | if (pdiv) | |
1587 | *pdiv = i; | |
1588 | return 1 << i; | |
1589 | } | |
1590 | } | |
1591 | return -EINVAL; | |
1592 | } | |
1593 | ||
1594 | static struct tegra_clk_pll_freq_table pll_x_freq_table[] = { | |
1595 | /* 1 GHz */ | |
eddb65e7 TR |
1596 | { 12000000, 1000000000, 166, 1, 2, 0 }, /* actual: 996.0 MHz */ |
1597 | { 13000000, 1000000000, 153, 1, 2, 0 }, /* actual: 994.0 MHz */ | |
1598 | { 38400000, 1000000000, 156, 3, 2, 0 }, /* actual: 998.4 MHz */ | |
6b301a05 RK |
1599 | { 0, 0, 0, 0, 0, 0 }, |
1600 | }; | |
1601 | ||
1602 | static struct tegra_clk_pll_params pll_x_params = { | |
1603 | .input_min = 12000000, | |
1604 | .input_max = 800000000, | |
1605 | .cf_min = 12000000, | |
1606 | .cf_max = 38400000, | |
1607 | .vco_min = 1350000000, | |
1608 | .vco_max = 3000000000UL, | |
1609 | .base_reg = PLLX_BASE, | |
1610 | .misc_reg = PLLX_MISC0, | |
1611 | .lock_mask = PLL_BASE_LOCK, | |
1612 | .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, | |
1613 | .lock_delay = 300, | |
1614 | .ext_misc_reg[0] = PLLX_MISC0, | |
1615 | .ext_misc_reg[1] = PLLX_MISC1, | |
1616 | .ext_misc_reg[2] = PLLX_MISC2, | |
1617 | .ext_misc_reg[3] = PLLX_MISC3, | |
1618 | .ext_misc_reg[4] = PLLX_MISC4, | |
1619 | .ext_misc_reg[5] = PLLX_MISC5, | |
1620 | .iddq_reg = PLLX_MISC3, | |
1621 | .iddq_bit_idx = PLLXP_IDDQ_BIT, | |
1622 | .max_p = PLL_QLIN_PDIV_MAX, | |
1623 | .mdiv_default = 2, | |
1624 | .dyn_ramp_reg = PLLX_MISC2, | |
1625 | .stepa_shift = 16, | |
1626 | .stepb_shift = 24, | |
1627 | .round_p_to_pdiv = pll_qlin_p_to_pdiv, | |
1628 | .pdiv_tohw = pll_qlin_pdiv_to_hw, | |
1629 | .div_nmp = &pllx_nmp, | |
1630 | .freq_table = pll_x_freq_table, | |
1631 | .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, | |
1632 | .dyn_ramp = tegra210_pllx_dyn_ramp, | |
1633 | .set_defaults = tegra210_pllx_set_defaults, | |
1634 | .calc_rate = tegra210_pll_fixed_mdiv_cfg, | |
1635 | }; | |
1636 | ||
1637 | static struct div_nmp pllc_nmp = { | |
1638 | .divm_shift = 0, | |
1639 | .divm_width = 8, | |
1640 | .divn_shift = 10, | |
1641 | .divn_width = 8, | |
1642 | .divp_shift = 20, | |
1643 | .divp_width = 5, | |
1644 | }; | |
1645 | ||
1646 | static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = { | |
eddb65e7 TR |
1647 | { 12000000, 510000000, 85, 1, 2, 0 }, |
1648 | { 13000000, 510000000, 78, 1, 2, 0 }, /* actual: 507.0 MHz */ | |
1649 | { 38400000, 510000000, 79, 3, 2, 0 }, /* actual: 505.6 MHz */ | |
6b301a05 RK |
1650 | { 0, 0, 0, 0, 0, 0 }, |
1651 | }; | |
1652 | ||
1653 | static struct tegra_clk_pll_params pll_c_params = { | |
1654 | .input_min = 12000000, | |
1655 | .input_max = 700000000, | |
1656 | .cf_min = 12000000, | |
1657 | .cf_max = 50000000, | |
1658 | .vco_min = 600000000, | |
1659 | .vco_max = 1200000000, | |
1660 | .base_reg = PLLC_BASE, | |
1661 | .misc_reg = PLLC_MISC0, | |
1662 | .lock_mask = PLL_BASE_LOCK, | |
1663 | .lock_delay = 300, | |
1664 | .iddq_reg = PLLC_MISC1, | |
1665 | .iddq_bit_idx = PLLCX_IDDQ_BIT, | |
1666 | .reset_reg = PLLC_MISC0, | |
1667 | .reset_bit_idx = PLLCX_RESET_BIT, | |
1668 | .max_p = PLL_QLIN_PDIV_MAX, | |
1669 | .ext_misc_reg[0] = PLLC_MISC0, | |
1670 | .ext_misc_reg[1] = PLLC_MISC1, | |
1671 | .ext_misc_reg[2] = PLLC_MISC2, | |
1672 | .ext_misc_reg[3] = PLLC_MISC3, | |
1673 | .round_p_to_pdiv = pll_qlin_p_to_pdiv, | |
1674 | .pdiv_tohw = pll_qlin_pdiv_to_hw, | |
1675 | .mdiv_default = 3, | |
1676 | .div_nmp = &pllc_nmp, | |
1677 | .freq_table = pll_cx_freq_table, | |
14050118 | 1678 | .flags = TEGRA_PLL_USE_LOCK, |
6b301a05 RK |
1679 | .set_defaults = _pllc_set_defaults, |
1680 | .calc_rate = tegra210_pll_fixed_mdiv_cfg, | |
1681 | }; | |
1682 | ||
1683 | static struct div_nmp pllcx_nmp = { | |
1684 | .divm_shift = 0, | |
1685 | .divm_width = 8, | |
1686 | .divn_shift = 10, | |
1687 | .divn_width = 8, | |
1688 | .divp_shift = 20, | |
1689 | .divp_width = 5, | |
1690 | }; | |
1691 | ||
1692 | static struct tegra_clk_pll_params pll_c2_params = { | |
1693 | .input_min = 12000000, | |
1694 | .input_max = 700000000, | |
1695 | .cf_min = 12000000, | |
1696 | .cf_max = 50000000, | |
1697 | .vco_min = 600000000, | |
1698 | .vco_max = 1200000000, | |
1699 | .base_reg = PLLC2_BASE, | |
1700 | .misc_reg = PLLC2_MISC0, | |
1701 | .iddq_reg = PLLC2_MISC1, | |
1702 | .iddq_bit_idx = PLLCX_IDDQ_BIT, | |
1703 | .reset_reg = PLLC2_MISC0, | |
1704 | .reset_bit_idx = PLLCX_RESET_BIT, | |
1705 | .lock_mask = PLLCX_BASE_LOCK, | |
1706 | .lock_delay = 300, | |
1707 | .round_p_to_pdiv = pll_qlin_p_to_pdiv, | |
1708 | .pdiv_tohw = pll_qlin_pdiv_to_hw, | |
1709 | .mdiv_default = 3, | |
1710 | .div_nmp = &pllcx_nmp, | |
1711 | .max_p = PLL_QLIN_PDIV_MAX, | |
1712 | .ext_misc_reg[0] = PLLC2_MISC0, | |
1713 | .ext_misc_reg[1] = PLLC2_MISC1, | |
1714 | .ext_misc_reg[2] = PLLC2_MISC2, | |
1715 | .ext_misc_reg[3] = PLLC2_MISC3, | |
1716 | .freq_table = pll_cx_freq_table, | |
14050118 | 1717 | .flags = TEGRA_PLL_USE_LOCK, |
6b301a05 RK |
1718 | .set_defaults = _pllc2_set_defaults, |
1719 | .calc_rate = tegra210_pll_fixed_mdiv_cfg, | |
1720 | }; | |
1721 | ||
1722 | static struct tegra_clk_pll_params pll_c3_params = { | |
1723 | .input_min = 12000000, | |
1724 | .input_max = 700000000, | |
1725 | .cf_min = 12000000, | |
1726 | .cf_max = 50000000, | |
1727 | .vco_min = 600000000, | |
1728 | .vco_max = 1200000000, | |
1729 | .base_reg = PLLC3_BASE, | |
1730 | .misc_reg = PLLC3_MISC0, | |
1731 | .lock_mask = PLLCX_BASE_LOCK, | |
1732 | .lock_delay = 300, | |
1733 | .iddq_reg = PLLC3_MISC1, | |
1734 | .iddq_bit_idx = PLLCX_IDDQ_BIT, | |
1735 | .reset_reg = PLLC3_MISC0, | |
1736 | .reset_bit_idx = PLLCX_RESET_BIT, | |
1737 | .round_p_to_pdiv = pll_qlin_p_to_pdiv, | |
1738 | .pdiv_tohw = pll_qlin_pdiv_to_hw, | |
1739 | .mdiv_default = 3, | |
1740 | .div_nmp = &pllcx_nmp, | |
1741 | .max_p = PLL_QLIN_PDIV_MAX, | |
1742 | .ext_misc_reg[0] = PLLC3_MISC0, | |
1743 | .ext_misc_reg[1] = PLLC3_MISC1, | |
1744 | .ext_misc_reg[2] = PLLC3_MISC2, | |
1745 | .ext_misc_reg[3] = PLLC3_MISC3, | |
1746 | .freq_table = pll_cx_freq_table, | |
14050118 | 1747 | .flags = TEGRA_PLL_USE_LOCK, |
6b301a05 RK |
1748 | .set_defaults = _pllc3_set_defaults, |
1749 | .calc_rate = tegra210_pll_fixed_mdiv_cfg, | |
1750 | }; | |
1751 | ||
1752 | static struct div_nmp pllss_nmp = { | |
1753 | .divm_shift = 0, | |
1754 | .divm_width = 8, | |
1755 | .divn_shift = 8, | |
1756 | .divn_width = 8, | |
1757 | .divp_shift = 19, | |
1758 | .divp_width = 5, | |
1759 | }; | |
1760 | ||
1761 | static struct tegra_clk_pll_freq_table pll_c4_vco_freq_table[] = { | |
eddb65e7 TR |
1762 | { 12000000, 600000000, 50, 1, 1, 0 }, |
1763 | { 13000000, 600000000, 46, 1, 1, 0 }, /* actual: 598.0 MHz */ | |
1764 | { 38400000, 600000000, 62, 4, 1, 0 }, /* actual: 595.2 MHz */ | |
6b301a05 RK |
1765 | { 0, 0, 0, 0, 0, 0 }, |
1766 | }; | |
1767 | ||
1768 | static const struct clk_div_table pll_vco_post_div_table[] = { | |
1769 | { .val = 0, .div = 1 }, | |
1770 | { .val = 1, .div = 2 }, | |
1771 | { .val = 2, .div = 3 }, | |
1772 | { .val = 3, .div = 4 }, | |
1773 | { .val = 4, .div = 5 }, | |
1774 | { .val = 5, .div = 6 }, | |
1775 | { .val = 6, .div = 8 }, | |
1776 | { .val = 7, .div = 10 }, | |
1777 | { .val = 8, .div = 12 }, | |
1778 | { .val = 9, .div = 16 }, | |
1779 | { .val = 10, .div = 12 }, | |
1780 | { .val = 11, .div = 16 }, | |
1781 | { .val = 12, .div = 20 }, | |
1782 | { .val = 13, .div = 24 }, | |
1783 | { .val = 14, .div = 32 }, | |
1784 | { .val = 0, .div = 0 }, | |
1785 | }; | |
1786 | ||
1787 | static struct tegra_clk_pll_params pll_c4_vco_params = { | |
1788 | .input_min = 9600000, | |
1789 | .input_max = 800000000, | |
1790 | .cf_min = 9600000, | |
1791 | .cf_max = 19200000, | |
1792 | .vco_min = 500000000, | |
1793 | .vco_max = 1080000000, | |
1794 | .base_reg = PLLC4_BASE, | |
1795 | .misc_reg = PLLC4_MISC0, | |
1796 | .lock_mask = PLL_BASE_LOCK, | |
6b301a05 RK |
1797 | .lock_delay = 300, |
1798 | .max_p = PLL_QLIN_PDIV_MAX, | |
1799 | .ext_misc_reg[0] = PLLC4_MISC0, | |
1800 | .iddq_reg = PLLC4_BASE, | |
1801 | .iddq_bit_idx = PLLSS_IDDQ_BIT, | |
1802 | .round_p_to_pdiv = pll_qlin_p_to_pdiv, | |
1803 | .pdiv_tohw = pll_qlin_pdiv_to_hw, | |
1804 | .mdiv_default = 3, | |
1805 | .div_nmp = &pllss_nmp, | |
1806 | .freq_table = pll_c4_vco_freq_table, | |
1807 | .set_defaults = tegra210_pllc4_set_defaults, | |
14050118 | 1808 | .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT, |
6b301a05 RK |
1809 | .calc_rate = tegra210_pll_fixed_mdiv_cfg, |
1810 | }; | |
1811 | ||
1812 | static struct tegra_clk_pll_freq_table pll_m_freq_table[] = { | |
eddb65e7 TR |
1813 | { 12000000, 800000000, 66, 1, 1, 0 }, /* actual: 792.0 MHz */ |
1814 | { 13000000, 800000000, 61, 1, 1, 0 }, /* actual: 793.0 MHz */ | |
1815 | { 38400000, 297600000, 93, 4, 3, 0 }, | |
1816 | { 38400000, 400000000, 125, 4, 3, 0 }, | |
1817 | { 38400000, 532800000, 111, 4, 2, 0 }, | |
1818 | { 38400000, 665600000, 104, 3, 2, 0 }, | |
1819 | { 38400000, 800000000, 125, 3, 2, 0 }, | |
1820 | { 38400000, 931200000, 97, 4, 1, 0 }, | |
1821 | { 38400000, 1065600000, 111, 4, 1, 0 }, | |
1822 | { 38400000, 1200000000, 125, 4, 1, 0 }, | |
1823 | { 38400000, 1331200000, 104, 3, 1, 0 }, | |
1824 | { 38400000, 1459200000, 76, 2, 1, 0 }, | |
1825 | { 38400000, 1600000000, 125, 3, 1, 0 }, | |
6b301a05 RK |
1826 | { 0, 0, 0, 0, 0, 0 }, |
1827 | }; | |
1828 | ||
1829 | static struct div_nmp pllm_nmp = { | |
1830 | .divm_shift = 0, | |
1831 | .divm_width = 8, | |
1832 | .override_divm_shift = 0, | |
1833 | .divn_shift = 8, | |
1834 | .divn_width = 8, | |
1835 | .override_divn_shift = 8, | |
1836 | .divp_shift = 20, | |
1837 | .divp_width = 5, | |
1838 | .override_divp_shift = 27, | |
1839 | }; | |
1840 | ||
1841 | static struct tegra_clk_pll_params pll_m_params = { | |
1842 | .input_min = 9600000, | |
1843 | .input_max = 500000000, | |
1844 | .cf_min = 9600000, | |
1845 | .cf_max = 19200000, | |
1846 | .vco_min = 800000000, | |
1847 | .vco_max = 1866000000, | |
1848 | .base_reg = PLLM_BASE, | |
474f2ba2 | 1849 | .misc_reg = PLLM_MISC2, |
6b301a05 RK |
1850 | .lock_mask = PLL_BASE_LOCK, |
1851 | .lock_enable_bit_idx = PLLM_MISC_LOCK_ENABLE, | |
1852 | .lock_delay = 300, | |
474f2ba2 | 1853 | .iddq_reg = PLLM_MISC2, |
6b301a05 RK |
1854 | .iddq_bit_idx = PLLM_IDDQ_BIT, |
1855 | .max_p = PLL_QLIN_PDIV_MAX, | |
474f2ba2 | 1856 | .ext_misc_reg[0] = PLLM_MISC2, |
d9e65791 | 1857 | .ext_misc_reg[1] = PLLM_MISC1, |
6b301a05 RK |
1858 | .round_p_to_pdiv = pll_qlin_p_to_pdiv, |
1859 | .pdiv_tohw = pll_qlin_pdiv_to_hw, | |
1860 | .div_nmp = &pllm_nmp, | |
1861 | .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE, | |
1862 | .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2, | |
1863 | .freq_table = pll_m_freq_table, | |
1864 | .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, | |
1865 | .calc_rate = tegra210_pll_fixed_mdiv_cfg, | |
1866 | }; | |
1867 | ||
1868 | static struct tegra_clk_pll_params pll_mb_params = { | |
1869 | .input_min = 9600000, | |
1870 | .input_max = 500000000, | |
1871 | .cf_min = 9600000, | |
1872 | .cf_max = 19200000, | |
1873 | .vco_min = 800000000, | |
1874 | .vco_max = 1866000000, | |
1875 | .base_reg = PLLMB_BASE, | |
474f2ba2 | 1876 | .misc_reg = PLLMB_MISC1, |
6b301a05 | 1877 | .lock_mask = PLL_BASE_LOCK, |
6b301a05 | 1878 | .lock_delay = 300, |
474f2ba2 | 1879 | .iddq_reg = PLLMB_MISC1, |
6b301a05 RK |
1880 | .iddq_bit_idx = PLLMB_IDDQ_BIT, |
1881 | .max_p = PLL_QLIN_PDIV_MAX, | |
474f2ba2 | 1882 | .ext_misc_reg[0] = PLLMB_MISC1, |
6b301a05 RK |
1883 | .round_p_to_pdiv = pll_qlin_p_to_pdiv, |
1884 | .pdiv_tohw = pll_qlin_pdiv_to_hw, | |
1885 | .div_nmp = &pllm_nmp, | |
1886 | .freq_table = pll_m_freq_table, | |
14050118 | 1887 | .flags = TEGRA_PLL_USE_LOCK, |
6b301a05 RK |
1888 | .set_defaults = tegra210_pllmb_set_defaults, |
1889 | .calc_rate = tegra210_pll_fixed_mdiv_cfg, | |
1890 | }; | |
1891 | ||
1892 | ||
1893 | static struct tegra_clk_pll_freq_table pll_e_freq_table[] = { | |
1894 | /* PLLE special case: use cpcon field to store cml divider value */ | |
1895 | { 672000000, 100000000, 125, 42, 0, 13 }, | |
1896 | { 624000000, 100000000, 125, 39, 0, 13 }, | |
1897 | { 336000000, 100000000, 125, 21, 0, 13 }, | |
1898 | { 312000000, 100000000, 200, 26, 0, 14 }, | |
1899 | { 38400000, 100000000, 125, 2, 0, 14 }, | |
1900 | { 12000000, 100000000, 200, 1, 0, 14 }, | |
1901 | { 0, 0, 0, 0, 0, 0 }, | |
1902 | }; | |
1903 | ||
1904 | static struct div_nmp plle_nmp = { | |
1905 | .divm_shift = 0, | |
1906 | .divm_width = 8, | |
1907 | .divn_shift = 8, | |
1908 | .divn_width = 8, | |
1909 | .divp_shift = 24, | |
1910 | .divp_width = 5, | |
1911 | }; | |
1912 | ||
1913 | static struct tegra_clk_pll_params pll_e_params = { | |
1914 | .input_min = 12000000, | |
1915 | .input_max = 800000000, | |
1916 | .cf_min = 12000000, | |
1917 | .cf_max = 38400000, | |
1918 | .vco_min = 1600000000, | |
1919 | .vco_max = 2500000000U, | |
1920 | .base_reg = PLLE_BASE, | |
1921 | .misc_reg = PLLE_MISC0, | |
1922 | .aux_reg = PLLE_AUX, | |
1923 | .lock_mask = PLLE_MISC_LOCK, | |
1924 | .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, | |
1925 | .lock_delay = 300, | |
1926 | .div_nmp = &plle_nmp, | |
1927 | .freq_table = pll_e_freq_table, | |
1928 | .flags = TEGRA_PLL_FIXED | TEGRA_PLL_LOCK_MISC | TEGRA_PLL_USE_LOCK | | |
1929 | TEGRA_PLL_HAS_LOCK_ENABLE, | |
1930 | .fixed_rate = 100000000, | |
1931 | .calc_rate = tegra210_pll_fixed_mdiv_cfg, | |
1932 | }; | |
1933 | ||
1934 | static struct tegra_clk_pll_freq_table pll_re_vco_freq_table[] = { | |
eddb65e7 TR |
1935 | { 12000000, 672000000, 56, 1, 1, 0 }, |
1936 | { 13000000, 672000000, 51, 1, 1, 0 }, /* actual: 663.0 MHz */ | |
1937 | { 38400000, 672000000, 70, 4, 1, 0 }, | |
6b301a05 RK |
1938 | { 0, 0, 0, 0, 0, 0 }, |
1939 | }; | |
1940 | ||
1941 | static struct div_nmp pllre_nmp = { | |
1942 | .divm_shift = 0, | |
1943 | .divm_width = 8, | |
1944 | .divn_shift = 8, | |
1945 | .divn_width = 8, | |
1946 | .divp_shift = 16, | |
1947 | .divp_width = 5, | |
1948 | }; | |
1949 | ||
1950 | static struct tegra_clk_pll_params pll_re_vco_params = { | |
1951 | .input_min = 9600000, | |
1952 | .input_max = 800000000, | |
1953 | .cf_min = 9600000, | |
1954 | .cf_max = 19200000, | |
1955 | .vco_min = 350000000, | |
1956 | .vco_max = 700000000, | |
1957 | .base_reg = PLLRE_BASE, | |
1958 | .misc_reg = PLLRE_MISC0, | |
1959 | .lock_mask = PLLRE_MISC_LOCK, | |
6b301a05 RK |
1960 | .lock_delay = 300, |
1961 | .max_p = PLL_QLIN_PDIV_MAX, | |
1962 | .ext_misc_reg[0] = PLLRE_MISC0, | |
1963 | .iddq_reg = PLLRE_MISC0, | |
1964 | .iddq_bit_idx = PLLRE_IDDQ_BIT, | |
1965 | .round_p_to_pdiv = pll_qlin_p_to_pdiv, | |
1966 | .pdiv_tohw = pll_qlin_pdiv_to_hw, | |
1967 | .div_nmp = &pllre_nmp, | |
1968 | .freq_table = pll_re_vco_freq_table, | |
14050118 | 1969 | .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_LOCK_MISC | TEGRA_PLL_VCO_OUT, |
6b301a05 RK |
1970 | .set_defaults = tegra210_pllre_set_defaults, |
1971 | .calc_rate = tegra210_pll_fixed_mdiv_cfg, | |
1972 | }; | |
1973 | ||
1974 | static struct div_nmp pllp_nmp = { | |
1975 | .divm_shift = 0, | |
1976 | .divm_width = 8, | |
1977 | .divn_shift = 10, | |
1978 | .divn_width = 8, | |
1979 | .divp_shift = 20, | |
1980 | .divp_width = 5, | |
1981 | }; | |
1982 | ||
1983 | static struct tegra_clk_pll_freq_table pll_p_freq_table[] = { | |
eddb65e7 TR |
1984 | { 12000000, 408000000, 34, 1, 1, 0 }, |
1985 | { 38400000, 408000000, 85, 8, 1, 0 }, /* cf = 4.8MHz, allowed exception */ | |
6b301a05 RK |
1986 | { 0, 0, 0, 0, 0, 0 }, |
1987 | }; | |
1988 | ||
1989 | static struct tegra_clk_pll_params pll_p_params = { | |
1990 | .input_min = 9600000, | |
1991 | .input_max = 800000000, | |
1992 | .cf_min = 9600000, | |
1993 | .cf_max = 19200000, | |
1994 | .vco_min = 350000000, | |
1995 | .vco_max = 700000000, | |
1996 | .base_reg = PLLP_BASE, | |
1997 | .misc_reg = PLLP_MISC0, | |
1998 | .lock_mask = PLL_BASE_LOCK, | |
6b301a05 RK |
1999 | .lock_delay = 300, |
2000 | .iddq_reg = PLLP_MISC0, | |
2001 | .iddq_bit_idx = PLLXP_IDDQ_BIT, | |
2002 | .ext_misc_reg[0] = PLLP_MISC0, | |
2003 | .ext_misc_reg[1] = PLLP_MISC1, | |
2004 | .div_nmp = &pllp_nmp, | |
2005 | .freq_table = pll_p_freq_table, | |
2006 | .fixed_rate = 408000000, | |
14050118 | 2007 | .flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT, |
6b301a05 RK |
2008 | .set_defaults = tegra210_pllp_set_defaults, |
2009 | .calc_rate = tegra210_pll_fixed_mdiv_cfg, | |
2010 | }; | |
2011 | ||
2012 | static struct tegra_clk_pll_params pll_a1_params = { | |
2013 | .input_min = 12000000, | |
2014 | .input_max = 700000000, | |
2015 | .cf_min = 12000000, | |
2016 | .cf_max = 50000000, | |
2017 | .vco_min = 600000000, | |
2018 | .vco_max = 1200000000, | |
2019 | .base_reg = PLLA1_BASE, | |
2020 | .misc_reg = PLLA1_MISC0, | |
2021 | .lock_mask = PLLCX_BASE_LOCK, | |
2022 | .lock_delay = 300, | |
9326947f | 2023 | .iddq_reg = PLLA1_MISC1, |
6b301a05 RK |
2024 | .iddq_bit_idx = PLLCX_IDDQ_BIT, |
2025 | .reset_reg = PLLA1_MISC0, | |
2026 | .reset_bit_idx = PLLCX_RESET_BIT, | |
2027 | .round_p_to_pdiv = pll_qlin_p_to_pdiv, | |
2028 | .pdiv_tohw = pll_qlin_pdiv_to_hw, | |
2029 | .div_nmp = &pllc_nmp, | |
2030 | .ext_misc_reg[0] = PLLA1_MISC0, | |
2031 | .ext_misc_reg[1] = PLLA1_MISC1, | |
2032 | .ext_misc_reg[2] = PLLA1_MISC2, | |
2033 | .ext_misc_reg[3] = PLLA1_MISC3, | |
2034 | .freq_table = pll_cx_freq_table, | |
14050118 | 2035 | .flags = TEGRA_PLL_USE_LOCK, |
6b301a05 RK |
2036 | .set_defaults = _plla1_set_defaults, |
2037 | .calc_rate = tegra210_pll_fixed_mdiv_cfg, | |
2038 | }; | |
2039 | ||
2040 | static struct div_nmp plla_nmp = { | |
2041 | .divm_shift = 0, | |
2042 | .divm_width = 8, | |
2043 | .divn_shift = 8, | |
2044 | .divn_width = 8, | |
2045 | .divp_shift = 20, | |
2046 | .divp_width = 5, | |
2047 | }; | |
2048 | ||
2049 | static struct tegra_clk_pll_freq_table pll_a_freq_table[] = { | |
eddb65e7 TR |
2050 | { 12000000, 282240000, 47, 1, 2, 1, 0xf148 }, /* actual: 282240234 */ |
2051 | { 12000000, 368640000, 61, 1, 2, 1, 0xfe15 }, /* actual: 368640381 */ | |
2052 | { 12000000, 240000000, 60, 1, 3, 1, 0 }, | |
2053 | { 13000000, 282240000, 43, 1, 2, 1, 0xfd7d }, /* actual: 282239807 */ | |
2054 | { 13000000, 368640000, 56, 1, 2, 1, 0x06d8 }, /* actual: 368640137 */ | |
2055 | { 13000000, 240000000, 55, 1, 3, 1, 0 }, /* actual: 238.3 MHz */ | |
2056 | { 38400000, 282240000, 44, 3, 2, 1, 0xf333 }, /* actual: 282239844 */ | |
2057 | { 38400000, 368640000, 57, 3, 2, 1, 0x0333 }, /* actual: 368639844 */ | |
6b301a05 RK |
2058 | { 38400000, 240000000, 75, 3, 3, 1, 0 }, |
2059 | { 0, 0, 0, 0, 0, 0, 0 }, | |
2060 | }; | |
2061 | ||
2062 | static struct tegra_clk_pll_params pll_a_params = { | |
2063 | .input_min = 12000000, | |
2064 | .input_max = 800000000, | |
2065 | .cf_min = 12000000, | |
2066 | .cf_max = 19200000, | |
2067 | .vco_min = 500000000, | |
2068 | .vco_max = 1000000000, | |
2069 | .base_reg = PLLA_BASE, | |
2070 | .misc_reg = PLLA_MISC0, | |
2071 | .lock_mask = PLL_BASE_LOCK, | |
6b301a05 RK |
2072 | .lock_delay = 300, |
2073 | .round_p_to_pdiv = pll_qlin_p_to_pdiv, | |
2074 | .pdiv_tohw = pll_qlin_pdiv_to_hw, | |
2075 | .iddq_reg = PLLA_BASE, | |
2076 | .iddq_bit_idx = PLLA_IDDQ_BIT, | |
2077 | .div_nmp = &plla_nmp, | |
2078 | .sdm_din_reg = PLLA_MISC1, | |
2079 | .sdm_din_mask = PLLA_SDM_DIN_MASK, | |
2080 | .sdm_ctrl_reg = PLLA_MISC2, | |
2081 | .sdm_ctrl_en_mask = PLLA_SDM_EN_MASK, | |
2082 | .ext_misc_reg[0] = PLLA_MISC0, | |
2083 | .ext_misc_reg[1] = PLLA_MISC1, | |
2084 | .ext_misc_reg[2] = PLLA_MISC2, | |
2085 | .freq_table = pll_a_freq_table, | |
14050118 | 2086 | .flags = TEGRA_PLL_USE_LOCK | TEGRA_MDIV_NEW, |
6b301a05 RK |
2087 | .set_defaults = tegra210_plla_set_defaults, |
2088 | .calc_rate = tegra210_pll_fixed_mdiv_cfg, | |
2089 | .set_gain = tegra210_clk_pll_set_gain, | |
2090 | .adjust_vco = tegra210_clk_adjust_vco_min, | |
2091 | }; | |
2092 | ||
2093 | static struct div_nmp plld_nmp = { | |
2094 | .divm_shift = 0, | |
2095 | .divm_width = 8, | |
2096 | .divn_shift = 11, | |
2097 | .divn_width = 8, | |
2098 | .divp_shift = 20, | |
2099 | .divp_width = 3, | |
2100 | }; | |
2101 | ||
2102 | static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { | |
eddb65e7 TR |
2103 | { 12000000, 594000000, 99, 1, 2, 0, 0 }, |
2104 | { 13000000, 594000000, 91, 1, 2, 0, 0xfc4f }, /* actual: 594000183 */ | |
2105 | { 38400000, 594000000, 30, 1, 2, 0, 0x0e00 }, | |
6b301a05 RK |
2106 | { 0, 0, 0, 0, 0, 0, 0 }, |
2107 | }; | |
2108 | ||
2109 | static struct tegra_clk_pll_params pll_d_params = { | |
2110 | .input_min = 12000000, | |
2111 | .input_max = 800000000, | |
2112 | .cf_min = 12000000, | |
2113 | .cf_max = 38400000, | |
2114 | .vco_min = 750000000, | |
2115 | .vco_max = 1500000000, | |
2116 | .base_reg = PLLD_BASE, | |
2117 | .misc_reg = PLLD_MISC0, | |
2118 | .lock_mask = PLL_BASE_LOCK, | |
6b301a05 RK |
2119 | .lock_delay = 1000, |
2120 | .iddq_reg = PLLD_MISC0, | |
2121 | .iddq_bit_idx = PLLD_IDDQ_BIT, | |
2122 | .round_p_to_pdiv = pll_expo_p_to_pdiv, | |
2123 | .pdiv_tohw = pll_expo_pdiv_to_hw, | |
2124 | .div_nmp = &plld_nmp, | |
2125 | .sdm_din_reg = PLLD_MISC0, | |
2126 | .sdm_din_mask = PLLA_SDM_DIN_MASK, | |
2127 | .sdm_ctrl_reg = PLLD_MISC0, | |
2128 | .sdm_ctrl_en_mask = PLLD_SDM_EN_MASK, | |
2129 | .ext_misc_reg[0] = PLLD_MISC0, | |
2130 | .ext_misc_reg[1] = PLLD_MISC1, | |
2131 | .freq_table = pll_d_freq_table, | |
14050118 | 2132 | .flags = TEGRA_PLL_USE_LOCK, |
6b301a05 RK |
2133 | .mdiv_default = 1, |
2134 | .set_defaults = tegra210_plld_set_defaults, | |
2135 | .calc_rate = tegra210_pll_fixed_mdiv_cfg, | |
2136 | .set_gain = tegra210_clk_pll_set_gain, | |
2137 | .adjust_vco = tegra210_clk_adjust_vco_min, | |
2138 | }; | |
2139 | ||
2140 | static struct tegra_clk_pll_freq_table tegra210_pll_d2_freq_table[] = { | |
eddb65e7 TR |
2141 | { 12000000, 594000000, 99, 1, 2, 0, 0xf000 }, |
2142 | { 13000000, 594000000, 91, 1, 2, 0, 0xfc4f }, /* actual: 594000183 */ | |
2143 | { 38400000, 594000000, 30, 1, 2, 0, 0x0e00 }, | |
6b301a05 RK |
2144 | { 0, 0, 0, 0, 0, 0, 0 }, |
2145 | }; | |
2146 | ||
2147 | /* s/w policy, always tegra_pll_ref */ | |
2148 | static struct tegra_clk_pll_params pll_d2_params = { | |
2149 | .input_min = 12000000, | |
2150 | .input_max = 800000000, | |
2151 | .cf_min = 12000000, | |
2152 | .cf_max = 38400000, | |
2153 | .vco_min = 750000000, | |
2154 | .vco_max = 1500000000, | |
2155 | .base_reg = PLLD2_BASE, | |
2156 | .misc_reg = PLLD2_MISC0, | |
2157 | .lock_mask = PLL_BASE_LOCK, | |
6b301a05 RK |
2158 | .lock_delay = 300, |
2159 | .iddq_reg = PLLD2_BASE, | |
2160 | .iddq_bit_idx = PLLSS_IDDQ_BIT, | |
2161 | .sdm_din_reg = PLLD2_MISC3, | |
2162 | .sdm_din_mask = PLLA_SDM_DIN_MASK, | |
2163 | .sdm_ctrl_reg = PLLD2_MISC1, | |
2164 | .sdm_ctrl_en_mask = PLLD2_SDM_EN_MASK, | |
e2f71656 TR |
2165 | /* disable spread-spectrum for pll_d2 */ |
2166 | .ssc_ctrl_reg = 0, | |
2167 | .ssc_ctrl_en_mask = 0, | |
6b301a05 RK |
2168 | .round_p_to_pdiv = pll_qlin_p_to_pdiv, |
2169 | .pdiv_tohw = pll_qlin_pdiv_to_hw, | |
2170 | .div_nmp = &pllss_nmp, | |
2171 | .ext_misc_reg[0] = PLLD2_MISC0, | |
2172 | .ext_misc_reg[1] = PLLD2_MISC1, | |
2173 | .ext_misc_reg[2] = PLLD2_MISC2, | |
2174 | .ext_misc_reg[3] = PLLD2_MISC3, | |
2175 | .max_p = PLL_QLIN_PDIV_MAX, | |
2176 | .mdiv_default = 1, | |
2177 | .freq_table = tegra210_pll_d2_freq_table, | |
2178 | .set_defaults = tegra210_plld2_set_defaults, | |
14050118 | 2179 | .flags = TEGRA_PLL_USE_LOCK, |
6b301a05 RK |
2180 | .calc_rate = tegra210_pll_fixed_mdiv_cfg, |
2181 | .set_gain = tegra210_clk_pll_set_gain, | |
2182 | .adjust_vco = tegra210_clk_adjust_vco_min, | |
2183 | }; | |
2184 | ||
2185 | static struct tegra_clk_pll_freq_table pll_dp_freq_table[] = { | |
eddb65e7 TR |
2186 | { 12000000, 270000000, 90, 1, 4, 0, 0xf000 }, |
2187 | { 13000000, 270000000, 83, 1, 4, 0, 0xf000 }, /* actual: 269.8 MHz */ | |
2188 | { 38400000, 270000000, 28, 1, 4, 0, 0xf400 }, | |
6b301a05 RK |
2189 | { 0, 0, 0, 0, 0, 0, 0 }, |
2190 | }; | |
2191 | ||
2192 | static struct tegra_clk_pll_params pll_dp_params = { | |
2193 | .input_min = 12000000, | |
2194 | .input_max = 800000000, | |
2195 | .cf_min = 12000000, | |
2196 | .cf_max = 38400000, | |
2197 | .vco_min = 750000000, | |
2198 | .vco_max = 1500000000, | |
2199 | .base_reg = PLLDP_BASE, | |
2200 | .misc_reg = PLLDP_MISC, | |
2201 | .lock_mask = PLL_BASE_LOCK, | |
6b301a05 RK |
2202 | .lock_delay = 300, |
2203 | .iddq_reg = PLLDP_BASE, | |
2204 | .iddq_bit_idx = PLLSS_IDDQ_BIT, | |
2205 | .sdm_din_reg = PLLDP_SS_CTRL2, | |
2206 | .sdm_din_mask = PLLA_SDM_DIN_MASK, | |
2207 | .sdm_ctrl_reg = PLLDP_SS_CFG, | |
2208 | .sdm_ctrl_en_mask = PLLDP_SDM_EN_MASK, | |
2209 | .ssc_ctrl_reg = PLLDP_SS_CFG, | |
2210 | .ssc_ctrl_en_mask = PLLDP_SSC_EN_MASK, | |
2211 | .round_p_to_pdiv = pll_qlin_p_to_pdiv, | |
2212 | .pdiv_tohw = pll_qlin_pdiv_to_hw, | |
2213 | .div_nmp = &pllss_nmp, | |
2214 | .ext_misc_reg[0] = PLLDP_MISC, | |
2215 | .ext_misc_reg[1] = PLLDP_SS_CFG, | |
2216 | .ext_misc_reg[2] = PLLDP_SS_CTRL1, | |
2217 | .ext_misc_reg[3] = PLLDP_SS_CTRL2, | |
2218 | .max_p = PLL_QLIN_PDIV_MAX, | |
2219 | .mdiv_default = 1, | |
2220 | .freq_table = pll_dp_freq_table, | |
2221 | .set_defaults = tegra210_plldp_set_defaults, | |
14050118 | 2222 | .flags = TEGRA_PLL_USE_LOCK, |
6b301a05 RK |
2223 | .calc_rate = tegra210_pll_fixed_mdiv_cfg, |
2224 | .set_gain = tegra210_clk_pll_set_gain, | |
2225 | .adjust_vco = tegra210_clk_adjust_vco_min, | |
2226 | }; | |
2227 | ||
2228 | static struct div_nmp pllu_nmp = { | |
2229 | .divm_shift = 0, | |
2230 | .divm_width = 8, | |
2231 | .divn_shift = 8, | |
2232 | .divn_width = 8, | |
2233 | .divp_shift = 16, | |
2234 | .divp_width = 5, | |
2235 | }; | |
2236 | ||
2237 | static struct tegra_clk_pll_freq_table pll_u_freq_table[] = { | |
0d34dfbf JK |
2238 | { 12000000, 480000000, 40, 1, 1, 0 }, |
2239 | { 13000000, 480000000, 36, 1, 1, 0 }, /* actual: 468.0 MHz */ | |
2240 | { 38400000, 480000000, 25, 2, 1, 0 }, | |
6b301a05 RK |
2241 | { 0, 0, 0, 0, 0, 0 }, |
2242 | }; | |
2243 | ||
2244 | static struct tegra_clk_pll_params pll_u_vco_params = { | |
2245 | .input_min = 9600000, | |
2246 | .input_max = 800000000, | |
2247 | .cf_min = 9600000, | |
2248 | .cf_max = 19200000, | |
2249 | .vco_min = 350000000, | |
2250 | .vco_max = 700000000, | |
2251 | .base_reg = PLLU_BASE, | |
2252 | .misc_reg = PLLU_MISC0, | |
2253 | .lock_mask = PLL_BASE_LOCK, | |
6b301a05 RK |
2254 | .lock_delay = 1000, |
2255 | .iddq_reg = PLLU_MISC0, | |
2256 | .iddq_bit_idx = PLLU_IDDQ_BIT, | |
2257 | .ext_misc_reg[0] = PLLU_MISC0, | |
2258 | .ext_misc_reg[1] = PLLU_MISC1, | |
2259 | .round_p_to_pdiv = pll_qlin_p_to_pdiv, | |
2260 | .pdiv_tohw = pll_qlin_pdiv_to_hw, | |
2261 | .div_nmp = &pllu_nmp, | |
2262 | .freq_table = pll_u_freq_table, | |
14050118 | 2263 | .flags = TEGRA_PLLU | TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT, |
e745f992 PDS |
2264 | }; |
2265 | ||
2266 | struct utmi_clk_param { | |
2267 | /* Oscillator Frequency in KHz */ | |
2268 | u32 osc_frequency; | |
2269 | /* UTMIP PLL Enable Delay Count */ | |
2270 | u8 enable_delay_count; | |
2271 | /* UTMIP PLL Stable count */ | |
2272 | u16 stable_count; | |
2273 | /* UTMIP PLL Active delay count */ | |
2274 | u8 active_delay_count; | |
2275 | /* UTMIP PLL Xtal frequency count */ | |
2276 | u16 xtal_freq_count; | |
2277 | }; | |
2278 | ||
2279 | static const struct utmi_clk_param utmi_parameters[] = { | |
2280 | { | |
2281 | .osc_frequency = 38400000, .enable_delay_count = 0x0, | |
2282 | .stable_count = 0x0, .active_delay_count = 0x6, | |
2283 | .xtal_freq_count = 0x80 | |
2284 | }, { | |
2285 | .osc_frequency = 13000000, .enable_delay_count = 0x02, | |
2286 | .stable_count = 0x33, .active_delay_count = 0x05, | |
2287 | .xtal_freq_count = 0x7f | |
2288 | }, { | |
2289 | .osc_frequency = 19200000, .enable_delay_count = 0x03, | |
2290 | .stable_count = 0x4b, .active_delay_count = 0x06, | |
2291 | .xtal_freq_count = 0xbb | |
2292 | }, { | |
2293 | .osc_frequency = 12000000, .enable_delay_count = 0x02, | |
2294 | .stable_count = 0x2f, .active_delay_count = 0x08, | |
2295 | .xtal_freq_count = 0x76 | |
2296 | }, { | |
2297 | .osc_frequency = 26000000, .enable_delay_count = 0x04, | |
2298 | .stable_count = 0x66, .active_delay_count = 0x09, | |
2299 | .xtal_freq_count = 0xfe | |
2300 | }, { | |
2301 | .osc_frequency = 16800000, .enable_delay_count = 0x03, | |
2302 | .stable_count = 0x41, .active_delay_count = 0x0a, | |
2303 | .xtal_freq_count = 0xa4 | |
2304 | }, | |
6b301a05 RK |
2305 | }; |
2306 | ||
6b301a05 RK |
2307 | static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = { |
2308 | [tegra_clk_ispb] = { .dt_id = TEGRA210_CLK_ISPB, .present = true }, | |
2309 | [tegra_clk_rtc] = { .dt_id = TEGRA210_CLK_RTC, .present = true }, | |
2310 | [tegra_clk_timer] = { .dt_id = TEGRA210_CLK_TIMER, .present = true }, | |
2311 | [tegra_clk_uarta_8] = { .dt_id = TEGRA210_CLK_UARTA, .present = true }, | |
6b301a05 RK |
2312 | [tegra_clk_i2s1] = { .dt_id = TEGRA210_CLK_I2S1, .present = true }, |
2313 | [tegra_clk_i2c1] = { .dt_id = TEGRA210_CLK_I2C1, .present = true }, | |
2314 | [tegra_clk_sdmmc1_9] = { .dt_id = TEGRA210_CLK_SDMMC1, .present = true }, | |
6b301a05 RK |
2315 | [tegra_clk_pwm] = { .dt_id = TEGRA210_CLK_PWM, .present = true }, |
2316 | [tegra_clk_i2s2] = { .dt_id = TEGRA210_CLK_I2S2, .present = true }, | |
2317 | [tegra_clk_usbd] = { .dt_id = TEGRA210_CLK_USBD, .present = true }, | |
2318 | [tegra_clk_isp_9] = { .dt_id = TEGRA210_CLK_ISP, .present = true }, | |
2319 | [tegra_clk_disp2_8] = { .dt_id = TEGRA210_CLK_DISP2, .present = true }, | |
2320 | [tegra_clk_disp1_8] = { .dt_id = TEGRA210_CLK_DISP1, .present = true }, | |
2321 | [tegra_clk_host1x_9] = { .dt_id = TEGRA210_CLK_HOST1X, .present = true }, | |
2322 | [tegra_clk_i2s0] = { .dt_id = TEGRA210_CLK_I2S0, .present = true }, | |
2323 | [tegra_clk_apbdma] = { .dt_id = TEGRA210_CLK_APBDMA, .present = true }, | |
2324 | [tegra_clk_kfuse] = { .dt_id = TEGRA210_CLK_KFUSE, .present = true }, | |
2325 | [tegra_clk_sbc1_9] = { .dt_id = TEGRA210_CLK_SBC1, .present = true }, | |
2326 | [tegra_clk_sbc2_9] = { .dt_id = TEGRA210_CLK_SBC2, .present = true }, | |
2327 | [tegra_clk_sbc3_9] = { .dt_id = TEGRA210_CLK_SBC3, .present = true }, | |
2328 | [tegra_clk_i2c5] = { .dt_id = TEGRA210_CLK_I2C5, .present = true }, | |
2329 | [tegra_clk_csi] = { .dt_id = TEGRA210_CLK_CSI, .present = true }, | |
2330 | [tegra_clk_i2c2] = { .dt_id = TEGRA210_CLK_I2C2, .present = true }, | |
2331 | [tegra_clk_uartc_8] = { .dt_id = TEGRA210_CLK_UARTC, .present = true }, | |
2332 | [tegra_clk_mipi_cal] = { .dt_id = TEGRA210_CLK_MIPI_CAL, .present = true }, | |
6b301a05 RK |
2333 | [tegra_clk_usb2] = { .dt_id = TEGRA210_CLK_USB2, .present = true }, |
2334 | [tegra_clk_bsev] = { .dt_id = TEGRA210_CLK_BSEV, .present = true }, | |
2335 | [tegra_clk_uartd_8] = { .dt_id = TEGRA210_CLK_UARTD, .present = true }, | |
2336 | [tegra_clk_i2c3] = { .dt_id = TEGRA210_CLK_I2C3, .present = true }, | |
2337 | [tegra_clk_sbc4_9] = { .dt_id = TEGRA210_CLK_SBC4, .present = true }, | |
2338 | [tegra_clk_sdmmc3_9] = { .dt_id = TEGRA210_CLK_SDMMC3, .present = true }, | |
2339 | [tegra_clk_pcie] = { .dt_id = TEGRA210_CLK_PCIE, .present = true }, | |
2340 | [tegra_clk_owr_8] = { .dt_id = TEGRA210_CLK_OWR, .present = true }, | |
2341 | [tegra_clk_afi] = { .dt_id = TEGRA210_CLK_AFI, .present = true }, | |
2342 | [tegra_clk_csite_8] = { .dt_id = TEGRA210_CLK_CSITE, .present = true }, | |
2343 | [tegra_clk_soc_therm_8] = { .dt_id = TEGRA210_CLK_SOC_THERM, .present = true }, | |
2344 | [tegra_clk_dtv] = { .dt_id = TEGRA210_CLK_DTV, .present = true }, | |
2345 | [tegra_clk_i2cslow] = { .dt_id = TEGRA210_CLK_I2CSLOW, .present = true }, | |
2346 | [tegra_clk_tsec_8] = { .dt_id = TEGRA210_CLK_TSEC, .present = true }, | |
2347 | [tegra_clk_xusb_host] = { .dt_id = TEGRA210_CLK_XUSB_HOST, .present = true }, | |
2348 | [tegra_clk_csus] = { .dt_id = TEGRA210_CLK_CSUS, .present = true }, | |
2349 | [tegra_clk_mselect] = { .dt_id = TEGRA210_CLK_MSELECT, .present = true }, | |
2350 | [tegra_clk_tsensor] = { .dt_id = TEGRA210_CLK_TSENSOR, .present = true }, | |
2351 | [tegra_clk_i2s3] = { .dt_id = TEGRA210_CLK_I2S3, .present = true }, | |
2352 | [tegra_clk_i2s4] = { .dt_id = TEGRA210_CLK_I2S4, .present = true }, | |
2353 | [tegra_clk_i2c4] = { .dt_id = TEGRA210_CLK_I2C4, .present = true }, | |
2354 | [tegra_clk_d_audio] = { .dt_id = TEGRA210_CLK_D_AUDIO, .present = true }, | |
2355 | [tegra_clk_hda2codec_2x_8] = { .dt_id = TEGRA210_CLK_HDA2CODEC_2X, .present = true }, | |
2356 | [tegra_clk_spdif_2x] = { .dt_id = TEGRA210_CLK_SPDIF_2X, .present = true }, | |
2357 | [tegra_clk_actmon] = { .dt_id = TEGRA210_CLK_ACTMON, .present = true }, | |
2358 | [tegra_clk_extern1] = { .dt_id = TEGRA210_CLK_EXTERN1, .present = true }, | |
2359 | [tegra_clk_extern2] = { .dt_id = TEGRA210_CLK_EXTERN2, .present = true }, | |
2360 | [tegra_clk_extern3] = { .dt_id = TEGRA210_CLK_EXTERN3, .present = true }, | |
2361 | [tegra_clk_sata_oob_8] = { .dt_id = TEGRA210_CLK_SATA_OOB, .present = true }, | |
2362 | [tegra_clk_sata_8] = { .dt_id = TEGRA210_CLK_SATA, .present = true }, | |
2363 | [tegra_clk_hda_8] = { .dt_id = TEGRA210_CLK_HDA, .present = true }, | |
2364 | [tegra_clk_hda2hdmi] = { .dt_id = TEGRA210_CLK_HDA2HDMI, .present = true }, | |
2365 | [tegra_clk_cilab] = { .dt_id = TEGRA210_CLK_CILAB, .present = true }, | |
2366 | [tegra_clk_cilcd] = { .dt_id = TEGRA210_CLK_CILCD, .present = true }, | |
2367 | [tegra_clk_cile] = { .dt_id = TEGRA210_CLK_CILE, .present = true }, | |
2368 | [tegra_clk_dsialp] = { .dt_id = TEGRA210_CLK_DSIALP, .present = true }, | |
2369 | [tegra_clk_dsiblp] = { .dt_id = TEGRA210_CLK_DSIBLP, .present = true }, | |
2370 | [tegra_clk_entropy_8] = { .dt_id = TEGRA210_CLK_ENTROPY, .present = true }, | |
2371 | [tegra_clk_xusb_ss] = { .dt_id = TEGRA210_CLK_XUSB_SS, .present = true }, | |
2372 | [tegra_clk_i2c6] = { .dt_id = TEGRA210_CLK_I2C6, .present = true }, | |
2373 | [tegra_clk_vim2_clk] = { .dt_id = TEGRA210_CLK_VIM2_CLK, .present = true }, | |
2374 | [tegra_clk_clk72Mhz_8] = { .dt_id = TEGRA210_CLK_CLK72MHZ, .present = true }, | |
2375 | [tegra_clk_vic03_8] = { .dt_id = TEGRA210_CLK_VIC03, .present = true }, | |
2376 | [tegra_clk_dpaux] = { .dt_id = TEGRA210_CLK_DPAUX, .present = true }, | |
98c4b366 | 2377 | [tegra_clk_dpaux1] = { .dt_id = TEGRA210_CLK_DPAUX1, .present = true }, |
6b301a05 | 2378 | [tegra_clk_sor0] = { .dt_id = TEGRA210_CLK_SOR0, .present = true }, |
da8d1a35 | 2379 | [tegra_clk_sor0_out] = { .dt_id = TEGRA210_CLK_SOR0_OUT, .present = true }, |
e452b818 | 2380 | [tegra_clk_sor1] = { .dt_id = TEGRA210_CLK_SOR1, .present = true }, |
991a051e | 2381 | [tegra_clk_sor1_out] = { .dt_id = TEGRA210_CLK_SOR1_OUT, .present = true }, |
6b301a05 RK |
2382 | [tegra_clk_gpu] = { .dt_id = TEGRA210_CLK_GPU, .present = true }, |
2383 | [tegra_clk_pll_g_ref] = { .dt_id = TEGRA210_CLK_PLL_G_REF, .present = true, }, | |
2384 | [tegra_clk_uartb_8] = { .dt_id = TEGRA210_CLK_UARTB, .present = true }, | |
6b301a05 RK |
2385 | [tegra_clk_spdif_in_8] = { .dt_id = TEGRA210_CLK_SPDIF_IN, .present = true }, |
2386 | [tegra_clk_spdif_out] = { .dt_id = TEGRA210_CLK_SPDIF_OUT, .present = true }, | |
2387 | [tegra_clk_vi_10] = { .dt_id = TEGRA210_CLK_VI, .present = true }, | |
2388 | [tegra_clk_vi_sensor_8] = { .dt_id = TEGRA210_CLK_VI_SENSOR, .present = true }, | |
2389 | [tegra_clk_fuse] = { .dt_id = TEGRA210_CLK_FUSE, .present = true }, | |
2390 | [tegra_clk_fuse_burn] = { .dt_id = TEGRA210_CLK_FUSE_BURN, .present = true }, | |
2391 | [tegra_clk_clk_32k] = { .dt_id = TEGRA210_CLK_CLK_32K, .present = true }, | |
2392 | [tegra_clk_clk_m] = { .dt_id = TEGRA210_CLK_CLK_M, .present = true }, | |
2b50e49b | 2393 | [tegra_clk_osc] = { .dt_id = TEGRA210_CLK_OSC, .present = true }, |
9a85eb4d SK |
2394 | [tegra_clk_osc_div2] = { .dt_id = TEGRA210_CLK_OSC_DIV2, .present = true }, |
2395 | [tegra_clk_osc_div4] = { .dt_id = TEGRA210_CLK_OSC_DIV4, .present = true }, | |
6b301a05 RK |
2396 | [tegra_clk_pll_ref] = { .dt_id = TEGRA210_CLK_PLL_REF, .present = true }, |
2397 | [tegra_clk_pll_c] = { .dt_id = TEGRA210_CLK_PLL_C, .present = true }, | |
2398 | [tegra_clk_pll_c_out1] = { .dt_id = TEGRA210_CLK_PLL_C_OUT1, .present = true }, | |
2399 | [tegra_clk_pll_c2] = { .dt_id = TEGRA210_CLK_PLL_C2, .present = true }, | |
2400 | [tegra_clk_pll_c3] = { .dt_id = TEGRA210_CLK_PLL_C3, .present = true }, | |
2401 | [tegra_clk_pll_m] = { .dt_id = TEGRA210_CLK_PLL_M, .present = true }, | |
6b301a05 RK |
2402 | [tegra_clk_pll_p] = { .dt_id = TEGRA210_CLK_PLL_P, .present = true }, |
2403 | [tegra_clk_pll_p_out1] = { .dt_id = TEGRA210_CLK_PLL_P_OUT1, .present = true }, | |
2404 | [tegra_clk_pll_p_out3] = { .dt_id = TEGRA210_CLK_PLL_P_OUT3, .present = true }, | |
2405 | [tegra_clk_pll_p_out4_cpu] = { .dt_id = TEGRA210_CLK_PLL_P_OUT4, .present = true }, | |
2406 | [tegra_clk_pll_p_out_hsio] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_HSIO, .present = true }, | |
2407 | [tegra_clk_pll_p_out_xusb] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_XUSB, .present = true }, | |
2408 | [tegra_clk_pll_p_out_cpu] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_CPU, .present = true }, | |
2409 | [tegra_clk_pll_p_out_adsp] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_ADSP, .present = true }, | |
2410 | [tegra_clk_pll_a] = { .dt_id = TEGRA210_CLK_PLL_A, .present = true }, | |
2411 | [tegra_clk_pll_a_out0] = { .dt_id = TEGRA210_CLK_PLL_A_OUT0, .present = true }, | |
2412 | [tegra_clk_pll_d] = { .dt_id = TEGRA210_CLK_PLL_D, .present = true }, | |
2413 | [tegra_clk_pll_d_out0] = { .dt_id = TEGRA210_CLK_PLL_D_OUT0, .present = true }, | |
2414 | [tegra_clk_pll_d2] = { .dt_id = TEGRA210_CLK_PLL_D2, .present = true }, | |
2415 | [tegra_clk_pll_d2_out0] = { .dt_id = TEGRA210_CLK_PLL_D2_OUT0, .present = true }, | |
2416 | [tegra_clk_pll_u] = { .dt_id = TEGRA210_CLK_PLL_U, .present = true }, | |
2417 | [tegra_clk_pll_u_out] = { .dt_id = TEGRA210_CLK_PLL_U_OUT, .present = true }, | |
2418 | [tegra_clk_pll_u_out1] = { .dt_id = TEGRA210_CLK_PLL_U_OUT1, .present = true }, | |
2419 | [tegra_clk_pll_u_out2] = { .dt_id = TEGRA210_CLK_PLL_U_OUT2, .present = true }, | |
2420 | [tegra_clk_pll_u_480m] = { .dt_id = TEGRA210_CLK_PLL_U_480M, .present = true }, | |
2421 | [tegra_clk_pll_u_60m] = { .dt_id = TEGRA210_CLK_PLL_U_60M, .present = true }, | |
2422 | [tegra_clk_pll_u_48m] = { .dt_id = TEGRA210_CLK_PLL_U_48M, .present = true }, | |
2423 | [tegra_clk_pll_x] = { .dt_id = TEGRA210_CLK_PLL_X, .present = true }, | |
2424 | [tegra_clk_pll_x_out0] = { .dt_id = TEGRA210_CLK_PLL_X_OUT0, .present = true }, | |
2425 | [tegra_clk_pll_re_vco] = { .dt_id = TEGRA210_CLK_PLL_RE_VCO, .present = true }, | |
2426 | [tegra_clk_pll_re_out] = { .dt_id = TEGRA210_CLK_PLL_RE_OUT, .present = true }, | |
2427 | [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA210_CLK_SPDIF_IN_SYNC, .present = true }, | |
2428 | [tegra_clk_i2s0_sync] = { .dt_id = TEGRA210_CLK_I2S0_SYNC, .present = true }, | |
2429 | [tegra_clk_i2s1_sync] = { .dt_id = TEGRA210_CLK_I2S1_SYNC, .present = true }, | |
2430 | [tegra_clk_i2s2_sync] = { .dt_id = TEGRA210_CLK_I2S2_SYNC, .present = true }, | |
2431 | [tegra_clk_i2s3_sync] = { .dt_id = TEGRA210_CLK_I2S3_SYNC, .present = true }, | |
2432 | [tegra_clk_i2s4_sync] = { .dt_id = TEGRA210_CLK_I2S4_SYNC, .present = true }, | |
2433 | [tegra_clk_vimclk_sync] = { .dt_id = TEGRA210_CLK_VIMCLK_SYNC, .present = true }, | |
2434 | [tegra_clk_audio0] = { .dt_id = TEGRA210_CLK_AUDIO0, .present = true }, | |
2435 | [tegra_clk_audio1] = { .dt_id = TEGRA210_CLK_AUDIO1, .present = true }, | |
2436 | [tegra_clk_audio2] = { .dt_id = TEGRA210_CLK_AUDIO2, .present = true }, | |
2437 | [tegra_clk_audio3] = { .dt_id = TEGRA210_CLK_AUDIO3, .present = true }, | |
2438 | [tegra_clk_audio4] = { .dt_id = TEGRA210_CLK_AUDIO4, .present = true }, | |
2439 | [tegra_clk_spdif] = { .dt_id = TEGRA210_CLK_SPDIF, .present = true }, | |
6b301a05 RK |
2440 | [tegra_clk_xusb_gate] = { .dt_id = TEGRA210_CLK_XUSB_GATE, .present = true }, |
2441 | [tegra_clk_xusb_host_src_8] = { .dt_id = TEGRA210_CLK_XUSB_HOST_SRC, .present = true }, | |
2442 | [tegra_clk_xusb_falcon_src_8] = { .dt_id = TEGRA210_CLK_XUSB_FALCON_SRC, .present = true }, | |
2443 | [tegra_clk_xusb_fs_src] = { .dt_id = TEGRA210_CLK_XUSB_FS_SRC, .present = true }, | |
2444 | [tegra_clk_xusb_ss_src_8] = { .dt_id = TEGRA210_CLK_XUSB_SS_SRC, .present = true }, | |
2445 | [tegra_clk_xusb_ss_div2] = { .dt_id = TEGRA210_CLK_XUSB_SS_DIV2, .present = true }, | |
2446 | [tegra_clk_xusb_dev_src_8] = { .dt_id = TEGRA210_CLK_XUSB_DEV_SRC, .present = true }, | |
2447 | [tegra_clk_xusb_dev] = { .dt_id = TEGRA210_CLK_XUSB_DEV, .present = true }, | |
2448 | [tegra_clk_xusb_hs_src_4] = { .dt_id = TEGRA210_CLK_XUSB_HS_SRC, .present = true }, | |
2449 | [tegra_clk_xusb_ssp_src] = { .dt_id = TEGRA210_CLK_XUSB_SSP_SRC, .present = true }, | |
2450 | [tegra_clk_usb2_hsic_trk] = { .dt_id = TEGRA210_CLK_USB2_HSIC_TRK, .present = true }, | |
2451 | [tegra_clk_hsic_trk] = { .dt_id = TEGRA210_CLK_HSIC_TRK, .present = true }, | |
2452 | [tegra_clk_usb2_trk] = { .dt_id = TEGRA210_CLK_USB2_TRK, .present = true }, | |
2453 | [tegra_clk_sclk] = { .dt_id = TEGRA210_CLK_SCLK, .present = true }, | |
2454 | [tegra_clk_sclk_mux] = { .dt_id = TEGRA210_CLK_SCLK_MUX, .present = true }, | |
2455 | [tegra_clk_hclk] = { .dt_id = TEGRA210_CLK_HCLK, .present = true }, | |
2456 | [tegra_clk_pclk] = { .dt_id = TEGRA210_CLK_PCLK, .present = true }, | |
2457 | [tegra_clk_cclk_g] = { .dt_id = TEGRA210_CLK_CCLK_G, .present = true }, | |
2458 | [tegra_clk_cclk_lp] = { .dt_id = TEGRA210_CLK_CCLK_LP, .present = true }, | |
2459 | [tegra_clk_dfll_ref] = { .dt_id = TEGRA210_CLK_DFLL_REF, .present = true }, | |
2460 | [tegra_clk_dfll_soc] = { .dt_id = TEGRA210_CLK_DFLL_SOC, .present = true }, | |
2461 | [tegra_clk_vi_sensor2_8] = { .dt_id = TEGRA210_CLK_VI_SENSOR2, .present = true }, | |
2462 | [tegra_clk_pll_p_out5] = { .dt_id = TEGRA210_CLK_PLL_P_OUT5, .present = true }, | |
2463 | [tegra_clk_pll_c4] = { .dt_id = TEGRA210_CLK_PLL_C4, .present = true }, | |
2464 | [tegra_clk_pll_dp] = { .dt_id = TEGRA210_CLK_PLL_DP, .present = true }, | |
2465 | [tegra_clk_audio0_mux] = { .dt_id = TEGRA210_CLK_AUDIO0_MUX, .present = true }, | |
2466 | [tegra_clk_audio1_mux] = { .dt_id = TEGRA210_CLK_AUDIO1_MUX, .present = true }, | |
2467 | [tegra_clk_audio2_mux] = { .dt_id = TEGRA210_CLK_AUDIO2_MUX, .present = true }, | |
2468 | [tegra_clk_audio3_mux] = { .dt_id = TEGRA210_CLK_AUDIO3_MUX, .present = true }, | |
2469 | [tegra_clk_audio4_mux] = { .dt_id = TEGRA210_CLK_AUDIO4_MUX, .present = true }, | |
2470 | [tegra_clk_spdif_mux] = { .dt_id = TEGRA210_CLK_SPDIF_MUX, .present = true }, | |
6b301a05 RK |
2471 | [tegra_clk_maud] = { .dt_id = TEGRA210_CLK_MAUD, .present = true }, |
2472 | [tegra_clk_mipibif] = { .dt_id = TEGRA210_CLK_MIPIBIF, .present = true }, | |
2473 | [tegra_clk_qspi] = { .dt_id = TEGRA210_CLK_QSPI, .present = true }, | |
2474 | [tegra_clk_sdmmc_legacy] = { .dt_id = TEGRA210_CLK_SDMMC_LEGACY, .present = true }, | |
2475 | [tegra_clk_tsecb] = { .dt_id = TEGRA210_CLK_TSECB, .present = true }, | |
2476 | [tegra_clk_uartape] = { .dt_id = TEGRA210_CLK_UARTAPE, .present = true }, | |
2477 | [tegra_clk_vi_i2c] = { .dt_id = TEGRA210_CLK_VI_I2C, .present = true }, | |
2478 | [tegra_clk_ape] = { .dt_id = TEGRA210_CLK_APE, .present = true }, | |
2479 | [tegra_clk_dbgapb] = { .dt_id = TEGRA210_CLK_DBGAPB, .present = true }, | |
2480 | [tegra_clk_nvdec] = { .dt_id = TEGRA210_CLK_NVDEC, .present = true }, | |
2481 | [tegra_clk_nvenc] = { .dt_id = TEGRA210_CLK_NVENC, .present = true }, | |
2482 | [tegra_clk_nvjpg] = { .dt_id = TEGRA210_CLK_NVJPG, .present = true }, | |
2483 | [tegra_clk_pll_c4_out0] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT0, .present = true }, | |
2484 | [tegra_clk_pll_c4_out1] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT1, .present = true }, | |
2485 | [tegra_clk_pll_c4_out2] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT2, .present = true }, | |
2486 | [tegra_clk_pll_c4_out3] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT3, .present = true }, | |
29569941 | 2487 | [tegra_clk_apb2ape] = { .dt_id = TEGRA210_CLK_APB2APE, .present = true }, |
9326947f | 2488 | [tegra_clk_pll_a1] = { .dt_id = TEGRA210_CLK_PLL_A1, .present = true }, |
34ac2c27 | 2489 | [tegra_clk_ispa] = { .dt_id = TEGRA210_CLK_ISPA, .present = true }, |
bfa34832 | 2490 | [tegra_clk_cec] = { .dt_id = TEGRA210_CLK_CEC, .present = true }, |
6cfc8bc9 PDS |
2491 | [tegra_clk_dmic1] = { .dt_id = TEGRA210_CLK_DMIC1, .present = true }, |
2492 | [tegra_clk_dmic2] = { .dt_id = TEGRA210_CLK_DMIC2, .present = true }, | |
2493 | [tegra_clk_dmic3] = { .dt_id = TEGRA210_CLK_DMIC3, .present = true }, | |
319af797 PDS |
2494 | [tegra_clk_dmic1_sync_clk] = { .dt_id = TEGRA210_CLK_DMIC1_SYNC_CLK, .present = true }, |
2495 | [tegra_clk_dmic2_sync_clk] = { .dt_id = TEGRA210_CLK_DMIC2_SYNC_CLK, .present = true }, | |
2496 | [tegra_clk_dmic3_sync_clk] = { .dt_id = TEGRA210_CLK_DMIC3_SYNC_CLK, .present = true }, | |
2497 | [tegra_clk_dmic1_sync_clk_mux] = { .dt_id = TEGRA210_CLK_DMIC1_SYNC_CLK_MUX, .present = true }, | |
2498 | [tegra_clk_dmic2_sync_clk_mux] = { .dt_id = TEGRA210_CLK_DMIC2_SYNC_CLK_MUX, .present = true }, | |
2499 | [tegra_clk_dmic3_sync_clk_mux] = { .dt_id = TEGRA210_CLK_DMIC3_SYNC_CLK_MUX, .present = true }, | |
88da44c5 PDS |
2500 | [tegra_clk_dp2] = { .dt_id = TEGRA210_CLK_DP2, .present = true }, |
2501 | [tegra_clk_iqc1] = { .dt_id = TEGRA210_CLK_IQC1, .present = true }, | |
2502 | [tegra_clk_iqc2] = { .dt_id = TEGRA210_CLK_IQC2, .present = true }, | |
2503 | [tegra_clk_pll_a_out_adsp] = { .dt_id = TEGRA210_CLK_PLL_A_OUT_ADSP, .present = true }, | |
2504 | [tegra_clk_pll_a_out0_out_adsp] = { .dt_id = TEGRA210_CLK_PLL_A_OUT0_OUT_ADSP, .present = true }, | |
2505 | [tegra_clk_adsp] = { .dt_id = TEGRA210_CLK_ADSP, .present = true }, | |
2506 | [tegra_clk_adsp_neon] = { .dt_id = TEGRA210_CLK_ADSP_NEON, .present = true }, | |
6b301a05 RK |
2507 | }; |
2508 | ||
2509 | static struct tegra_devclk devclks[] __initdata = { | |
2510 | { .con_id = "clk_m", .dt_id = TEGRA210_CLK_CLK_M }, | |
2511 | { .con_id = "pll_ref", .dt_id = TEGRA210_CLK_PLL_REF }, | |
2512 | { .con_id = "clk_32k", .dt_id = TEGRA210_CLK_CLK_32K }, | |
2b50e49b | 2513 | { .con_id = "osc", .dt_id = TEGRA210_CLK_OSC }, |
9a85eb4d SK |
2514 | { .con_id = "osc_div2", .dt_id = TEGRA210_CLK_OSC_DIV2 }, |
2515 | { .con_id = "osc_div4", .dt_id = TEGRA210_CLK_OSC_DIV4 }, | |
6b301a05 RK |
2516 | { .con_id = "pll_c", .dt_id = TEGRA210_CLK_PLL_C }, |
2517 | { .con_id = "pll_c_out1", .dt_id = TEGRA210_CLK_PLL_C_OUT1 }, | |
2518 | { .con_id = "pll_c2", .dt_id = TEGRA210_CLK_PLL_C2 }, | |
2519 | { .con_id = "pll_c3", .dt_id = TEGRA210_CLK_PLL_C3 }, | |
2520 | { .con_id = "pll_p", .dt_id = TEGRA210_CLK_PLL_P }, | |
2521 | { .con_id = "pll_p_out1", .dt_id = TEGRA210_CLK_PLL_P_OUT1 }, | |
2522 | { .con_id = "pll_p_out2", .dt_id = TEGRA210_CLK_PLL_P_OUT2 }, | |
2523 | { .con_id = "pll_p_out3", .dt_id = TEGRA210_CLK_PLL_P_OUT3 }, | |
2524 | { .con_id = "pll_p_out4", .dt_id = TEGRA210_CLK_PLL_P_OUT4 }, | |
2525 | { .con_id = "pll_m", .dt_id = TEGRA210_CLK_PLL_M }, | |
6b301a05 RK |
2526 | { .con_id = "pll_x", .dt_id = TEGRA210_CLK_PLL_X }, |
2527 | { .con_id = "pll_x_out0", .dt_id = TEGRA210_CLK_PLL_X_OUT0 }, | |
2528 | { .con_id = "pll_u", .dt_id = TEGRA210_CLK_PLL_U }, | |
2529 | { .con_id = "pll_u_out", .dt_id = TEGRA210_CLK_PLL_U_OUT }, | |
2530 | { .con_id = "pll_u_out1", .dt_id = TEGRA210_CLK_PLL_U_OUT1 }, | |
2531 | { .con_id = "pll_u_out2", .dt_id = TEGRA210_CLK_PLL_U_OUT2 }, | |
2532 | { .con_id = "pll_u_480M", .dt_id = TEGRA210_CLK_PLL_U_480M }, | |
2533 | { .con_id = "pll_u_60M", .dt_id = TEGRA210_CLK_PLL_U_60M }, | |
2534 | { .con_id = "pll_u_48M", .dt_id = TEGRA210_CLK_PLL_U_48M }, | |
2535 | { .con_id = "pll_d", .dt_id = TEGRA210_CLK_PLL_D }, | |
2536 | { .con_id = "pll_d_out0", .dt_id = TEGRA210_CLK_PLL_D_OUT0 }, | |
2537 | { .con_id = "pll_d2", .dt_id = TEGRA210_CLK_PLL_D2 }, | |
2538 | { .con_id = "pll_d2_out0", .dt_id = TEGRA210_CLK_PLL_D2_OUT0 }, | |
2539 | { .con_id = "pll_a", .dt_id = TEGRA210_CLK_PLL_A }, | |
2540 | { .con_id = "pll_a_out0", .dt_id = TEGRA210_CLK_PLL_A_OUT0 }, | |
2541 | { .con_id = "pll_re_vco", .dt_id = TEGRA210_CLK_PLL_RE_VCO }, | |
2542 | { .con_id = "pll_re_out", .dt_id = TEGRA210_CLK_PLL_RE_OUT }, | |
2543 | { .con_id = "spdif_in_sync", .dt_id = TEGRA210_CLK_SPDIF_IN_SYNC }, | |
2544 | { .con_id = "i2s0_sync", .dt_id = TEGRA210_CLK_I2S0_SYNC }, | |
2545 | { .con_id = "i2s1_sync", .dt_id = TEGRA210_CLK_I2S1_SYNC }, | |
2546 | { .con_id = "i2s2_sync", .dt_id = TEGRA210_CLK_I2S2_SYNC }, | |
2547 | { .con_id = "i2s3_sync", .dt_id = TEGRA210_CLK_I2S3_SYNC }, | |
2548 | { .con_id = "i2s4_sync", .dt_id = TEGRA210_CLK_I2S4_SYNC }, | |
2549 | { .con_id = "vimclk_sync", .dt_id = TEGRA210_CLK_VIMCLK_SYNC }, | |
2550 | { .con_id = "audio0", .dt_id = TEGRA210_CLK_AUDIO0 }, | |
2551 | { .con_id = "audio1", .dt_id = TEGRA210_CLK_AUDIO1 }, | |
2552 | { .con_id = "audio2", .dt_id = TEGRA210_CLK_AUDIO2 }, | |
2553 | { .con_id = "audio3", .dt_id = TEGRA210_CLK_AUDIO3 }, | |
2554 | { .con_id = "audio4", .dt_id = TEGRA210_CLK_AUDIO4 }, | |
2555 | { .con_id = "spdif", .dt_id = TEGRA210_CLK_SPDIF }, | |
2556 | { .con_id = "spdif_2x", .dt_id = TEGRA210_CLK_SPDIF_2X }, | |
acbeec3d SK |
2557 | { .con_id = "extern1", .dt_id = TEGRA210_CLK_EXTERN1 }, |
2558 | { .con_id = "extern2", .dt_id = TEGRA210_CLK_EXTERN2 }, | |
2559 | { .con_id = "extern3", .dt_id = TEGRA210_CLK_EXTERN3 }, | |
6b301a05 RK |
2560 | { .con_id = "cclk_g", .dt_id = TEGRA210_CLK_CCLK_G }, |
2561 | { .con_id = "cclk_lp", .dt_id = TEGRA210_CLK_CCLK_LP }, | |
2562 | { .con_id = "sclk", .dt_id = TEGRA210_CLK_SCLK }, | |
2563 | { .con_id = "hclk", .dt_id = TEGRA210_CLK_HCLK }, | |
2564 | { .con_id = "pclk", .dt_id = TEGRA210_CLK_PCLK }, | |
2565 | { .con_id = "fuse", .dt_id = TEGRA210_CLK_FUSE }, | |
2566 | { .dev_id = "rtc-tegra", .dt_id = TEGRA210_CLK_RTC }, | |
2567 | { .dev_id = "timer", .dt_id = TEGRA210_CLK_TIMER }, | |
2568 | { .con_id = "pll_c4_out0", .dt_id = TEGRA210_CLK_PLL_C4_OUT0 }, | |
2569 | { .con_id = "pll_c4_out1", .dt_id = TEGRA210_CLK_PLL_C4_OUT1 }, | |
2570 | { .con_id = "pll_c4_out2", .dt_id = TEGRA210_CLK_PLL_C4_OUT2 }, | |
2571 | { .con_id = "pll_c4_out3", .dt_id = TEGRA210_CLK_PLL_C4_OUT3 }, | |
2572 | { .con_id = "dpaux", .dt_id = TEGRA210_CLK_DPAUX }, | |
6b301a05 RK |
2573 | }; |
2574 | ||
2575 | static struct tegra_audio_clk_info tegra210_audio_plls[] = { | |
2576 | { "pll_a", &pll_a_params, tegra_clk_pll_a, "pll_ref" }, | |
2577 | { "pll_a1", &pll_a1_params, tegra_clk_pll_a1, "pll_ref" }, | |
2578 | }; | |
2579 | ||
24c3ebef PDS |
2580 | static const char * const aclk_parents[] = { |
2581 | "pll_a1", "pll_c", "pll_p", "pll_a_out0", "pll_c2", "pll_c3", | |
2582 | "clk_m" | |
2583 | }; | |
2584 | ||
e403d005 PDS |
2585 | static const unsigned int nvjpg_slcg_clkids[] = { TEGRA210_CLK_NVDEC }; |
2586 | static const unsigned int nvdec_slcg_clkids[] = { TEGRA210_CLK_NVJPG }; | |
2587 | static const unsigned int sor_slcg_clkids[] = { TEGRA210_CLK_HDA2CODEC_2X, | |
2588 | TEGRA210_CLK_HDA2HDMI, TEGRA210_CLK_DISP1, TEGRA210_CLK_DISP2 }; | |
2589 | static const unsigned int disp_slcg_clkids[] = { TEGRA210_CLK_LA, | |
2590 | TEGRA210_CLK_HOST1X}; | |
2591 | static const unsigned int xusba_slcg_clkids[] = { TEGRA210_CLK_XUSB_HOST, | |
2592 | TEGRA210_CLK_XUSB_DEV }; | |
2593 | static const unsigned int xusbb_slcg_clkids[] = { TEGRA210_CLK_XUSB_HOST, | |
2594 | TEGRA210_CLK_XUSB_SS }; | |
2595 | static const unsigned int xusbc_slcg_clkids[] = { TEGRA210_CLK_XUSB_DEV, | |
2596 | TEGRA210_CLK_XUSB_SS }; | |
2597 | static const unsigned int venc_slcg_clkids[] = { TEGRA210_CLK_HOST1X, | |
2598 | TEGRA210_CLK_PLL_D }; | |
2599 | static const unsigned int ape_slcg_clkids[] = { TEGRA210_CLK_ACLK, | |
2600 | TEGRA210_CLK_I2S0, TEGRA210_CLK_I2S1, TEGRA210_CLK_I2S2, | |
2601 | TEGRA210_CLK_I2S3, TEGRA210_CLK_I2S4, TEGRA210_CLK_SPDIF_OUT, | |
2602 | TEGRA210_CLK_D_AUDIO }; | |
2603 | static const unsigned int vic_slcg_clkids[] = { TEGRA210_CLK_HOST1X }; | |
2604 | ||
2605 | static struct tegra210_domain_mbist_war tegra210_pg_mbist_war[] = { | |
2606 | [TEGRA_POWERGATE_VENC] = { | |
2607 | .handle_lvl2_ovr = tegra210_venc_mbist_war, | |
2608 | .num_clks = ARRAY_SIZE(venc_slcg_clkids), | |
2609 | .clk_init_data = venc_slcg_clkids, | |
2610 | }, | |
2611 | [TEGRA_POWERGATE_SATA] = { | |
2612 | .handle_lvl2_ovr = tegra210_generic_mbist_war, | |
2613 | .lvl2_offset = LVL2_CLK_GATE_OVRC, | |
2614 | .lvl2_mask = BIT(0) | BIT(17) | BIT(19), | |
2615 | }, | |
2616 | [TEGRA_POWERGATE_MPE] = { | |
2617 | .handle_lvl2_ovr = tegra210_generic_mbist_war, | |
2618 | .lvl2_offset = LVL2_CLK_GATE_OVRE, | |
a4dbbcee | 2619 | .lvl2_mask = BIT(29), |
e403d005 PDS |
2620 | }, |
2621 | [TEGRA_POWERGATE_SOR] = { | |
2622 | .handle_lvl2_ovr = tegra210_generic_mbist_war, | |
2623 | .num_clks = ARRAY_SIZE(sor_slcg_clkids), | |
2624 | .clk_init_data = sor_slcg_clkids, | |
2625 | .lvl2_offset = LVL2_CLK_GATE_OVRA, | |
2626 | .lvl2_mask = BIT(1) | BIT(2), | |
2627 | }, | |
2628 | [TEGRA_POWERGATE_DIS] = { | |
2629 | .handle_lvl2_ovr = tegra210_disp_mbist_war, | |
2630 | .num_clks = ARRAY_SIZE(disp_slcg_clkids), | |
2631 | .clk_init_data = disp_slcg_clkids, | |
2632 | }, | |
2633 | [TEGRA_POWERGATE_DISB] = { | |
2634 | .num_clks = ARRAY_SIZE(disp_slcg_clkids), | |
2635 | .clk_init_data = disp_slcg_clkids, | |
2636 | .handle_lvl2_ovr = tegra210_generic_mbist_war, | |
2637 | .lvl2_offset = LVL2_CLK_GATE_OVRA, | |
2638 | .lvl2_mask = BIT(2), | |
2639 | }, | |
2640 | [TEGRA_POWERGATE_XUSBA] = { | |
2641 | .num_clks = ARRAY_SIZE(xusba_slcg_clkids), | |
2642 | .clk_init_data = xusba_slcg_clkids, | |
2643 | .handle_lvl2_ovr = tegra210_generic_mbist_war, | |
2644 | .lvl2_offset = LVL2_CLK_GATE_OVRC, | |
2645 | .lvl2_mask = BIT(30) | BIT(31), | |
2646 | }, | |
2647 | [TEGRA_POWERGATE_XUSBB] = { | |
2648 | .num_clks = ARRAY_SIZE(xusbb_slcg_clkids), | |
2649 | .clk_init_data = xusbb_slcg_clkids, | |
2650 | .handle_lvl2_ovr = tegra210_generic_mbist_war, | |
2651 | .lvl2_offset = LVL2_CLK_GATE_OVRC, | |
2652 | .lvl2_mask = BIT(30) | BIT(31), | |
2653 | }, | |
2654 | [TEGRA_POWERGATE_XUSBC] = { | |
2655 | .num_clks = ARRAY_SIZE(xusbc_slcg_clkids), | |
2656 | .clk_init_data = xusbc_slcg_clkids, | |
2657 | .handle_lvl2_ovr = tegra210_generic_mbist_war, | |
2658 | .lvl2_offset = LVL2_CLK_GATE_OVRC, | |
2659 | .lvl2_mask = BIT(30) | BIT(31), | |
2660 | }, | |
2661 | [TEGRA_POWERGATE_VIC] = { | |
2662 | .num_clks = ARRAY_SIZE(vic_slcg_clkids), | |
2663 | .clk_init_data = vic_slcg_clkids, | |
2664 | .handle_lvl2_ovr = tegra210_vic_mbist_war, | |
2665 | }, | |
2666 | [TEGRA_POWERGATE_NVDEC] = { | |
2667 | .num_clks = ARRAY_SIZE(nvdec_slcg_clkids), | |
2668 | .clk_init_data = nvdec_slcg_clkids, | |
2669 | .handle_lvl2_ovr = tegra210_generic_mbist_war, | |
a4dbbcee | 2670 | .lvl2_offset = LVL2_CLK_GATE_OVRE, |
e403d005 PDS |
2671 | .lvl2_mask = BIT(9) | BIT(31), |
2672 | }, | |
2673 | [TEGRA_POWERGATE_NVJPG] = { | |
2674 | .num_clks = ARRAY_SIZE(nvjpg_slcg_clkids), | |
2675 | .clk_init_data = nvjpg_slcg_clkids, | |
2676 | .handle_lvl2_ovr = tegra210_generic_mbist_war, | |
a4dbbcee | 2677 | .lvl2_offset = LVL2_CLK_GATE_OVRE, |
e403d005 PDS |
2678 | .lvl2_mask = BIT(9) | BIT(31), |
2679 | }, | |
2680 | [TEGRA_POWERGATE_AUD] = { | |
2681 | .num_clks = ARRAY_SIZE(ape_slcg_clkids), | |
2682 | .clk_init_data = ape_slcg_clkids, | |
2683 | .handle_lvl2_ovr = tegra210_ape_mbist_war, | |
2684 | }, | |
2685 | [TEGRA_POWERGATE_VE2] = { | |
2686 | .handle_lvl2_ovr = tegra210_generic_mbist_war, | |
2687 | .lvl2_offset = LVL2_CLK_GATE_OVRD, | |
2688 | .lvl2_mask = BIT(22), | |
2689 | }, | |
2690 | }; | |
2691 | ||
2692 | int tegra210_clk_handle_mbist_war(unsigned int id) | |
2693 | { | |
2694 | int err; | |
2695 | struct tegra210_domain_mbist_war *mbist_war; | |
2696 | ||
2697 | if (id >= ARRAY_SIZE(tegra210_pg_mbist_war)) { | |
2698 | WARN(1, "unknown domain id in MBIST WAR handler\n"); | |
2699 | return -EINVAL; | |
2700 | } | |
2701 | ||
2702 | mbist_war = &tegra210_pg_mbist_war[id]; | |
2703 | if (!mbist_war->handle_lvl2_ovr) | |
2704 | return 0; | |
2705 | ||
2706 | if (mbist_war->num_clks && !mbist_war->clks) | |
2707 | return -ENODEV; | |
2708 | ||
2709 | err = clk_bulk_prepare_enable(mbist_war->num_clks, mbist_war->clks); | |
2710 | if (err < 0) | |
2711 | return err; | |
2712 | ||
2713 | mutex_lock(&lvl2_ovr_lock); | |
2714 | ||
2715 | mbist_war->handle_lvl2_ovr(mbist_war); | |
2716 | ||
2717 | mutex_unlock(&lvl2_ovr_lock); | |
2718 | ||
2719 | clk_bulk_disable_unprepare(mbist_war->num_clks, mbist_war->clks); | |
2720 | ||
2721 | return 0; | |
2722 | } | |
2723 | ||
3843832f PDS |
2724 | void tegra210_put_utmipll_in_iddq(void) |
2725 | { | |
2726 | u32 reg; | |
2727 | ||
2728 | reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); | |
2729 | ||
2730 | if (reg & UTMIPLL_HW_PWRDN_CFG0_UTMIPLL_LOCK) { | |
2731 | pr_err("trying to assert IDDQ while UTMIPLL is locked\n"); | |
2732 | return; | |
2733 | } | |
2734 | ||
2735 | reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE; | |
2736 | writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); | |
2737 | } | |
2738 | EXPORT_SYMBOL_GPL(tegra210_put_utmipll_in_iddq); | |
2739 | ||
2740 | void tegra210_put_utmipll_out_iddq(void) | |
2741 | { | |
2742 | u32 reg; | |
2743 | ||
2744 | reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); | |
2745 | reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE; | |
2746 | writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); | |
2747 | } | |
2748 | EXPORT_SYMBOL_GPL(tegra210_put_utmipll_out_iddq); | |
2749 | ||
e745f992 PDS |
2750 | static void tegra210_utmi_param_configure(void) |
2751 | { | |
2752 | u32 reg; | |
2753 | int i; | |
2754 | ||
2755 | for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) { | |
2756 | if (osc_freq == utmi_parameters[i].osc_frequency) | |
2757 | break; | |
2758 | } | |
2759 | ||
2760 | if (i >= ARRAY_SIZE(utmi_parameters)) { | |
2761 | pr_err("%s: Unexpected oscillator freq %lu\n", __func__, | |
2762 | osc_freq); | |
2763 | return; | |
2764 | } | |
2765 | ||
2766 | reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); | |
2767 | reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE; | |
2768 | writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); | |
2769 | ||
2770 | udelay(10); | |
2771 | ||
2772 | reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2); | |
2773 | ||
2774 | /* Program UTMIP PLL stable and active counts */ | |
2775 | /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */ | |
2776 | reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0); | |
2777 | reg |= UTMIP_PLL_CFG2_STABLE_COUNT(utmi_parameters[i].stable_count); | |
2778 | ||
2779 | reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0); | |
e745f992 PDS |
2780 | reg |= |
2781 | UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(utmi_parameters[i].active_delay_count); | |
2782 | writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2); | |
2783 | ||
2784 | /* Program UTMIP PLL delay and oscillator frequency counts */ | |
2785 | reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); | |
e745f992 | 2786 | |
71422dbb | 2787 | reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0); |
e745f992 PDS |
2788 | reg |= |
2789 | UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(utmi_parameters[i].enable_delay_count); | |
2790 | ||
2791 | reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0); | |
2792 | reg |= | |
2793 | UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(utmi_parameters[i].xtal_freq_count); | |
2794 | ||
2795 | reg |= UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN; | |
2796 | writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); | |
2797 | ||
2798 | /* Remove power downs from UTMIP PLL control bits */ | |
2799 | reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); | |
2800 | reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; | |
2801 | reg |= UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP; | |
2802 | writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); | |
71422dbb AF |
2803 | |
2804 | udelay(20); | |
e745f992 PDS |
2805 | |
2806 | /* Enable samplers for SNPS, XUSB_HOST, XUSB_DEV */ | |
2807 | reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2); | |
2808 | reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP; | |
2809 | reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP; | |
2810 | reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP; | |
2811 | reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN; | |
2812 | reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN; | |
2813 | reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN; | |
2814 | writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2); | |
2815 | ||
2816 | /* Setup HW control of UTMIPLL */ | |
2817 | reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); | |
2818 | reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; | |
2819 | reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP; | |
2820 | writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); | |
2821 | ||
2822 | reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); | |
2823 | reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET; | |
2824 | reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL; | |
2825 | writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); | |
2826 | ||
2827 | udelay(1); | |
2828 | ||
2829 | reg = readl_relaxed(clk_base + XUSB_PLL_CFG0); | |
2830 | reg &= ~XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY; | |
2831 | writel_relaxed(reg, clk_base + XUSB_PLL_CFG0); | |
2832 | ||
2833 | udelay(1); | |
2834 | ||
2835 | /* Enable HW control UTMIPLL */ | |
2836 | reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); | |
2837 | reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE; | |
2838 | writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); | |
2839 | } | |
2840 | ||
2841 | static int tegra210_enable_pllu(void) | |
2842 | { | |
2843 | struct tegra_clk_pll_freq_table *fentry; | |
2844 | struct tegra_clk_pll pllu; | |
2845 | u32 reg; | |
535f296d | 2846 | int ret; |
e745f992 PDS |
2847 | |
2848 | for (fentry = pll_u_freq_table; fentry->input_rate; fentry++) { | |
2849 | if (fentry->input_rate == pll_ref_freq) | |
2850 | break; | |
2851 | } | |
2852 | ||
2853 | if (!fentry->input_rate) { | |
2854 | pr_err("Unknown PLL_U reference frequency %lu\n", pll_ref_freq); | |
2855 | return -EINVAL; | |
2856 | } | |
2857 | ||
2858 | /* clear IDDQ bit */ | |
2859 | pllu.params = &pll_u_vco_params; | |
2860 | reg = readl_relaxed(clk_base + pllu.params->ext_misc_reg[0]); | |
2861 | reg &= ~BIT(pllu.params->iddq_bit_idx); | |
2862 | writel_relaxed(reg, clk_base + pllu.params->ext_misc_reg[0]); | |
f68cbb35 | 2863 | fence_udelay(5, clk_base); |
e745f992 PDS |
2864 | |
2865 | reg = readl_relaxed(clk_base + PLLU_BASE); | |
2866 | reg &= ~GENMASK(20, 0); | |
2867 | reg |= fentry->m; | |
2868 | reg |= fentry->n << 8; | |
2869 | reg |= fentry->p << 16; | |
2870 | writel(reg, clk_base + PLLU_BASE); | |
f68cbb35 | 2871 | fence_udelay(1, clk_base); |
e745f992 PDS |
2872 | reg |= PLL_ENABLE; |
2873 | writel(reg, clk_base + PLLU_BASE); | |
2874 | ||
535f296d SK |
2875 | /* |
2876 | * During clocks resume, same PLLU init and enable sequence get | |
2877 | * executed. So, readx_poll_timeout_atomic can't be used here as it | |
2878 | * uses ktime_get() and timekeeping resume doesn't happen by that | |
2879 | * time. So, using tegra210_wait_for_mask for PLL LOCK. | |
2880 | */ | |
2881 | ret = tegra210_wait_for_mask(&pllu, PLLU_BASE, PLL_BASE_LOCK); | |
2882 | if (ret) { | |
e745f992 PDS |
2883 | pr_err("Timed out waiting for PLL_U to lock\n"); |
2884 | return -ETIMEDOUT; | |
2885 | } | |
2886 | ||
2887 | return 0; | |
2888 | } | |
2889 | ||
2890 | static int tegra210_init_pllu(void) | |
2891 | { | |
2892 | u32 reg; | |
2893 | int err; | |
2894 | ||
2895 | tegra210_pllu_set_defaults(&pll_u_vco_params); | |
2896 | /* skip initialization when pllu is in hw controlled mode */ | |
2897 | reg = readl_relaxed(clk_base + PLLU_BASE); | |
2898 | if (reg & PLLU_BASE_OVERRIDE) { | |
2899 | if (!(reg & PLL_ENABLE)) { | |
2900 | err = tegra210_enable_pllu(); | |
2901 | if (err < 0) { | |
2902 | WARN_ON(1); | |
2903 | return err; | |
2904 | } | |
2905 | } | |
2906 | /* enable hw controlled mode */ | |
2907 | reg = readl_relaxed(clk_base + PLLU_BASE); | |
2908 | reg &= ~PLLU_BASE_OVERRIDE; | |
2909 | writel(reg, clk_base + PLLU_BASE); | |
2910 | ||
2911 | reg = readl_relaxed(clk_base + PLLU_HW_PWRDN_CFG0); | |
2912 | reg |= PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE | | |
2913 | PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT | | |
2914 | PLLU_HW_PWRDN_CFG0_USE_LOCKDET; | |
2915 | reg &= ~(PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL | | |
2916 | PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL); | |
2917 | writel_relaxed(reg, clk_base + PLLU_HW_PWRDN_CFG0); | |
2918 | ||
2919 | reg = readl_relaxed(clk_base + XUSB_PLL_CFG0); | |
2920 | reg &= ~XUSB_PLL_CFG0_PLLU_LOCK_DLY_MASK; | |
2921 | writel_relaxed(reg, clk_base + XUSB_PLL_CFG0); | |
f68cbb35 | 2922 | fence_udelay(1, clk_base); |
e745f992 PDS |
2923 | |
2924 | reg = readl_relaxed(clk_base + PLLU_HW_PWRDN_CFG0); | |
2925 | reg |= PLLU_HW_PWRDN_CFG0_SEQ_ENABLE; | |
2926 | writel_relaxed(reg, clk_base + PLLU_HW_PWRDN_CFG0); | |
f68cbb35 | 2927 | fence_udelay(1, clk_base); |
e745f992 PDS |
2928 | |
2929 | reg = readl_relaxed(clk_base + PLLU_BASE); | |
2930 | reg &= ~PLLU_BASE_CLKENABLE_USB; | |
2931 | writel_relaxed(reg, clk_base + PLLU_BASE); | |
2932 | } | |
2933 | ||
2934 | /* enable UTMIPLL hw control if not yet done by the bootloader */ | |
2935 | reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); | |
2936 | if (!(reg & UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE)) | |
2937 | tegra210_utmi_param_configure(); | |
2938 | ||
2939 | return 0; | |
2940 | } | |
2941 | ||
05308d7e TR |
2942 | /* |
2943 | * The SOR hardware blocks are driven by two clocks: a module clock that is | |
2944 | * used to access registers and a pixel clock that is sourced from the same | |
2945 | * pixel clock that also drives the head attached to the SOR. The module | |
2946 | * clock is typically called sorX (with X being the SOR instance) and the | |
2947 | * pixel clock is called sorX_out. The source for the SOR pixel clock is | |
2948 | * referred to as the "parent" clock. | |
2949 | * | |
2950 | * On Tegra186 and newer, clocks are provided by the BPMP. Unfortunately the | |
2951 | * BPMP implementation for the SOR clocks doesn't exactly match the above in | |
2952 | * some aspects. For example, the SOR module is really clocked by the pad or | |
2953 | * sor_safe clocks, but BPMP models the sorX clock as being sourced by the | |
2954 | * pixel clocks. Conversely the sorX_out clock is sourced by the sor_safe or | |
2955 | * pad clocks on BPMP. | |
2956 | * | |
2957 | * In order to allow the display driver to deal with all SoC generations in | |
2958 | * a unified way, implement the BPMP semantics in this driver. | |
2959 | */ | |
2960 | ||
2961 | static const char * const sor0_parents[] = { | |
2962 | "pll_d_out0", | |
2963 | }; | |
2964 | ||
2965 | static const char * const sor0_out_parents[] = { | |
2966 | "sor_safe", "sor0_pad_clkout", | |
2967 | }; | |
2968 | ||
2969 | static const char * const sor1_parents[] = { | |
2970 | "pll_p", "pll_d_out0", "pll_d2_out0", "clk_m", | |
2971 | }; | |
2972 | ||
2973 | static u32 sor1_parents_idx[] = { 0, 2, 5, 6 }; | |
2974 | ||
1d3e3c4e JL |
2975 | static const struct clk_div_table mc_div_table_tegra210[] = { |
2976 | { .val = 0, .div = 2 }, | |
2977 | { .val = 1, .div = 4 }, | |
2978 | { .val = 2, .div = 1 }, | |
2979 | { .val = 3, .div = 2 }, | |
2980 | { .val = 0, .div = 0 }, | |
2981 | }; | |
2982 | ||
2983 | static void tegra210_clk_register_mc(const char *name, | |
2984 | const char *parent_name) | |
2985 | { | |
2986 | struct clk *clk; | |
2987 | ||
2988 | clk = clk_register_divider_table(NULL, name, parent_name, | |
2989 | CLK_IS_CRITICAL, | |
2990 | clk_base + CLK_SOURCE_EMC, | |
2991 | 15, 2, CLK_DIVIDER_READ_ONLY, | |
2992 | mc_div_table_tegra210, &emc_lock); | |
2993 | clks[TEGRA210_CLK_MC] = clk; | |
2994 | } | |
2995 | ||
bc2e4d29 TR |
2996 | static const char * const sor1_out_parents[] = { |
2997 | /* | |
2998 | * Bit 0 of the mux selects sor1_pad_clkout, irrespective of bit 1, so | |
2999 | * the sor1_pad_clkout parent appears twice in the list below. This is | |
3000 | * merely to support clk_get_parent() if firmware happened to set | |
3001 | * these bits to 0b11. While not an invalid setting, code should | |
3002 | * always set the bits to 0b01 to select sor1_pad_clkout. | |
3003 | */ | |
05308d7e | 3004 | "sor_safe", "sor1_pad_clkout", "sor1_out", "sor1_pad_clkout", |
bc2e4d29 TR |
3005 | }; |
3006 | ||
bc2e4d29 | 3007 | static struct tegra_periph_init_data tegra210_periph[] = { |
05308d7e TR |
3008 | /* |
3009 | * On Tegra210, the sor0 clock doesn't have a mux it bitfield 31:29, | |
3010 | * but it is hardwired to the pll_d_out0 clock. | |
3011 | */ | |
3012 | TEGRA_INIT_DATA_TABLE("sor0", NULL, NULL, sor0_parents, | |
3013 | CLK_SOURCE_SOR0, 29, 0x0, 0, 0, 0, 0, | |
3014 | 0, 182, 0, tegra_clk_sor0, NULL, 0, | |
3015 | &sor0_lock), | |
3016 | TEGRA_INIT_DATA_TABLE("sor0_out", NULL, NULL, sor0_out_parents, | |
3017 | CLK_SOURCE_SOR0, 14, 0x1, 0, 0, 0, 0, | |
3018 | 0, 0, TEGRA_PERIPH_NO_GATE, tegra_clk_sor0_out, | |
3019 | NULL, 0, &sor0_lock), | |
bc2e4d29 TR |
3020 | TEGRA_INIT_DATA_TABLE("sor1", NULL, NULL, sor1_parents, |
3021 | CLK_SOURCE_SOR1, 29, 0x7, 0, 0, 8, 1, | |
05308d7e TR |
3022 | TEGRA_DIVIDER_ROUND_UP, 183, 0, |
3023 | tegra_clk_sor1, sor1_parents_idx, 0, | |
3024 | &sor1_lock), | |
3025 | TEGRA_INIT_DATA_TABLE("sor1_out", NULL, NULL, sor1_out_parents, | |
3026 | CLK_SOURCE_SOR1, 14, 0x3, 0, 0, 0, 0, | |
3027 | 0, 0, TEGRA_PERIPH_NO_GATE, | |
3028 | tegra_clk_sor1_out, NULL, 0, &sor1_lock), | |
bc2e4d29 TR |
3029 | }; |
3030 | ||
89e423c3 PDS |
3031 | static const char * const la_parents[] = { |
3032 | "pll_p", "pll_c2", "pll_c", "pll_c3", "pll_re_out1", "pll_a1", "clk_m", "pll_c4_out0" | |
3033 | }; | |
3034 | ||
3035 | static struct tegra_clk_periph tegra210_la = | |
ba0eb9d5 | 3036 | TEGRA_CLK_PERIPH(29, 7, 9, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, 76, 0, NULL, NULL); |
89e423c3 | 3037 | |
1d3e3c4e JL |
3038 | static __init void tegra210_periph_clk_init(struct device_node *np, |
3039 | void __iomem *clk_base, | |
6b301a05 RK |
3040 | void __iomem *pmc_base) |
3041 | { | |
3042 | struct clk *clk; | |
bc2e4d29 | 3043 | unsigned int i; |
6b301a05 RK |
3044 | |
3045 | /* xusb_ss_div2 */ | |
3046 | clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0, | |
3047 | 1, 2); | |
3048 | clks[TEGRA210_CLK_XUSB_SS_DIV2] = clk; | |
3049 | ||
74d3ba0b TR |
3050 | clk = tegra_clk_register_periph_fixed("sor_safe", "pll_p", 0, clk_base, |
3051 | 1, 17, 222); | |
3052 | clks[TEGRA210_CLK_SOR_SAFE] = clk; | |
3053 | ||
2e34c2ac | 3054 | clk = tegra_clk_register_periph_fixed("dpaux", "sor_safe", 0, clk_base, |
eede7113 TR |
3055 | 1, 17, 181); |
3056 | clks[TEGRA210_CLK_DPAUX] = clk; | |
3057 | ||
2e34c2ac | 3058 | clk = tegra_clk_register_periph_fixed("dpaux1", "sor_safe", 0, clk_base, |
eede7113 TR |
3059 | 1, 17, 207); |
3060 | clks[TEGRA210_CLK_DPAUX1] = clk; | |
3061 | ||
6b301a05 RK |
3062 | /* pll_d_dsi_out */ |
3063 | clk = clk_register_gate(NULL, "pll_d_dsi_out", "pll_d_out0", 0, | |
3064 | clk_base + PLLD_MISC0, 21, 0, &pll_d_lock); | |
3065 | clks[TEGRA210_CLK_PLL_D_DSI_OUT] = clk; | |
3066 | ||
3067 | /* dsia */ | |
3068 | clk = tegra_clk_register_periph_gate("dsia", "pll_d_dsi_out", 0, | |
3069 | clk_base, 0, 48, | |
3070 | periph_clk_enb_refcnt); | |
3071 | clks[TEGRA210_CLK_DSIA] = clk; | |
3072 | ||
3073 | /* dsib */ | |
3074 | clk = tegra_clk_register_periph_gate("dsib", "pll_d_dsi_out", 0, | |
3075 | clk_base, 0, 82, | |
3076 | periph_clk_enb_refcnt); | |
3077 | clks[TEGRA210_CLK_DSIB] = clk; | |
3078 | ||
dec39632 SK |
3079 | /* csi_tpg */ |
3080 | clk = clk_register_gate(NULL, "csi_tpg", "pll_d", | |
3081 | CLK_SET_RATE_PARENT, clk_base + PLLD_BASE, | |
3082 | 23, 0, &pll_d_lock); | |
3083 | clk_register_clkdev(clk, "csi_tpg", NULL); | |
3084 | clks[TEGRA210_CLK_CSI_TPG] = clk; | |
3085 | ||
89e423c3 PDS |
3086 | /* la */ |
3087 | clk = tegra_clk_register_periph("la", la_parents, | |
3088 | ARRAY_SIZE(la_parents), &tegra210_la, clk_base, | |
3089 | CLK_SOURCE_LA, 0); | |
3090 | clks[TEGRA210_CLK_LA] = clk; | |
3091 | ||
6b301a05 RK |
3092 | /* cml0 */ |
3093 | clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX, | |
3094 | 0, 0, &pll_e_lock); | |
3095 | clk_register_clkdev(clk, "cml0", NULL); | |
3096 | clks[TEGRA210_CLK_CML0] = clk; | |
3097 | ||
3098 | /* cml1 */ | |
3099 | clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX, | |
3100 | 1, 0, &pll_e_lock); | |
3101 | clk_register_clkdev(clk, "cml1", NULL); | |
3102 | clks[TEGRA210_CLK_CML1] = clk; | |
3103 | ||
24c3ebef PDS |
3104 | clk = tegra_clk_register_super_clk("aclk", aclk_parents, |
3105 | ARRAY_SIZE(aclk_parents), 0, clk_base + 0x6e0, | |
3106 | 0, NULL); | |
3107 | clks[TEGRA210_CLK_ACLK] = clk; | |
3108 | ||
c76a69e4 PDS |
3109 | clk = tegra_clk_register_sdmmc_mux_div("sdmmc2", clk_base, |
3110 | CLK_SOURCE_SDMMC2, 9, | |
3111 | TEGRA_DIVIDER_ROUND_UP, 0, NULL); | |
3112 | clks[TEGRA210_CLK_SDMMC2] = clk; | |
3113 | ||
3114 | clk = tegra_clk_register_sdmmc_mux_div("sdmmc4", clk_base, | |
3115 | CLK_SOURCE_SDMMC4, 15, | |
3116 | TEGRA_DIVIDER_ROUND_UP, 0, NULL); | |
3117 | clks[TEGRA210_CLK_SDMMC4] = clk; | |
3118 | ||
bc2e4d29 TR |
3119 | for (i = 0; i < ARRAY_SIZE(tegra210_periph); i++) { |
3120 | struct tegra_periph_init_data *init = &tegra210_periph[i]; | |
3121 | struct clk **clkp; | |
3122 | ||
3123 | clkp = tegra_lookup_dt_id(init->clk_id, tegra210_clks); | |
3124 | if (!clkp) { | |
3125 | pr_warn("clock %u not found\n", init->clk_id); | |
3126 | continue; | |
3127 | } | |
3128 | ||
3129 | clk = tegra_clk_register_periph_data(clk_base, init); | |
3130 | *clkp = clk; | |
3131 | } | |
3132 | ||
6b301a05 | 3133 | tegra_periph_clk_init(clk_base, pmc_base, tegra210_clks, &pll_p_params); |
1d3e3c4e JL |
3134 | |
3135 | /* emc */ | |
3136 | clk = tegra210_clk_register_emc(np, clk_base); | |
3137 | clks[TEGRA210_CLK_EMC] = clk; | |
3138 | ||
3139 | /* mc */ | |
3140 | tegra210_clk_register_mc("mc", "emc"); | |
6b301a05 RK |
3141 | } |
3142 | ||
3143 | static void __init tegra210_pll_init(void __iomem *clk_base, | |
3144 | void __iomem *pmc) | |
3145 | { | |
6b301a05 RK |
3146 | struct clk *clk; |
3147 | ||
3148 | /* PLLC */ | |
ac99afe5 | 3149 | clk = tegra_clk_register_pllc_tegra210("pll_c", "pll_ref", clk_base, |
6b301a05 RK |
3150 | pmc, 0, &pll_c_params, NULL); |
3151 | if (!WARN_ON(IS_ERR(clk))) | |
3152 | clk_register_clkdev(clk, "pll_c", NULL); | |
3153 | clks[TEGRA210_CLK_PLL_C] = clk; | |
3154 | ||
3155 | /* PLLC_OUT1 */ | |
3156 | clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c", | |
3157 | clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, | |
3158 | 8, 8, 1, NULL); | |
3159 | clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div", | |
3160 | clk_base + PLLC_OUT, 1, 0, | |
3161 | CLK_SET_RATE_PARENT, 0, NULL); | |
3162 | clk_register_clkdev(clk, "pll_c_out1", NULL); | |
3163 | clks[TEGRA210_CLK_PLL_C_OUT1] = clk; | |
3164 | ||
3165 | /* PLLC_UD */ | |
3166 | clk = clk_register_fixed_factor(NULL, "pll_c_ud", "pll_c", | |
3167 | CLK_SET_RATE_PARENT, 1, 1); | |
3168 | clk_register_clkdev(clk, "pll_c_ud", NULL); | |
3169 | clks[TEGRA210_CLK_PLL_C_UD] = clk; | |
3170 | ||
3171 | /* PLLC2 */ | |
3172 | clk = tegra_clk_register_pllc_tegra210("pll_c2", "pll_ref", clk_base, | |
3173 | pmc, 0, &pll_c2_params, NULL); | |
3174 | clk_register_clkdev(clk, "pll_c2", NULL); | |
3175 | clks[TEGRA210_CLK_PLL_C2] = clk; | |
3176 | ||
3177 | /* PLLC3 */ | |
3178 | clk = tegra_clk_register_pllc_tegra210("pll_c3", "pll_ref", clk_base, | |
3179 | pmc, 0, &pll_c3_params, NULL); | |
3180 | clk_register_clkdev(clk, "pll_c3", NULL); | |
3181 | clks[TEGRA210_CLK_PLL_C3] = clk; | |
3182 | ||
3183 | /* PLLM */ | |
3184 | clk = tegra_clk_register_pllm("pll_m", "osc", clk_base, pmc, | |
3185 | CLK_SET_RATE_GATE, &pll_m_params, NULL); | |
3186 | clk_register_clkdev(clk, "pll_m", NULL); | |
3187 | clks[TEGRA210_CLK_PLL_M] = clk; | |
3188 | ||
3189 | /* PLLMB */ | |
3190 | clk = tegra_clk_register_pllmb("pll_mb", "osc", clk_base, pmc, | |
3191 | CLK_SET_RATE_GATE, &pll_mb_params, NULL); | |
3192 | clk_register_clkdev(clk, "pll_mb", NULL); | |
3193 | clks[TEGRA210_CLK_PLL_MB] = clk; | |
3194 | ||
6b301a05 RK |
3195 | /* PLLM_UD */ |
3196 | clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m", | |
3197 | CLK_SET_RATE_PARENT, 1, 1); | |
3198 | clk_register_clkdev(clk, "pll_m_ud", NULL); | |
3199 | clks[TEGRA210_CLK_PLL_M_UD] = clk; | |
3200 | ||
cd4d6f35 JL |
3201 | /* PLLMB_UD */ |
3202 | clk = clk_register_fixed_factor(NULL, "pll_mb_ud", "pll_mb", | |
3203 | CLK_SET_RATE_PARENT, 1, 1); | |
3204 | clk_register_clkdev(clk, "pll_mb_ud", NULL); | |
3205 | clks[TEGRA210_CLK_PLL_MB_UD] = clk; | |
3206 | ||
3207 | /* PLLP_UD */ | |
3208 | clk = clk_register_fixed_factor(NULL, "pll_p_ud", "pll_p", | |
3209 | 0, 1, 1); | |
3210 | clks[TEGRA210_CLK_PLL_P_UD] = clk; | |
3211 | ||
6b301a05 | 3212 | /* PLLU_VCO */ |
e745f992 PDS |
3213 | if (!tegra210_init_pllu()) { |
3214 | clk = clk_register_fixed_rate(NULL, "pll_u_vco", "pll_ref", 0, | |
3215 | 480*1000*1000); | |
3216 | clk_register_clkdev(clk, "pll_u_vco", NULL); | |
3217 | clks[TEGRA210_CLK_PLL_U] = clk; | |
3218 | } | |
6b301a05 RK |
3219 | |
3220 | /* PLLU_OUT */ | |
3221 | clk = clk_register_divider_table(NULL, "pll_u_out", "pll_u_vco", 0, | |
3222 | clk_base + PLLU_BASE, 16, 4, 0, | |
3223 | pll_vco_post_div_table, NULL); | |
3224 | clk_register_clkdev(clk, "pll_u_out", NULL); | |
3225 | clks[TEGRA210_CLK_PLL_U_OUT] = clk; | |
3226 | ||
3227 | /* PLLU_OUT1 */ | |
3228 | clk = tegra_clk_register_divider("pll_u_out1_div", "pll_u_out", | |
3229 | clk_base + PLLU_OUTA, 0, | |
3230 | TEGRA_DIVIDER_ROUND_UP, | |
3231 | 8, 8, 1, &pll_u_lock); | |
3232 | clk = tegra_clk_register_pll_out("pll_u_out1", "pll_u_out1_div", | |
3233 | clk_base + PLLU_OUTA, 1, 0, | |
3234 | CLK_SET_RATE_PARENT, 0, &pll_u_lock); | |
3235 | clk_register_clkdev(clk, "pll_u_out1", NULL); | |
3236 | clks[TEGRA210_CLK_PLL_U_OUT1] = clk; | |
3237 | ||
3238 | /* PLLU_OUT2 */ | |
3239 | clk = tegra_clk_register_divider("pll_u_out2_div", "pll_u_out", | |
3240 | clk_base + PLLU_OUTA, 0, | |
3241 | TEGRA_DIVIDER_ROUND_UP, | |
3242 | 24, 8, 1, &pll_u_lock); | |
3243 | clk = tegra_clk_register_pll_out("pll_u_out2", "pll_u_out2_div", | |
3244 | clk_base + PLLU_OUTA, 17, 16, | |
3245 | CLK_SET_RATE_PARENT, 0, &pll_u_lock); | |
3246 | clk_register_clkdev(clk, "pll_u_out2", NULL); | |
3247 | clks[TEGRA210_CLK_PLL_U_OUT2] = clk; | |
3248 | ||
6b301a05 RK |
3249 | /* PLLU_480M */ |
3250 | clk = clk_register_gate(NULL, "pll_u_480M", "pll_u_vco", | |
3251 | CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, | |
3252 | 22, 0, &pll_u_lock); | |
3253 | clk_register_clkdev(clk, "pll_u_480M", NULL); | |
3254 | clks[TEGRA210_CLK_PLL_U_480M] = clk; | |
3255 | ||
3256 | /* PLLU_60M */ | |
3257 | clk = clk_register_gate(NULL, "pll_u_60M", "pll_u_out2", | |
3258 | CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, | |
7157c69a | 3259 | 23, 0, &pll_u_lock); |
6b301a05 RK |
3260 | clk_register_clkdev(clk, "pll_u_60M", NULL); |
3261 | clks[TEGRA210_CLK_PLL_U_60M] = clk; | |
3262 | ||
3263 | /* PLLU_48M */ | |
3264 | clk = clk_register_gate(NULL, "pll_u_48M", "pll_u_out1", | |
3265 | CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, | |
7157c69a | 3266 | 25, 0, &pll_u_lock); |
6b301a05 RK |
3267 | clk_register_clkdev(clk, "pll_u_48M", NULL); |
3268 | clks[TEGRA210_CLK_PLL_U_48M] = clk; | |
3269 | ||
3270 | /* PLLD */ | |
3271 | clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0, | |
3272 | &pll_d_params, &pll_d_lock); | |
3273 | clk_register_clkdev(clk, "pll_d", NULL); | |
3274 | clks[TEGRA210_CLK_PLL_D] = clk; | |
3275 | ||
3276 | /* PLLD_OUT0 */ | |
3277 | clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d", | |
3278 | CLK_SET_RATE_PARENT, 1, 2); | |
3279 | clk_register_clkdev(clk, "pll_d_out0", NULL); | |
3280 | clks[TEGRA210_CLK_PLL_D_OUT0] = clk; | |
3281 | ||
3282 | /* PLLRE */ | |
926655f9 RK |
3283 | clk = tegra_clk_register_pllre_tegra210("pll_re_vco", "pll_ref", |
3284 | clk_base, pmc, 0, | |
3285 | &pll_re_vco_params, | |
3286 | &pll_re_lock, pll_ref_freq); | |
6b301a05 RK |
3287 | clk_register_clkdev(clk, "pll_re_vco", NULL); |
3288 | clks[TEGRA210_CLK_PLL_RE_VCO] = clk; | |
3289 | ||
3290 | clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0, | |
3291 | clk_base + PLLRE_BASE, 16, 5, 0, | |
3292 | pll_vco_post_div_table, &pll_re_lock); | |
3293 | clk_register_clkdev(clk, "pll_re_out", NULL); | |
3294 | clks[TEGRA210_CLK_PLL_RE_OUT] = clk; | |
3295 | ||
926655f9 RK |
3296 | clk = tegra_clk_register_divider("pll_re_out1_div", "pll_re_vco", |
3297 | clk_base + PLLRE_OUT1, 0, | |
3298 | TEGRA_DIVIDER_ROUND_UP, | |
3299 | 8, 8, 1, NULL); | |
3300 | clk = tegra_clk_register_pll_out("pll_re_out1", "pll_re_out1_div", | |
3301 | clk_base + PLLRE_OUT1, 1, 0, | |
3302 | CLK_SET_RATE_PARENT, 0, NULL); | |
3303 | clks[TEGRA210_CLK_PLL_RE_OUT1] = clk; | |
3304 | ||
6b301a05 RK |
3305 | /* PLLE */ |
3306 | clk = tegra_clk_register_plle_tegra210("pll_e", "pll_ref", | |
3307 | clk_base, 0, &pll_e_params, NULL); | |
3308 | clk_register_clkdev(clk, "pll_e", NULL); | |
3309 | clks[TEGRA210_CLK_PLL_E] = clk; | |
3310 | ||
3311 | /* PLLC4 */ | |
3312 | clk = tegra_clk_register_pllre("pll_c4_vco", "pll_ref", clk_base, pmc, | |
3313 | 0, &pll_c4_vco_params, NULL, pll_ref_freq); | |
3314 | clk_register_clkdev(clk, "pll_c4_vco", NULL); | |
3315 | clks[TEGRA210_CLK_PLL_C4] = clk; | |
3316 | ||
3317 | /* PLLC4_OUT0 */ | |
3318 | clk = clk_register_divider_table(NULL, "pll_c4_out0", "pll_c4_vco", 0, | |
3319 | clk_base + PLLC4_BASE, 19, 4, 0, | |
3320 | pll_vco_post_div_table, NULL); | |
3321 | clk_register_clkdev(clk, "pll_c4_out0", NULL); | |
3322 | clks[TEGRA210_CLK_PLL_C4_OUT0] = clk; | |
3323 | ||
3324 | /* PLLC4_OUT1 */ | |
3325 | clk = clk_register_fixed_factor(NULL, "pll_c4_out1", "pll_c4_vco", | |
3326 | CLK_SET_RATE_PARENT, 1, 3); | |
3327 | clk_register_clkdev(clk, "pll_c4_out1", NULL); | |
3328 | clks[TEGRA210_CLK_PLL_C4_OUT1] = clk; | |
3329 | ||
3330 | /* PLLC4_OUT2 */ | |
3331 | clk = clk_register_fixed_factor(NULL, "pll_c4_out2", "pll_c4_vco", | |
3332 | CLK_SET_RATE_PARENT, 1, 5); | |
3333 | clk_register_clkdev(clk, "pll_c4_out2", NULL); | |
3334 | clks[TEGRA210_CLK_PLL_C4_OUT2] = clk; | |
3335 | ||
3336 | /* PLLC4_OUT3 */ | |
3337 | clk = tegra_clk_register_divider("pll_c4_out3_div", "pll_c4_out0", | |
3338 | clk_base + PLLC4_OUT, 0, TEGRA_DIVIDER_ROUND_UP, | |
3339 | 8, 8, 1, NULL); | |
3340 | clk = tegra_clk_register_pll_out("pll_c4_out3", "pll_c4_out3_div", | |
3341 | clk_base + PLLC4_OUT, 1, 0, | |
3342 | CLK_SET_RATE_PARENT, 0, NULL); | |
3343 | clk_register_clkdev(clk, "pll_c4_out3", NULL); | |
3344 | clks[TEGRA210_CLK_PLL_C4_OUT3] = clk; | |
3345 | ||
3346 | /* PLLDP */ | |
3347 | clk = tegra_clk_register_pllss_tegra210("pll_dp", "pll_ref", clk_base, | |
3348 | 0, &pll_dp_params, NULL); | |
3349 | clk_register_clkdev(clk, "pll_dp", NULL); | |
3350 | clks[TEGRA210_CLK_PLL_DP] = clk; | |
3351 | ||
3352 | /* PLLD2 */ | |
3353 | clk = tegra_clk_register_pllss_tegra210("pll_d2", "pll_ref", clk_base, | |
3354 | 0, &pll_d2_params, NULL); | |
3355 | clk_register_clkdev(clk, "pll_d2", NULL); | |
3356 | clks[TEGRA210_CLK_PLL_D2] = clk; | |
3357 | ||
3358 | /* PLLD2_OUT0 */ | |
3359 | clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2", | |
3360 | CLK_SET_RATE_PARENT, 1, 1); | |
3361 | clk_register_clkdev(clk, "pll_d2_out0", NULL); | |
3362 | clks[TEGRA210_CLK_PLL_D2_OUT0] = clk; | |
3363 | ||
3364 | /* PLLP_OUT2 */ | |
3365 | clk = clk_register_fixed_factor(NULL, "pll_p_out2", "pll_p", | |
3366 | CLK_SET_RATE_PARENT, 1, 2); | |
3367 | clk_register_clkdev(clk, "pll_p_out2", NULL); | |
3368 | clks[TEGRA210_CLK_PLL_P_OUT2] = clk; | |
3369 | ||
3370 | } | |
3371 | ||
3372 | /* Tegra210 CPU clock and reset control functions */ | |
3373 | static void tegra210_wait_cpu_in_reset(u32 cpu) | |
3374 | { | |
3375 | unsigned int reg; | |
3376 | ||
3377 | do { | |
3378 | reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS); | |
3379 | cpu_relax(); | |
3380 | } while (!(reg & (1 << cpu))); /* check CPU been reset or not */ | |
3381 | } | |
3382 | ||
3383 | static void tegra210_disable_cpu_clock(u32 cpu) | |
3384 | { | |
3385 | /* flow controller would take care in the power sequence. */ | |
3386 | } | |
3387 | ||
3388 | #ifdef CONFIG_PM_SLEEP | |
535f296d SK |
3389 | #define car_readl(_base, _off) readl_relaxed(clk_base + (_base) + ((_off) * 4)) |
3390 | #define car_writel(_val, _base, _off) \ | |
3391 | writel_relaxed(_val, clk_base + (_base) + ((_off) * 4)) | |
3392 | ||
3393 | static u32 spare_reg_ctx, misc_clk_enb_ctx, clk_msk_arm_ctx; | |
3394 | static u32 cpu_softrst_ctx[3]; | |
3395 | ||
3396 | static int tegra210_clk_suspend(void) | |
3397 | { | |
3398 | unsigned int i; | |
3399 | ||
3400 | clk_save_context(); | |
3401 | ||
3402 | /* | |
3403 | * Save the bootloader configured clock registers SPARE_REG0, | |
3404 | * MISC_CLK_ENB, CLK_MASK_ARM, CPU_SOFTRST_CTRL. | |
3405 | */ | |
3406 | spare_reg_ctx = readl_relaxed(clk_base + SPARE_REG0); | |
3407 | misc_clk_enb_ctx = readl_relaxed(clk_base + MISC_CLK_ENB); | |
3408 | clk_msk_arm_ctx = readl_relaxed(clk_base + CLK_MASK_ARM); | |
3409 | ||
3410 | for (i = 0; i < ARRAY_SIZE(cpu_softrst_ctx); i++) | |
3411 | cpu_softrst_ctx[i] = car_readl(CPU_SOFTRST_CTRL, i); | |
3412 | ||
3413 | tegra_clk_periph_suspend(); | |
3414 | return 0; | |
3415 | } | |
3416 | ||
3417 | static void tegra210_clk_resume(void) | |
3418 | { | |
3419 | unsigned int i; | |
3420 | ||
3421 | tegra_clk_osc_resume(clk_base); | |
3422 | ||
3423 | /* | |
3424 | * Restore the bootloader configured clock registers SPARE_REG0, | |
3425 | * MISC_CLK_ENB, CLK_MASK_ARM, CPU_SOFTRST_CTRL from saved context. | |
3426 | */ | |
3427 | writel_relaxed(spare_reg_ctx, clk_base + SPARE_REG0); | |
3428 | writel_relaxed(misc_clk_enb_ctx, clk_base + MISC_CLK_ENB); | |
3429 | writel_relaxed(clk_msk_arm_ctx, clk_base + CLK_MASK_ARM); | |
3430 | ||
3431 | for (i = 0; i < ARRAY_SIZE(cpu_softrst_ctx); i++) | |
3432 | car_writel(cpu_softrst_ctx[i], CPU_SOFTRST_CTRL, i); | |
3433 | ||
3434 | /* | |
3435 | * Tegra clock programming sequence recommends peripheral clock to | |
3436 | * be enabled prior to changing its clock source and divider to | |
3437 | * prevent glitchless frequency switch. | |
3438 | * So, enable all peripheral clocks before restoring their source | |
3439 | * and dividers. | |
3440 | */ | |
3441 | writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_L, clk_base + CLK_OUT_ENB_L); | |
3442 | writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_H, clk_base + CLK_OUT_ENB_H); | |
3443 | writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_U, clk_base + CLK_OUT_ENB_U); | |
3444 | writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_V, clk_base + CLK_OUT_ENB_V); | |
3445 | writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_W, clk_base + CLK_OUT_ENB_W); | |
3446 | writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_X, clk_base + CLK_OUT_ENB_X); | |
3447 | writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_Y, clk_base + CLK_OUT_ENB_Y); | |
3448 | ||
3449 | /* wait for all writes to happen to have all the clocks enabled */ | |
3450 | fence_udelay(2, clk_base); | |
3451 | ||
3452 | /* restore PLLs and all peripheral clock rates */ | |
3453 | tegra210_init_pllu(); | |
3454 | clk_restore_context(); | |
3455 | ||
3456 | /* restore saved context of peripheral clocks and reset state */ | |
3457 | tegra_clk_periph_resume(); | |
3458 | } | |
3459 | ||
6b301a05 RK |
3460 | static void tegra210_cpu_clock_suspend(void) |
3461 | { | |
3462 | /* switch coresite to clk_m, save off original source */ | |
3463 | tegra210_cpu_clk_sctx.clk_csite_src = | |
3464 | readl(clk_base + CLK_SOURCE_CSITE); | |
3465 | writel(3 << 30, clk_base + CLK_SOURCE_CSITE); | |
3466 | } | |
3467 | ||
3468 | static void tegra210_cpu_clock_resume(void) | |
3469 | { | |
3470 | writel(tegra210_cpu_clk_sctx.clk_csite_src, | |
3471 | clk_base + CLK_SOURCE_CSITE); | |
3472 | } | |
3473 | #endif | |
3474 | ||
535f296d | 3475 | static struct syscore_ops tegra_clk_syscore_ops = { |
07b293c5 | 3476 | #ifdef CONFIG_PM_SLEEP |
535f296d SK |
3477 | .suspend = tegra210_clk_suspend, |
3478 | .resume = tegra210_clk_resume, | |
07b293c5 | 3479 | #endif |
535f296d SK |
3480 | }; |
3481 | ||
6b301a05 RK |
3482 | static struct tegra_cpu_car_ops tegra210_cpu_car_ops = { |
3483 | .wait_for_reset = tegra210_wait_cpu_in_reset, | |
3484 | .disable_clock = tegra210_disable_cpu_clock, | |
3485 | #ifdef CONFIG_PM_SLEEP | |
3486 | .suspend = tegra210_cpu_clock_suspend, | |
3487 | .resume = tegra210_cpu_clock_resume, | |
3488 | #endif | |
3489 | }; | |
3490 | ||
3491 | static const struct of_device_id pmc_match[] __initconst = { | |
3492 | { .compatible = "nvidia,tegra210-pmc" }, | |
3493 | { }, | |
3494 | }; | |
3495 | ||
3496 | static struct tegra_clk_init_table init_table[] __initdata = { | |
3497 | { TEGRA210_CLK_UARTA, TEGRA210_CLK_PLL_P, 408000000, 0 }, | |
3498 | { TEGRA210_CLK_UARTB, TEGRA210_CLK_PLL_P, 408000000, 0 }, | |
3499 | { TEGRA210_CLK_UARTC, TEGRA210_CLK_PLL_P, 408000000, 0 }, | |
3500 | { TEGRA210_CLK_UARTD, TEGRA210_CLK_PLL_P, 408000000, 0 }, | |
efdd205c SK |
3501 | { TEGRA210_CLK_PLL_A, TEGRA210_CLK_CLK_MAX, 564480000, 0 }, |
3502 | { TEGRA210_CLK_PLL_A_OUT0, TEGRA210_CLK_CLK_MAX, 11289600, 0 }, | |
6b301a05 RK |
3503 | { TEGRA210_CLK_I2S0, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 }, |
3504 | { TEGRA210_CLK_I2S1, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 }, | |
3505 | { TEGRA210_CLK_I2S2, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 }, | |
3506 | { TEGRA210_CLK_I2S3, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 }, | |
3507 | { TEGRA210_CLK_I2S4, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 }, | |
3508 | { TEGRA210_CLK_HOST1X, TEGRA210_CLK_PLL_P, 136000000, 1 }, | |
3509 | { TEGRA210_CLK_SCLK_MUX, TEGRA210_CLK_PLL_P, 0, 1 }, | |
2dcabf05 | 3510 | { TEGRA210_CLK_SCLK, TEGRA210_CLK_CLK_MAX, 102000000, 0 }, |
6b301a05 RK |
3511 | { TEGRA210_CLK_DFLL_SOC, TEGRA210_CLK_PLL_P, 51000000, 1 }, |
3512 | { TEGRA210_CLK_DFLL_REF, TEGRA210_CLK_PLL_P, 51000000, 1 }, | |
3513 | { TEGRA210_CLK_SBC4, TEGRA210_CLK_PLL_P, 12000000, 1 }, | |
0d34dfbf | 3514 | { TEGRA210_CLK_PLL_U_OUT1, TEGRA210_CLK_CLK_MAX, 48000000, 1 }, |
6b301a05 RK |
3515 | { TEGRA210_CLK_XUSB_GATE, TEGRA210_CLK_CLK_MAX, 0, 1 }, |
3516 | { TEGRA210_CLK_XUSB_SS_SRC, TEGRA210_CLK_PLL_U_480M, 120000000, 0 }, | |
3517 | { TEGRA210_CLK_XUSB_FS_SRC, TEGRA210_CLK_PLL_U_48M, 48000000, 0 }, | |
3518 | { TEGRA210_CLK_XUSB_HS_SRC, TEGRA210_CLK_XUSB_SS_SRC, 120000000, 0 }, | |
3519 | { TEGRA210_CLK_XUSB_SSP_SRC, TEGRA210_CLK_XUSB_SS_SRC, 120000000, 0 }, | |
3520 | { TEGRA210_CLK_XUSB_FALCON_SRC, TEGRA210_CLK_PLL_P_OUT_XUSB, 204000000, 0 }, | |
3521 | { TEGRA210_CLK_XUSB_HOST_SRC, TEGRA210_CLK_PLL_P_OUT_XUSB, 102000000, 0 }, | |
3522 | { TEGRA210_CLK_XUSB_DEV_SRC, TEGRA210_CLK_PLL_P_OUT_XUSB, 102000000, 0 }, | |
3523 | { TEGRA210_CLK_SATA, TEGRA210_CLK_PLL_P, 104000000, 0 }, | |
3524 | { TEGRA210_CLK_SATA_OOB, TEGRA210_CLK_PLL_P, 204000000, 0 }, | |
6b301a05 RK |
3525 | { TEGRA210_CLK_MSELECT, TEGRA210_CLK_CLK_MAX, 0, 1 }, |
3526 | { TEGRA210_CLK_CSITE, TEGRA210_CLK_CLK_MAX, 0, 1 }, | |
bea1baa1 PDS |
3527 | /* TODO find a way to enable this on-demand */ |
3528 | { TEGRA210_CLK_DBGAPB, TEGRA210_CLK_CLK_MAX, 0, 1 }, | |
6b301a05 RK |
3529 | { TEGRA210_CLK_TSENSOR, TEGRA210_CLK_CLK_M, 400000, 0 }, |
3530 | { TEGRA210_CLK_I2C1, TEGRA210_CLK_PLL_P, 0, 0 }, | |
3531 | { TEGRA210_CLK_I2C2, TEGRA210_CLK_PLL_P, 0, 0 }, | |
3532 | { TEGRA210_CLK_I2C3, TEGRA210_CLK_PLL_P, 0, 0 }, | |
3533 | { TEGRA210_CLK_I2C4, TEGRA210_CLK_PLL_P, 0, 0 }, | |
3534 | { TEGRA210_CLK_I2C5, TEGRA210_CLK_PLL_P, 0, 0 }, | |
3535 | { TEGRA210_CLK_I2C6, TEGRA210_CLK_PLL_P, 0, 0 }, | |
3536 | { TEGRA210_CLK_PLL_DP, TEGRA210_CLK_CLK_MAX, 270000000, 0 }, | |
3537 | { TEGRA210_CLK_SOC_THERM, TEGRA210_CLK_PLL_P, 51000000, 0 }, | |
3538 | { TEGRA210_CLK_CCLK_G, TEGRA210_CLK_CLK_MAX, 0, 1 }, | |
e745f992 | 3539 | { TEGRA210_CLK_PLL_U_OUT2, TEGRA210_CLK_CLK_MAX, 60000000, 1 }, |
845d782d JH |
3540 | { TEGRA210_CLK_SPDIF_IN_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 }, |
3541 | { TEGRA210_CLK_I2S0_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 }, | |
3542 | { TEGRA210_CLK_I2S1_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 }, | |
3543 | { TEGRA210_CLK_I2S2_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 }, | |
3544 | { TEGRA210_CLK_I2S3_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 }, | |
3545 | { TEGRA210_CLK_I2S4_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 }, | |
3546 | { TEGRA210_CLK_VIMCLK_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 }, | |
9caec662 JH |
3547 | { TEGRA210_CLK_HDA, TEGRA210_CLK_PLL_P, 51000000, 0 }, |
3548 | { TEGRA210_CLK_HDA2CODEC_2X, TEGRA210_CLK_PLL_P, 48000000, 0 }, | |
6b301a05 RK |
3549 | /* This MUST be the last entry. */ |
3550 | { TEGRA210_CLK_CLK_MAX, TEGRA210_CLK_CLK_MAX, 0, 0 }, | |
3551 | }; | |
3552 | ||
3553 | /** | |
3554 | * tegra210_clock_apply_init_table - initialize clocks on Tegra210 SoCs | |
3555 | * | |
3556 | * Program an initial clock rate and enable or disable clocks needed | |
3557 | * by the rest of the kernel, for Tegra210 SoCs. It is intended to be | |
3558 | * called by assigning a pointer to it to tegra_clk_apply_init_table - | |
3559 | * this will be called as an arch_initcall. No return value. | |
3560 | */ | |
3561 | static void __init tegra210_clock_apply_init_table(void) | |
3562 | { | |
3563 | tegra_init_from_table(init_table, clks, TEGRA210_CLK_CLK_MAX); | |
3564 | } | |
3565 | ||
68d724ce PDS |
3566 | /** |
3567 | * tegra210_car_barrier - wait for pending writes to the CAR to complete | |
3568 | * | |
3569 | * Wait for any outstanding writes to the CAR MMIO space from this CPU | |
3570 | * to complete before continuing execution. No return value. | |
3571 | */ | |
3572 | static void tegra210_car_barrier(void) | |
3573 | { | |
3574 | readl_relaxed(clk_base + RST_DFLL_DVCO); | |
3575 | } | |
3576 | ||
3577 | /** | |
3578 | * tegra210_clock_assert_dfll_dvco_reset - assert the DFLL's DVCO reset | |
3579 | * | |
3580 | * Assert the reset line of the DFLL's DVCO. No return value. | |
3581 | */ | |
3582 | static void tegra210_clock_assert_dfll_dvco_reset(void) | |
3583 | { | |
3584 | u32 v; | |
3585 | ||
3586 | v = readl_relaxed(clk_base + RST_DFLL_DVCO); | |
3587 | v |= (1 << DVFS_DFLL_RESET_SHIFT); | |
3588 | writel_relaxed(v, clk_base + RST_DFLL_DVCO); | |
3589 | tegra210_car_barrier(); | |
3590 | } | |
3591 | ||
3592 | /** | |
3593 | * tegra210_clock_deassert_dfll_dvco_reset - deassert the DFLL's DVCO reset | |
3594 | * | |
3595 | * Deassert the reset line of the DFLL's DVCO, allowing the DVCO to | |
3596 | * operate. No return value. | |
3597 | */ | |
3598 | static void tegra210_clock_deassert_dfll_dvco_reset(void) | |
3599 | { | |
3600 | u32 v; | |
3601 | ||
3602 | v = readl_relaxed(clk_base + RST_DFLL_DVCO); | |
3603 | v &= ~(1 << DVFS_DFLL_RESET_SHIFT); | |
3604 | writel_relaxed(v, clk_base + RST_DFLL_DVCO); | |
3605 | tegra210_car_barrier(); | |
3606 | } | |
3607 | ||
3608 | static int tegra210_reset_assert(unsigned long id) | |
3609 | { | |
3610 | if (id == TEGRA210_RST_DFLL_DVCO) | |
3611 | tegra210_clock_assert_dfll_dvco_reset(); | |
3612 | else if (id == TEGRA210_RST_ADSP) | |
3613 | writel(GENMASK(26, 21) | BIT(7), | |
3614 | clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_SET); | |
3615 | else | |
3616 | return -EINVAL; | |
3617 | ||
3618 | return 0; | |
3619 | } | |
3620 | ||
3621 | static int tegra210_reset_deassert(unsigned long id) | |
3622 | { | |
3623 | if (id == TEGRA210_RST_DFLL_DVCO) | |
3624 | tegra210_clock_deassert_dfll_dvco_reset(); | |
3625 | else if (id == TEGRA210_RST_ADSP) { | |
3626 | writel(BIT(21), clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_CLR); | |
3627 | /* | |
3628 | * Considering adsp cpu clock (min: 12.5MHZ, max: 1GHz) | |
3629 | * a delay of 5us ensures that it's at least | |
3630 | * 6 * adsp_cpu_cycle_period long. | |
3631 | */ | |
3632 | udelay(5); | |
3633 | writel(GENMASK(26, 22) | BIT(7), | |
3634 | clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_CLR); | |
3635 | } else | |
3636 | return -EINVAL; | |
3637 | ||
3638 | return 0; | |
3639 | } | |
3640 | ||
e403d005 PDS |
3641 | static void tegra210_mbist_clk_init(void) |
3642 | { | |
3643 | unsigned int i, j; | |
3644 | ||
3645 | for (i = 0; i < ARRAY_SIZE(tegra210_pg_mbist_war); i++) { | |
3646 | unsigned int num_clks = tegra210_pg_mbist_war[i].num_clks; | |
3647 | struct clk_bulk_data *clk_data; | |
3648 | ||
3649 | if (!num_clks) | |
3650 | continue; | |
3651 | ||
3652 | clk_data = kmalloc_array(num_clks, sizeof(*clk_data), | |
3653 | GFP_KERNEL); | |
3654 | if (WARN_ON(!clk_data)) | |
3655 | return; | |
3656 | ||
3657 | tegra210_pg_mbist_war[i].clks = clk_data; | |
3658 | for (j = 0; j < num_clks; j++) { | |
3659 | int clk_id = tegra210_pg_mbist_war[i].clk_init_data[j]; | |
3660 | struct clk *clk = clks[clk_id]; | |
3661 | ||
3662 | if (WARN(IS_ERR(clk), "clk_id: %d\n", clk_id)) { | |
3663 | kfree(clk_data); | |
3664 | tegra210_pg_mbist_war[i].clks = NULL; | |
3665 | break; | |
3666 | } | |
3667 | clk_data[j].clk = clk; | |
3668 | } | |
3669 | } | |
3670 | } | |
3671 | ||
6b301a05 RK |
3672 | /** |
3673 | * tegra210_clock_init - Tegra210-specific clock initialization | |
3674 | * @np: struct device_node * of the DT node for the SoC CAR IP block | |
3675 | * | |
3676 | * Register most SoC clocks for the Tegra210 system-on-chip. Intended | |
3677 | * to be called by the OF init code when a DT node with the | |
3678 | * "nvidia,tegra210-car" string is encountered, and declared with | |
3679 | * CLK_OF_DECLARE. No return value. | |
3680 | */ | |
3681 | static void __init tegra210_clock_init(struct device_node *np) | |
3682 | { | |
3683 | struct device_node *node; | |
3684 | u32 value, clk_m_div; | |
3685 | ||
3686 | clk_base = of_iomap(np, 0); | |
3687 | if (!clk_base) { | |
3688 | pr_err("ioremap tegra210 CAR failed\n"); | |
3689 | return; | |
3690 | } | |
3691 | ||
3692 | node = of_find_matching_node(NULL, pmc_match); | |
3693 | if (!node) { | |
3694 | pr_err("Failed to find pmc node\n"); | |
3695 | WARN_ON(1); | |
3696 | return; | |
3697 | } | |
3698 | ||
3699 | pmc_base = of_iomap(node, 0); | |
3700 | if (!pmc_base) { | |
3701 | pr_err("Can't map pmc registers\n"); | |
3702 | WARN_ON(1); | |
3703 | return; | |
3704 | } | |
3705 | ||
e403d005 PDS |
3706 | ahub_base = ioremap(TEGRA210_AHUB_BASE, SZ_64K); |
3707 | if (!ahub_base) { | |
3708 | pr_err("ioremap tegra210 APE failed\n"); | |
3709 | return; | |
3710 | } | |
3711 | ||
3712 | dispa_base = ioremap(TEGRA210_DISPA_BASE, SZ_256K); | |
3713 | if (!dispa_base) { | |
3714 | pr_err("ioremap tegra210 DISPA failed\n"); | |
3715 | return; | |
3716 | } | |
3717 | ||
3718 | vic_base = ioremap(TEGRA210_VIC_BASE, SZ_256K); | |
3719 | if (!vic_base) { | |
3720 | pr_err("ioremap tegra210 VIC failed\n"); | |
3721 | return; | |
3722 | } | |
3723 | ||
6b301a05 RK |
3724 | clks = tegra_clk_init(clk_base, TEGRA210_CLK_CLK_MAX, |
3725 | TEGRA210_CAR_BANK_COUNT); | |
3726 | if (!clks) | |
3727 | return; | |
3728 | ||
5834fd75 | 3729 | value = readl(clk_base + SPARE_REG0) >> CLK_M_DIVISOR_SHIFT; |
6b301a05 RK |
3730 | clk_m_div = (value & CLK_M_DIVISOR_MASK) + 1; |
3731 | ||
3732 | if (tegra_osc_clk_init(clk_base, tegra210_clks, tegra210_input_freq, | |
3733 | ARRAY_SIZE(tegra210_input_freq), clk_m_div, | |
3734 | &osc_freq, &pll_ref_freq) < 0) | |
3735 | return; | |
3736 | ||
3737 | tegra_fixed_clk_init(tegra210_clks); | |
3738 | tegra210_pll_init(clk_base, pmc_base); | |
1d3e3c4e | 3739 | tegra210_periph_clk_init(np, clk_base, pmc_base); |
6b301a05 RK |
3740 | tegra_audio_clk_init(clk_base, pmc_base, tegra210_clks, |
3741 | tegra210_audio_plls, | |
845d782d | 3742 | ARRAY_SIZE(tegra210_audio_plls), 24576000); |
6b301a05 RK |
3743 | |
3744 | /* For Tegra210, PLLD is the only source for DSIA & DSIB */ | |
5834fd75 | 3745 | value = readl(clk_base + PLLD_BASE); |
6b301a05 | 3746 | value &= ~BIT(25); |
5834fd75 | 3747 | writel(value, clk_base + PLLD_BASE); |
6b301a05 RK |
3748 | |
3749 | tegra_clk_apply_init_table = tegra210_clock_apply_init_table; | |
3750 | ||
3751 | tegra_super_clk_gen5_init(clk_base, pmc_base, tegra210_clks, | |
3752 | &pll_x_params); | |
68d724ce PDS |
3753 | tegra_init_special_resets(2, tegra210_reset_assert, |
3754 | tegra210_reset_deassert); | |
3755 | ||
5d797111 | 3756 | tegra_add_of_provider(np, of_clk_src_onecell_get); |
6b301a05 RK |
3757 | tegra_register_devclks(devclks, ARRAY_SIZE(devclks)); |
3758 | ||
e403d005 PDS |
3759 | tegra210_mbist_clk_init(); |
3760 | ||
6b301a05 | 3761 | tegra_cpu_car_ops = &tegra210_cpu_car_ops; |
535f296d SK |
3762 | |
3763 | register_syscore_ops(&tegra_clk_syscore_ops); | |
6b301a05 RK |
3764 | } |
3765 | CLK_OF_DECLARE(tegra210, "nvidia,tegra210-car", tegra210_clock_init); |