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6b301a05 RK |
1 | /* |
2 | * Copyright (c) 2012-2014 NVIDIA CORPORATION. All rights reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License | |
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
15 | */ | |
16 | ||
17 | #include <linux/io.h> | |
18 | #include <linux/clk.h> | |
19 | #include <linux/clk-provider.h> | |
20 | #include <linux/clkdev.h> | |
21 | #include <linux/of.h> | |
22 | #include <linux/of_address.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/export.h> | |
25 | #include <linux/clk/tegra.h> | |
26 | #include <dt-bindings/clock/tegra210-car.h> | |
68d724ce | 27 | #include <dt-bindings/reset/tegra210-car.h> |
e745f992 | 28 | #include <linux/iopoll.h> |
6b301a05 RK |
29 | |
30 | #include "clk.h" | |
31 | #include "clk-id.h" | |
32 | ||
33 | /* | |
34 | * TEGRA210_CAR_BANK_COUNT: the number of peripheral clock register | |
35 | * banks present in the Tegra210 CAR IP block. The banks are | |
36 | * identified by single letters, e.g.: L, H, U, V, W, X, Y. See | |
37 | * periph_regs[] in drivers/clk/tegra/clk.c | |
38 | */ | |
39 | #define TEGRA210_CAR_BANK_COUNT 7 | |
40 | ||
41 | #define CLK_SOURCE_CSITE 0x1d4 | |
42 | #define CLK_SOURCE_EMC 0x19c | |
43 | ||
44 | #define PLLC_BASE 0x80 | |
45 | #define PLLC_OUT 0x84 | |
46 | #define PLLC_MISC0 0x88 | |
47 | #define PLLC_MISC1 0x8c | |
48 | #define PLLC_MISC2 0x5d0 | |
49 | #define PLLC_MISC3 0x5d4 | |
50 | ||
51 | #define PLLC2_BASE 0x4e8 | |
52 | #define PLLC2_MISC0 0x4ec | |
53 | #define PLLC2_MISC1 0x4f0 | |
54 | #define PLLC2_MISC2 0x4f4 | |
55 | #define PLLC2_MISC3 0x4f8 | |
56 | ||
57 | #define PLLC3_BASE 0x4fc | |
58 | #define PLLC3_MISC0 0x500 | |
59 | #define PLLC3_MISC1 0x504 | |
60 | #define PLLC3_MISC2 0x508 | |
61 | #define PLLC3_MISC3 0x50c | |
62 | ||
63 | #define PLLM_BASE 0x90 | |
6b301a05 | 64 | #define PLLM_MISC1 0x98 |
474f2ba2 | 65 | #define PLLM_MISC2 0x9c |
6b301a05 RK |
66 | #define PLLP_BASE 0xa0 |
67 | #define PLLP_MISC0 0xac | |
68 | #define PLLP_MISC1 0x680 | |
69 | #define PLLA_BASE 0xb0 | |
70 | #define PLLA_MISC0 0xbc | |
71 | #define PLLA_MISC1 0xb8 | |
72 | #define PLLA_MISC2 0x5d8 | |
73 | #define PLLD_BASE 0xd0 | |
74 | #define PLLD_MISC0 0xdc | |
75 | #define PLLD_MISC1 0xd8 | |
76 | #define PLLU_BASE 0xc0 | |
77 | #define PLLU_OUTA 0xc4 | |
78 | #define PLLU_MISC0 0xcc | |
79 | #define PLLU_MISC1 0xc8 | |
80 | #define PLLX_BASE 0xe0 | |
81 | #define PLLX_MISC0 0xe4 | |
82 | #define PLLX_MISC1 0x510 | |
83 | #define PLLX_MISC2 0x514 | |
84 | #define PLLX_MISC3 0x518 | |
85 | #define PLLX_MISC4 0x5f0 | |
86 | #define PLLX_MISC5 0x5f4 | |
87 | #define PLLE_BASE 0xe8 | |
88 | #define PLLE_MISC0 0xec | |
89 | #define PLLD2_BASE 0x4b8 | |
90 | #define PLLD2_MISC0 0x4bc | |
91 | #define PLLD2_MISC1 0x570 | |
92 | #define PLLD2_MISC2 0x574 | |
93 | #define PLLD2_MISC3 0x578 | |
94 | #define PLLE_AUX 0x48c | |
95 | #define PLLRE_BASE 0x4c4 | |
96 | #define PLLRE_MISC0 0x4c8 | |
926655f9 | 97 | #define PLLRE_OUT1 0x4cc |
6b301a05 RK |
98 | #define PLLDP_BASE 0x590 |
99 | #define PLLDP_MISC 0x594 | |
100 | ||
101 | #define PLLC4_BASE 0x5a4 | |
102 | #define PLLC4_MISC0 0x5a8 | |
103 | #define PLLC4_OUT 0x5e4 | |
104 | #define PLLMB_BASE 0x5e8 | |
474f2ba2 | 105 | #define PLLMB_MISC1 0x5ec |
6b301a05 RK |
106 | #define PLLA1_BASE 0x6a4 |
107 | #define PLLA1_MISC0 0x6a8 | |
108 | #define PLLA1_MISC1 0x6ac | |
109 | #define PLLA1_MISC2 0x6b0 | |
110 | #define PLLA1_MISC3 0x6b4 | |
111 | ||
112 | #define PLLU_IDDQ_BIT 31 | |
113 | #define PLLCX_IDDQ_BIT 27 | |
114 | #define PLLRE_IDDQ_BIT 24 | |
115 | #define PLLA_IDDQ_BIT 25 | |
116 | #define PLLD_IDDQ_BIT 20 | |
117 | #define PLLSS_IDDQ_BIT 18 | |
118 | #define PLLM_IDDQ_BIT 5 | |
119 | #define PLLMB_IDDQ_BIT 17 | |
120 | #define PLLXP_IDDQ_BIT 3 | |
121 | ||
122 | #define PLLCX_RESET_BIT 30 | |
123 | ||
124 | #define PLL_BASE_LOCK BIT(27) | |
125 | #define PLLCX_BASE_LOCK BIT(26) | |
126 | #define PLLE_MISC_LOCK BIT(11) | |
127 | #define PLLRE_MISC_LOCK BIT(27) | |
128 | ||
129 | #define PLL_MISC_LOCK_ENABLE 18 | |
130 | #define PLLC_MISC_LOCK_ENABLE 24 | |
131 | #define PLLDU_MISC_LOCK_ENABLE 22 | |
132 | #define PLLU_MISC_LOCK_ENABLE 29 | |
133 | #define PLLE_MISC_LOCK_ENABLE 9 | |
134 | #define PLLRE_MISC_LOCK_ENABLE 30 | |
135 | #define PLLSS_MISC_LOCK_ENABLE 30 | |
136 | #define PLLP_MISC_LOCK_ENABLE 18 | |
137 | #define PLLM_MISC_LOCK_ENABLE 4 | |
138 | #define PLLMB_MISC_LOCK_ENABLE 16 | |
139 | #define PLLA_MISC_LOCK_ENABLE 28 | |
140 | #define PLLU_MISC_LOCK_ENABLE 29 | |
141 | #define PLLD_MISC_LOCK_ENABLE 18 | |
142 | ||
143 | #define PLLA_SDM_DIN_MASK 0xffff | |
144 | #define PLLA_SDM_EN_MASK BIT(26) | |
145 | ||
146 | #define PLLD_SDM_EN_MASK BIT(16) | |
147 | ||
148 | #define PLLD2_SDM_EN_MASK BIT(31) | |
030999fe | 149 | #define PLLD2_SSC_EN_MASK 0 |
6b301a05 RK |
150 | |
151 | #define PLLDP_SS_CFG 0x598 | |
152 | #define PLLDP_SDM_EN_MASK BIT(31) | |
153 | #define PLLDP_SSC_EN_MASK BIT(30) | |
154 | #define PLLDP_SS_CTRL1 0x59c | |
155 | #define PLLDP_SS_CTRL2 0x5a0 | |
156 | ||
157 | #define PMC_PLLM_WB0_OVERRIDE 0x1dc | |
158 | #define PMC_PLLM_WB0_OVERRIDE_2 0x2b0 | |
159 | ||
e745f992 PDS |
160 | #define UTMIP_PLL_CFG2 0x488 |
161 | #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6) | |
162 | #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18) | |
163 | #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0) | |
164 | #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP BIT(1) | |
165 | #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2) | |
166 | #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP BIT(3) | |
167 | #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4) | |
168 | #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP BIT(5) | |
169 | #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN BIT(24) | |
170 | #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP BIT(25) | |
171 | ||
172 | #define UTMIP_PLL_CFG1 0x484 | |
173 | #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27) | |
174 | #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0) | |
175 | #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17) | |
176 | #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16) | |
177 | #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15) | |
178 | #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14) | |
179 | #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12) | |
180 | ||
3358d2d9 AB |
181 | #define SATA_PLL_CFG0 0x490 |
182 | #define SATA_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0) | |
183 | #define SATA_PLL_CFG0_PADPLL_USE_LOCKDET BIT(2) | |
59af78d7 PDS |
184 | #define SATA_PLL_CFG0_SATA_SEQ_IN_SWCTL BIT(4) |
185 | #define SATA_PLL_CFG0_SATA_SEQ_RESET_INPUT_VALUE BIT(5) | |
186 | #define SATA_PLL_CFG0_SATA_SEQ_LANE_PD_INPUT_VALUE BIT(6) | |
187 | #define SATA_PLL_CFG0_SATA_SEQ_PADPLL_PD_INPUT_VALUE BIT(7) | |
188 | ||
3358d2d9 AB |
189 | #define SATA_PLL_CFG0_PADPLL_SLEEP_IDDQ BIT(13) |
190 | #define SATA_PLL_CFG0_SEQ_ENABLE BIT(24) | |
191 | ||
192 | #define XUSBIO_PLL_CFG0 0x51c | |
193 | #define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0) | |
194 | #define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL BIT(2) | |
195 | #define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET BIT(6) | |
196 | #define XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ BIT(13) | |
197 | #define XUSBIO_PLL_CFG0_SEQ_ENABLE BIT(24) | |
198 | ||
6b301a05 RK |
199 | #define UTMIPLL_HW_PWRDN_CFG0 0x52c |
200 | #define UTMIPLL_HW_PWRDN_CFG0_UTMIPLL_LOCK BIT(31) | |
201 | #define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE BIT(25) | |
202 | #define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24) | |
203 | #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE BIT(7) | |
204 | #define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET BIT(6) | |
205 | #define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5) | |
206 | #define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL BIT(4) | |
207 | #define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2) | |
208 | #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1) | |
209 | #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0) | |
210 | ||
211 | #define PLLU_HW_PWRDN_CFG0 0x530 | |
212 | #define PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE BIT(28) | |
213 | #define PLLU_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24) | |
214 | #define PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT BIT(7) | |
215 | #define PLLU_HW_PWRDN_CFG0_USE_LOCKDET BIT(6) | |
216 | #define PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2) | |
217 | #define PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL BIT(0) | |
218 | ||
219 | #define XUSB_PLL_CFG0 0x534 | |
220 | #define XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY 0x3ff | |
221 | #define XUSB_PLL_CFG0_PLLU_LOCK_DLY_MASK (0x3ff << 14) | |
222 | ||
223 | #define SPARE_REG0 0x55c | |
224 | #define CLK_M_DIVISOR_SHIFT 2 | |
225 | #define CLK_M_DIVISOR_MASK 0x3 | |
226 | ||
68d724ce PDS |
227 | #define RST_DFLL_DVCO 0x2f4 |
228 | #define DVFS_DFLL_RESET_SHIFT 0 | |
229 | ||
230 | #define CLK_RST_CONTROLLER_RST_DEV_Y_SET 0x2a8 | |
231 | #define CLK_RST_CONTROLLER_RST_DEV_Y_CLR 0x2ac | |
232 | ||
6b301a05 RK |
233 | /* |
234 | * SDM fractional divisor is 16-bit 2's complement signed number within | |
235 | * (-2^12 ... 2^12-1) range. Represented in PLL data structure as unsigned | |
236 | * 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used to | |
237 | * indicate that SDM is disabled. | |
238 | * | |
239 | * Effective ndiv value when SDM is enabled: ndiv + 1/2 + sdm_din/2^13 | |
240 | */ | |
241 | #define PLL_SDM_COEFF BIT(13) | |
242 | #define sdin_din_to_data(din) ((u16)((din) ? : 0xFFFFU)) | |
243 | #define sdin_data_to_din(dat) (((dat) == 0xFFFFU) ? 0 : (s16)dat) | |
a851ea2b AF |
244 | /* This macro returns ndiv effective scaled to SDM range */ |
245 | #define sdin_get_n_eff(cfg) ((cfg)->n * PLL_SDM_COEFF + ((cfg)->sdm_data ? \ | |
246 | (PLL_SDM_COEFF/2 + sdin_data_to_din((cfg)->sdm_data)) : 0)) | |
6b301a05 RK |
247 | |
248 | /* Tegra CPU clock and reset control regs */ | |
249 | #define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470 | |
250 | ||
251 | #ifdef CONFIG_PM_SLEEP | |
252 | static struct cpu_clk_suspend_context { | |
253 | u32 clk_csite_src; | |
254 | } tegra210_cpu_clk_sctx; | |
255 | #endif | |
256 | ||
257 | static void __iomem *clk_base; | |
258 | static void __iomem *pmc_base; | |
259 | ||
260 | static unsigned long osc_freq; | |
261 | static unsigned long pll_ref_freq; | |
262 | ||
263 | static DEFINE_SPINLOCK(pll_d_lock); | |
264 | static DEFINE_SPINLOCK(pll_e_lock); | |
265 | static DEFINE_SPINLOCK(pll_re_lock); | |
266 | static DEFINE_SPINLOCK(pll_u_lock); | |
267 | static DEFINE_SPINLOCK(emc_lock); | |
268 | ||
269 | /* possible OSC frequencies in Hz */ | |
270 | static unsigned long tegra210_input_freq[] = { | |
271 | [5] = 38400000, | |
272 | [8] = 12000000, | |
273 | }; | |
274 | ||
275 | static const char *mux_pllmcp_clkm[] = { | |
4f8d4440 JH |
276 | "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_mb", "pll_mb", |
277 | "pll_p", | |
6b301a05 RK |
278 | }; |
279 | #define mux_pllmcp_clkm_idx NULL | |
280 | ||
281 | #define PLL_ENABLE (1 << 30) | |
282 | ||
283 | #define PLLCX_MISC1_IDDQ (1 << 27) | |
284 | #define PLLCX_MISC0_RESET (1 << 30) | |
285 | ||
286 | #define PLLCX_MISC0_DEFAULT_VALUE 0x40080000 | |
287 | #define PLLCX_MISC0_WRITE_MASK 0x400ffffb | |
288 | #define PLLCX_MISC1_DEFAULT_VALUE 0x08000000 | |
289 | #define PLLCX_MISC1_WRITE_MASK 0x08003cff | |
290 | #define PLLCX_MISC2_DEFAULT_VALUE 0x1f720f05 | |
291 | #define PLLCX_MISC2_WRITE_MASK 0xffffff17 | |
292 | #define PLLCX_MISC3_DEFAULT_VALUE 0x000000c4 | |
293 | #define PLLCX_MISC3_WRITE_MASK 0x00ffffff | |
294 | ||
295 | /* PLLA */ | |
296 | #define PLLA_BASE_IDDQ (1 << 25) | |
297 | #define PLLA_BASE_LOCK (1 << 27) | |
298 | ||
299 | #define PLLA_MISC0_LOCK_ENABLE (1 << 28) | |
300 | #define PLLA_MISC0_LOCK_OVERRIDE (1 << 27) | |
301 | ||
302 | #define PLLA_MISC2_EN_SDM (1 << 26) | |
303 | #define PLLA_MISC2_EN_DYNRAMP (1 << 25) | |
304 | ||
305 | #define PLLA_MISC0_DEFAULT_VALUE 0x12000020 | |
306 | #define PLLA_MISC0_WRITE_MASK 0x7fffffff | |
307 | #define PLLA_MISC2_DEFAULT_VALUE 0x0 | |
308 | #define PLLA_MISC2_WRITE_MASK 0x06ffffff | |
309 | ||
310 | /* PLLD */ | |
311 | #define PLLD_MISC0_EN_SDM (1 << 16) | |
312 | #define PLLD_MISC0_LOCK_OVERRIDE (1 << 17) | |
313 | #define PLLD_MISC0_LOCK_ENABLE (1 << 18) | |
314 | #define PLLD_MISC0_IDDQ (1 << 20) | |
315 | #define PLLD_MISC0_DSI_CLKENABLE (1 << 21) | |
316 | ||
317 | #define PLLD_MISC0_DEFAULT_VALUE 0x00140000 | |
318 | #define PLLD_MISC0_WRITE_MASK 0x3ff7ffff | |
319 | #define PLLD_MISC1_DEFAULT_VALUE 0x20 | |
320 | #define PLLD_MISC1_WRITE_MASK 0x00ffffff | |
321 | ||
322 | /* PLLD2 and PLLDP and PLLC4 */ | |
323 | #define PLLDSS_BASE_LOCK (1 << 27) | |
324 | #define PLLDSS_BASE_LOCK_OVERRIDE (1 << 24) | |
325 | #define PLLDSS_BASE_IDDQ (1 << 18) | |
326 | #define PLLDSS_BASE_REF_SEL_SHIFT 25 | |
327 | #define PLLDSS_BASE_REF_SEL_MASK (0x3 << PLLDSS_BASE_REF_SEL_SHIFT) | |
328 | ||
329 | #define PLLDSS_MISC0_LOCK_ENABLE (1 << 30) | |
330 | ||
331 | #define PLLDSS_MISC1_CFG_EN_SDM (1 << 31) | |
332 | #define PLLDSS_MISC1_CFG_EN_SSC (1 << 30) | |
333 | ||
334 | #define PLLD2_MISC0_DEFAULT_VALUE 0x40000020 | |
335 | #define PLLD2_MISC1_CFG_DEFAULT_VALUE 0x10000000 | |
336 | #define PLLD2_MISC2_CTRL1_DEFAULT_VALUE 0x0 | |
337 | #define PLLD2_MISC3_CTRL2_DEFAULT_VALUE 0x0 | |
338 | ||
339 | #define PLLDP_MISC0_DEFAULT_VALUE 0x40000020 | |
340 | #define PLLDP_MISC1_CFG_DEFAULT_VALUE 0xc0000000 | |
341 | #define PLLDP_MISC2_CTRL1_DEFAULT_VALUE 0xf400f0da | |
342 | #define PLLDP_MISC3_CTRL2_DEFAULT_VALUE 0x2004f400 | |
343 | ||
344 | #define PLLDSS_MISC0_WRITE_MASK 0x47ffffff | |
345 | #define PLLDSS_MISC1_CFG_WRITE_MASK 0xf8000000 | |
346 | #define PLLDSS_MISC2_CTRL1_WRITE_MASK 0xffffffff | |
347 | #define PLLDSS_MISC3_CTRL2_WRITE_MASK 0xffffffff | |
348 | ||
349 | #define PLLC4_MISC0_DEFAULT_VALUE 0x40000000 | |
350 | ||
351 | /* PLLRE */ | |
352 | #define PLLRE_MISC0_LOCK_ENABLE (1 << 30) | |
353 | #define PLLRE_MISC0_LOCK_OVERRIDE (1 << 29) | |
354 | #define PLLRE_MISC0_LOCK (1 << 27) | |
355 | #define PLLRE_MISC0_IDDQ (1 << 24) | |
356 | ||
357 | #define PLLRE_BASE_DEFAULT_VALUE 0x0 | |
358 | #define PLLRE_MISC0_DEFAULT_VALUE 0x41000000 | |
359 | ||
360 | #define PLLRE_BASE_DEFAULT_MASK 0x1c000000 | |
361 | #define PLLRE_MISC0_WRITE_MASK 0x67ffffff | |
362 | ||
363 | /* PLLX */ | |
364 | #define PLLX_USE_DYN_RAMP 1 | |
365 | #define PLLX_BASE_LOCK (1 << 27) | |
366 | ||
367 | #define PLLX_MISC0_FO_G_DISABLE (0x1 << 28) | |
368 | #define PLLX_MISC0_LOCK_ENABLE (0x1 << 18) | |
369 | ||
370 | #define PLLX_MISC2_DYNRAMP_STEPB_SHIFT 24 | |
371 | #define PLLX_MISC2_DYNRAMP_STEPB_MASK (0xFF << PLLX_MISC2_DYNRAMP_STEPB_SHIFT) | |
372 | #define PLLX_MISC2_DYNRAMP_STEPA_SHIFT 16 | |
373 | #define PLLX_MISC2_DYNRAMP_STEPA_MASK (0xFF << PLLX_MISC2_DYNRAMP_STEPA_SHIFT) | |
374 | #define PLLX_MISC2_NDIV_NEW_SHIFT 8 | |
375 | #define PLLX_MISC2_NDIV_NEW_MASK (0xFF << PLLX_MISC2_NDIV_NEW_SHIFT) | |
376 | #define PLLX_MISC2_LOCK_OVERRIDE (0x1 << 4) | |
377 | #define PLLX_MISC2_DYNRAMP_DONE (0x1 << 2) | |
378 | #define PLLX_MISC2_EN_DYNRAMP (0x1 << 0) | |
379 | ||
380 | #define PLLX_MISC3_IDDQ (0x1 << 3) | |
381 | ||
382 | #define PLLX_MISC0_DEFAULT_VALUE PLLX_MISC0_LOCK_ENABLE | |
383 | #define PLLX_MISC0_WRITE_MASK 0x10c40000 | |
384 | #define PLLX_MISC1_DEFAULT_VALUE 0x20 | |
385 | #define PLLX_MISC1_WRITE_MASK 0x00ffffff | |
386 | #define PLLX_MISC2_DEFAULT_VALUE 0x0 | |
387 | #define PLLX_MISC2_WRITE_MASK 0xffffff11 | |
388 | #define PLLX_MISC3_DEFAULT_VALUE PLLX_MISC3_IDDQ | |
389 | #define PLLX_MISC3_WRITE_MASK 0x01ff0f0f | |
390 | #define PLLX_MISC4_DEFAULT_VALUE 0x0 | |
391 | #define PLLX_MISC4_WRITE_MASK 0x8000ffff | |
392 | #define PLLX_MISC5_DEFAULT_VALUE 0x0 | |
393 | #define PLLX_MISC5_WRITE_MASK 0x0000ffff | |
394 | ||
395 | #define PLLX_HW_CTRL_CFG 0x548 | |
396 | #define PLLX_HW_CTRL_CFG_SWCTRL (0x1 << 0) | |
397 | ||
398 | /* PLLMB */ | |
399 | #define PLLMB_BASE_LOCK (1 << 27) | |
400 | ||
474f2ba2 RK |
401 | #define PLLMB_MISC1_LOCK_OVERRIDE (1 << 18) |
402 | #define PLLMB_MISC1_IDDQ (1 << 17) | |
403 | #define PLLMB_MISC1_LOCK_ENABLE (1 << 16) | |
6b301a05 | 404 | |
474f2ba2 RK |
405 | #define PLLMB_MISC1_DEFAULT_VALUE 0x00030000 |
406 | #define PLLMB_MISC1_WRITE_MASK 0x0007ffff | |
6b301a05 RK |
407 | |
408 | /* PLLP */ | |
409 | #define PLLP_BASE_OVERRIDE (1 << 28) | |
410 | #define PLLP_BASE_LOCK (1 << 27) | |
411 | ||
412 | #define PLLP_MISC0_LOCK_ENABLE (1 << 18) | |
413 | #define PLLP_MISC0_LOCK_OVERRIDE (1 << 17) | |
414 | #define PLLP_MISC0_IDDQ (1 << 3) | |
415 | ||
416 | #define PLLP_MISC1_HSIO_EN_SHIFT 29 | |
417 | #define PLLP_MISC1_HSIO_EN (1 << PLLP_MISC1_HSIO_EN_SHIFT) | |
418 | #define PLLP_MISC1_XUSB_EN_SHIFT 28 | |
419 | #define PLLP_MISC1_XUSB_EN (1 << PLLP_MISC1_XUSB_EN_SHIFT) | |
420 | ||
421 | #define PLLP_MISC0_DEFAULT_VALUE 0x00040008 | |
422 | #define PLLP_MISC1_DEFAULT_VALUE 0x0 | |
423 | ||
424 | #define PLLP_MISC0_WRITE_MASK 0xdc6000f | |
425 | #define PLLP_MISC1_WRITE_MASK 0x70ffffff | |
426 | ||
427 | /* PLLU */ | |
428 | #define PLLU_BASE_LOCK (1 << 27) | |
429 | #define PLLU_BASE_OVERRIDE (1 << 24) | |
430 | #define PLLU_BASE_CLKENABLE_USB (1 << 21) | |
431 | #define PLLU_BASE_CLKENABLE_HSIC (1 << 22) | |
432 | #define PLLU_BASE_CLKENABLE_ICUSB (1 << 23) | |
433 | #define PLLU_BASE_CLKENABLE_48M (1 << 25) | |
434 | #define PLLU_BASE_CLKENABLE_ALL (PLLU_BASE_CLKENABLE_USB |\ | |
435 | PLLU_BASE_CLKENABLE_HSIC |\ | |
436 | PLLU_BASE_CLKENABLE_ICUSB |\ | |
437 | PLLU_BASE_CLKENABLE_48M) | |
438 | ||
439 | #define PLLU_MISC0_IDDQ (1 << 31) | |
440 | #define PLLU_MISC0_LOCK_ENABLE (1 << 29) | |
441 | #define PLLU_MISC1_LOCK_OVERRIDE (1 << 0) | |
442 | ||
443 | #define PLLU_MISC0_DEFAULT_VALUE 0xa0000000 | |
444 | #define PLLU_MISC1_DEFAULT_VALUE 0x0 | |
445 | ||
446 | #define PLLU_MISC0_WRITE_MASK 0xbfffffff | |
447 | #define PLLU_MISC1_WRITE_MASK 0x00000007 | |
448 | ||
3358d2d9 AB |
449 | void tegra210_xusb_pll_hw_control_enable(void) |
450 | { | |
451 | u32 val; | |
452 | ||
453 | val = readl_relaxed(clk_base + XUSBIO_PLL_CFG0); | |
454 | val &= ~(XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL | | |
455 | XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL); | |
456 | val |= XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET | | |
457 | XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ; | |
458 | writel_relaxed(val, clk_base + XUSBIO_PLL_CFG0); | |
459 | } | |
460 | EXPORT_SYMBOL_GPL(tegra210_xusb_pll_hw_control_enable); | |
461 | ||
462 | void tegra210_xusb_pll_hw_sequence_start(void) | |
463 | { | |
464 | u32 val; | |
465 | ||
466 | val = readl_relaxed(clk_base + XUSBIO_PLL_CFG0); | |
467 | val |= XUSBIO_PLL_CFG0_SEQ_ENABLE; | |
468 | writel_relaxed(val, clk_base + XUSBIO_PLL_CFG0); | |
469 | } | |
470 | EXPORT_SYMBOL_GPL(tegra210_xusb_pll_hw_sequence_start); | |
471 | ||
472 | void tegra210_sata_pll_hw_control_enable(void) | |
473 | { | |
474 | u32 val; | |
475 | ||
476 | val = readl_relaxed(clk_base + SATA_PLL_CFG0); | |
477 | val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL; | |
478 | val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET | | |
479 | SATA_PLL_CFG0_PADPLL_SLEEP_IDDQ; | |
480 | writel_relaxed(val, clk_base + SATA_PLL_CFG0); | |
481 | } | |
482 | EXPORT_SYMBOL_GPL(tegra210_sata_pll_hw_control_enable); | |
483 | ||
484 | void tegra210_sata_pll_hw_sequence_start(void) | |
485 | { | |
486 | u32 val; | |
487 | ||
488 | val = readl_relaxed(clk_base + SATA_PLL_CFG0); | |
489 | val |= SATA_PLL_CFG0_SEQ_ENABLE; | |
490 | writel_relaxed(val, clk_base + SATA_PLL_CFG0); | |
491 | } | |
492 | EXPORT_SYMBOL_GPL(tegra210_sata_pll_hw_sequence_start); | |
493 | ||
59af78d7 PDS |
494 | void tegra210_set_sata_pll_seq_sw(bool state) |
495 | { | |
496 | u32 val; | |
497 | ||
498 | val = readl_relaxed(clk_base + SATA_PLL_CFG0); | |
499 | if (state) { | |
500 | val |= SATA_PLL_CFG0_SATA_SEQ_IN_SWCTL; | |
501 | val |= SATA_PLL_CFG0_SATA_SEQ_RESET_INPUT_VALUE; | |
502 | val |= SATA_PLL_CFG0_SATA_SEQ_LANE_PD_INPUT_VALUE; | |
503 | val |= SATA_PLL_CFG0_SATA_SEQ_PADPLL_PD_INPUT_VALUE; | |
504 | } else { | |
505 | val &= ~SATA_PLL_CFG0_SATA_SEQ_IN_SWCTL; | |
506 | val &= ~SATA_PLL_CFG0_SATA_SEQ_RESET_INPUT_VALUE; | |
507 | val &= ~SATA_PLL_CFG0_SATA_SEQ_LANE_PD_INPUT_VALUE; | |
508 | val &= ~SATA_PLL_CFG0_SATA_SEQ_PADPLL_PD_INPUT_VALUE; | |
509 | } | |
510 | writel_relaxed(val, clk_base + SATA_PLL_CFG0); | |
511 | } | |
512 | EXPORT_SYMBOL_GPL(tegra210_set_sata_pll_seq_sw); | |
513 | ||
6b301a05 RK |
514 | static inline void _pll_misc_chk_default(void __iomem *base, |
515 | struct tegra_clk_pll_params *params, | |
516 | u8 misc_num, u32 default_val, u32 mask) | |
517 | { | |
518 | u32 boot_val = readl_relaxed(base + params->ext_misc_reg[misc_num]); | |
519 | ||
520 | boot_val &= mask; | |
521 | default_val &= mask; | |
522 | if (boot_val != default_val) { | |
523 | pr_warn("boot misc%d 0x%x: expected 0x%x\n", | |
524 | misc_num, boot_val, default_val); | |
525 | pr_warn(" (comparison mask = 0x%x)\n", mask); | |
526 | params->defaults_set = false; | |
527 | } | |
528 | } | |
529 | ||
530 | /* | |
531 | * PLLCX: PLLC, PLLC2, PLLC3, PLLA1 | |
532 | * Hybrid PLLs with dynamic ramp. Dynamic ramp is allowed for any transition | |
533 | * that changes NDIV only, while PLL is already locked. | |
534 | */ | |
535 | static void pllcx_check_defaults(struct tegra_clk_pll_params *params) | |
536 | { | |
537 | u32 default_val; | |
538 | ||
539 | default_val = PLLCX_MISC0_DEFAULT_VALUE & (~PLLCX_MISC0_RESET); | |
540 | _pll_misc_chk_default(clk_base, params, 0, default_val, | |
541 | PLLCX_MISC0_WRITE_MASK); | |
542 | ||
543 | default_val = PLLCX_MISC1_DEFAULT_VALUE & (~PLLCX_MISC1_IDDQ); | |
544 | _pll_misc_chk_default(clk_base, params, 1, default_val, | |
545 | PLLCX_MISC1_WRITE_MASK); | |
546 | ||
547 | default_val = PLLCX_MISC2_DEFAULT_VALUE; | |
548 | _pll_misc_chk_default(clk_base, params, 2, default_val, | |
549 | PLLCX_MISC2_WRITE_MASK); | |
550 | ||
551 | default_val = PLLCX_MISC3_DEFAULT_VALUE; | |
552 | _pll_misc_chk_default(clk_base, params, 3, default_val, | |
553 | PLLCX_MISC3_WRITE_MASK); | |
554 | } | |
555 | ||
fd360e20 JH |
556 | static void tegra210_pllcx_set_defaults(const char *name, |
557 | struct tegra_clk_pll *pllcx) | |
6b301a05 RK |
558 | { |
559 | pllcx->params->defaults_set = true; | |
560 | ||
1116d5a7 | 561 | if (readl_relaxed(clk_base + pllcx->params->base_reg) & PLL_ENABLE) { |
6b301a05 RK |
562 | /* PLL is ON: only check if defaults already set */ |
563 | pllcx_check_defaults(pllcx->params); | |
1116d5a7 JH |
564 | if (!pllcx->params->defaults_set) |
565 | pr_warn("%s already enabled. Postponing set full defaults\n", | |
566 | name); | |
6b301a05 RK |
567 | return; |
568 | } | |
569 | ||
570 | /* Defaults assert PLL reset, and set IDDQ */ | |
571 | writel_relaxed(PLLCX_MISC0_DEFAULT_VALUE, | |
572 | clk_base + pllcx->params->ext_misc_reg[0]); | |
573 | writel_relaxed(PLLCX_MISC1_DEFAULT_VALUE, | |
574 | clk_base + pllcx->params->ext_misc_reg[1]); | |
575 | writel_relaxed(PLLCX_MISC2_DEFAULT_VALUE, | |
576 | clk_base + pllcx->params->ext_misc_reg[2]); | |
577 | writel_relaxed(PLLCX_MISC3_DEFAULT_VALUE, | |
578 | clk_base + pllcx->params->ext_misc_reg[3]); | |
579 | udelay(1); | |
580 | } | |
581 | ||
fd360e20 | 582 | static void _pllc_set_defaults(struct tegra_clk_pll *pllcx) |
6b301a05 RK |
583 | { |
584 | tegra210_pllcx_set_defaults("PLL_C", pllcx); | |
585 | } | |
586 | ||
fd360e20 | 587 | static void _pllc2_set_defaults(struct tegra_clk_pll *pllcx) |
6b301a05 RK |
588 | { |
589 | tegra210_pllcx_set_defaults("PLL_C2", pllcx); | |
590 | } | |
591 | ||
fd360e20 | 592 | static void _pllc3_set_defaults(struct tegra_clk_pll *pllcx) |
6b301a05 RK |
593 | { |
594 | tegra210_pllcx_set_defaults("PLL_C3", pllcx); | |
595 | } | |
596 | ||
fd360e20 | 597 | static void _plla1_set_defaults(struct tegra_clk_pll *pllcx) |
6b301a05 RK |
598 | { |
599 | tegra210_pllcx_set_defaults("PLL_A1", pllcx); | |
600 | } | |
601 | ||
602 | /* | |
603 | * PLLA | |
604 | * PLL with dynamic ramp and fractional SDM. Dynamic ramp is not used. | |
605 | * Fractional SDM is allowed to provide exact audio rates. | |
606 | */ | |
fd360e20 | 607 | static void tegra210_plla_set_defaults(struct tegra_clk_pll *plla) |
6b301a05 RK |
608 | { |
609 | u32 mask; | |
610 | u32 val = readl_relaxed(clk_base + plla->params->base_reg); | |
611 | ||
612 | plla->params->defaults_set = true; | |
613 | ||
614 | if (val & PLL_ENABLE) { | |
615 | /* | |
616 | * PLL is ON: check if defaults already set, then set those | |
617 | * that can be updated in flight. | |
618 | */ | |
619 | if (val & PLLA_BASE_IDDQ) { | |
620 | pr_warn("PLL_A boot enabled with IDDQ set\n"); | |
621 | plla->params->defaults_set = false; | |
622 | } | |
623 | ||
624 | pr_warn("PLL_A already enabled. Postponing set full defaults\n"); | |
625 | ||
626 | val = PLLA_MISC0_DEFAULT_VALUE; /* ignore lock enable */ | |
627 | mask = PLLA_MISC0_LOCK_ENABLE | PLLA_MISC0_LOCK_OVERRIDE; | |
628 | _pll_misc_chk_default(clk_base, plla->params, 0, val, | |
629 | ~mask & PLLA_MISC0_WRITE_MASK); | |
630 | ||
631 | val = PLLA_MISC2_DEFAULT_VALUE; /* ignore all but control bit */ | |
632 | _pll_misc_chk_default(clk_base, plla->params, 2, val, | |
633 | PLLA_MISC2_EN_DYNRAMP); | |
634 | ||
635 | /* Enable lock detect */ | |
636 | val = readl_relaxed(clk_base + plla->params->ext_misc_reg[0]); | |
637 | val &= ~mask; | |
638 | val |= PLLA_MISC0_DEFAULT_VALUE & mask; | |
639 | writel_relaxed(val, clk_base + plla->params->ext_misc_reg[0]); | |
640 | udelay(1); | |
641 | ||
642 | return; | |
643 | } | |
644 | ||
645 | /* set IDDQ, enable lock detect, disable dynamic ramp and SDM */ | |
646 | val |= PLLA_BASE_IDDQ; | |
647 | writel_relaxed(val, clk_base + plla->params->base_reg); | |
648 | writel_relaxed(PLLA_MISC0_DEFAULT_VALUE, | |
649 | clk_base + plla->params->ext_misc_reg[0]); | |
650 | writel_relaxed(PLLA_MISC2_DEFAULT_VALUE, | |
651 | clk_base + plla->params->ext_misc_reg[2]); | |
652 | udelay(1); | |
653 | } | |
654 | ||
655 | /* | |
656 | * PLLD | |
657 | * PLL with fractional SDM. | |
658 | */ | |
fd360e20 | 659 | static void tegra210_plld_set_defaults(struct tegra_clk_pll *plld) |
6b301a05 RK |
660 | { |
661 | u32 val; | |
662 | u32 mask = 0xffff; | |
663 | ||
664 | plld->params->defaults_set = true; | |
665 | ||
666 | if (readl_relaxed(clk_base + plld->params->base_reg) & | |
667 | PLL_ENABLE) { | |
6b301a05 RK |
668 | |
669 | /* | |
670 | * PLL is ON: check if defaults already set, then set those | |
671 | * that can be updated in flight. | |
672 | */ | |
673 | val = PLLD_MISC1_DEFAULT_VALUE; | |
674 | _pll_misc_chk_default(clk_base, plld->params, 1, | |
675 | val, PLLD_MISC1_WRITE_MASK); | |
676 | ||
677 | /* ignore lock, DSI and SDM controls, make sure IDDQ not set */ | |
678 | val = PLLD_MISC0_DEFAULT_VALUE & (~PLLD_MISC0_IDDQ); | |
679 | mask |= PLLD_MISC0_DSI_CLKENABLE | PLLD_MISC0_LOCK_ENABLE | | |
680 | PLLD_MISC0_LOCK_OVERRIDE | PLLD_MISC0_EN_SDM; | |
681 | _pll_misc_chk_default(clk_base, plld->params, 0, val, | |
682 | ~mask & PLLD_MISC0_WRITE_MASK); | |
683 | ||
8dce89a1 PDS |
684 | if (!plld->params->defaults_set) |
685 | pr_warn("PLL_D already enabled. Postponing set full defaults\n"); | |
686 | ||
6b301a05 RK |
687 | /* Enable lock detect */ |
688 | mask = PLLD_MISC0_LOCK_ENABLE | PLLD_MISC0_LOCK_OVERRIDE; | |
689 | val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]); | |
690 | val &= ~mask; | |
691 | val |= PLLD_MISC0_DEFAULT_VALUE & mask; | |
692 | writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]); | |
693 | udelay(1); | |
694 | ||
695 | return; | |
696 | } | |
697 | ||
698 | val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]); | |
699 | val &= PLLD_MISC0_DSI_CLKENABLE; | |
700 | val |= PLLD_MISC0_DEFAULT_VALUE; | |
701 | /* set IDDQ, enable lock detect, disable SDM */ | |
702 | writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]); | |
703 | writel_relaxed(PLLD_MISC1_DEFAULT_VALUE, clk_base + | |
704 | plld->params->ext_misc_reg[1]); | |
705 | udelay(1); | |
706 | } | |
707 | ||
708 | /* | |
709 | * PLLD2, PLLDP | |
710 | * PLL with fractional SDM and Spread Spectrum (SDM is a must if SSC is used). | |
711 | */ | |
712 | static void plldss_defaults(const char *pll_name, struct tegra_clk_pll *plldss, | |
713 | u32 misc0_val, u32 misc1_val, u32 misc2_val, u32 misc3_val) | |
714 | { | |
715 | u32 default_val; | |
716 | u32 val = readl_relaxed(clk_base + plldss->params->base_reg); | |
717 | ||
718 | plldss->params->defaults_set = true; | |
719 | ||
720 | if (val & PLL_ENABLE) { | |
6b301a05 RK |
721 | |
722 | /* | |
723 | * PLL is ON: check if defaults already set, then set those | |
724 | * that can be updated in flight. | |
725 | */ | |
726 | if (val & PLLDSS_BASE_IDDQ) { | |
727 | pr_warn("plldss boot enabled with IDDQ set\n"); | |
728 | plldss->params->defaults_set = false; | |
729 | } | |
730 | ||
731 | /* ignore lock enable */ | |
732 | default_val = misc0_val; | |
733 | _pll_misc_chk_default(clk_base, plldss->params, 0, default_val, | |
734 | PLLDSS_MISC0_WRITE_MASK & | |
735 | (~PLLDSS_MISC0_LOCK_ENABLE)); | |
736 | ||
737 | /* | |
738 | * If SSC is used, check all settings, otherwise just confirm | |
739 | * that SSC is not used on boot as well. Do nothing when using | |
740 | * this function for PLLC4 that has only MISC0. | |
741 | */ | |
742 | if (plldss->params->ssc_ctrl_en_mask) { | |
743 | default_val = misc1_val; | |
744 | _pll_misc_chk_default(clk_base, plldss->params, 1, | |
745 | default_val, PLLDSS_MISC1_CFG_WRITE_MASK); | |
746 | default_val = misc2_val; | |
747 | _pll_misc_chk_default(clk_base, plldss->params, 2, | |
748 | default_val, PLLDSS_MISC2_CTRL1_WRITE_MASK); | |
749 | default_val = misc3_val; | |
750 | _pll_misc_chk_default(clk_base, plldss->params, 3, | |
751 | default_val, PLLDSS_MISC3_CTRL2_WRITE_MASK); | |
752 | } else if (plldss->params->ext_misc_reg[1]) { | |
753 | default_val = misc1_val; | |
754 | _pll_misc_chk_default(clk_base, plldss->params, 1, | |
755 | default_val, PLLDSS_MISC1_CFG_WRITE_MASK & | |
756 | (~PLLDSS_MISC1_CFG_EN_SDM)); | |
757 | } | |
758 | ||
1934ffd0 PDS |
759 | if (!plldss->params->defaults_set) |
760 | pr_warn("%s already enabled. Postponing set full defaults\n", | |
761 | pll_name); | |
762 | ||
6b301a05 RK |
763 | /* Enable lock detect */ |
764 | if (val & PLLDSS_BASE_LOCK_OVERRIDE) { | |
765 | val &= ~PLLDSS_BASE_LOCK_OVERRIDE; | |
766 | writel_relaxed(val, clk_base + | |
767 | plldss->params->base_reg); | |
768 | } | |
769 | ||
770 | val = readl_relaxed(clk_base + plldss->params->ext_misc_reg[0]); | |
771 | val &= ~PLLDSS_MISC0_LOCK_ENABLE; | |
772 | val |= misc0_val & PLLDSS_MISC0_LOCK_ENABLE; | |
773 | writel_relaxed(val, clk_base + plldss->params->ext_misc_reg[0]); | |
774 | udelay(1); | |
775 | ||
776 | return; | |
777 | } | |
778 | ||
779 | /* set IDDQ, enable lock detect, configure SDM/SSC */ | |
780 | val |= PLLDSS_BASE_IDDQ; | |
781 | val &= ~PLLDSS_BASE_LOCK_OVERRIDE; | |
782 | writel_relaxed(val, clk_base + plldss->params->base_reg); | |
783 | ||
784 | /* When using this function for PLLC4 exit here */ | |
785 | if (!plldss->params->ext_misc_reg[1]) { | |
786 | writel_relaxed(misc0_val, clk_base + | |
787 | plldss->params->ext_misc_reg[0]); | |
788 | udelay(1); | |
789 | return; | |
790 | } | |
791 | ||
792 | writel_relaxed(misc0_val, clk_base + | |
793 | plldss->params->ext_misc_reg[0]); | |
794 | /* if SSC used set by 1st enable */ | |
795 | writel_relaxed(misc1_val & (~PLLDSS_MISC1_CFG_EN_SSC), | |
796 | clk_base + plldss->params->ext_misc_reg[1]); | |
797 | writel_relaxed(misc2_val, clk_base + plldss->params->ext_misc_reg[2]); | |
798 | writel_relaxed(misc3_val, clk_base + plldss->params->ext_misc_reg[3]); | |
799 | udelay(1); | |
800 | } | |
801 | ||
fd360e20 | 802 | static void tegra210_plld2_set_defaults(struct tegra_clk_pll *plld2) |
6b301a05 RK |
803 | { |
804 | plldss_defaults("PLL_D2", plld2, PLLD2_MISC0_DEFAULT_VALUE, | |
805 | PLLD2_MISC1_CFG_DEFAULT_VALUE, | |
806 | PLLD2_MISC2_CTRL1_DEFAULT_VALUE, | |
807 | PLLD2_MISC3_CTRL2_DEFAULT_VALUE); | |
808 | } | |
809 | ||
fd360e20 | 810 | static void tegra210_plldp_set_defaults(struct tegra_clk_pll *plldp) |
6b301a05 RK |
811 | { |
812 | plldss_defaults("PLL_DP", plldp, PLLDP_MISC0_DEFAULT_VALUE, | |
813 | PLLDP_MISC1_CFG_DEFAULT_VALUE, | |
814 | PLLDP_MISC2_CTRL1_DEFAULT_VALUE, | |
815 | PLLDP_MISC3_CTRL2_DEFAULT_VALUE); | |
816 | } | |
817 | ||
818 | /* | |
819 | * PLLC4 | |
820 | * Base and misc0 layout is the same as PLLD2/PLLDP, but no SDM/SSC support. | |
821 | * VCO is exposed to the clock tree via fixed 1/3 and 1/5 dividers. | |
822 | */ | |
fd360e20 | 823 | static void tegra210_pllc4_set_defaults(struct tegra_clk_pll *pllc4) |
6b301a05 RK |
824 | { |
825 | plldss_defaults("PLL_C4", pllc4, PLLC4_MISC0_DEFAULT_VALUE, 0, 0, 0); | |
826 | } | |
827 | ||
828 | /* | |
829 | * PLLRE | |
830 | * VCO is exposed to the clock tree directly along with post-divider output | |
831 | */ | |
fd360e20 | 832 | static void tegra210_pllre_set_defaults(struct tegra_clk_pll *pllre) |
6b301a05 RK |
833 | { |
834 | u32 mask; | |
835 | u32 val = readl_relaxed(clk_base + pllre->params->base_reg); | |
836 | ||
837 | pllre->params->defaults_set = true; | |
838 | ||
839 | if (val & PLL_ENABLE) { | |
840 | pr_warn("PLL_RE already enabled. Postponing set full defaults\n"); | |
841 | ||
842 | /* | |
843 | * PLL is ON: check if defaults already set, then set those | |
844 | * that can be updated in flight. | |
845 | */ | |
846 | val &= PLLRE_BASE_DEFAULT_MASK; | |
847 | if (val != PLLRE_BASE_DEFAULT_VALUE) { | |
848 | pr_warn("pllre boot base 0x%x : expected 0x%x\n", | |
849 | val, PLLRE_BASE_DEFAULT_VALUE); | |
850 | pr_warn("(comparison mask = 0x%x)\n", | |
851 | PLLRE_BASE_DEFAULT_MASK); | |
852 | pllre->params->defaults_set = false; | |
853 | } | |
854 | ||
855 | /* Ignore lock enable */ | |
856 | val = PLLRE_MISC0_DEFAULT_VALUE & (~PLLRE_MISC0_IDDQ); | |
857 | mask = PLLRE_MISC0_LOCK_ENABLE | PLLRE_MISC0_LOCK_OVERRIDE; | |
858 | _pll_misc_chk_default(clk_base, pllre->params, 0, val, | |
859 | ~mask & PLLRE_MISC0_WRITE_MASK); | |
860 | ||
861 | /* Enable lock detect */ | |
862 | val = readl_relaxed(clk_base + pllre->params->ext_misc_reg[0]); | |
863 | val &= ~mask; | |
864 | val |= PLLRE_MISC0_DEFAULT_VALUE & mask; | |
865 | writel_relaxed(val, clk_base + pllre->params->ext_misc_reg[0]); | |
866 | udelay(1); | |
867 | ||
868 | return; | |
869 | } | |
870 | ||
871 | /* set IDDQ, enable lock detect */ | |
872 | val &= ~PLLRE_BASE_DEFAULT_MASK; | |
873 | val |= PLLRE_BASE_DEFAULT_VALUE & PLLRE_BASE_DEFAULT_MASK; | |
874 | writel_relaxed(val, clk_base + pllre->params->base_reg); | |
875 | writel_relaxed(PLLRE_MISC0_DEFAULT_VALUE, | |
876 | clk_base + pllre->params->ext_misc_reg[0]); | |
877 | udelay(1); | |
878 | } | |
879 | ||
880 | static void pllx_get_dyn_steps(struct clk_hw *hw, u32 *step_a, u32 *step_b) | |
881 | { | |
882 | unsigned long input_rate; | |
883 | ||
3dad5c5f RK |
884 | /* cf rate */ |
885 | if (!IS_ERR_OR_NULL(hw->clk)) | |
6b301a05 | 886 | input_rate = clk_hw_get_rate(clk_hw_get_parent(hw)); |
3dad5c5f | 887 | else |
6b301a05 | 888 | input_rate = 38400000; |
3dad5c5f RK |
889 | |
890 | input_rate /= tegra_pll_get_fixed_mdiv(hw, input_rate); | |
6b301a05 RK |
891 | |
892 | switch (input_rate) { | |
893 | case 12000000: | |
894 | case 12800000: | |
895 | case 13000000: | |
896 | *step_a = 0x2B; | |
897 | *step_b = 0x0B; | |
898 | return; | |
899 | case 19200000: | |
900 | *step_a = 0x12; | |
901 | *step_b = 0x08; | |
902 | return; | |
903 | case 38400000: | |
904 | *step_a = 0x04; | |
905 | *step_b = 0x05; | |
906 | return; | |
907 | default: | |
908 | pr_err("%s: Unexpected reference rate %lu\n", | |
909 | __func__, input_rate); | |
910 | BUG(); | |
911 | } | |
912 | } | |
913 | ||
914 | static void pllx_check_defaults(struct tegra_clk_pll *pll) | |
915 | { | |
916 | u32 default_val; | |
917 | ||
918 | default_val = PLLX_MISC0_DEFAULT_VALUE; | |
919 | /* ignore lock enable */ | |
920 | _pll_misc_chk_default(clk_base, pll->params, 0, default_val, | |
921 | PLLX_MISC0_WRITE_MASK & (~PLLX_MISC0_LOCK_ENABLE)); | |
922 | ||
923 | default_val = PLLX_MISC1_DEFAULT_VALUE; | |
924 | _pll_misc_chk_default(clk_base, pll->params, 1, default_val, | |
925 | PLLX_MISC1_WRITE_MASK); | |
926 | ||
927 | /* ignore all but control bit */ | |
928 | default_val = PLLX_MISC2_DEFAULT_VALUE; | |
929 | _pll_misc_chk_default(clk_base, pll->params, 2, | |
930 | default_val, PLLX_MISC2_EN_DYNRAMP); | |
931 | ||
932 | default_val = PLLX_MISC3_DEFAULT_VALUE & (~PLLX_MISC3_IDDQ); | |
933 | _pll_misc_chk_default(clk_base, pll->params, 3, default_val, | |
934 | PLLX_MISC3_WRITE_MASK); | |
935 | ||
936 | default_val = PLLX_MISC4_DEFAULT_VALUE; | |
937 | _pll_misc_chk_default(clk_base, pll->params, 4, default_val, | |
938 | PLLX_MISC4_WRITE_MASK); | |
939 | ||
940 | default_val = PLLX_MISC5_DEFAULT_VALUE; | |
941 | _pll_misc_chk_default(clk_base, pll->params, 5, default_val, | |
942 | PLLX_MISC5_WRITE_MASK); | |
943 | } | |
944 | ||
fd360e20 | 945 | static void tegra210_pllx_set_defaults(struct tegra_clk_pll *pllx) |
6b301a05 RK |
946 | { |
947 | u32 val; | |
948 | u32 step_a, step_b; | |
949 | ||
950 | pllx->params->defaults_set = true; | |
951 | ||
952 | /* Get ready dyn ramp state machine settings */ | |
953 | pllx_get_dyn_steps(&pllx->hw, &step_a, &step_b); | |
954 | val = PLLX_MISC2_DEFAULT_VALUE & (~PLLX_MISC2_DYNRAMP_STEPA_MASK) & | |
955 | (~PLLX_MISC2_DYNRAMP_STEPB_MASK); | |
956 | val |= step_a << PLLX_MISC2_DYNRAMP_STEPA_SHIFT; | |
957 | val |= step_b << PLLX_MISC2_DYNRAMP_STEPB_SHIFT; | |
958 | ||
959 | if (readl_relaxed(clk_base + pllx->params->base_reg) & PLL_ENABLE) { | |
6b301a05 RK |
960 | |
961 | /* | |
962 | * PLL is ON: check if defaults already set, then set those | |
963 | * that can be updated in flight. | |
964 | */ | |
965 | pllx_check_defaults(pllx); | |
966 | ||
8dce89a1 PDS |
967 | if (!pllx->params->defaults_set) |
968 | pr_warn("PLL_X already enabled. Postponing set full defaults\n"); | |
6b301a05 RK |
969 | /* Configure dyn ramp, disable lock override */ |
970 | writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); | |
971 | ||
972 | /* Enable lock detect */ | |
973 | val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[0]); | |
974 | val &= ~PLLX_MISC0_LOCK_ENABLE; | |
975 | val |= PLLX_MISC0_DEFAULT_VALUE & PLLX_MISC0_LOCK_ENABLE; | |
976 | writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[0]); | |
977 | udelay(1); | |
978 | ||
979 | return; | |
980 | } | |
981 | ||
982 | /* Enable lock detect and CPU output */ | |
983 | writel_relaxed(PLLX_MISC0_DEFAULT_VALUE, clk_base + | |
984 | pllx->params->ext_misc_reg[0]); | |
985 | ||
986 | /* Setup */ | |
987 | writel_relaxed(PLLX_MISC1_DEFAULT_VALUE, clk_base + | |
988 | pllx->params->ext_misc_reg[1]); | |
989 | ||
990 | /* Configure dyn ramp state machine, disable lock override */ | |
991 | writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); | |
992 | ||
993 | /* Set IDDQ */ | |
994 | writel_relaxed(PLLX_MISC3_DEFAULT_VALUE, clk_base + | |
995 | pllx->params->ext_misc_reg[3]); | |
996 | ||
997 | /* Disable SDM */ | |
998 | writel_relaxed(PLLX_MISC4_DEFAULT_VALUE, clk_base + | |
999 | pllx->params->ext_misc_reg[4]); | |
1000 | writel_relaxed(PLLX_MISC5_DEFAULT_VALUE, clk_base + | |
1001 | pllx->params->ext_misc_reg[5]); | |
1002 | udelay(1); | |
1003 | } | |
1004 | ||
1005 | /* PLLMB */ | |
fd360e20 | 1006 | static void tegra210_pllmb_set_defaults(struct tegra_clk_pll *pllmb) |
6b301a05 RK |
1007 | { |
1008 | u32 mask, val = readl_relaxed(clk_base + pllmb->params->base_reg); | |
1009 | ||
1010 | pllmb->params->defaults_set = true; | |
1011 | ||
1012 | if (val & PLL_ENABLE) { | |
6b301a05 RK |
1013 | |
1014 | /* | |
1015 | * PLL is ON: check if defaults already set, then set those | |
1016 | * that can be updated in flight. | |
1017 | */ | |
474f2ba2 RK |
1018 | val = PLLMB_MISC1_DEFAULT_VALUE & (~PLLMB_MISC1_IDDQ); |
1019 | mask = PLLMB_MISC1_LOCK_ENABLE | PLLMB_MISC1_LOCK_OVERRIDE; | |
6b301a05 | 1020 | _pll_misc_chk_default(clk_base, pllmb->params, 0, val, |
474f2ba2 | 1021 | ~mask & PLLMB_MISC1_WRITE_MASK); |
6b301a05 | 1022 | |
8dce89a1 PDS |
1023 | if (!pllmb->params->defaults_set) |
1024 | pr_warn("PLL_MB already enabled. Postponing set full defaults\n"); | |
6b301a05 RK |
1025 | /* Enable lock detect */ |
1026 | val = readl_relaxed(clk_base + pllmb->params->ext_misc_reg[0]); | |
1027 | val &= ~mask; | |
474f2ba2 | 1028 | val |= PLLMB_MISC1_DEFAULT_VALUE & mask; |
6b301a05 RK |
1029 | writel_relaxed(val, clk_base + pllmb->params->ext_misc_reg[0]); |
1030 | udelay(1); | |
1031 | ||
1032 | return; | |
1033 | } | |
1034 | ||
1035 | /* set IDDQ, enable lock detect */ | |
474f2ba2 | 1036 | writel_relaxed(PLLMB_MISC1_DEFAULT_VALUE, |
6b301a05 RK |
1037 | clk_base + pllmb->params->ext_misc_reg[0]); |
1038 | udelay(1); | |
1039 | } | |
1040 | ||
1041 | /* | |
1042 | * PLLP | |
1043 | * VCO is exposed to the clock tree directly along with post-divider output. | |
1044 | * Both VCO and post-divider output rates are fixed at 408MHz and 204MHz, | |
1045 | * respectively. | |
1046 | */ | |
1047 | static void pllp_check_defaults(struct tegra_clk_pll *pll, bool enabled) | |
1048 | { | |
1049 | u32 val, mask; | |
1050 | ||
1051 | /* Ignore lock enable (will be set), make sure not in IDDQ if enabled */ | |
1052 | val = PLLP_MISC0_DEFAULT_VALUE & (~PLLP_MISC0_IDDQ); | |
1053 | mask = PLLP_MISC0_LOCK_ENABLE | PLLP_MISC0_LOCK_OVERRIDE; | |
1054 | if (!enabled) | |
1055 | mask |= PLLP_MISC0_IDDQ; | |
1056 | _pll_misc_chk_default(clk_base, pll->params, 0, val, | |
1057 | ~mask & PLLP_MISC0_WRITE_MASK); | |
1058 | ||
1059 | /* Ignore branch controls */ | |
1060 | val = PLLP_MISC1_DEFAULT_VALUE; | |
1061 | mask = PLLP_MISC1_HSIO_EN | PLLP_MISC1_XUSB_EN; | |
1062 | _pll_misc_chk_default(clk_base, pll->params, 1, val, | |
1063 | ~mask & PLLP_MISC1_WRITE_MASK); | |
1064 | } | |
1065 | ||
fd360e20 | 1066 | static void tegra210_pllp_set_defaults(struct tegra_clk_pll *pllp) |
6b301a05 RK |
1067 | { |
1068 | u32 mask; | |
1069 | u32 val = readl_relaxed(clk_base + pllp->params->base_reg); | |
1070 | ||
1071 | pllp->params->defaults_set = true; | |
1072 | ||
1073 | if (val & PLL_ENABLE) { | |
6b301a05 RK |
1074 | |
1075 | /* | |
1076 | * PLL is ON: check if defaults already set, then set those | |
1077 | * that can be updated in flight. | |
1078 | */ | |
1079 | pllp_check_defaults(pllp, true); | |
8dce89a1 PDS |
1080 | if (!pllp->params->defaults_set) |
1081 | pr_warn("PLL_P already enabled. Postponing set full defaults\n"); | |
6b301a05 RK |
1082 | |
1083 | /* Enable lock detect */ | |
1084 | val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[0]); | |
1085 | mask = PLLP_MISC0_LOCK_ENABLE | PLLP_MISC0_LOCK_OVERRIDE; | |
1086 | val &= ~mask; | |
1087 | val |= PLLP_MISC0_DEFAULT_VALUE & mask; | |
1088 | writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[0]); | |
1089 | udelay(1); | |
1090 | ||
1091 | return; | |
1092 | } | |
1093 | ||
1094 | /* set IDDQ, enable lock detect */ | |
1095 | writel_relaxed(PLLP_MISC0_DEFAULT_VALUE, | |
1096 | clk_base + pllp->params->ext_misc_reg[0]); | |
1097 | ||
1098 | /* Preserve branch control */ | |
1099 | val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[1]); | |
1100 | mask = PLLP_MISC1_HSIO_EN | PLLP_MISC1_XUSB_EN; | |
1101 | val &= mask; | |
1102 | val |= ~mask & PLLP_MISC1_DEFAULT_VALUE; | |
1103 | writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[1]); | |
1104 | udelay(1); | |
1105 | } | |
1106 | ||
1107 | /* | |
1108 | * PLLU | |
1109 | * VCO is exposed to the clock tree directly along with post-divider output. | |
1110 | * Both VCO and post-divider output rates are fixed at 480MHz and 240MHz, | |
1111 | * respectively. | |
1112 | */ | |
e745f992 PDS |
1113 | static void pllu_check_defaults(struct tegra_clk_pll_params *params, |
1114 | bool hw_control) | |
6b301a05 RK |
1115 | { |
1116 | u32 val, mask; | |
1117 | ||
1118 | /* Ignore lock enable (will be set) and IDDQ if under h/w control */ | |
1119 | val = PLLU_MISC0_DEFAULT_VALUE & (~PLLU_MISC0_IDDQ); | |
1120 | mask = PLLU_MISC0_LOCK_ENABLE | (hw_control ? PLLU_MISC0_IDDQ : 0); | |
e745f992 | 1121 | _pll_misc_chk_default(clk_base, params, 0, val, |
6b301a05 RK |
1122 | ~mask & PLLU_MISC0_WRITE_MASK); |
1123 | ||
1124 | val = PLLU_MISC1_DEFAULT_VALUE; | |
1125 | mask = PLLU_MISC1_LOCK_OVERRIDE; | |
e745f992 | 1126 | _pll_misc_chk_default(clk_base, params, 1, val, |
6b301a05 RK |
1127 | ~mask & PLLU_MISC1_WRITE_MASK); |
1128 | } | |
1129 | ||
e745f992 | 1130 | static void tegra210_pllu_set_defaults(struct tegra_clk_pll_params *pllu) |
6b301a05 | 1131 | { |
e745f992 | 1132 | u32 val = readl_relaxed(clk_base + pllu->base_reg); |
6b301a05 | 1133 | |
e745f992 | 1134 | pllu->defaults_set = true; |
6b301a05 RK |
1135 | |
1136 | if (val & PLL_ENABLE) { | |
6b301a05 RK |
1137 | |
1138 | /* | |
1139 | * PLL is ON: check if defaults already set, then set those | |
1140 | * that can be updated in flight. | |
1141 | */ | |
1142 | pllu_check_defaults(pllu, false); | |
e745f992 | 1143 | if (!pllu->defaults_set) |
8dce89a1 | 1144 | pr_warn("PLL_U already enabled. Postponing set full defaults\n"); |
6b301a05 RK |
1145 | |
1146 | /* Enable lock detect */ | |
e745f992 | 1147 | val = readl_relaxed(clk_base + pllu->ext_misc_reg[0]); |
6b301a05 RK |
1148 | val &= ~PLLU_MISC0_LOCK_ENABLE; |
1149 | val |= PLLU_MISC0_DEFAULT_VALUE & PLLU_MISC0_LOCK_ENABLE; | |
e745f992 | 1150 | writel_relaxed(val, clk_base + pllu->ext_misc_reg[0]); |
6b301a05 | 1151 | |
e745f992 | 1152 | val = readl_relaxed(clk_base + pllu->ext_misc_reg[1]); |
6b301a05 RK |
1153 | val &= ~PLLU_MISC1_LOCK_OVERRIDE; |
1154 | val |= PLLU_MISC1_DEFAULT_VALUE & PLLU_MISC1_LOCK_OVERRIDE; | |
e745f992 | 1155 | writel_relaxed(val, clk_base + pllu->ext_misc_reg[1]); |
6b301a05 RK |
1156 | udelay(1); |
1157 | ||
1158 | return; | |
1159 | } | |
1160 | ||
1161 | /* set IDDQ, enable lock detect */ | |
1162 | writel_relaxed(PLLU_MISC0_DEFAULT_VALUE, | |
e745f992 | 1163 | clk_base + pllu->ext_misc_reg[0]); |
6b301a05 | 1164 | writel_relaxed(PLLU_MISC1_DEFAULT_VALUE, |
e745f992 | 1165 | clk_base + pllu->ext_misc_reg[1]); |
6b301a05 RK |
1166 | udelay(1); |
1167 | } | |
1168 | ||
1169 | #define mask(w) ((1 << (w)) - 1) | |
1170 | #define divm_mask(p) mask(p->params->div_nmp->divm_width) | |
1171 | #define divn_mask(p) mask(p->params->div_nmp->divn_width) | |
1172 | #define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\ | |
1173 | mask(p->params->div_nmp->divp_width)) | |
1174 | ||
1175 | #define divm_shift(p) ((p)->params->div_nmp->divm_shift) | |
1176 | #define divn_shift(p) ((p)->params->div_nmp->divn_shift) | |
1177 | #define divp_shift(p) ((p)->params->div_nmp->divp_shift) | |
1178 | ||
1179 | #define divm_mask_shifted(p) (divm_mask(p) << divm_shift(p)) | |
1180 | #define divn_mask_shifted(p) (divn_mask(p) << divn_shift(p)) | |
1181 | #define divp_mask_shifted(p) (divp_mask(p) << divp_shift(p)) | |
1182 | ||
1183 | #define PLL_LOCKDET_DELAY 2 /* Lock detection safety delays */ | |
1184 | static int tegra210_wait_for_mask(struct tegra_clk_pll *pll, | |
1185 | u32 reg, u32 mask) | |
1186 | { | |
1187 | int i; | |
1188 | u32 val = 0; | |
1189 | ||
1190 | for (i = 0; i < pll->params->lock_delay / PLL_LOCKDET_DELAY + 1; i++) { | |
1191 | udelay(PLL_LOCKDET_DELAY); | |
1192 | val = readl_relaxed(clk_base + reg); | |
1193 | if ((val & mask) == mask) { | |
1194 | udelay(PLL_LOCKDET_DELAY); | |
1195 | return 0; | |
1196 | } | |
1197 | } | |
1198 | return -ETIMEDOUT; | |
1199 | } | |
1200 | ||
1201 | static int tegra210_pllx_dyn_ramp(struct tegra_clk_pll *pllx, | |
1202 | struct tegra_clk_pll_freq_table *cfg) | |
1203 | { | |
1204 | u32 val, base, ndiv_new_mask; | |
1205 | ||
1206 | ndiv_new_mask = (divn_mask(pllx) >> pllx->params->div_nmp->divn_shift) | |
1207 | << PLLX_MISC2_NDIV_NEW_SHIFT; | |
1208 | ||
1209 | val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[2]); | |
1210 | val &= (~ndiv_new_mask); | |
1211 | val |= cfg->n << PLLX_MISC2_NDIV_NEW_SHIFT; | |
1212 | writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); | |
1213 | udelay(1); | |
1214 | ||
1215 | val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[2]); | |
1216 | val |= PLLX_MISC2_EN_DYNRAMP; | |
1217 | writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); | |
1218 | udelay(1); | |
1219 | ||
1220 | tegra210_wait_for_mask(pllx, pllx->params->ext_misc_reg[2], | |
1221 | PLLX_MISC2_DYNRAMP_DONE); | |
1222 | ||
1223 | base = readl_relaxed(clk_base + pllx->params->base_reg) & | |
1224 | (~divn_mask_shifted(pllx)); | |
1225 | base |= cfg->n << pllx->params->div_nmp->divn_shift; | |
1226 | writel_relaxed(base, clk_base + pllx->params->base_reg); | |
1227 | udelay(1); | |
1228 | ||
1229 | val &= ~PLLX_MISC2_EN_DYNRAMP; | |
1230 | writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); | |
1231 | udelay(1); | |
1232 | ||
1233 | pr_debug("%s: dynamic ramp to m = %u n = %u p = %u, Fout = %lu kHz\n", | |
1234 | __clk_get_name(pllx->hw.clk), cfg->m, cfg->n, cfg->p, | |
1235 | cfg->input_rate / cfg->m * cfg->n / | |
1236 | pllx->params->pdiv_tohw[cfg->p].pdiv / 1000); | |
1237 | ||
1238 | return 0; | |
1239 | } | |
1240 | ||
1241 | /* | |
1242 | * Common configuration for PLLs with fixed input divider policy: | |
1243 | * - always set fixed M-value based on the reference rate | |
1244 | * - always set P-value value 1:1 for output rates above VCO minimum, and | |
1245 | * choose minimum necessary P-value for output rates below VCO maximum | |
1246 | * - calculate N-value based on selected M and P | |
1247 | * - calculate SDM_DIN fractional part | |
1248 | */ | |
1249 | static int tegra210_pll_fixed_mdiv_cfg(struct clk_hw *hw, | |
1250 | struct tegra_clk_pll_freq_table *cfg, | |
1251 | unsigned long rate, unsigned long input_rate) | |
1252 | { | |
1253 | struct tegra_clk_pll *pll = to_clk_pll(hw); | |
1254 | struct tegra_clk_pll_params *params = pll->params; | |
1255 | int p; | |
1256 | unsigned long cf, p_rate; | |
1257 | u32 pdiv; | |
1258 | ||
1259 | if (!rate) | |
1260 | return -EINVAL; | |
1261 | ||
1262 | if (!(params->flags & TEGRA_PLL_VCO_OUT)) { | |
1263 | p = DIV_ROUND_UP(params->vco_min, rate); | |
1264 | p = params->round_p_to_pdiv(p, &pdiv); | |
1265 | } else { | |
1266 | p = rate >= params->vco_min ? 1 : -EINVAL; | |
1267 | } | |
1268 | ||
287980e4 | 1269 | if (p < 0) |
6b301a05 RK |
1270 | return -EINVAL; |
1271 | ||
1272 | cfg->m = tegra_pll_get_fixed_mdiv(hw, input_rate); | |
1273 | cfg->p = p; | |
1274 | ||
1275 | /* Store P as HW value, as that is what is expected */ | |
1276 | cfg->p = tegra_pll_p_div_to_hw(pll, cfg->p); | |
1277 | ||
1278 | p_rate = rate * p; | |
1279 | if (p_rate > params->vco_max) | |
1280 | p_rate = params->vco_max; | |
1281 | cf = input_rate / cfg->m; | |
1282 | cfg->n = p_rate / cf; | |
1283 | ||
1284 | cfg->sdm_data = 0; | |
ef6ed2b9 | 1285 | cfg->output_rate = input_rate; |
6b301a05 RK |
1286 | if (params->sdm_ctrl_reg) { |
1287 | unsigned long rem = p_rate - cf * cfg->n; | |
1288 | /* If ssc is enabled SDM enabled as well, even for integer n */ | |
1289 | if (rem || params->ssc_ctrl_reg) { | |
1290 | u64 s = rem * PLL_SDM_COEFF; | |
1291 | ||
1292 | do_div(s, cf); | |
1293 | s -= PLL_SDM_COEFF / 2; | |
1294 | cfg->sdm_data = sdin_din_to_data(s); | |
1295 | } | |
a851ea2b | 1296 | cfg->output_rate *= sdin_get_n_eff(cfg); |
ef6ed2b9 PDS |
1297 | cfg->output_rate /= p * cfg->m * PLL_SDM_COEFF; |
1298 | } else { | |
1299 | cfg->output_rate *= cfg->n; | |
1300 | cfg->output_rate /= p * cfg->m; | |
6b301a05 RK |
1301 | } |
1302 | ||
1303 | cfg->input_rate = input_rate; | |
6b301a05 RK |
1304 | |
1305 | return 0; | |
1306 | } | |
1307 | ||
1308 | /* | |
1309 | * clk_pll_set_gain - set gain to m, n to calculate correct VCO rate | |
1310 | * | |
1311 | * @cfg: struct tegra_clk_pll_freq_table * cfg | |
1312 | * | |
1313 | * For Normal mode: | |
1314 | * Fvco = Fref * NDIV / MDIV | |
1315 | * | |
1316 | * For fractional mode: | |
1317 | * Fvco = Fref * (NDIV + 0.5 + SDM_DIN / PLL_SDM_COEFF) / MDIV | |
1318 | */ | |
1319 | static void tegra210_clk_pll_set_gain(struct tegra_clk_pll_freq_table *cfg) | |
1320 | { | |
a851ea2b | 1321 | cfg->n = sdin_get_n_eff(cfg); |
6b301a05 RK |
1322 | cfg->m *= PLL_SDM_COEFF; |
1323 | } | |
1324 | ||
fd360e20 JH |
1325 | static unsigned long |
1326 | tegra210_clk_adjust_vco_min(struct tegra_clk_pll_params *params, | |
1327 | unsigned long parent_rate) | |
6b301a05 RK |
1328 | { |
1329 | unsigned long vco_min = params->vco_min; | |
1330 | ||
1331 | params->vco_min += DIV_ROUND_UP(parent_rate, PLL_SDM_COEFF); | |
1332 | vco_min = min(vco_min, params->vco_min); | |
1333 | ||
1334 | return vco_min; | |
1335 | } | |
1336 | ||
1337 | static struct div_nmp pllx_nmp = { | |
1338 | .divm_shift = 0, | |
1339 | .divm_width = 8, | |
1340 | .divn_shift = 8, | |
1341 | .divn_width = 8, | |
1342 | .divp_shift = 20, | |
1343 | .divp_width = 5, | |
1344 | }; | |
1345 | /* | |
1346 | * PLL post divider maps - two types: quasi-linear and exponential | |
1347 | * post divider. | |
1348 | */ | |
1349 | #define PLL_QLIN_PDIV_MAX 16 | |
1350 | static const struct pdiv_map pll_qlin_pdiv_to_hw[] = { | |
1351 | { .pdiv = 1, .hw_val = 0 }, | |
1352 | { .pdiv = 2, .hw_val = 1 }, | |
1353 | { .pdiv = 3, .hw_val = 2 }, | |
1354 | { .pdiv = 4, .hw_val = 3 }, | |
1355 | { .pdiv = 5, .hw_val = 4 }, | |
1356 | { .pdiv = 6, .hw_val = 5 }, | |
1357 | { .pdiv = 8, .hw_val = 6 }, | |
1358 | { .pdiv = 9, .hw_val = 7 }, | |
1359 | { .pdiv = 10, .hw_val = 8 }, | |
1360 | { .pdiv = 12, .hw_val = 9 }, | |
1361 | { .pdiv = 15, .hw_val = 10 }, | |
1362 | { .pdiv = 16, .hw_val = 11 }, | |
1363 | { .pdiv = 18, .hw_val = 12 }, | |
1364 | { .pdiv = 20, .hw_val = 13 }, | |
1365 | { .pdiv = 24, .hw_val = 14 }, | |
1366 | { .pdiv = 30, .hw_val = 15 }, | |
1367 | { .pdiv = 32, .hw_val = 16 }, | |
1368 | }; | |
1369 | ||
1370 | static u32 pll_qlin_p_to_pdiv(u32 p, u32 *pdiv) | |
1371 | { | |
1372 | int i; | |
1373 | ||
1374 | if (p) { | |
1375 | for (i = 0; i <= PLL_QLIN_PDIV_MAX; i++) { | |
1376 | if (p <= pll_qlin_pdiv_to_hw[i].pdiv) { | |
1377 | if (pdiv) | |
1378 | *pdiv = i; | |
1379 | return pll_qlin_pdiv_to_hw[i].pdiv; | |
1380 | } | |
1381 | } | |
1382 | } | |
1383 | ||
1384 | return -EINVAL; | |
1385 | } | |
1386 | ||
1387 | #define PLL_EXPO_PDIV_MAX 7 | |
1388 | static const struct pdiv_map pll_expo_pdiv_to_hw[] = { | |
1389 | { .pdiv = 1, .hw_val = 0 }, | |
1390 | { .pdiv = 2, .hw_val = 1 }, | |
1391 | { .pdiv = 4, .hw_val = 2 }, | |
1392 | { .pdiv = 8, .hw_val = 3 }, | |
1393 | { .pdiv = 16, .hw_val = 4 }, | |
1394 | { .pdiv = 32, .hw_val = 5 }, | |
1395 | { .pdiv = 64, .hw_val = 6 }, | |
1396 | { .pdiv = 128, .hw_val = 7 }, | |
1397 | }; | |
1398 | ||
1399 | static u32 pll_expo_p_to_pdiv(u32 p, u32 *pdiv) | |
1400 | { | |
1401 | if (p) { | |
1402 | u32 i = fls(p); | |
1403 | ||
1404 | if (i == ffs(p)) | |
1405 | i--; | |
1406 | ||
1407 | if (i <= PLL_EXPO_PDIV_MAX) { | |
1408 | if (pdiv) | |
1409 | *pdiv = i; | |
1410 | return 1 << i; | |
1411 | } | |
1412 | } | |
1413 | return -EINVAL; | |
1414 | } | |
1415 | ||
1416 | static struct tegra_clk_pll_freq_table pll_x_freq_table[] = { | |
1417 | /* 1 GHz */ | |
eddb65e7 TR |
1418 | { 12000000, 1000000000, 166, 1, 2, 0 }, /* actual: 996.0 MHz */ |
1419 | { 13000000, 1000000000, 153, 1, 2, 0 }, /* actual: 994.0 MHz */ | |
1420 | { 38400000, 1000000000, 156, 3, 2, 0 }, /* actual: 998.4 MHz */ | |
6b301a05 RK |
1421 | { 0, 0, 0, 0, 0, 0 }, |
1422 | }; | |
1423 | ||
1424 | static struct tegra_clk_pll_params pll_x_params = { | |
1425 | .input_min = 12000000, | |
1426 | .input_max = 800000000, | |
1427 | .cf_min = 12000000, | |
1428 | .cf_max = 38400000, | |
1429 | .vco_min = 1350000000, | |
1430 | .vco_max = 3000000000UL, | |
1431 | .base_reg = PLLX_BASE, | |
1432 | .misc_reg = PLLX_MISC0, | |
1433 | .lock_mask = PLL_BASE_LOCK, | |
1434 | .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, | |
1435 | .lock_delay = 300, | |
1436 | .ext_misc_reg[0] = PLLX_MISC0, | |
1437 | .ext_misc_reg[1] = PLLX_MISC1, | |
1438 | .ext_misc_reg[2] = PLLX_MISC2, | |
1439 | .ext_misc_reg[3] = PLLX_MISC3, | |
1440 | .ext_misc_reg[4] = PLLX_MISC4, | |
1441 | .ext_misc_reg[5] = PLLX_MISC5, | |
1442 | .iddq_reg = PLLX_MISC3, | |
1443 | .iddq_bit_idx = PLLXP_IDDQ_BIT, | |
1444 | .max_p = PLL_QLIN_PDIV_MAX, | |
1445 | .mdiv_default = 2, | |
1446 | .dyn_ramp_reg = PLLX_MISC2, | |
1447 | .stepa_shift = 16, | |
1448 | .stepb_shift = 24, | |
1449 | .round_p_to_pdiv = pll_qlin_p_to_pdiv, | |
1450 | .pdiv_tohw = pll_qlin_pdiv_to_hw, | |
1451 | .div_nmp = &pllx_nmp, | |
1452 | .freq_table = pll_x_freq_table, | |
1453 | .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, | |
1454 | .dyn_ramp = tegra210_pllx_dyn_ramp, | |
1455 | .set_defaults = tegra210_pllx_set_defaults, | |
1456 | .calc_rate = tegra210_pll_fixed_mdiv_cfg, | |
1457 | }; | |
1458 | ||
1459 | static struct div_nmp pllc_nmp = { | |
1460 | .divm_shift = 0, | |
1461 | .divm_width = 8, | |
1462 | .divn_shift = 10, | |
1463 | .divn_width = 8, | |
1464 | .divp_shift = 20, | |
1465 | .divp_width = 5, | |
1466 | }; | |
1467 | ||
1468 | static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = { | |
eddb65e7 TR |
1469 | { 12000000, 510000000, 85, 1, 2, 0 }, |
1470 | { 13000000, 510000000, 78, 1, 2, 0 }, /* actual: 507.0 MHz */ | |
1471 | { 38400000, 510000000, 79, 3, 2, 0 }, /* actual: 505.6 MHz */ | |
6b301a05 RK |
1472 | { 0, 0, 0, 0, 0, 0 }, |
1473 | }; | |
1474 | ||
1475 | static struct tegra_clk_pll_params pll_c_params = { | |
1476 | .input_min = 12000000, | |
1477 | .input_max = 700000000, | |
1478 | .cf_min = 12000000, | |
1479 | .cf_max = 50000000, | |
1480 | .vco_min = 600000000, | |
1481 | .vco_max = 1200000000, | |
1482 | .base_reg = PLLC_BASE, | |
1483 | .misc_reg = PLLC_MISC0, | |
1484 | .lock_mask = PLL_BASE_LOCK, | |
1485 | .lock_delay = 300, | |
1486 | .iddq_reg = PLLC_MISC1, | |
1487 | .iddq_bit_idx = PLLCX_IDDQ_BIT, | |
1488 | .reset_reg = PLLC_MISC0, | |
1489 | .reset_bit_idx = PLLCX_RESET_BIT, | |
1490 | .max_p = PLL_QLIN_PDIV_MAX, | |
1491 | .ext_misc_reg[0] = PLLC_MISC0, | |
1492 | .ext_misc_reg[1] = PLLC_MISC1, | |
1493 | .ext_misc_reg[2] = PLLC_MISC2, | |
1494 | .ext_misc_reg[3] = PLLC_MISC3, | |
1495 | .round_p_to_pdiv = pll_qlin_p_to_pdiv, | |
1496 | .pdiv_tohw = pll_qlin_pdiv_to_hw, | |
1497 | .mdiv_default = 3, | |
1498 | .div_nmp = &pllc_nmp, | |
1499 | .freq_table = pll_cx_freq_table, | |
14050118 | 1500 | .flags = TEGRA_PLL_USE_LOCK, |
6b301a05 RK |
1501 | .set_defaults = _pllc_set_defaults, |
1502 | .calc_rate = tegra210_pll_fixed_mdiv_cfg, | |
1503 | }; | |
1504 | ||
1505 | static struct div_nmp pllcx_nmp = { | |
1506 | .divm_shift = 0, | |
1507 | .divm_width = 8, | |
1508 | .divn_shift = 10, | |
1509 | .divn_width = 8, | |
1510 | .divp_shift = 20, | |
1511 | .divp_width = 5, | |
1512 | }; | |
1513 | ||
1514 | static struct tegra_clk_pll_params pll_c2_params = { | |
1515 | .input_min = 12000000, | |
1516 | .input_max = 700000000, | |
1517 | .cf_min = 12000000, | |
1518 | .cf_max = 50000000, | |
1519 | .vco_min = 600000000, | |
1520 | .vco_max = 1200000000, | |
1521 | .base_reg = PLLC2_BASE, | |
1522 | .misc_reg = PLLC2_MISC0, | |
1523 | .iddq_reg = PLLC2_MISC1, | |
1524 | .iddq_bit_idx = PLLCX_IDDQ_BIT, | |
1525 | .reset_reg = PLLC2_MISC0, | |
1526 | .reset_bit_idx = PLLCX_RESET_BIT, | |
1527 | .lock_mask = PLLCX_BASE_LOCK, | |
1528 | .lock_delay = 300, | |
1529 | .round_p_to_pdiv = pll_qlin_p_to_pdiv, | |
1530 | .pdiv_tohw = pll_qlin_pdiv_to_hw, | |
1531 | .mdiv_default = 3, | |
1532 | .div_nmp = &pllcx_nmp, | |
1533 | .max_p = PLL_QLIN_PDIV_MAX, | |
1534 | .ext_misc_reg[0] = PLLC2_MISC0, | |
1535 | .ext_misc_reg[1] = PLLC2_MISC1, | |
1536 | .ext_misc_reg[2] = PLLC2_MISC2, | |
1537 | .ext_misc_reg[3] = PLLC2_MISC3, | |
1538 | .freq_table = pll_cx_freq_table, | |
14050118 | 1539 | .flags = TEGRA_PLL_USE_LOCK, |
6b301a05 RK |
1540 | .set_defaults = _pllc2_set_defaults, |
1541 | .calc_rate = tegra210_pll_fixed_mdiv_cfg, | |
1542 | }; | |
1543 | ||
1544 | static struct tegra_clk_pll_params pll_c3_params = { | |
1545 | .input_min = 12000000, | |
1546 | .input_max = 700000000, | |
1547 | .cf_min = 12000000, | |
1548 | .cf_max = 50000000, | |
1549 | .vco_min = 600000000, | |
1550 | .vco_max = 1200000000, | |
1551 | .base_reg = PLLC3_BASE, | |
1552 | .misc_reg = PLLC3_MISC0, | |
1553 | .lock_mask = PLLCX_BASE_LOCK, | |
1554 | .lock_delay = 300, | |
1555 | .iddq_reg = PLLC3_MISC1, | |
1556 | .iddq_bit_idx = PLLCX_IDDQ_BIT, | |
1557 | .reset_reg = PLLC3_MISC0, | |
1558 | .reset_bit_idx = PLLCX_RESET_BIT, | |
1559 | .round_p_to_pdiv = pll_qlin_p_to_pdiv, | |
1560 | .pdiv_tohw = pll_qlin_pdiv_to_hw, | |
1561 | .mdiv_default = 3, | |
1562 | .div_nmp = &pllcx_nmp, | |
1563 | .max_p = PLL_QLIN_PDIV_MAX, | |
1564 | .ext_misc_reg[0] = PLLC3_MISC0, | |
1565 | .ext_misc_reg[1] = PLLC3_MISC1, | |
1566 | .ext_misc_reg[2] = PLLC3_MISC2, | |
1567 | .ext_misc_reg[3] = PLLC3_MISC3, | |
1568 | .freq_table = pll_cx_freq_table, | |
14050118 | 1569 | .flags = TEGRA_PLL_USE_LOCK, |
6b301a05 RK |
1570 | .set_defaults = _pllc3_set_defaults, |
1571 | .calc_rate = tegra210_pll_fixed_mdiv_cfg, | |
1572 | }; | |
1573 | ||
1574 | static struct div_nmp pllss_nmp = { | |
1575 | .divm_shift = 0, | |
1576 | .divm_width = 8, | |
1577 | .divn_shift = 8, | |
1578 | .divn_width = 8, | |
1579 | .divp_shift = 19, | |
1580 | .divp_width = 5, | |
1581 | }; | |
1582 | ||
1583 | static struct tegra_clk_pll_freq_table pll_c4_vco_freq_table[] = { | |
eddb65e7 TR |
1584 | { 12000000, 600000000, 50, 1, 1, 0 }, |
1585 | { 13000000, 600000000, 46, 1, 1, 0 }, /* actual: 598.0 MHz */ | |
1586 | { 38400000, 600000000, 62, 4, 1, 0 }, /* actual: 595.2 MHz */ | |
6b301a05 RK |
1587 | { 0, 0, 0, 0, 0, 0 }, |
1588 | }; | |
1589 | ||
1590 | static const struct clk_div_table pll_vco_post_div_table[] = { | |
1591 | { .val = 0, .div = 1 }, | |
1592 | { .val = 1, .div = 2 }, | |
1593 | { .val = 2, .div = 3 }, | |
1594 | { .val = 3, .div = 4 }, | |
1595 | { .val = 4, .div = 5 }, | |
1596 | { .val = 5, .div = 6 }, | |
1597 | { .val = 6, .div = 8 }, | |
1598 | { .val = 7, .div = 10 }, | |
1599 | { .val = 8, .div = 12 }, | |
1600 | { .val = 9, .div = 16 }, | |
1601 | { .val = 10, .div = 12 }, | |
1602 | { .val = 11, .div = 16 }, | |
1603 | { .val = 12, .div = 20 }, | |
1604 | { .val = 13, .div = 24 }, | |
1605 | { .val = 14, .div = 32 }, | |
1606 | { .val = 0, .div = 0 }, | |
1607 | }; | |
1608 | ||
1609 | static struct tegra_clk_pll_params pll_c4_vco_params = { | |
1610 | .input_min = 9600000, | |
1611 | .input_max = 800000000, | |
1612 | .cf_min = 9600000, | |
1613 | .cf_max = 19200000, | |
1614 | .vco_min = 500000000, | |
1615 | .vco_max = 1080000000, | |
1616 | .base_reg = PLLC4_BASE, | |
1617 | .misc_reg = PLLC4_MISC0, | |
1618 | .lock_mask = PLL_BASE_LOCK, | |
6b301a05 RK |
1619 | .lock_delay = 300, |
1620 | .max_p = PLL_QLIN_PDIV_MAX, | |
1621 | .ext_misc_reg[0] = PLLC4_MISC0, | |
1622 | .iddq_reg = PLLC4_BASE, | |
1623 | .iddq_bit_idx = PLLSS_IDDQ_BIT, | |
1624 | .round_p_to_pdiv = pll_qlin_p_to_pdiv, | |
1625 | .pdiv_tohw = pll_qlin_pdiv_to_hw, | |
1626 | .mdiv_default = 3, | |
1627 | .div_nmp = &pllss_nmp, | |
1628 | .freq_table = pll_c4_vco_freq_table, | |
1629 | .set_defaults = tegra210_pllc4_set_defaults, | |
14050118 | 1630 | .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT, |
6b301a05 RK |
1631 | .calc_rate = tegra210_pll_fixed_mdiv_cfg, |
1632 | }; | |
1633 | ||
1634 | static struct tegra_clk_pll_freq_table pll_m_freq_table[] = { | |
eddb65e7 TR |
1635 | { 12000000, 800000000, 66, 1, 1, 0 }, /* actual: 792.0 MHz */ |
1636 | { 13000000, 800000000, 61, 1, 1, 0 }, /* actual: 793.0 MHz */ | |
1637 | { 38400000, 297600000, 93, 4, 3, 0 }, | |
1638 | { 38400000, 400000000, 125, 4, 3, 0 }, | |
1639 | { 38400000, 532800000, 111, 4, 2, 0 }, | |
1640 | { 38400000, 665600000, 104, 3, 2, 0 }, | |
1641 | { 38400000, 800000000, 125, 3, 2, 0 }, | |
1642 | { 38400000, 931200000, 97, 4, 1, 0 }, | |
1643 | { 38400000, 1065600000, 111, 4, 1, 0 }, | |
1644 | { 38400000, 1200000000, 125, 4, 1, 0 }, | |
1645 | { 38400000, 1331200000, 104, 3, 1, 0 }, | |
1646 | { 38400000, 1459200000, 76, 2, 1, 0 }, | |
1647 | { 38400000, 1600000000, 125, 3, 1, 0 }, | |
6b301a05 RK |
1648 | { 0, 0, 0, 0, 0, 0 }, |
1649 | }; | |
1650 | ||
1651 | static struct div_nmp pllm_nmp = { | |
1652 | .divm_shift = 0, | |
1653 | .divm_width = 8, | |
1654 | .override_divm_shift = 0, | |
1655 | .divn_shift = 8, | |
1656 | .divn_width = 8, | |
1657 | .override_divn_shift = 8, | |
1658 | .divp_shift = 20, | |
1659 | .divp_width = 5, | |
1660 | .override_divp_shift = 27, | |
1661 | }; | |
1662 | ||
1663 | static struct tegra_clk_pll_params pll_m_params = { | |
1664 | .input_min = 9600000, | |
1665 | .input_max = 500000000, | |
1666 | .cf_min = 9600000, | |
1667 | .cf_max = 19200000, | |
1668 | .vco_min = 800000000, | |
1669 | .vco_max = 1866000000, | |
1670 | .base_reg = PLLM_BASE, | |
474f2ba2 | 1671 | .misc_reg = PLLM_MISC2, |
6b301a05 RK |
1672 | .lock_mask = PLL_BASE_LOCK, |
1673 | .lock_enable_bit_idx = PLLM_MISC_LOCK_ENABLE, | |
1674 | .lock_delay = 300, | |
474f2ba2 | 1675 | .iddq_reg = PLLM_MISC2, |
6b301a05 RK |
1676 | .iddq_bit_idx = PLLM_IDDQ_BIT, |
1677 | .max_p = PLL_QLIN_PDIV_MAX, | |
474f2ba2 | 1678 | .ext_misc_reg[0] = PLLM_MISC2, |
d9e65791 | 1679 | .ext_misc_reg[1] = PLLM_MISC1, |
6b301a05 RK |
1680 | .round_p_to_pdiv = pll_qlin_p_to_pdiv, |
1681 | .pdiv_tohw = pll_qlin_pdiv_to_hw, | |
1682 | .div_nmp = &pllm_nmp, | |
1683 | .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE, | |
1684 | .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2, | |
1685 | .freq_table = pll_m_freq_table, | |
1686 | .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, | |
1687 | .calc_rate = tegra210_pll_fixed_mdiv_cfg, | |
1688 | }; | |
1689 | ||
1690 | static struct tegra_clk_pll_params pll_mb_params = { | |
1691 | .input_min = 9600000, | |
1692 | .input_max = 500000000, | |
1693 | .cf_min = 9600000, | |
1694 | .cf_max = 19200000, | |
1695 | .vco_min = 800000000, | |
1696 | .vco_max = 1866000000, | |
1697 | .base_reg = PLLMB_BASE, | |
474f2ba2 | 1698 | .misc_reg = PLLMB_MISC1, |
6b301a05 | 1699 | .lock_mask = PLL_BASE_LOCK, |
6b301a05 | 1700 | .lock_delay = 300, |
474f2ba2 | 1701 | .iddq_reg = PLLMB_MISC1, |
6b301a05 RK |
1702 | .iddq_bit_idx = PLLMB_IDDQ_BIT, |
1703 | .max_p = PLL_QLIN_PDIV_MAX, | |
474f2ba2 | 1704 | .ext_misc_reg[0] = PLLMB_MISC1, |
6b301a05 RK |
1705 | .round_p_to_pdiv = pll_qlin_p_to_pdiv, |
1706 | .pdiv_tohw = pll_qlin_pdiv_to_hw, | |
1707 | .div_nmp = &pllm_nmp, | |
1708 | .freq_table = pll_m_freq_table, | |
14050118 | 1709 | .flags = TEGRA_PLL_USE_LOCK, |
6b301a05 RK |
1710 | .set_defaults = tegra210_pllmb_set_defaults, |
1711 | .calc_rate = tegra210_pll_fixed_mdiv_cfg, | |
1712 | }; | |
1713 | ||
1714 | ||
1715 | static struct tegra_clk_pll_freq_table pll_e_freq_table[] = { | |
1716 | /* PLLE special case: use cpcon field to store cml divider value */ | |
1717 | { 672000000, 100000000, 125, 42, 0, 13 }, | |
1718 | { 624000000, 100000000, 125, 39, 0, 13 }, | |
1719 | { 336000000, 100000000, 125, 21, 0, 13 }, | |
1720 | { 312000000, 100000000, 200, 26, 0, 14 }, | |
1721 | { 38400000, 100000000, 125, 2, 0, 14 }, | |
1722 | { 12000000, 100000000, 200, 1, 0, 14 }, | |
1723 | { 0, 0, 0, 0, 0, 0 }, | |
1724 | }; | |
1725 | ||
1726 | static struct div_nmp plle_nmp = { | |
1727 | .divm_shift = 0, | |
1728 | .divm_width = 8, | |
1729 | .divn_shift = 8, | |
1730 | .divn_width = 8, | |
1731 | .divp_shift = 24, | |
1732 | .divp_width = 5, | |
1733 | }; | |
1734 | ||
1735 | static struct tegra_clk_pll_params pll_e_params = { | |
1736 | .input_min = 12000000, | |
1737 | .input_max = 800000000, | |
1738 | .cf_min = 12000000, | |
1739 | .cf_max = 38400000, | |
1740 | .vco_min = 1600000000, | |
1741 | .vco_max = 2500000000U, | |
1742 | .base_reg = PLLE_BASE, | |
1743 | .misc_reg = PLLE_MISC0, | |
1744 | .aux_reg = PLLE_AUX, | |
1745 | .lock_mask = PLLE_MISC_LOCK, | |
1746 | .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, | |
1747 | .lock_delay = 300, | |
1748 | .div_nmp = &plle_nmp, | |
1749 | .freq_table = pll_e_freq_table, | |
1750 | .flags = TEGRA_PLL_FIXED | TEGRA_PLL_LOCK_MISC | TEGRA_PLL_USE_LOCK | | |
1751 | TEGRA_PLL_HAS_LOCK_ENABLE, | |
1752 | .fixed_rate = 100000000, | |
1753 | .calc_rate = tegra210_pll_fixed_mdiv_cfg, | |
1754 | }; | |
1755 | ||
1756 | static struct tegra_clk_pll_freq_table pll_re_vco_freq_table[] = { | |
eddb65e7 TR |
1757 | { 12000000, 672000000, 56, 1, 1, 0 }, |
1758 | { 13000000, 672000000, 51, 1, 1, 0 }, /* actual: 663.0 MHz */ | |
1759 | { 38400000, 672000000, 70, 4, 1, 0 }, | |
6b301a05 RK |
1760 | { 0, 0, 0, 0, 0, 0 }, |
1761 | }; | |
1762 | ||
1763 | static struct div_nmp pllre_nmp = { | |
1764 | .divm_shift = 0, | |
1765 | .divm_width = 8, | |
1766 | .divn_shift = 8, | |
1767 | .divn_width = 8, | |
1768 | .divp_shift = 16, | |
1769 | .divp_width = 5, | |
1770 | }; | |
1771 | ||
1772 | static struct tegra_clk_pll_params pll_re_vco_params = { | |
1773 | .input_min = 9600000, | |
1774 | .input_max = 800000000, | |
1775 | .cf_min = 9600000, | |
1776 | .cf_max = 19200000, | |
1777 | .vco_min = 350000000, | |
1778 | .vco_max = 700000000, | |
1779 | .base_reg = PLLRE_BASE, | |
1780 | .misc_reg = PLLRE_MISC0, | |
1781 | .lock_mask = PLLRE_MISC_LOCK, | |
6b301a05 RK |
1782 | .lock_delay = 300, |
1783 | .max_p = PLL_QLIN_PDIV_MAX, | |
1784 | .ext_misc_reg[0] = PLLRE_MISC0, | |
1785 | .iddq_reg = PLLRE_MISC0, | |
1786 | .iddq_bit_idx = PLLRE_IDDQ_BIT, | |
1787 | .round_p_to_pdiv = pll_qlin_p_to_pdiv, | |
1788 | .pdiv_tohw = pll_qlin_pdiv_to_hw, | |
1789 | .div_nmp = &pllre_nmp, | |
1790 | .freq_table = pll_re_vco_freq_table, | |
14050118 | 1791 | .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_LOCK_MISC | TEGRA_PLL_VCO_OUT, |
6b301a05 RK |
1792 | .set_defaults = tegra210_pllre_set_defaults, |
1793 | .calc_rate = tegra210_pll_fixed_mdiv_cfg, | |
1794 | }; | |
1795 | ||
1796 | static struct div_nmp pllp_nmp = { | |
1797 | .divm_shift = 0, | |
1798 | .divm_width = 8, | |
1799 | .divn_shift = 10, | |
1800 | .divn_width = 8, | |
1801 | .divp_shift = 20, | |
1802 | .divp_width = 5, | |
1803 | }; | |
1804 | ||
1805 | static struct tegra_clk_pll_freq_table pll_p_freq_table[] = { | |
eddb65e7 TR |
1806 | { 12000000, 408000000, 34, 1, 1, 0 }, |
1807 | { 38400000, 408000000, 85, 8, 1, 0 }, /* cf = 4.8MHz, allowed exception */ | |
6b301a05 RK |
1808 | { 0, 0, 0, 0, 0, 0 }, |
1809 | }; | |
1810 | ||
1811 | static struct tegra_clk_pll_params pll_p_params = { | |
1812 | .input_min = 9600000, | |
1813 | .input_max = 800000000, | |
1814 | .cf_min = 9600000, | |
1815 | .cf_max = 19200000, | |
1816 | .vco_min = 350000000, | |
1817 | .vco_max = 700000000, | |
1818 | .base_reg = PLLP_BASE, | |
1819 | .misc_reg = PLLP_MISC0, | |
1820 | .lock_mask = PLL_BASE_LOCK, | |
6b301a05 RK |
1821 | .lock_delay = 300, |
1822 | .iddq_reg = PLLP_MISC0, | |
1823 | .iddq_bit_idx = PLLXP_IDDQ_BIT, | |
1824 | .ext_misc_reg[0] = PLLP_MISC0, | |
1825 | .ext_misc_reg[1] = PLLP_MISC1, | |
1826 | .div_nmp = &pllp_nmp, | |
1827 | .freq_table = pll_p_freq_table, | |
1828 | .fixed_rate = 408000000, | |
14050118 | 1829 | .flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT, |
6b301a05 RK |
1830 | .set_defaults = tegra210_pllp_set_defaults, |
1831 | .calc_rate = tegra210_pll_fixed_mdiv_cfg, | |
1832 | }; | |
1833 | ||
1834 | static struct tegra_clk_pll_params pll_a1_params = { | |
1835 | .input_min = 12000000, | |
1836 | .input_max = 700000000, | |
1837 | .cf_min = 12000000, | |
1838 | .cf_max = 50000000, | |
1839 | .vco_min = 600000000, | |
1840 | .vco_max = 1200000000, | |
1841 | .base_reg = PLLA1_BASE, | |
1842 | .misc_reg = PLLA1_MISC0, | |
1843 | .lock_mask = PLLCX_BASE_LOCK, | |
1844 | .lock_delay = 300, | |
9326947f | 1845 | .iddq_reg = PLLA1_MISC1, |
6b301a05 RK |
1846 | .iddq_bit_idx = PLLCX_IDDQ_BIT, |
1847 | .reset_reg = PLLA1_MISC0, | |
1848 | .reset_bit_idx = PLLCX_RESET_BIT, | |
1849 | .round_p_to_pdiv = pll_qlin_p_to_pdiv, | |
1850 | .pdiv_tohw = pll_qlin_pdiv_to_hw, | |
1851 | .div_nmp = &pllc_nmp, | |
1852 | .ext_misc_reg[0] = PLLA1_MISC0, | |
1853 | .ext_misc_reg[1] = PLLA1_MISC1, | |
1854 | .ext_misc_reg[2] = PLLA1_MISC2, | |
1855 | .ext_misc_reg[3] = PLLA1_MISC3, | |
1856 | .freq_table = pll_cx_freq_table, | |
14050118 | 1857 | .flags = TEGRA_PLL_USE_LOCK, |
6b301a05 RK |
1858 | .set_defaults = _plla1_set_defaults, |
1859 | .calc_rate = tegra210_pll_fixed_mdiv_cfg, | |
1860 | }; | |
1861 | ||
1862 | static struct div_nmp plla_nmp = { | |
1863 | .divm_shift = 0, | |
1864 | .divm_width = 8, | |
1865 | .divn_shift = 8, | |
1866 | .divn_width = 8, | |
1867 | .divp_shift = 20, | |
1868 | .divp_width = 5, | |
1869 | }; | |
1870 | ||
1871 | static struct tegra_clk_pll_freq_table pll_a_freq_table[] = { | |
eddb65e7 TR |
1872 | { 12000000, 282240000, 47, 1, 2, 1, 0xf148 }, /* actual: 282240234 */ |
1873 | { 12000000, 368640000, 61, 1, 2, 1, 0xfe15 }, /* actual: 368640381 */ | |
1874 | { 12000000, 240000000, 60, 1, 3, 1, 0 }, | |
1875 | { 13000000, 282240000, 43, 1, 2, 1, 0xfd7d }, /* actual: 282239807 */ | |
1876 | { 13000000, 368640000, 56, 1, 2, 1, 0x06d8 }, /* actual: 368640137 */ | |
1877 | { 13000000, 240000000, 55, 1, 3, 1, 0 }, /* actual: 238.3 MHz */ | |
1878 | { 38400000, 282240000, 44, 3, 2, 1, 0xf333 }, /* actual: 282239844 */ | |
1879 | { 38400000, 368640000, 57, 3, 2, 1, 0x0333 }, /* actual: 368639844 */ | |
6b301a05 RK |
1880 | { 38400000, 240000000, 75, 3, 3, 1, 0 }, |
1881 | { 0, 0, 0, 0, 0, 0, 0 }, | |
1882 | }; | |
1883 | ||
1884 | static struct tegra_clk_pll_params pll_a_params = { | |
1885 | .input_min = 12000000, | |
1886 | .input_max = 800000000, | |
1887 | .cf_min = 12000000, | |
1888 | .cf_max = 19200000, | |
1889 | .vco_min = 500000000, | |
1890 | .vco_max = 1000000000, | |
1891 | .base_reg = PLLA_BASE, | |
1892 | .misc_reg = PLLA_MISC0, | |
1893 | .lock_mask = PLL_BASE_LOCK, | |
6b301a05 RK |
1894 | .lock_delay = 300, |
1895 | .round_p_to_pdiv = pll_qlin_p_to_pdiv, | |
1896 | .pdiv_tohw = pll_qlin_pdiv_to_hw, | |
1897 | .iddq_reg = PLLA_BASE, | |
1898 | .iddq_bit_idx = PLLA_IDDQ_BIT, | |
1899 | .div_nmp = &plla_nmp, | |
1900 | .sdm_din_reg = PLLA_MISC1, | |
1901 | .sdm_din_mask = PLLA_SDM_DIN_MASK, | |
1902 | .sdm_ctrl_reg = PLLA_MISC2, | |
1903 | .sdm_ctrl_en_mask = PLLA_SDM_EN_MASK, | |
1904 | .ext_misc_reg[0] = PLLA_MISC0, | |
1905 | .ext_misc_reg[1] = PLLA_MISC1, | |
1906 | .ext_misc_reg[2] = PLLA_MISC2, | |
1907 | .freq_table = pll_a_freq_table, | |
14050118 | 1908 | .flags = TEGRA_PLL_USE_LOCK | TEGRA_MDIV_NEW, |
6b301a05 RK |
1909 | .set_defaults = tegra210_plla_set_defaults, |
1910 | .calc_rate = tegra210_pll_fixed_mdiv_cfg, | |
1911 | .set_gain = tegra210_clk_pll_set_gain, | |
1912 | .adjust_vco = tegra210_clk_adjust_vco_min, | |
1913 | }; | |
1914 | ||
1915 | static struct div_nmp plld_nmp = { | |
1916 | .divm_shift = 0, | |
1917 | .divm_width = 8, | |
1918 | .divn_shift = 11, | |
1919 | .divn_width = 8, | |
1920 | .divp_shift = 20, | |
1921 | .divp_width = 3, | |
1922 | }; | |
1923 | ||
1924 | static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { | |
eddb65e7 TR |
1925 | { 12000000, 594000000, 99, 1, 2, 0, 0 }, |
1926 | { 13000000, 594000000, 91, 1, 2, 0, 0xfc4f }, /* actual: 594000183 */ | |
1927 | { 38400000, 594000000, 30, 1, 2, 0, 0x0e00 }, | |
6b301a05 RK |
1928 | { 0, 0, 0, 0, 0, 0, 0 }, |
1929 | }; | |
1930 | ||
1931 | static struct tegra_clk_pll_params pll_d_params = { | |
1932 | .input_min = 12000000, | |
1933 | .input_max = 800000000, | |
1934 | .cf_min = 12000000, | |
1935 | .cf_max = 38400000, | |
1936 | .vco_min = 750000000, | |
1937 | .vco_max = 1500000000, | |
1938 | .base_reg = PLLD_BASE, | |
1939 | .misc_reg = PLLD_MISC0, | |
1940 | .lock_mask = PLL_BASE_LOCK, | |
6b301a05 RK |
1941 | .lock_delay = 1000, |
1942 | .iddq_reg = PLLD_MISC0, | |
1943 | .iddq_bit_idx = PLLD_IDDQ_BIT, | |
1944 | .round_p_to_pdiv = pll_expo_p_to_pdiv, | |
1945 | .pdiv_tohw = pll_expo_pdiv_to_hw, | |
1946 | .div_nmp = &plld_nmp, | |
1947 | .sdm_din_reg = PLLD_MISC0, | |
1948 | .sdm_din_mask = PLLA_SDM_DIN_MASK, | |
1949 | .sdm_ctrl_reg = PLLD_MISC0, | |
1950 | .sdm_ctrl_en_mask = PLLD_SDM_EN_MASK, | |
1951 | .ext_misc_reg[0] = PLLD_MISC0, | |
1952 | .ext_misc_reg[1] = PLLD_MISC1, | |
1953 | .freq_table = pll_d_freq_table, | |
14050118 | 1954 | .flags = TEGRA_PLL_USE_LOCK, |
6b301a05 RK |
1955 | .mdiv_default = 1, |
1956 | .set_defaults = tegra210_plld_set_defaults, | |
1957 | .calc_rate = tegra210_pll_fixed_mdiv_cfg, | |
1958 | .set_gain = tegra210_clk_pll_set_gain, | |
1959 | .adjust_vco = tegra210_clk_adjust_vco_min, | |
1960 | }; | |
1961 | ||
1962 | static struct tegra_clk_pll_freq_table tegra210_pll_d2_freq_table[] = { | |
eddb65e7 TR |
1963 | { 12000000, 594000000, 99, 1, 2, 0, 0xf000 }, |
1964 | { 13000000, 594000000, 91, 1, 2, 0, 0xfc4f }, /* actual: 594000183 */ | |
1965 | { 38400000, 594000000, 30, 1, 2, 0, 0x0e00 }, | |
6b301a05 RK |
1966 | { 0, 0, 0, 0, 0, 0, 0 }, |
1967 | }; | |
1968 | ||
1969 | /* s/w policy, always tegra_pll_ref */ | |
1970 | static struct tegra_clk_pll_params pll_d2_params = { | |
1971 | .input_min = 12000000, | |
1972 | .input_max = 800000000, | |
1973 | .cf_min = 12000000, | |
1974 | .cf_max = 38400000, | |
1975 | .vco_min = 750000000, | |
1976 | .vco_max = 1500000000, | |
1977 | .base_reg = PLLD2_BASE, | |
1978 | .misc_reg = PLLD2_MISC0, | |
1979 | .lock_mask = PLL_BASE_LOCK, | |
6b301a05 RK |
1980 | .lock_delay = 300, |
1981 | .iddq_reg = PLLD2_BASE, | |
1982 | .iddq_bit_idx = PLLSS_IDDQ_BIT, | |
1983 | .sdm_din_reg = PLLD2_MISC3, | |
1984 | .sdm_din_mask = PLLA_SDM_DIN_MASK, | |
1985 | .sdm_ctrl_reg = PLLD2_MISC1, | |
1986 | .sdm_ctrl_en_mask = PLLD2_SDM_EN_MASK, | |
e2f71656 TR |
1987 | /* disable spread-spectrum for pll_d2 */ |
1988 | .ssc_ctrl_reg = 0, | |
1989 | .ssc_ctrl_en_mask = 0, | |
6b301a05 RK |
1990 | .round_p_to_pdiv = pll_qlin_p_to_pdiv, |
1991 | .pdiv_tohw = pll_qlin_pdiv_to_hw, | |
1992 | .div_nmp = &pllss_nmp, | |
1993 | .ext_misc_reg[0] = PLLD2_MISC0, | |
1994 | .ext_misc_reg[1] = PLLD2_MISC1, | |
1995 | .ext_misc_reg[2] = PLLD2_MISC2, | |
1996 | .ext_misc_reg[3] = PLLD2_MISC3, | |
1997 | .max_p = PLL_QLIN_PDIV_MAX, | |
1998 | .mdiv_default = 1, | |
1999 | .freq_table = tegra210_pll_d2_freq_table, | |
2000 | .set_defaults = tegra210_plld2_set_defaults, | |
14050118 | 2001 | .flags = TEGRA_PLL_USE_LOCK, |
6b301a05 RK |
2002 | .calc_rate = tegra210_pll_fixed_mdiv_cfg, |
2003 | .set_gain = tegra210_clk_pll_set_gain, | |
2004 | .adjust_vco = tegra210_clk_adjust_vco_min, | |
2005 | }; | |
2006 | ||
2007 | static struct tegra_clk_pll_freq_table pll_dp_freq_table[] = { | |
eddb65e7 TR |
2008 | { 12000000, 270000000, 90, 1, 4, 0, 0xf000 }, |
2009 | { 13000000, 270000000, 83, 1, 4, 0, 0xf000 }, /* actual: 269.8 MHz */ | |
2010 | { 38400000, 270000000, 28, 1, 4, 0, 0xf400 }, | |
6b301a05 RK |
2011 | { 0, 0, 0, 0, 0, 0, 0 }, |
2012 | }; | |
2013 | ||
2014 | static struct tegra_clk_pll_params pll_dp_params = { | |
2015 | .input_min = 12000000, | |
2016 | .input_max = 800000000, | |
2017 | .cf_min = 12000000, | |
2018 | .cf_max = 38400000, | |
2019 | .vco_min = 750000000, | |
2020 | .vco_max = 1500000000, | |
2021 | .base_reg = PLLDP_BASE, | |
2022 | .misc_reg = PLLDP_MISC, | |
2023 | .lock_mask = PLL_BASE_LOCK, | |
6b301a05 RK |
2024 | .lock_delay = 300, |
2025 | .iddq_reg = PLLDP_BASE, | |
2026 | .iddq_bit_idx = PLLSS_IDDQ_BIT, | |
2027 | .sdm_din_reg = PLLDP_SS_CTRL2, | |
2028 | .sdm_din_mask = PLLA_SDM_DIN_MASK, | |
2029 | .sdm_ctrl_reg = PLLDP_SS_CFG, | |
2030 | .sdm_ctrl_en_mask = PLLDP_SDM_EN_MASK, | |
2031 | .ssc_ctrl_reg = PLLDP_SS_CFG, | |
2032 | .ssc_ctrl_en_mask = PLLDP_SSC_EN_MASK, | |
2033 | .round_p_to_pdiv = pll_qlin_p_to_pdiv, | |
2034 | .pdiv_tohw = pll_qlin_pdiv_to_hw, | |
2035 | .div_nmp = &pllss_nmp, | |
2036 | .ext_misc_reg[0] = PLLDP_MISC, | |
2037 | .ext_misc_reg[1] = PLLDP_SS_CFG, | |
2038 | .ext_misc_reg[2] = PLLDP_SS_CTRL1, | |
2039 | .ext_misc_reg[3] = PLLDP_SS_CTRL2, | |
2040 | .max_p = PLL_QLIN_PDIV_MAX, | |
2041 | .mdiv_default = 1, | |
2042 | .freq_table = pll_dp_freq_table, | |
2043 | .set_defaults = tegra210_plldp_set_defaults, | |
14050118 | 2044 | .flags = TEGRA_PLL_USE_LOCK, |
6b301a05 RK |
2045 | .calc_rate = tegra210_pll_fixed_mdiv_cfg, |
2046 | .set_gain = tegra210_clk_pll_set_gain, | |
2047 | .adjust_vco = tegra210_clk_adjust_vco_min, | |
2048 | }; | |
2049 | ||
2050 | static struct div_nmp pllu_nmp = { | |
2051 | .divm_shift = 0, | |
2052 | .divm_width = 8, | |
2053 | .divn_shift = 8, | |
2054 | .divn_width = 8, | |
2055 | .divp_shift = 16, | |
2056 | .divp_width = 5, | |
2057 | }; | |
2058 | ||
2059 | static struct tegra_clk_pll_freq_table pll_u_freq_table[] = { | |
e745f992 PDS |
2060 | { 12000000, 480000000, 40, 1, 0, 0 }, |
2061 | { 13000000, 480000000, 36, 1, 0, 0 }, /* actual: 468.0 MHz */ | |
2062 | { 38400000, 480000000, 25, 2, 0, 0 }, | |
6b301a05 RK |
2063 | { 0, 0, 0, 0, 0, 0 }, |
2064 | }; | |
2065 | ||
2066 | static struct tegra_clk_pll_params pll_u_vco_params = { | |
2067 | .input_min = 9600000, | |
2068 | .input_max = 800000000, | |
2069 | .cf_min = 9600000, | |
2070 | .cf_max = 19200000, | |
2071 | .vco_min = 350000000, | |
2072 | .vco_max = 700000000, | |
2073 | .base_reg = PLLU_BASE, | |
2074 | .misc_reg = PLLU_MISC0, | |
2075 | .lock_mask = PLL_BASE_LOCK, | |
6b301a05 RK |
2076 | .lock_delay = 1000, |
2077 | .iddq_reg = PLLU_MISC0, | |
2078 | .iddq_bit_idx = PLLU_IDDQ_BIT, | |
2079 | .ext_misc_reg[0] = PLLU_MISC0, | |
2080 | .ext_misc_reg[1] = PLLU_MISC1, | |
2081 | .round_p_to_pdiv = pll_qlin_p_to_pdiv, | |
2082 | .pdiv_tohw = pll_qlin_pdiv_to_hw, | |
2083 | .div_nmp = &pllu_nmp, | |
2084 | .freq_table = pll_u_freq_table, | |
14050118 | 2085 | .flags = TEGRA_PLLU | TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT, |
e745f992 PDS |
2086 | }; |
2087 | ||
2088 | struct utmi_clk_param { | |
2089 | /* Oscillator Frequency in KHz */ | |
2090 | u32 osc_frequency; | |
2091 | /* UTMIP PLL Enable Delay Count */ | |
2092 | u8 enable_delay_count; | |
2093 | /* UTMIP PLL Stable count */ | |
2094 | u16 stable_count; | |
2095 | /* UTMIP PLL Active delay count */ | |
2096 | u8 active_delay_count; | |
2097 | /* UTMIP PLL Xtal frequency count */ | |
2098 | u16 xtal_freq_count; | |
2099 | }; | |
2100 | ||
2101 | static const struct utmi_clk_param utmi_parameters[] = { | |
2102 | { | |
2103 | .osc_frequency = 38400000, .enable_delay_count = 0x0, | |
2104 | .stable_count = 0x0, .active_delay_count = 0x6, | |
2105 | .xtal_freq_count = 0x80 | |
2106 | }, { | |
2107 | .osc_frequency = 13000000, .enable_delay_count = 0x02, | |
2108 | .stable_count = 0x33, .active_delay_count = 0x05, | |
2109 | .xtal_freq_count = 0x7f | |
2110 | }, { | |
2111 | .osc_frequency = 19200000, .enable_delay_count = 0x03, | |
2112 | .stable_count = 0x4b, .active_delay_count = 0x06, | |
2113 | .xtal_freq_count = 0xbb | |
2114 | }, { | |
2115 | .osc_frequency = 12000000, .enable_delay_count = 0x02, | |
2116 | .stable_count = 0x2f, .active_delay_count = 0x08, | |
2117 | .xtal_freq_count = 0x76 | |
2118 | }, { | |
2119 | .osc_frequency = 26000000, .enable_delay_count = 0x04, | |
2120 | .stable_count = 0x66, .active_delay_count = 0x09, | |
2121 | .xtal_freq_count = 0xfe | |
2122 | }, { | |
2123 | .osc_frequency = 16800000, .enable_delay_count = 0x03, | |
2124 | .stable_count = 0x41, .active_delay_count = 0x0a, | |
2125 | .xtal_freq_count = 0xa4 | |
2126 | }, | |
6b301a05 RK |
2127 | }; |
2128 | ||
6b301a05 RK |
2129 | static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = { |
2130 | [tegra_clk_ispb] = { .dt_id = TEGRA210_CLK_ISPB, .present = true }, | |
2131 | [tegra_clk_rtc] = { .dt_id = TEGRA210_CLK_RTC, .present = true }, | |
2132 | [tegra_clk_timer] = { .dt_id = TEGRA210_CLK_TIMER, .present = true }, | |
2133 | [tegra_clk_uarta_8] = { .dt_id = TEGRA210_CLK_UARTA, .present = true }, | |
2134 | [tegra_clk_sdmmc2_9] = { .dt_id = TEGRA210_CLK_SDMMC2, .present = true }, | |
2135 | [tegra_clk_i2s1] = { .dt_id = TEGRA210_CLK_I2S1, .present = true }, | |
2136 | [tegra_clk_i2c1] = { .dt_id = TEGRA210_CLK_I2C1, .present = true }, | |
2137 | [tegra_clk_sdmmc1_9] = { .dt_id = TEGRA210_CLK_SDMMC1, .present = true }, | |
2138 | [tegra_clk_sdmmc4_9] = { .dt_id = TEGRA210_CLK_SDMMC4, .present = true }, | |
2139 | [tegra_clk_pwm] = { .dt_id = TEGRA210_CLK_PWM, .present = true }, | |
2140 | [tegra_clk_i2s2] = { .dt_id = TEGRA210_CLK_I2S2, .present = true }, | |
2141 | [tegra_clk_usbd] = { .dt_id = TEGRA210_CLK_USBD, .present = true }, | |
2142 | [tegra_clk_isp_9] = { .dt_id = TEGRA210_CLK_ISP, .present = true }, | |
2143 | [tegra_clk_disp2_8] = { .dt_id = TEGRA210_CLK_DISP2, .present = true }, | |
2144 | [tegra_clk_disp1_8] = { .dt_id = TEGRA210_CLK_DISP1, .present = true }, | |
2145 | [tegra_clk_host1x_9] = { .dt_id = TEGRA210_CLK_HOST1X, .present = true }, | |
2146 | [tegra_clk_i2s0] = { .dt_id = TEGRA210_CLK_I2S0, .present = true }, | |
2147 | [tegra_clk_apbdma] = { .dt_id = TEGRA210_CLK_APBDMA, .present = true }, | |
2148 | [tegra_clk_kfuse] = { .dt_id = TEGRA210_CLK_KFUSE, .present = true }, | |
2149 | [tegra_clk_sbc1_9] = { .dt_id = TEGRA210_CLK_SBC1, .present = true }, | |
2150 | [tegra_clk_sbc2_9] = { .dt_id = TEGRA210_CLK_SBC2, .present = true }, | |
2151 | [tegra_clk_sbc3_9] = { .dt_id = TEGRA210_CLK_SBC3, .present = true }, | |
2152 | [tegra_clk_i2c5] = { .dt_id = TEGRA210_CLK_I2C5, .present = true }, | |
2153 | [tegra_clk_csi] = { .dt_id = TEGRA210_CLK_CSI, .present = true }, | |
2154 | [tegra_clk_i2c2] = { .dt_id = TEGRA210_CLK_I2C2, .present = true }, | |
2155 | [tegra_clk_uartc_8] = { .dt_id = TEGRA210_CLK_UARTC, .present = true }, | |
2156 | [tegra_clk_mipi_cal] = { .dt_id = TEGRA210_CLK_MIPI_CAL, .present = true }, | |
2157 | [tegra_clk_emc] = { .dt_id = TEGRA210_CLK_EMC, .present = true }, | |
2158 | [tegra_clk_usb2] = { .dt_id = TEGRA210_CLK_USB2, .present = true }, | |
2159 | [tegra_clk_bsev] = { .dt_id = TEGRA210_CLK_BSEV, .present = true }, | |
2160 | [tegra_clk_uartd_8] = { .dt_id = TEGRA210_CLK_UARTD, .present = true }, | |
2161 | [tegra_clk_i2c3] = { .dt_id = TEGRA210_CLK_I2C3, .present = true }, | |
2162 | [tegra_clk_sbc4_9] = { .dt_id = TEGRA210_CLK_SBC4, .present = true }, | |
2163 | [tegra_clk_sdmmc3_9] = { .dt_id = TEGRA210_CLK_SDMMC3, .present = true }, | |
2164 | [tegra_clk_pcie] = { .dt_id = TEGRA210_CLK_PCIE, .present = true }, | |
2165 | [tegra_clk_owr_8] = { .dt_id = TEGRA210_CLK_OWR, .present = true }, | |
2166 | [tegra_clk_afi] = { .dt_id = TEGRA210_CLK_AFI, .present = true }, | |
2167 | [tegra_clk_csite_8] = { .dt_id = TEGRA210_CLK_CSITE, .present = true }, | |
2168 | [tegra_clk_soc_therm_8] = { .dt_id = TEGRA210_CLK_SOC_THERM, .present = true }, | |
2169 | [tegra_clk_dtv] = { .dt_id = TEGRA210_CLK_DTV, .present = true }, | |
2170 | [tegra_clk_i2cslow] = { .dt_id = TEGRA210_CLK_I2CSLOW, .present = true }, | |
2171 | [tegra_clk_tsec_8] = { .dt_id = TEGRA210_CLK_TSEC, .present = true }, | |
2172 | [tegra_clk_xusb_host] = { .dt_id = TEGRA210_CLK_XUSB_HOST, .present = true }, | |
2173 | [tegra_clk_csus] = { .dt_id = TEGRA210_CLK_CSUS, .present = true }, | |
2174 | [tegra_clk_mselect] = { .dt_id = TEGRA210_CLK_MSELECT, .present = true }, | |
2175 | [tegra_clk_tsensor] = { .dt_id = TEGRA210_CLK_TSENSOR, .present = true }, | |
2176 | [tegra_clk_i2s3] = { .dt_id = TEGRA210_CLK_I2S3, .present = true }, | |
2177 | [tegra_clk_i2s4] = { .dt_id = TEGRA210_CLK_I2S4, .present = true }, | |
2178 | [tegra_clk_i2c4] = { .dt_id = TEGRA210_CLK_I2C4, .present = true }, | |
2179 | [tegra_clk_d_audio] = { .dt_id = TEGRA210_CLK_D_AUDIO, .present = true }, | |
2180 | [tegra_clk_hda2codec_2x_8] = { .dt_id = TEGRA210_CLK_HDA2CODEC_2X, .present = true }, | |
2181 | [tegra_clk_spdif_2x] = { .dt_id = TEGRA210_CLK_SPDIF_2X, .present = true }, | |
2182 | [tegra_clk_actmon] = { .dt_id = TEGRA210_CLK_ACTMON, .present = true }, | |
2183 | [tegra_clk_extern1] = { .dt_id = TEGRA210_CLK_EXTERN1, .present = true }, | |
2184 | [tegra_clk_extern2] = { .dt_id = TEGRA210_CLK_EXTERN2, .present = true }, | |
2185 | [tegra_clk_extern3] = { .dt_id = TEGRA210_CLK_EXTERN3, .present = true }, | |
2186 | [tegra_clk_sata_oob_8] = { .dt_id = TEGRA210_CLK_SATA_OOB, .present = true }, | |
2187 | [tegra_clk_sata_8] = { .dt_id = TEGRA210_CLK_SATA, .present = true }, | |
2188 | [tegra_clk_hda_8] = { .dt_id = TEGRA210_CLK_HDA, .present = true }, | |
2189 | [tegra_clk_hda2hdmi] = { .dt_id = TEGRA210_CLK_HDA2HDMI, .present = true }, | |
2190 | [tegra_clk_cilab] = { .dt_id = TEGRA210_CLK_CILAB, .present = true }, | |
2191 | [tegra_clk_cilcd] = { .dt_id = TEGRA210_CLK_CILCD, .present = true }, | |
2192 | [tegra_clk_cile] = { .dt_id = TEGRA210_CLK_CILE, .present = true }, | |
2193 | [tegra_clk_dsialp] = { .dt_id = TEGRA210_CLK_DSIALP, .present = true }, | |
2194 | [tegra_clk_dsiblp] = { .dt_id = TEGRA210_CLK_DSIBLP, .present = true }, | |
2195 | [tegra_clk_entropy_8] = { .dt_id = TEGRA210_CLK_ENTROPY, .present = true }, | |
2196 | [tegra_clk_xusb_ss] = { .dt_id = TEGRA210_CLK_XUSB_SS, .present = true }, | |
2197 | [tegra_clk_i2c6] = { .dt_id = TEGRA210_CLK_I2C6, .present = true }, | |
2198 | [tegra_clk_vim2_clk] = { .dt_id = TEGRA210_CLK_VIM2_CLK, .present = true }, | |
2199 | [tegra_clk_clk72Mhz_8] = { .dt_id = TEGRA210_CLK_CLK72MHZ, .present = true }, | |
2200 | [tegra_clk_vic03_8] = { .dt_id = TEGRA210_CLK_VIC03, .present = true }, | |
2201 | [tegra_clk_dpaux] = { .dt_id = TEGRA210_CLK_DPAUX, .present = true }, | |
98c4b366 | 2202 | [tegra_clk_dpaux1] = { .dt_id = TEGRA210_CLK_DPAUX1, .present = true }, |
6b301a05 RK |
2203 | [tegra_clk_sor0] = { .dt_id = TEGRA210_CLK_SOR0, .present = true }, |
2204 | [tegra_clk_sor0_lvds] = { .dt_id = TEGRA210_CLK_SOR0_LVDS, .present = true }, | |
e452b818 TR |
2205 | [tegra_clk_sor1] = { .dt_id = TEGRA210_CLK_SOR1, .present = true }, |
2206 | [tegra_clk_sor1_src] = { .dt_id = TEGRA210_CLK_SOR1_SRC, .present = true }, | |
6b301a05 RK |
2207 | [tegra_clk_gpu] = { .dt_id = TEGRA210_CLK_GPU, .present = true }, |
2208 | [tegra_clk_pll_g_ref] = { .dt_id = TEGRA210_CLK_PLL_G_REF, .present = true, }, | |
2209 | [tegra_clk_uartb_8] = { .dt_id = TEGRA210_CLK_UARTB, .present = true }, | |
6b301a05 RK |
2210 | [tegra_clk_spdif_in_8] = { .dt_id = TEGRA210_CLK_SPDIF_IN, .present = true }, |
2211 | [tegra_clk_spdif_out] = { .dt_id = TEGRA210_CLK_SPDIF_OUT, .present = true }, | |
2212 | [tegra_clk_vi_10] = { .dt_id = TEGRA210_CLK_VI, .present = true }, | |
2213 | [tegra_clk_vi_sensor_8] = { .dt_id = TEGRA210_CLK_VI_SENSOR, .present = true }, | |
2214 | [tegra_clk_fuse] = { .dt_id = TEGRA210_CLK_FUSE, .present = true }, | |
2215 | [tegra_clk_fuse_burn] = { .dt_id = TEGRA210_CLK_FUSE_BURN, .present = true }, | |
2216 | [tegra_clk_clk_32k] = { .dt_id = TEGRA210_CLK_CLK_32K, .present = true }, | |
2217 | [tegra_clk_clk_m] = { .dt_id = TEGRA210_CLK_CLK_M, .present = true }, | |
2218 | [tegra_clk_clk_m_div2] = { .dt_id = TEGRA210_CLK_CLK_M_DIV2, .present = true }, | |
2219 | [tegra_clk_clk_m_div4] = { .dt_id = TEGRA210_CLK_CLK_M_DIV4, .present = true }, | |
2220 | [tegra_clk_pll_ref] = { .dt_id = TEGRA210_CLK_PLL_REF, .present = true }, | |
2221 | [tegra_clk_pll_c] = { .dt_id = TEGRA210_CLK_PLL_C, .present = true }, | |
2222 | [tegra_clk_pll_c_out1] = { .dt_id = TEGRA210_CLK_PLL_C_OUT1, .present = true }, | |
2223 | [tegra_clk_pll_c2] = { .dt_id = TEGRA210_CLK_PLL_C2, .present = true }, | |
2224 | [tegra_clk_pll_c3] = { .dt_id = TEGRA210_CLK_PLL_C3, .present = true }, | |
2225 | [tegra_clk_pll_m] = { .dt_id = TEGRA210_CLK_PLL_M, .present = true }, | |
6b301a05 RK |
2226 | [tegra_clk_pll_p] = { .dt_id = TEGRA210_CLK_PLL_P, .present = true }, |
2227 | [tegra_clk_pll_p_out1] = { .dt_id = TEGRA210_CLK_PLL_P_OUT1, .present = true }, | |
2228 | [tegra_clk_pll_p_out3] = { .dt_id = TEGRA210_CLK_PLL_P_OUT3, .present = true }, | |
2229 | [tegra_clk_pll_p_out4_cpu] = { .dt_id = TEGRA210_CLK_PLL_P_OUT4, .present = true }, | |
2230 | [tegra_clk_pll_p_out_hsio] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_HSIO, .present = true }, | |
2231 | [tegra_clk_pll_p_out_xusb] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_XUSB, .present = true }, | |
2232 | [tegra_clk_pll_p_out_cpu] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_CPU, .present = true }, | |
2233 | [tegra_clk_pll_p_out_adsp] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_ADSP, .present = true }, | |
2234 | [tegra_clk_pll_a] = { .dt_id = TEGRA210_CLK_PLL_A, .present = true }, | |
2235 | [tegra_clk_pll_a_out0] = { .dt_id = TEGRA210_CLK_PLL_A_OUT0, .present = true }, | |
2236 | [tegra_clk_pll_d] = { .dt_id = TEGRA210_CLK_PLL_D, .present = true }, | |
2237 | [tegra_clk_pll_d_out0] = { .dt_id = TEGRA210_CLK_PLL_D_OUT0, .present = true }, | |
2238 | [tegra_clk_pll_d2] = { .dt_id = TEGRA210_CLK_PLL_D2, .present = true }, | |
2239 | [tegra_clk_pll_d2_out0] = { .dt_id = TEGRA210_CLK_PLL_D2_OUT0, .present = true }, | |
2240 | [tegra_clk_pll_u] = { .dt_id = TEGRA210_CLK_PLL_U, .present = true }, | |
2241 | [tegra_clk_pll_u_out] = { .dt_id = TEGRA210_CLK_PLL_U_OUT, .present = true }, | |
2242 | [tegra_clk_pll_u_out1] = { .dt_id = TEGRA210_CLK_PLL_U_OUT1, .present = true }, | |
2243 | [tegra_clk_pll_u_out2] = { .dt_id = TEGRA210_CLK_PLL_U_OUT2, .present = true }, | |
2244 | [tegra_clk_pll_u_480m] = { .dt_id = TEGRA210_CLK_PLL_U_480M, .present = true }, | |
2245 | [tegra_clk_pll_u_60m] = { .dt_id = TEGRA210_CLK_PLL_U_60M, .present = true }, | |
2246 | [tegra_clk_pll_u_48m] = { .dt_id = TEGRA210_CLK_PLL_U_48M, .present = true }, | |
2247 | [tegra_clk_pll_x] = { .dt_id = TEGRA210_CLK_PLL_X, .present = true }, | |
2248 | [tegra_clk_pll_x_out0] = { .dt_id = TEGRA210_CLK_PLL_X_OUT0, .present = true }, | |
2249 | [tegra_clk_pll_re_vco] = { .dt_id = TEGRA210_CLK_PLL_RE_VCO, .present = true }, | |
2250 | [tegra_clk_pll_re_out] = { .dt_id = TEGRA210_CLK_PLL_RE_OUT, .present = true }, | |
2251 | [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA210_CLK_SPDIF_IN_SYNC, .present = true }, | |
2252 | [tegra_clk_i2s0_sync] = { .dt_id = TEGRA210_CLK_I2S0_SYNC, .present = true }, | |
2253 | [tegra_clk_i2s1_sync] = { .dt_id = TEGRA210_CLK_I2S1_SYNC, .present = true }, | |
2254 | [tegra_clk_i2s2_sync] = { .dt_id = TEGRA210_CLK_I2S2_SYNC, .present = true }, | |
2255 | [tegra_clk_i2s3_sync] = { .dt_id = TEGRA210_CLK_I2S3_SYNC, .present = true }, | |
2256 | [tegra_clk_i2s4_sync] = { .dt_id = TEGRA210_CLK_I2S4_SYNC, .present = true }, | |
2257 | [tegra_clk_vimclk_sync] = { .dt_id = TEGRA210_CLK_VIMCLK_SYNC, .present = true }, | |
2258 | [tegra_clk_audio0] = { .dt_id = TEGRA210_CLK_AUDIO0, .present = true }, | |
2259 | [tegra_clk_audio1] = { .dt_id = TEGRA210_CLK_AUDIO1, .present = true }, | |
2260 | [tegra_clk_audio2] = { .dt_id = TEGRA210_CLK_AUDIO2, .present = true }, | |
2261 | [tegra_clk_audio3] = { .dt_id = TEGRA210_CLK_AUDIO3, .present = true }, | |
2262 | [tegra_clk_audio4] = { .dt_id = TEGRA210_CLK_AUDIO4, .present = true }, | |
2263 | [tegra_clk_spdif] = { .dt_id = TEGRA210_CLK_SPDIF, .present = true }, | |
2264 | [tegra_clk_clk_out_1] = { .dt_id = TEGRA210_CLK_CLK_OUT_1, .present = true }, | |
2265 | [tegra_clk_clk_out_2] = { .dt_id = TEGRA210_CLK_CLK_OUT_2, .present = true }, | |
2266 | [tegra_clk_clk_out_3] = { .dt_id = TEGRA210_CLK_CLK_OUT_3, .present = true }, | |
2267 | [tegra_clk_blink] = { .dt_id = TEGRA210_CLK_BLINK, .present = true }, | |
2268 | [tegra_clk_xusb_gate] = { .dt_id = TEGRA210_CLK_XUSB_GATE, .present = true }, | |
2269 | [tegra_clk_xusb_host_src_8] = { .dt_id = TEGRA210_CLK_XUSB_HOST_SRC, .present = true }, | |
2270 | [tegra_clk_xusb_falcon_src_8] = { .dt_id = TEGRA210_CLK_XUSB_FALCON_SRC, .present = true }, | |
2271 | [tegra_clk_xusb_fs_src] = { .dt_id = TEGRA210_CLK_XUSB_FS_SRC, .present = true }, | |
2272 | [tegra_clk_xusb_ss_src_8] = { .dt_id = TEGRA210_CLK_XUSB_SS_SRC, .present = true }, | |
2273 | [tegra_clk_xusb_ss_div2] = { .dt_id = TEGRA210_CLK_XUSB_SS_DIV2, .present = true }, | |
2274 | [tegra_clk_xusb_dev_src_8] = { .dt_id = TEGRA210_CLK_XUSB_DEV_SRC, .present = true }, | |
2275 | [tegra_clk_xusb_dev] = { .dt_id = TEGRA210_CLK_XUSB_DEV, .present = true }, | |
2276 | [tegra_clk_xusb_hs_src_4] = { .dt_id = TEGRA210_CLK_XUSB_HS_SRC, .present = true }, | |
2277 | [tegra_clk_xusb_ssp_src] = { .dt_id = TEGRA210_CLK_XUSB_SSP_SRC, .present = true }, | |
2278 | [tegra_clk_usb2_hsic_trk] = { .dt_id = TEGRA210_CLK_USB2_HSIC_TRK, .present = true }, | |
2279 | [tegra_clk_hsic_trk] = { .dt_id = TEGRA210_CLK_HSIC_TRK, .present = true }, | |
2280 | [tegra_clk_usb2_trk] = { .dt_id = TEGRA210_CLK_USB2_TRK, .present = true }, | |
2281 | [tegra_clk_sclk] = { .dt_id = TEGRA210_CLK_SCLK, .present = true }, | |
2282 | [tegra_clk_sclk_mux] = { .dt_id = TEGRA210_CLK_SCLK_MUX, .present = true }, | |
2283 | [tegra_clk_hclk] = { .dt_id = TEGRA210_CLK_HCLK, .present = true }, | |
2284 | [tegra_clk_pclk] = { .dt_id = TEGRA210_CLK_PCLK, .present = true }, | |
2285 | [tegra_clk_cclk_g] = { .dt_id = TEGRA210_CLK_CCLK_G, .present = true }, | |
2286 | [tegra_clk_cclk_lp] = { .dt_id = TEGRA210_CLK_CCLK_LP, .present = true }, | |
2287 | [tegra_clk_dfll_ref] = { .dt_id = TEGRA210_CLK_DFLL_REF, .present = true }, | |
2288 | [tegra_clk_dfll_soc] = { .dt_id = TEGRA210_CLK_DFLL_SOC, .present = true }, | |
2289 | [tegra_clk_vi_sensor2_8] = { .dt_id = TEGRA210_CLK_VI_SENSOR2, .present = true }, | |
2290 | [tegra_clk_pll_p_out5] = { .dt_id = TEGRA210_CLK_PLL_P_OUT5, .present = true }, | |
2291 | [tegra_clk_pll_c4] = { .dt_id = TEGRA210_CLK_PLL_C4, .present = true }, | |
2292 | [tegra_clk_pll_dp] = { .dt_id = TEGRA210_CLK_PLL_DP, .present = true }, | |
2293 | [tegra_clk_audio0_mux] = { .dt_id = TEGRA210_CLK_AUDIO0_MUX, .present = true }, | |
2294 | [tegra_clk_audio1_mux] = { .dt_id = TEGRA210_CLK_AUDIO1_MUX, .present = true }, | |
2295 | [tegra_clk_audio2_mux] = { .dt_id = TEGRA210_CLK_AUDIO2_MUX, .present = true }, | |
2296 | [tegra_clk_audio3_mux] = { .dt_id = TEGRA210_CLK_AUDIO3_MUX, .present = true }, | |
2297 | [tegra_clk_audio4_mux] = { .dt_id = TEGRA210_CLK_AUDIO4_MUX, .present = true }, | |
2298 | [tegra_clk_spdif_mux] = { .dt_id = TEGRA210_CLK_SPDIF_MUX, .present = true }, | |
2299 | [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA210_CLK_CLK_OUT_1_MUX, .present = true }, | |
2300 | [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA210_CLK_CLK_OUT_2_MUX, .present = true }, | |
2301 | [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA210_CLK_CLK_OUT_3_MUX, .present = true }, | |
2302 | [tegra_clk_maud] = { .dt_id = TEGRA210_CLK_MAUD, .present = true }, | |
2303 | [tegra_clk_mipibif] = { .dt_id = TEGRA210_CLK_MIPIBIF, .present = true }, | |
2304 | [tegra_clk_qspi] = { .dt_id = TEGRA210_CLK_QSPI, .present = true }, | |
2305 | [tegra_clk_sdmmc_legacy] = { .dt_id = TEGRA210_CLK_SDMMC_LEGACY, .present = true }, | |
2306 | [tegra_clk_tsecb] = { .dt_id = TEGRA210_CLK_TSECB, .present = true }, | |
2307 | [tegra_clk_uartape] = { .dt_id = TEGRA210_CLK_UARTAPE, .present = true }, | |
2308 | [tegra_clk_vi_i2c] = { .dt_id = TEGRA210_CLK_VI_I2C, .present = true }, | |
2309 | [tegra_clk_ape] = { .dt_id = TEGRA210_CLK_APE, .present = true }, | |
2310 | [tegra_clk_dbgapb] = { .dt_id = TEGRA210_CLK_DBGAPB, .present = true }, | |
2311 | [tegra_clk_nvdec] = { .dt_id = TEGRA210_CLK_NVDEC, .present = true }, | |
2312 | [tegra_clk_nvenc] = { .dt_id = TEGRA210_CLK_NVENC, .present = true }, | |
2313 | [tegra_clk_nvjpg] = { .dt_id = TEGRA210_CLK_NVJPG, .present = true }, | |
2314 | [tegra_clk_pll_c4_out0] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT0, .present = true }, | |
2315 | [tegra_clk_pll_c4_out1] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT1, .present = true }, | |
2316 | [tegra_clk_pll_c4_out2] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT2, .present = true }, | |
2317 | [tegra_clk_pll_c4_out3] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT3, .present = true }, | |
29569941 | 2318 | [tegra_clk_apb2ape] = { .dt_id = TEGRA210_CLK_APB2APE, .present = true }, |
9326947f | 2319 | [tegra_clk_pll_a1] = { .dt_id = TEGRA210_CLK_PLL_A1, .present = true }, |
34ac2c27 | 2320 | [tegra_clk_ispa] = { .dt_id = TEGRA210_CLK_ISPA, .present = true }, |
bfa34832 | 2321 | [tegra_clk_cec] = { .dt_id = TEGRA210_CLK_CEC, .present = true }, |
6cfc8bc9 PDS |
2322 | [tegra_clk_dmic1] = { .dt_id = TEGRA210_CLK_DMIC1, .present = true }, |
2323 | [tegra_clk_dmic2] = { .dt_id = TEGRA210_CLK_DMIC2, .present = true }, | |
2324 | [tegra_clk_dmic3] = { .dt_id = TEGRA210_CLK_DMIC3, .present = true }, | |
319af797 PDS |
2325 | [tegra_clk_dmic1_sync_clk] = { .dt_id = TEGRA210_CLK_DMIC1_SYNC_CLK, .present = true }, |
2326 | [tegra_clk_dmic2_sync_clk] = { .dt_id = TEGRA210_CLK_DMIC2_SYNC_CLK, .present = true }, | |
2327 | [tegra_clk_dmic3_sync_clk] = { .dt_id = TEGRA210_CLK_DMIC3_SYNC_CLK, .present = true }, | |
2328 | [tegra_clk_dmic1_sync_clk_mux] = { .dt_id = TEGRA210_CLK_DMIC1_SYNC_CLK_MUX, .present = true }, | |
2329 | [tegra_clk_dmic2_sync_clk_mux] = { .dt_id = TEGRA210_CLK_DMIC2_SYNC_CLK_MUX, .present = true }, | |
2330 | [tegra_clk_dmic3_sync_clk_mux] = { .dt_id = TEGRA210_CLK_DMIC3_SYNC_CLK_MUX, .present = true }, | |
88da44c5 PDS |
2331 | [tegra_clk_dp2] = { .dt_id = TEGRA210_CLK_DP2, .present = true }, |
2332 | [tegra_clk_iqc1] = { .dt_id = TEGRA210_CLK_IQC1, .present = true }, | |
2333 | [tegra_clk_iqc2] = { .dt_id = TEGRA210_CLK_IQC2, .present = true }, | |
2334 | [tegra_clk_pll_a_out_adsp] = { .dt_id = TEGRA210_CLK_PLL_A_OUT_ADSP, .present = true }, | |
2335 | [tegra_clk_pll_a_out0_out_adsp] = { .dt_id = TEGRA210_CLK_PLL_A_OUT0_OUT_ADSP, .present = true }, | |
2336 | [tegra_clk_adsp] = { .dt_id = TEGRA210_CLK_ADSP, .present = true }, | |
2337 | [tegra_clk_adsp_neon] = { .dt_id = TEGRA210_CLK_ADSP_NEON, .present = true }, | |
6b301a05 RK |
2338 | }; |
2339 | ||
2340 | static struct tegra_devclk devclks[] __initdata = { | |
2341 | { .con_id = "clk_m", .dt_id = TEGRA210_CLK_CLK_M }, | |
2342 | { .con_id = "pll_ref", .dt_id = TEGRA210_CLK_PLL_REF }, | |
2343 | { .con_id = "clk_32k", .dt_id = TEGRA210_CLK_CLK_32K }, | |
2344 | { .con_id = "clk_m_div2", .dt_id = TEGRA210_CLK_CLK_M_DIV2 }, | |
2345 | { .con_id = "clk_m_div4", .dt_id = TEGRA210_CLK_CLK_M_DIV4 }, | |
2346 | { .con_id = "pll_c", .dt_id = TEGRA210_CLK_PLL_C }, | |
2347 | { .con_id = "pll_c_out1", .dt_id = TEGRA210_CLK_PLL_C_OUT1 }, | |
2348 | { .con_id = "pll_c2", .dt_id = TEGRA210_CLK_PLL_C2 }, | |
2349 | { .con_id = "pll_c3", .dt_id = TEGRA210_CLK_PLL_C3 }, | |
2350 | { .con_id = "pll_p", .dt_id = TEGRA210_CLK_PLL_P }, | |
2351 | { .con_id = "pll_p_out1", .dt_id = TEGRA210_CLK_PLL_P_OUT1 }, | |
2352 | { .con_id = "pll_p_out2", .dt_id = TEGRA210_CLK_PLL_P_OUT2 }, | |
2353 | { .con_id = "pll_p_out3", .dt_id = TEGRA210_CLK_PLL_P_OUT3 }, | |
2354 | { .con_id = "pll_p_out4", .dt_id = TEGRA210_CLK_PLL_P_OUT4 }, | |
2355 | { .con_id = "pll_m", .dt_id = TEGRA210_CLK_PLL_M }, | |
6b301a05 RK |
2356 | { .con_id = "pll_x", .dt_id = TEGRA210_CLK_PLL_X }, |
2357 | { .con_id = "pll_x_out0", .dt_id = TEGRA210_CLK_PLL_X_OUT0 }, | |
2358 | { .con_id = "pll_u", .dt_id = TEGRA210_CLK_PLL_U }, | |
2359 | { .con_id = "pll_u_out", .dt_id = TEGRA210_CLK_PLL_U_OUT }, | |
2360 | { .con_id = "pll_u_out1", .dt_id = TEGRA210_CLK_PLL_U_OUT1 }, | |
2361 | { .con_id = "pll_u_out2", .dt_id = TEGRA210_CLK_PLL_U_OUT2 }, | |
2362 | { .con_id = "pll_u_480M", .dt_id = TEGRA210_CLK_PLL_U_480M }, | |
2363 | { .con_id = "pll_u_60M", .dt_id = TEGRA210_CLK_PLL_U_60M }, | |
2364 | { .con_id = "pll_u_48M", .dt_id = TEGRA210_CLK_PLL_U_48M }, | |
2365 | { .con_id = "pll_d", .dt_id = TEGRA210_CLK_PLL_D }, | |
2366 | { .con_id = "pll_d_out0", .dt_id = TEGRA210_CLK_PLL_D_OUT0 }, | |
2367 | { .con_id = "pll_d2", .dt_id = TEGRA210_CLK_PLL_D2 }, | |
2368 | { .con_id = "pll_d2_out0", .dt_id = TEGRA210_CLK_PLL_D2_OUT0 }, | |
2369 | { .con_id = "pll_a", .dt_id = TEGRA210_CLK_PLL_A }, | |
2370 | { .con_id = "pll_a_out0", .dt_id = TEGRA210_CLK_PLL_A_OUT0 }, | |
2371 | { .con_id = "pll_re_vco", .dt_id = TEGRA210_CLK_PLL_RE_VCO }, | |
2372 | { .con_id = "pll_re_out", .dt_id = TEGRA210_CLK_PLL_RE_OUT }, | |
2373 | { .con_id = "spdif_in_sync", .dt_id = TEGRA210_CLK_SPDIF_IN_SYNC }, | |
2374 | { .con_id = "i2s0_sync", .dt_id = TEGRA210_CLK_I2S0_SYNC }, | |
2375 | { .con_id = "i2s1_sync", .dt_id = TEGRA210_CLK_I2S1_SYNC }, | |
2376 | { .con_id = "i2s2_sync", .dt_id = TEGRA210_CLK_I2S2_SYNC }, | |
2377 | { .con_id = "i2s3_sync", .dt_id = TEGRA210_CLK_I2S3_SYNC }, | |
2378 | { .con_id = "i2s4_sync", .dt_id = TEGRA210_CLK_I2S4_SYNC }, | |
2379 | { .con_id = "vimclk_sync", .dt_id = TEGRA210_CLK_VIMCLK_SYNC }, | |
2380 | { .con_id = "audio0", .dt_id = TEGRA210_CLK_AUDIO0 }, | |
2381 | { .con_id = "audio1", .dt_id = TEGRA210_CLK_AUDIO1 }, | |
2382 | { .con_id = "audio2", .dt_id = TEGRA210_CLK_AUDIO2 }, | |
2383 | { .con_id = "audio3", .dt_id = TEGRA210_CLK_AUDIO3 }, | |
2384 | { .con_id = "audio4", .dt_id = TEGRA210_CLK_AUDIO4 }, | |
2385 | { .con_id = "spdif", .dt_id = TEGRA210_CLK_SPDIF }, | |
2386 | { .con_id = "spdif_2x", .dt_id = TEGRA210_CLK_SPDIF_2X }, | |
2387 | { .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA210_CLK_EXTERN1 }, | |
2388 | { .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA210_CLK_EXTERN2 }, | |
2389 | { .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA210_CLK_EXTERN3 }, | |
2390 | { .con_id = "blink", .dt_id = TEGRA210_CLK_BLINK }, | |
2391 | { .con_id = "cclk_g", .dt_id = TEGRA210_CLK_CCLK_G }, | |
2392 | { .con_id = "cclk_lp", .dt_id = TEGRA210_CLK_CCLK_LP }, | |
2393 | { .con_id = "sclk", .dt_id = TEGRA210_CLK_SCLK }, | |
2394 | { .con_id = "hclk", .dt_id = TEGRA210_CLK_HCLK }, | |
2395 | { .con_id = "pclk", .dt_id = TEGRA210_CLK_PCLK }, | |
2396 | { .con_id = "fuse", .dt_id = TEGRA210_CLK_FUSE }, | |
2397 | { .dev_id = "rtc-tegra", .dt_id = TEGRA210_CLK_RTC }, | |
2398 | { .dev_id = "timer", .dt_id = TEGRA210_CLK_TIMER }, | |
2399 | { .con_id = "pll_c4_out0", .dt_id = TEGRA210_CLK_PLL_C4_OUT0 }, | |
2400 | { .con_id = "pll_c4_out1", .dt_id = TEGRA210_CLK_PLL_C4_OUT1 }, | |
2401 | { .con_id = "pll_c4_out2", .dt_id = TEGRA210_CLK_PLL_C4_OUT2 }, | |
2402 | { .con_id = "pll_c4_out3", .dt_id = TEGRA210_CLK_PLL_C4_OUT3 }, | |
2403 | { .con_id = "dpaux", .dt_id = TEGRA210_CLK_DPAUX }, | |
2404 | { .con_id = "sor0", .dt_id = TEGRA210_CLK_SOR0 }, | |
2405 | }; | |
2406 | ||
2407 | static struct tegra_audio_clk_info tegra210_audio_plls[] = { | |
2408 | { "pll_a", &pll_a_params, tegra_clk_pll_a, "pll_ref" }, | |
2409 | { "pll_a1", &pll_a1_params, tegra_clk_pll_a1, "pll_ref" }, | |
2410 | }; | |
2411 | ||
2412 | static struct clk **clks; | |
2413 | ||
24c3ebef PDS |
2414 | static const char * const aclk_parents[] = { |
2415 | "pll_a1", "pll_c", "pll_p", "pll_a_out0", "pll_c2", "pll_c3", | |
2416 | "clk_m" | |
2417 | }; | |
2418 | ||
3843832f PDS |
2419 | void tegra210_put_utmipll_in_iddq(void) |
2420 | { | |
2421 | u32 reg; | |
2422 | ||
2423 | reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); | |
2424 | ||
2425 | if (reg & UTMIPLL_HW_PWRDN_CFG0_UTMIPLL_LOCK) { | |
2426 | pr_err("trying to assert IDDQ while UTMIPLL is locked\n"); | |
2427 | return; | |
2428 | } | |
2429 | ||
2430 | reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE; | |
2431 | writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); | |
2432 | } | |
2433 | EXPORT_SYMBOL_GPL(tegra210_put_utmipll_in_iddq); | |
2434 | ||
2435 | void tegra210_put_utmipll_out_iddq(void) | |
2436 | { | |
2437 | u32 reg; | |
2438 | ||
2439 | reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); | |
2440 | reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE; | |
2441 | writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); | |
2442 | } | |
2443 | EXPORT_SYMBOL_GPL(tegra210_put_utmipll_out_iddq); | |
2444 | ||
e745f992 PDS |
2445 | static void tegra210_utmi_param_configure(void) |
2446 | { | |
2447 | u32 reg; | |
2448 | int i; | |
2449 | ||
2450 | for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) { | |
2451 | if (osc_freq == utmi_parameters[i].osc_frequency) | |
2452 | break; | |
2453 | } | |
2454 | ||
2455 | if (i >= ARRAY_SIZE(utmi_parameters)) { | |
2456 | pr_err("%s: Unexpected oscillator freq %lu\n", __func__, | |
2457 | osc_freq); | |
2458 | return; | |
2459 | } | |
2460 | ||
2461 | reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); | |
2462 | reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE; | |
2463 | writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); | |
2464 | ||
2465 | udelay(10); | |
2466 | ||
2467 | reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2); | |
2468 | ||
2469 | /* Program UTMIP PLL stable and active counts */ | |
2470 | /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */ | |
2471 | reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0); | |
2472 | reg |= UTMIP_PLL_CFG2_STABLE_COUNT(utmi_parameters[i].stable_count); | |
2473 | ||
2474 | reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0); | |
2475 | ||
2476 | reg |= | |
2477 | UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(utmi_parameters[i].active_delay_count); | |
2478 | writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2); | |
2479 | ||
2480 | /* Program UTMIP PLL delay and oscillator frequency counts */ | |
2481 | reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); | |
2482 | reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0); | |
2483 | ||
2484 | reg |= | |
2485 | UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(utmi_parameters[i].enable_delay_count); | |
2486 | ||
2487 | reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0); | |
2488 | reg |= | |
2489 | UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(utmi_parameters[i].xtal_freq_count); | |
2490 | ||
2491 | reg |= UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN; | |
2492 | writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); | |
2493 | ||
2494 | /* Remove power downs from UTMIP PLL control bits */ | |
2495 | reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); | |
2496 | reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; | |
2497 | reg |= UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP; | |
2498 | writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); | |
2499 | udelay(1); | |
2500 | ||
2501 | /* Enable samplers for SNPS, XUSB_HOST, XUSB_DEV */ | |
2502 | reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2); | |
2503 | reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP; | |
2504 | reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP; | |
2505 | reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP; | |
2506 | reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN; | |
2507 | reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN; | |
2508 | reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN; | |
2509 | writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2); | |
2510 | ||
2511 | /* Setup HW control of UTMIPLL */ | |
2512 | reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); | |
2513 | reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; | |
2514 | reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP; | |
2515 | writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); | |
2516 | ||
2517 | reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); | |
2518 | reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET; | |
2519 | reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL; | |
2520 | writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); | |
2521 | ||
2522 | udelay(1); | |
2523 | ||
2524 | reg = readl_relaxed(clk_base + XUSB_PLL_CFG0); | |
2525 | reg &= ~XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY; | |
2526 | writel_relaxed(reg, clk_base + XUSB_PLL_CFG0); | |
2527 | ||
2528 | udelay(1); | |
2529 | ||
2530 | /* Enable HW control UTMIPLL */ | |
2531 | reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); | |
2532 | reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE; | |
2533 | writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); | |
2534 | } | |
2535 | ||
2536 | static int tegra210_enable_pllu(void) | |
2537 | { | |
2538 | struct tegra_clk_pll_freq_table *fentry; | |
2539 | struct tegra_clk_pll pllu; | |
2540 | u32 reg; | |
2541 | ||
2542 | for (fentry = pll_u_freq_table; fentry->input_rate; fentry++) { | |
2543 | if (fentry->input_rate == pll_ref_freq) | |
2544 | break; | |
2545 | } | |
2546 | ||
2547 | if (!fentry->input_rate) { | |
2548 | pr_err("Unknown PLL_U reference frequency %lu\n", pll_ref_freq); | |
2549 | return -EINVAL; | |
2550 | } | |
2551 | ||
2552 | /* clear IDDQ bit */ | |
2553 | pllu.params = &pll_u_vco_params; | |
2554 | reg = readl_relaxed(clk_base + pllu.params->ext_misc_reg[0]); | |
2555 | reg &= ~BIT(pllu.params->iddq_bit_idx); | |
2556 | writel_relaxed(reg, clk_base + pllu.params->ext_misc_reg[0]); | |
2557 | ||
2558 | reg = readl_relaxed(clk_base + PLLU_BASE); | |
2559 | reg &= ~GENMASK(20, 0); | |
2560 | reg |= fentry->m; | |
2561 | reg |= fentry->n << 8; | |
2562 | reg |= fentry->p << 16; | |
2563 | writel(reg, clk_base + PLLU_BASE); | |
2564 | reg |= PLL_ENABLE; | |
2565 | writel(reg, clk_base + PLLU_BASE); | |
2566 | ||
2567 | readl_relaxed_poll_timeout(clk_base + PLLU_BASE, reg, | |
2568 | reg & PLL_BASE_LOCK, 2, 1000); | |
2569 | if (!(reg & PLL_BASE_LOCK)) { | |
2570 | pr_err("Timed out waiting for PLL_U to lock\n"); | |
2571 | return -ETIMEDOUT; | |
2572 | } | |
2573 | ||
2574 | return 0; | |
2575 | } | |
2576 | ||
2577 | static int tegra210_init_pllu(void) | |
2578 | { | |
2579 | u32 reg; | |
2580 | int err; | |
2581 | ||
2582 | tegra210_pllu_set_defaults(&pll_u_vco_params); | |
2583 | /* skip initialization when pllu is in hw controlled mode */ | |
2584 | reg = readl_relaxed(clk_base + PLLU_BASE); | |
2585 | if (reg & PLLU_BASE_OVERRIDE) { | |
2586 | if (!(reg & PLL_ENABLE)) { | |
2587 | err = tegra210_enable_pllu(); | |
2588 | if (err < 0) { | |
2589 | WARN_ON(1); | |
2590 | return err; | |
2591 | } | |
2592 | } | |
2593 | /* enable hw controlled mode */ | |
2594 | reg = readl_relaxed(clk_base + PLLU_BASE); | |
2595 | reg &= ~PLLU_BASE_OVERRIDE; | |
2596 | writel(reg, clk_base + PLLU_BASE); | |
2597 | ||
2598 | reg = readl_relaxed(clk_base + PLLU_HW_PWRDN_CFG0); | |
2599 | reg |= PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE | | |
2600 | PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT | | |
2601 | PLLU_HW_PWRDN_CFG0_USE_LOCKDET; | |
2602 | reg &= ~(PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL | | |
2603 | PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL); | |
2604 | writel_relaxed(reg, clk_base + PLLU_HW_PWRDN_CFG0); | |
2605 | ||
2606 | reg = readl_relaxed(clk_base + XUSB_PLL_CFG0); | |
2607 | reg &= ~XUSB_PLL_CFG0_PLLU_LOCK_DLY_MASK; | |
2608 | writel_relaxed(reg, clk_base + XUSB_PLL_CFG0); | |
2609 | udelay(1); | |
2610 | ||
2611 | reg = readl_relaxed(clk_base + PLLU_HW_PWRDN_CFG0); | |
2612 | reg |= PLLU_HW_PWRDN_CFG0_SEQ_ENABLE; | |
2613 | writel_relaxed(reg, clk_base + PLLU_HW_PWRDN_CFG0); | |
2614 | udelay(1); | |
2615 | ||
2616 | reg = readl_relaxed(clk_base + PLLU_BASE); | |
2617 | reg &= ~PLLU_BASE_CLKENABLE_USB; | |
2618 | writel_relaxed(reg, clk_base + PLLU_BASE); | |
2619 | } | |
2620 | ||
2621 | /* enable UTMIPLL hw control if not yet done by the bootloader */ | |
2622 | reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); | |
2623 | if (!(reg & UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE)) | |
2624 | tegra210_utmi_param_configure(); | |
2625 | ||
2626 | return 0; | |
2627 | } | |
2628 | ||
6b301a05 RK |
2629 | static __init void tegra210_periph_clk_init(void __iomem *clk_base, |
2630 | void __iomem *pmc_base) | |
2631 | { | |
2632 | struct clk *clk; | |
2633 | ||
2634 | /* xusb_ss_div2 */ | |
2635 | clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0, | |
2636 | 1, 2); | |
2637 | clks[TEGRA210_CLK_XUSB_SS_DIV2] = clk; | |
2638 | ||
74d3ba0b TR |
2639 | clk = tegra_clk_register_periph_fixed("sor_safe", "pll_p", 0, clk_base, |
2640 | 1, 17, 222); | |
2641 | clks[TEGRA210_CLK_SOR_SAFE] = clk; | |
2642 | ||
2e34c2ac | 2643 | clk = tegra_clk_register_periph_fixed("dpaux", "sor_safe", 0, clk_base, |
eede7113 TR |
2644 | 1, 17, 181); |
2645 | clks[TEGRA210_CLK_DPAUX] = clk; | |
2646 | ||
2e34c2ac | 2647 | clk = tegra_clk_register_periph_fixed("dpaux1", "sor_safe", 0, clk_base, |
eede7113 TR |
2648 | 1, 17, 207); |
2649 | clks[TEGRA210_CLK_DPAUX1] = clk; | |
2650 | ||
6b301a05 RK |
2651 | /* pll_d_dsi_out */ |
2652 | clk = clk_register_gate(NULL, "pll_d_dsi_out", "pll_d_out0", 0, | |
2653 | clk_base + PLLD_MISC0, 21, 0, &pll_d_lock); | |
2654 | clks[TEGRA210_CLK_PLL_D_DSI_OUT] = clk; | |
2655 | ||
2656 | /* dsia */ | |
2657 | clk = tegra_clk_register_periph_gate("dsia", "pll_d_dsi_out", 0, | |
2658 | clk_base, 0, 48, | |
2659 | periph_clk_enb_refcnt); | |
2660 | clks[TEGRA210_CLK_DSIA] = clk; | |
2661 | ||
2662 | /* dsib */ | |
2663 | clk = tegra_clk_register_periph_gate("dsib", "pll_d_dsi_out", 0, | |
2664 | clk_base, 0, 82, | |
2665 | periph_clk_enb_refcnt); | |
2666 | clks[TEGRA210_CLK_DSIB] = clk; | |
2667 | ||
2668 | /* emc mux */ | |
2669 | clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, | |
2670 | ARRAY_SIZE(mux_pllmcp_clkm), 0, | |
2671 | clk_base + CLK_SOURCE_EMC, | |
2672 | 29, 3, 0, &emc_lock); | |
2673 | ||
2674 | clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC, | |
2675 | &emc_lock); | |
2676 | clks[TEGRA210_CLK_MC] = clk; | |
2677 | ||
2678 | /* cml0 */ | |
2679 | clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX, | |
2680 | 0, 0, &pll_e_lock); | |
2681 | clk_register_clkdev(clk, "cml0", NULL); | |
2682 | clks[TEGRA210_CLK_CML0] = clk; | |
2683 | ||
2684 | /* cml1 */ | |
2685 | clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX, | |
2686 | 1, 0, &pll_e_lock); | |
2687 | clk_register_clkdev(clk, "cml1", NULL); | |
2688 | clks[TEGRA210_CLK_CML1] = clk; | |
2689 | ||
24c3ebef PDS |
2690 | clk = tegra_clk_register_super_clk("aclk", aclk_parents, |
2691 | ARRAY_SIZE(aclk_parents), 0, clk_base + 0x6e0, | |
2692 | 0, NULL); | |
2693 | clks[TEGRA210_CLK_ACLK] = clk; | |
2694 | ||
6b301a05 RK |
2695 | tegra_periph_clk_init(clk_base, pmc_base, tegra210_clks, &pll_p_params); |
2696 | } | |
2697 | ||
2698 | static void __init tegra210_pll_init(void __iomem *clk_base, | |
2699 | void __iomem *pmc) | |
2700 | { | |
6b301a05 RK |
2701 | struct clk *clk; |
2702 | ||
2703 | /* PLLC */ | |
2704 | clk = tegra_clk_register_pllxc_tegra210("pll_c", "pll_ref", clk_base, | |
2705 | pmc, 0, &pll_c_params, NULL); | |
2706 | if (!WARN_ON(IS_ERR(clk))) | |
2707 | clk_register_clkdev(clk, "pll_c", NULL); | |
2708 | clks[TEGRA210_CLK_PLL_C] = clk; | |
2709 | ||
2710 | /* PLLC_OUT1 */ | |
2711 | clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c", | |
2712 | clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, | |
2713 | 8, 8, 1, NULL); | |
2714 | clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div", | |
2715 | clk_base + PLLC_OUT, 1, 0, | |
2716 | CLK_SET_RATE_PARENT, 0, NULL); | |
2717 | clk_register_clkdev(clk, "pll_c_out1", NULL); | |
2718 | clks[TEGRA210_CLK_PLL_C_OUT1] = clk; | |
2719 | ||
2720 | /* PLLC_UD */ | |
2721 | clk = clk_register_fixed_factor(NULL, "pll_c_ud", "pll_c", | |
2722 | CLK_SET_RATE_PARENT, 1, 1); | |
2723 | clk_register_clkdev(clk, "pll_c_ud", NULL); | |
2724 | clks[TEGRA210_CLK_PLL_C_UD] = clk; | |
2725 | ||
2726 | /* PLLC2 */ | |
2727 | clk = tegra_clk_register_pllc_tegra210("pll_c2", "pll_ref", clk_base, | |
2728 | pmc, 0, &pll_c2_params, NULL); | |
2729 | clk_register_clkdev(clk, "pll_c2", NULL); | |
2730 | clks[TEGRA210_CLK_PLL_C2] = clk; | |
2731 | ||
2732 | /* PLLC3 */ | |
2733 | clk = tegra_clk_register_pllc_tegra210("pll_c3", "pll_ref", clk_base, | |
2734 | pmc, 0, &pll_c3_params, NULL); | |
2735 | clk_register_clkdev(clk, "pll_c3", NULL); | |
2736 | clks[TEGRA210_CLK_PLL_C3] = clk; | |
2737 | ||
2738 | /* PLLM */ | |
2739 | clk = tegra_clk_register_pllm("pll_m", "osc", clk_base, pmc, | |
2740 | CLK_SET_RATE_GATE, &pll_m_params, NULL); | |
2741 | clk_register_clkdev(clk, "pll_m", NULL); | |
2742 | clks[TEGRA210_CLK_PLL_M] = clk; | |
2743 | ||
2744 | /* PLLMB */ | |
2745 | clk = tegra_clk_register_pllmb("pll_mb", "osc", clk_base, pmc, | |
2746 | CLK_SET_RATE_GATE, &pll_mb_params, NULL); | |
2747 | clk_register_clkdev(clk, "pll_mb", NULL); | |
2748 | clks[TEGRA210_CLK_PLL_MB] = clk; | |
2749 | ||
6b301a05 RK |
2750 | /* PLLM_UD */ |
2751 | clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m", | |
2752 | CLK_SET_RATE_PARENT, 1, 1); | |
2753 | clk_register_clkdev(clk, "pll_m_ud", NULL); | |
2754 | clks[TEGRA210_CLK_PLL_M_UD] = clk; | |
2755 | ||
2756 | /* PLLU_VCO */ | |
e745f992 PDS |
2757 | if (!tegra210_init_pllu()) { |
2758 | clk = clk_register_fixed_rate(NULL, "pll_u_vco", "pll_ref", 0, | |
2759 | 480*1000*1000); | |
2760 | clk_register_clkdev(clk, "pll_u_vco", NULL); | |
2761 | clks[TEGRA210_CLK_PLL_U] = clk; | |
2762 | } | |
6b301a05 RK |
2763 | |
2764 | /* PLLU_OUT */ | |
2765 | clk = clk_register_divider_table(NULL, "pll_u_out", "pll_u_vco", 0, | |
2766 | clk_base + PLLU_BASE, 16, 4, 0, | |
2767 | pll_vco_post_div_table, NULL); | |
2768 | clk_register_clkdev(clk, "pll_u_out", NULL); | |
2769 | clks[TEGRA210_CLK_PLL_U_OUT] = clk; | |
2770 | ||
2771 | /* PLLU_OUT1 */ | |
2772 | clk = tegra_clk_register_divider("pll_u_out1_div", "pll_u_out", | |
2773 | clk_base + PLLU_OUTA, 0, | |
2774 | TEGRA_DIVIDER_ROUND_UP, | |
2775 | 8, 8, 1, &pll_u_lock); | |
2776 | clk = tegra_clk_register_pll_out("pll_u_out1", "pll_u_out1_div", | |
2777 | clk_base + PLLU_OUTA, 1, 0, | |
2778 | CLK_SET_RATE_PARENT, 0, &pll_u_lock); | |
2779 | clk_register_clkdev(clk, "pll_u_out1", NULL); | |
2780 | clks[TEGRA210_CLK_PLL_U_OUT1] = clk; | |
2781 | ||
2782 | /* PLLU_OUT2 */ | |
2783 | clk = tegra_clk_register_divider("pll_u_out2_div", "pll_u_out", | |
2784 | clk_base + PLLU_OUTA, 0, | |
2785 | TEGRA_DIVIDER_ROUND_UP, | |
2786 | 24, 8, 1, &pll_u_lock); | |
2787 | clk = tegra_clk_register_pll_out("pll_u_out2", "pll_u_out2_div", | |
2788 | clk_base + PLLU_OUTA, 17, 16, | |
2789 | CLK_SET_RATE_PARENT, 0, &pll_u_lock); | |
2790 | clk_register_clkdev(clk, "pll_u_out2", NULL); | |
2791 | clks[TEGRA210_CLK_PLL_U_OUT2] = clk; | |
2792 | ||
6b301a05 RK |
2793 | /* PLLU_480M */ |
2794 | clk = clk_register_gate(NULL, "pll_u_480M", "pll_u_vco", | |
2795 | CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, | |
2796 | 22, 0, &pll_u_lock); | |
2797 | clk_register_clkdev(clk, "pll_u_480M", NULL); | |
2798 | clks[TEGRA210_CLK_PLL_U_480M] = clk; | |
2799 | ||
2800 | /* PLLU_60M */ | |
2801 | clk = clk_register_gate(NULL, "pll_u_60M", "pll_u_out2", | |
2802 | CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, | |
2803 | 23, 0, NULL); | |
2804 | clk_register_clkdev(clk, "pll_u_60M", NULL); | |
2805 | clks[TEGRA210_CLK_PLL_U_60M] = clk; | |
2806 | ||
2807 | /* PLLU_48M */ | |
2808 | clk = clk_register_gate(NULL, "pll_u_48M", "pll_u_out1", | |
2809 | CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, | |
2810 | 25, 0, NULL); | |
2811 | clk_register_clkdev(clk, "pll_u_48M", NULL); | |
2812 | clks[TEGRA210_CLK_PLL_U_48M] = clk; | |
2813 | ||
2814 | /* PLLD */ | |
2815 | clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0, | |
2816 | &pll_d_params, &pll_d_lock); | |
2817 | clk_register_clkdev(clk, "pll_d", NULL); | |
2818 | clks[TEGRA210_CLK_PLL_D] = clk; | |
2819 | ||
2820 | /* PLLD_OUT0 */ | |
2821 | clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d", | |
2822 | CLK_SET_RATE_PARENT, 1, 2); | |
2823 | clk_register_clkdev(clk, "pll_d_out0", NULL); | |
2824 | clks[TEGRA210_CLK_PLL_D_OUT0] = clk; | |
2825 | ||
2826 | /* PLLRE */ | |
926655f9 RK |
2827 | clk = tegra_clk_register_pllre_tegra210("pll_re_vco", "pll_ref", |
2828 | clk_base, pmc, 0, | |
2829 | &pll_re_vco_params, | |
2830 | &pll_re_lock, pll_ref_freq); | |
6b301a05 RK |
2831 | clk_register_clkdev(clk, "pll_re_vco", NULL); |
2832 | clks[TEGRA210_CLK_PLL_RE_VCO] = clk; | |
2833 | ||
2834 | clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0, | |
2835 | clk_base + PLLRE_BASE, 16, 5, 0, | |
2836 | pll_vco_post_div_table, &pll_re_lock); | |
2837 | clk_register_clkdev(clk, "pll_re_out", NULL); | |
2838 | clks[TEGRA210_CLK_PLL_RE_OUT] = clk; | |
2839 | ||
926655f9 RK |
2840 | clk = tegra_clk_register_divider("pll_re_out1_div", "pll_re_vco", |
2841 | clk_base + PLLRE_OUT1, 0, | |
2842 | TEGRA_DIVIDER_ROUND_UP, | |
2843 | 8, 8, 1, NULL); | |
2844 | clk = tegra_clk_register_pll_out("pll_re_out1", "pll_re_out1_div", | |
2845 | clk_base + PLLRE_OUT1, 1, 0, | |
2846 | CLK_SET_RATE_PARENT, 0, NULL); | |
2847 | clks[TEGRA210_CLK_PLL_RE_OUT1] = clk; | |
2848 | ||
6b301a05 RK |
2849 | /* PLLE */ |
2850 | clk = tegra_clk_register_plle_tegra210("pll_e", "pll_ref", | |
2851 | clk_base, 0, &pll_e_params, NULL); | |
2852 | clk_register_clkdev(clk, "pll_e", NULL); | |
2853 | clks[TEGRA210_CLK_PLL_E] = clk; | |
2854 | ||
2855 | /* PLLC4 */ | |
2856 | clk = tegra_clk_register_pllre("pll_c4_vco", "pll_ref", clk_base, pmc, | |
2857 | 0, &pll_c4_vco_params, NULL, pll_ref_freq); | |
2858 | clk_register_clkdev(clk, "pll_c4_vco", NULL); | |
2859 | clks[TEGRA210_CLK_PLL_C4] = clk; | |
2860 | ||
2861 | /* PLLC4_OUT0 */ | |
2862 | clk = clk_register_divider_table(NULL, "pll_c4_out0", "pll_c4_vco", 0, | |
2863 | clk_base + PLLC4_BASE, 19, 4, 0, | |
2864 | pll_vco_post_div_table, NULL); | |
2865 | clk_register_clkdev(clk, "pll_c4_out0", NULL); | |
2866 | clks[TEGRA210_CLK_PLL_C4_OUT0] = clk; | |
2867 | ||
2868 | /* PLLC4_OUT1 */ | |
2869 | clk = clk_register_fixed_factor(NULL, "pll_c4_out1", "pll_c4_vco", | |
2870 | CLK_SET_RATE_PARENT, 1, 3); | |
2871 | clk_register_clkdev(clk, "pll_c4_out1", NULL); | |
2872 | clks[TEGRA210_CLK_PLL_C4_OUT1] = clk; | |
2873 | ||
2874 | /* PLLC4_OUT2 */ | |
2875 | clk = clk_register_fixed_factor(NULL, "pll_c4_out2", "pll_c4_vco", | |
2876 | CLK_SET_RATE_PARENT, 1, 5); | |
2877 | clk_register_clkdev(clk, "pll_c4_out2", NULL); | |
2878 | clks[TEGRA210_CLK_PLL_C4_OUT2] = clk; | |
2879 | ||
2880 | /* PLLC4_OUT3 */ | |
2881 | clk = tegra_clk_register_divider("pll_c4_out3_div", "pll_c4_out0", | |
2882 | clk_base + PLLC4_OUT, 0, TEGRA_DIVIDER_ROUND_UP, | |
2883 | 8, 8, 1, NULL); | |
2884 | clk = tegra_clk_register_pll_out("pll_c4_out3", "pll_c4_out3_div", | |
2885 | clk_base + PLLC4_OUT, 1, 0, | |
2886 | CLK_SET_RATE_PARENT, 0, NULL); | |
2887 | clk_register_clkdev(clk, "pll_c4_out3", NULL); | |
2888 | clks[TEGRA210_CLK_PLL_C4_OUT3] = clk; | |
2889 | ||
2890 | /* PLLDP */ | |
2891 | clk = tegra_clk_register_pllss_tegra210("pll_dp", "pll_ref", clk_base, | |
2892 | 0, &pll_dp_params, NULL); | |
2893 | clk_register_clkdev(clk, "pll_dp", NULL); | |
2894 | clks[TEGRA210_CLK_PLL_DP] = clk; | |
2895 | ||
2896 | /* PLLD2 */ | |
2897 | clk = tegra_clk_register_pllss_tegra210("pll_d2", "pll_ref", clk_base, | |
2898 | 0, &pll_d2_params, NULL); | |
2899 | clk_register_clkdev(clk, "pll_d2", NULL); | |
2900 | clks[TEGRA210_CLK_PLL_D2] = clk; | |
2901 | ||
2902 | /* PLLD2_OUT0 */ | |
2903 | clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2", | |
2904 | CLK_SET_RATE_PARENT, 1, 1); | |
2905 | clk_register_clkdev(clk, "pll_d2_out0", NULL); | |
2906 | clks[TEGRA210_CLK_PLL_D2_OUT0] = clk; | |
2907 | ||
2908 | /* PLLP_OUT2 */ | |
2909 | clk = clk_register_fixed_factor(NULL, "pll_p_out2", "pll_p", | |
2910 | CLK_SET_RATE_PARENT, 1, 2); | |
2911 | clk_register_clkdev(clk, "pll_p_out2", NULL); | |
2912 | clks[TEGRA210_CLK_PLL_P_OUT2] = clk; | |
2913 | ||
2914 | } | |
2915 | ||
2916 | /* Tegra210 CPU clock and reset control functions */ | |
2917 | static void tegra210_wait_cpu_in_reset(u32 cpu) | |
2918 | { | |
2919 | unsigned int reg; | |
2920 | ||
2921 | do { | |
2922 | reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS); | |
2923 | cpu_relax(); | |
2924 | } while (!(reg & (1 << cpu))); /* check CPU been reset or not */ | |
2925 | } | |
2926 | ||
2927 | static void tegra210_disable_cpu_clock(u32 cpu) | |
2928 | { | |
2929 | /* flow controller would take care in the power sequence. */ | |
2930 | } | |
2931 | ||
2932 | #ifdef CONFIG_PM_SLEEP | |
2933 | static void tegra210_cpu_clock_suspend(void) | |
2934 | { | |
2935 | /* switch coresite to clk_m, save off original source */ | |
2936 | tegra210_cpu_clk_sctx.clk_csite_src = | |
2937 | readl(clk_base + CLK_SOURCE_CSITE); | |
2938 | writel(3 << 30, clk_base + CLK_SOURCE_CSITE); | |
2939 | } | |
2940 | ||
2941 | static void tegra210_cpu_clock_resume(void) | |
2942 | { | |
2943 | writel(tegra210_cpu_clk_sctx.clk_csite_src, | |
2944 | clk_base + CLK_SOURCE_CSITE); | |
2945 | } | |
2946 | #endif | |
2947 | ||
2948 | static struct tegra_cpu_car_ops tegra210_cpu_car_ops = { | |
2949 | .wait_for_reset = tegra210_wait_cpu_in_reset, | |
2950 | .disable_clock = tegra210_disable_cpu_clock, | |
2951 | #ifdef CONFIG_PM_SLEEP | |
2952 | .suspend = tegra210_cpu_clock_suspend, | |
2953 | .resume = tegra210_cpu_clock_resume, | |
2954 | #endif | |
2955 | }; | |
2956 | ||
2957 | static const struct of_device_id pmc_match[] __initconst = { | |
2958 | { .compatible = "nvidia,tegra210-pmc" }, | |
2959 | { }, | |
2960 | }; | |
2961 | ||
2962 | static struct tegra_clk_init_table init_table[] __initdata = { | |
2963 | { TEGRA210_CLK_UARTA, TEGRA210_CLK_PLL_P, 408000000, 0 }, | |
2964 | { TEGRA210_CLK_UARTB, TEGRA210_CLK_PLL_P, 408000000, 0 }, | |
2965 | { TEGRA210_CLK_UARTC, TEGRA210_CLK_PLL_P, 408000000, 0 }, | |
2966 | { TEGRA210_CLK_UARTD, TEGRA210_CLK_PLL_P, 408000000, 0 }, | |
2967 | { TEGRA210_CLK_PLL_A, TEGRA210_CLK_CLK_MAX, 564480000, 1 }, | |
2968 | { TEGRA210_CLK_PLL_A_OUT0, TEGRA210_CLK_CLK_MAX, 11289600, 1 }, | |
2969 | { TEGRA210_CLK_EXTERN1, TEGRA210_CLK_PLL_A_OUT0, 0, 1 }, | |
2970 | { TEGRA210_CLK_CLK_OUT_1_MUX, TEGRA210_CLK_EXTERN1, 0, 1 }, | |
2971 | { TEGRA210_CLK_CLK_OUT_1, TEGRA210_CLK_CLK_MAX, 0, 1 }, | |
2972 | { TEGRA210_CLK_I2S0, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 }, | |
2973 | { TEGRA210_CLK_I2S1, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 }, | |
2974 | { TEGRA210_CLK_I2S2, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 }, | |
2975 | { TEGRA210_CLK_I2S3, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 }, | |
2976 | { TEGRA210_CLK_I2S4, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 }, | |
2977 | { TEGRA210_CLK_HOST1X, TEGRA210_CLK_PLL_P, 136000000, 1 }, | |
2978 | { TEGRA210_CLK_SCLK_MUX, TEGRA210_CLK_PLL_P, 0, 1 }, | |
2979 | { TEGRA210_CLK_SCLK, TEGRA210_CLK_CLK_MAX, 102000000, 1 }, | |
2980 | { TEGRA210_CLK_DFLL_SOC, TEGRA210_CLK_PLL_P, 51000000, 1 }, | |
2981 | { TEGRA210_CLK_DFLL_REF, TEGRA210_CLK_PLL_P, 51000000, 1 }, | |
2982 | { TEGRA210_CLK_SBC4, TEGRA210_CLK_PLL_P, 12000000, 1 }, | |
2983 | { TEGRA210_CLK_PLL_RE_VCO, TEGRA210_CLK_CLK_MAX, 672000000, 1 }, | |
6b301a05 RK |
2984 | { TEGRA210_CLK_XUSB_GATE, TEGRA210_CLK_CLK_MAX, 0, 1 }, |
2985 | { TEGRA210_CLK_XUSB_SS_SRC, TEGRA210_CLK_PLL_U_480M, 120000000, 0 }, | |
2986 | { TEGRA210_CLK_XUSB_FS_SRC, TEGRA210_CLK_PLL_U_48M, 48000000, 0 }, | |
2987 | { TEGRA210_CLK_XUSB_HS_SRC, TEGRA210_CLK_XUSB_SS_SRC, 120000000, 0 }, | |
2988 | { TEGRA210_CLK_XUSB_SSP_SRC, TEGRA210_CLK_XUSB_SS_SRC, 120000000, 0 }, | |
2989 | { TEGRA210_CLK_XUSB_FALCON_SRC, TEGRA210_CLK_PLL_P_OUT_XUSB, 204000000, 0 }, | |
2990 | { TEGRA210_CLK_XUSB_HOST_SRC, TEGRA210_CLK_PLL_P_OUT_XUSB, 102000000, 0 }, | |
2991 | { TEGRA210_CLK_XUSB_DEV_SRC, TEGRA210_CLK_PLL_P_OUT_XUSB, 102000000, 0 }, | |
2992 | { TEGRA210_CLK_SATA, TEGRA210_CLK_PLL_P, 104000000, 0 }, | |
2993 | { TEGRA210_CLK_SATA_OOB, TEGRA210_CLK_PLL_P, 204000000, 0 }, | |
2994 | { TEGRA210_CLK_EMC, TEGRA210_CLK_CLK_MAX, 0, 1 }, | |
2995 | { TEGRA210_CLK_MSELECT, TEGRA210_CLK_CLK_MAX, 0, 1 }, | |
2996 | { TEGRA210_CLK_CSITE, TEGRA210_CLK_CLK_MAX, 0, 1 }, | |
bea1baa1 PDS |
2997 | /* TODO find a way to enable this on-demand */ |
2998 | { TEGRA210_CLK_DBGAPB, TEGRA210_CLK_CLK_MAX, 0, 1 }, | |
6b301a05 RK |
2999 | { TEGRA210_CLK_TSENSOR, TEGRA210_CLK_CLK_M, 400000, 0 }, |
3000 | { TEGRA210_CLK_I2C1, TEGRA210_CLK_PLL_P, 0, 0 }, | |
3001 | { TEGRA210_CLK_I2C2, TEGRA210_CLK_PLL_P, 0, 0 }, | |
3002 | { TEGRA210_CLK_I2C3, TEGRA210_CLK_PLL_P, 0, 0 }, | |
3003 | { TEGRA210_CLK_I2C4, TEGRA210_CLK_PLL_P, 0, 0 }, | |
3004 | { TEGRA210_CLK_I2C5, TEGRA210_CLK_PLL_P, 0, 0 }, | |
3005 | { TEGRA210_CLK_I2C6, TEGRA210_CLK_PLL_P, 0, 0 }, | |
3006 | { TEGRA210_CLK_PLL_DP, TEGRA210_CLK_CLK_MAX, 270000000, 0 }, | |
3007 | { TEGRA210_CLK_SOC_THERM, TEGRA210_CLK_PLL_P, 51000000, 0 }, | |
3008 | { TEGRA210_CLK_CCLK_G, TEGRA210_CLK_CLK_MAX, 0, 1 }, | |
e745f992 PDS |
3009 | { TEGRA210_CLK_PLL_U_OUT1, TEGRA210_CLK_CLK_MAX, 48000000, 1 }, |
3010 | { TEGRA210_CLK_PLL_U_OUT2, TEGRA210_CLK_CLK_MAX, 60000000, 1 }, | |
6b301a05 RK |
3011 | /* This MUST be the last entry. */ |
3012 | { TEGRA210_CLK_CLK_MAX, TEGRA210_CLK_CLK_MAX, 0, 0 }, | |
3013 | }; | |
3014 | ||
3015 | /** | |
3016 | * tegra210_clock_apply_init_table - initialize clocks on Tegra210 SoCs | |
3017 | * | |
3018 | * Program an initial clock rate and enable or disable clocks needed | |
3019 | * by the rest of the kernel, for Tegra210 SoCs. It is intended to be | |
3020 | * called by assigning a pointer to it to tegra_clk_apply_init_table - | |
3021 | * this will be called as an arch_initcall. No return value. | |
3022 | */ | |
3023 | static void __init tegra210_clock_apply_init_table(void) | |
3024 | { | |
3025 | tegra_init_from_table(init_table, clks, TEGRA210_CLK_CLK_MAX); | |
3026 | } | |
3027 | ||
68d724ce PDS |
3028 | /** |
3029 | * tegra210_car_barrier - wait for pending writes to the CAR to complete | |
3030 | * | |
3031 | * Wait for any outstanding writes to the CAR MMIO space from this CPU | |
3032 | * to complete before continuing execution. No return value. | |
3033 | */ | |
3034 | static void tegra210_car_barrier(void) | |
3035 | { | |
3036 | readl_relaxed(clk_base + RST_DFLL_DVCO); | |
3037 | } | |
3038 | ||
3039 | /** | |
3040 | * tegra210_clock_assert_dfll_dvco_reset - assert the DFLL's DVCO reset | |
3041 | * | |
3042 | * Assert the reset line of the DFLL's DVCO. No return value. | |
3043 | */ | |
3044 | static void tegra210_clock_assert_dfll_dvco_reset(void) | |
3045 | { | |
3046 | u32 v; | |
3047 | ||
3048 | v = readl_relaxed(clk_base + RST_DFLL_DVCO); | |
3049 | v |= (1 << DVFS_DFLL_RESET_SHIFT); | |
3050 | writel_relaxed(v, clk_base + RST_DFLL_DVCO); | |
3051 | tegra210_car_barrier(); | |
3052 | } | |
3053 | ||
3054 | /** | |
3055 | * tegra210_clock_deassert_dfll_dvco_reset - deassert the DFLL's DVCO reset | |
3056 | * | |
3057 | * Deassert the reset line of the DFLL's DVCO, allowing the DVCO to | |
3058 | * operate. No return value. | |
3059 | */ | |
3060 | static void tegra210_clock_deassert_dfll_dvco_reset(void) | |
3061 | { | |
3062 | u32 v; | |
3063 | ||
3064 | v = readl_relaxed(clk_base + RST_DFLL_DVCO); | |
3065 | v &= ~(1 << DVFS_DFLL_RESET_SHIFT); | |
3066 | writel_relaxed(v, clk_base + RST_DFLL_DVCO); | |
3067 | tegra210_car_barrier(); | |
3068 | } | |
3069 | ||
3070 | static int tegra210_reset_assert(unsigned long id) | |
3071 | { | |
3072 | if (id == TEGRA210_RST_DFLL_DVCO) | |
3073 | tegra210_clock_assert_dfll_dvco_reset(); | |
3074 | else if (id == TEGRA210_RST_ADSP) | |
3075 | writel(GENMASK(26, 21) | BIT(7), | |
3076 | clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_SET); | |
3077 | else | |
3078 | return -EINVAL; | |
3079 | ||
3080 | return 0; | |
3081 | } | |
3082 | ||
3083 | static int tegra210_reset_deassert(unsigned long id) | |
3084 | { | |
3085 | if (id == TEGRA210_RST_DFLL_DVCO) | |
3086 | tegra210_clock_deassert_dfll_dvco_reset(); | |
3087 | else if (id == TEGRA210_RST_ADSP) { | |
3088 | writel(BIT(21), clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_CLR); | |
3089 | /* | |
3090 | * Considering adsp cpu clock (min: 12.5MHZ, max: 1GHz) | |
3091 | * a delay of 5us ensures that it's at least | |
3092 | * 6 * adsp_cpu_cycle_period long. | |
3093 | */ | |
3094 | udelay(5); | |
3095 | writel(GENMASK(26, 22) | BIT(7), | |
3096 | clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_CLR); | |
3097 | } else | |
3098 | return -EINVAL; | |
3099 | ||
3100 | return 0; | |
3101 | } | |
3102 | ||
6b301a05 RK |
3103 | /** |
3104 | * tegra210_clock_init - Tegra210-specific clock initialization | |
3105 | * @np: struct device_node * of the DT node for the SoC CAR IP block | |
3106 | * | |
3107 | * Register most SoC clocks for the Tegra210 system-on-chip. Intended | |
3108 | * to be called by the OF init code when a DT node with the | |
3109 | * "nvidia,tegra210-car" string is encountered, and declared with | |
3110 | * CLK_OF_DECLARE. No return value. | |
3111 | */ | |
3112 | static void __init tegra210_clock_init(struct device_node *np) | |
3113 | { | |
3114 | struct device_node *node; | |
3115 | u32 value, clk_m_div; | |
3116 | ||
3117 | clk_base = of_iomap(np, 0); | |
3118 | if (!clk_base) { | |
3119 | pr_err("ioremap tegra210 CAR failed\n"); | |
3120 | return; | |
3121 | } | |
3122 | ||
3123 | node = of_find_matching_node(NULL, pmc_match); | |
3124 | if (!node) { | |
3125 | pr_err("Failed to find pmc node\n"); | |
3126 | WARN_ON(1); | |
3127 | return; | |
3128 | } | |
3129 | ||
3130 | pmc_base = of_iomap(node, 0); | |
3131 | if (!pmc_base) { | |
3132 | pr_err("Can't map pmc registers\n"); | |
3133 | WARN_ON(1); | |
3134 | return; | |
3135 | } | |
3136 | ||
3137 | clks = tegra_clk_init(clk_base, TEGRA210_CLK_CLK_MAX, | |
3138 | TEGRA210_CAR_BANK_COUNT); | |
3139 | if (!clks) | |
3140 | return; | |
3141 | ||
3142 | value = clk_readl(clk_base + SPARE_REG0) >> CLK_M_DIVISOR_SHIFT; | |
3143 | clk_m_div = (value & CLK_M_DIVISOR_MASK) + 1; | |
3144 | ||
3145 | if (tegra_osc_clk_init(clk_base, tegra210_clks, tegra210_input_freq, | |
3146 | ARRAY_SIZE(tegra210_input_freq), clk_m_div, | |
3147 | &osc_freq, &pll_ref_freq) < 0) | |
3148 | return; | |
3149 | ||
3150 | tegra_fixed_clk_init(tegra210_clks); | |
3151 | tegra210_pll_init(clk_base, pmc_base); | |
3152 | tegra210_periph_clk_init(clk_base, pmc_base); | |
3153 | tegra_audio_clk_init(clk_base, pmc_base, tegra210_clks, | |
3154 | tegra210_audio_plls, | |
3155 | ARRAY_SIZE(tegra210_audio_plls)); | |
3156 | tegra_pmc_clk_init(pmc_base, tegra210_clks); | |
3157 | ||
3158 | /* For Tegra210, PLLD is the only source for DSIA & DSIB */ | |
3159 | value = clk_readl(clk_base + PLLD_BASE); | |
3160 | value &= ~BIT(25); | |
3161 | clk_writel(value, clk_base + PLLD_BASE); | |
3162 | ||
3163 | tegra_clk_apply_init_table = tegra210_clock_apply_init_table; | |
3164 | ||
3165 | tegra_super_clk_gen5_init(clk_base, pmc_base, tegra210_clks, | |
3166 | &pll_x_params); | |
68d724ce PDS |
3167 | tegra_init_special_resets(2, tegra210_reset_assert, |
3168 | tegra210_reset_deassert); | |
3169 | ||
6b301a05 RK |
3170 | tegra_add_of_provider(np); |
3171 | tegra_register_devclks(devclks, ARRAY_SIZE(devclks)); | |
3172 | ||
3173 | tegra_cpu_car_ops = &tegra210_cpu_car_ops; | |
3174 | } | |
3175 | CLK_OF_DECLARE(tegra210, "nvidia,tegra210-car", tegra210_clock_init); |