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2cb5efef PDS |
1 | /* |
2 | * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License | |
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
15 | */ | |
16 | ||
17 | #include <linux/io.h> | |
18 | #include <linux/clk.h> | |
19 | #include <linux/clk-provider.h> | |
20 | #include <linux/clkdev.h> | |
21 | #include <linux/of.h> | |
22 | #include <linux/of_address.h> | |
23 | #include <linux/delay.h> | |
25c9ded6 | 24 | #include <linux/export.h> |
2cb5efef | 25 | #include <linux/clk/tegra.h> |
c9e2d69a | 26 | #include <dt-bindings/clock/tegra114-car.h> |
2cb5efef PDS |
27 | |
28 | #include "clk.h" | |
29 | ||
1c472d8e | 30 | #define RST_DFLL_DVCO 0x2F4 |
25c9ded6 PW |
31 | #define CPU_FINETRIM_SELECT 0x4d4 /* override default prop dlys */ |
32 | #define CPU_FINETRIM_DR 0x4d8 /* rise->rise prop dly A */ | |
33 | #define CPU_FINETRIM_R 0x4e4 /* rise->rise prop dly inc A */ | |
2cb5efef | 34 | |
1c472d8e PW |
35 | /* RST_DFLL_DVCO bitfields */ |
36 | #define DVFS_DFLL_RESET_SHIFT 0 | |
37 | ||
25c9ded6 PW |
38 | /* CPU_FINETRIM_SELECT and CPU_FINETRIM_DR bitfields */ |
39 | #define CPU_FINETRIM_1_FCPU_1 BIT(0) /* fcpu0 */ | |
40 | #define CPU_FINETRIM_1_FCPU_2 BIT(1) /* fcpu1 */ | |
41 | #define CPU_FINETRIM_1_FCPU_3 BIT(2) /* fcpu2 */ | |
42 | #define CPU_FINETRIM_1_FCPU_4 BIT(3) /* fcpu3 */ | |
43 | #define CPU_FINETRIM_1_FCPU_5 BIT(4) /* fl2 */ | |
44 | #define CPU_FINETRIM_1_FCPU_6 BIT(5) /* ftop */ | |
45 | ||
46 | /* CPU_FINETRIM_R bitfields */ | |
47 | #define CPU_FINETRIM_R_FCPU_1_SHIFT 0 /* fcpu0 */ | |
48 | #define CPU_FINETRIM_R_FCPU_1_MASK (0x3 << CPU_FINETRIM_R_FCPU_1_SHIFT) | |
49 | #define CPU_FINETRIM_R_FCPU_2_SHIFT 2 /* fcpu1 */ | |
50 | #define CPU_FINETRIM_R_FCPU_2_MASK (0x3 << CPU_FINETRIM_R_FCPU_2_SHIFT) | |
51 | #define CPU_FINETRIM_R_FCPU_3_SHIFT 4 /* fcpu2 */ | |
52 | #define CPU_FINETRIM_R_FCPU_3_MASK (0x3 << CPU_FINETRIM_R_FCPU_3_SHIFT) | |
53 | #define CPU_FINETRIM_R_FCPU_4_SHIFT 6 /* fcpu3 */ | |
54 | #define CPU_FINETRIM_R_FCPU_4_MASK (0x3 << CPU_FINETRIM_R_FCPU_4_SHIFT) | |
55 | #define CPU_FINETRIM_R_FCPU_5_SHIFT 8 /* fl2 */ | |
56 | #define CPU_FINETRIM_R_FCPU_5_MASK (0x3 << CPU_FINETRIM_R_FCPU_5_SHIFT) | |
57 | #define CPU_FINETRIM_R_FCPU_6_SHIFT 10 /* ftop */ | |
58 | #define CPU_FINETRIM_R_FCPU_6_MASK (0x3 << CPU_FINETRIM_R_FCPU_6_SHIFT) | |
59 | ||
d5ff89a8 PDS |
60 | #define TEGRA114_CLK_PERIPH_BANKS 5 |
61 | ||
2cb5efef PDS |
62 | #define PLLC_BASE 0x80 |
63 | #define PLLC_MISC2 0x88 | |
64 | #define PLLC_MISC 0x8c | |
65 | #define PLLC2_BASE 0x4e8 | |
66 | #define PLLC2_MISC 0x4ec | |
67 | #define PLLC3_BASE 0x4fc | |
68 | #define PLLC3_MISC 0x500 | |
69 | #define PLLM_BASE 0x90 | |
70 | #define PLLM_MISC 0x9c | |
71 | #define PLLP_BASE 0xa0 | |
72 | #define PLLP_MISC 0xac | |
73 | #define PLLX_BASE 0xe0 | |
74 | #define PLLX_MISC 0xe4 | |
75 | #define PLLX_MISC2 0x514 | |
76 | #define PLLX_MISC3 0x518 | |
77 | #define PLLD_BASE 0xd0 | |
78 | #define PLLD_MISC 0xdc | |
79 | #define PLLD2_BASE 0x4b8 | |
80 | #define PLLD2_MISC 0x4bc | |
81 | #define PLLE_BASE 0xe8 | |
82 | #define PLLE_MISC 0xec | |
83 | #define PLLA_BASE 0xb0 | |
84 | #define PLLA_MISC 0xbc | |
85 | #define PLLU_BASE 0xc0 | |
86 | #define PLLU_MISC 0xcc | |
87 | #define PLLRE_BASE 0x4c4 | |
88 | #define PLLRE_MISC 0x4c8 | |
89 | ||
90 | #define PLL_MISC_LOCK_ENABLE 18 | |
91 | #define PLLC_MISC_LOCK_ENABLE 24 | |
92 | #define PLLDU_MISC_LOCK_ENABLE 22 | |
93 | #define PLLE_MISC_LOCK_ENABLE 9 | |
94 | #define PLLRE_MISC_LOCK_ENABLE 30 | |
95 | ||
96 | #define PLLC_IDDQ_BIT 26 | |
97 | #define PLLX_IDDQ_BIT 3 | |
98 | #define PLLRE_IDDQ_BIT 16 | |
99 | ||
100 | #define PLL_BASE_LOCK BIT(27) | |
101 | #define PLLE_MISC_LOCK BIT(11) | |
102 | #define PLLRE_MISC_LOCK BIT(24) | |
103 | #define PLLCX_BASE_LOCK (BIT(26)|BIT(27)) | |
104 | ||
105 | #define PLLE_AUX 0x48c | |
106 | #define PLLC_OUT 0x84 | |
107 | #define PLLM_OUT 0x94 | |
108 | #define PLLP_OUTA 0xa4 | |
109 | #define PLLP_OUTB 0xa8 | |
110 | #define PLLA_OUT 0xb4 | |
111 | ||
112 | #define AUDIO_SYNC_CLK_I2S0 0x4a0 | |
113 | #define AUDIO_SYNC_CLK_I2S1 0x4a4 | |
114 | #define AUDIO_SYNC_CLK_I2S2 0x4a8 | |
115 | #define AUDIO_SYNC_CLK_I2S3 0x4ac | |
116 | #define AUDIO_SYNC_CLK_I2S4 0x4b0 | |
117 | #define AUDIO_SYNC_CLK_SPDIF 0x4b4 | |
118 | ||
119 | #define AUDIO_SYNC_DOUBLER 0x49c | |
120 | ||
121 | #define PMC_CLK_OUT_CNTRL 0x1a8 | |
122 | #define PMC_DPD_PADS_ORIDE 0x1c | |
123 | #define PMC_DPD_PADS_ORIDE_BLINK_ENB 20 | |
124 | #define PMC_CTRL 0 | |
125 | #define PMC_CTRL_BLINK_ENB 7 | |
9139227d | 126 | #define PMC_BLINK_TIMER 0x40 |
2cb5efef PDS |
127 | |
128 | #define OSC_CTRL 0x50 | |
129 | #define OSC_CTRL_OSC_FREQ_SHIFT 28 | |
130 | #define OSC_CTRL_PLL_REF_DIV_SHIFT 26 | |
131 | ||
132 | #define PLLXC_SW_MAX_P 6 | |
133 | ||
134 | #define CCLKG_BURST_POLICY 0x368 | |
135 | #define CCLKLP_BURST_POLICY 0x370 | |
136 | #define SCLK_BURST_POLICY 0x028 | |
137 | #define SYSTEM_CLK_RATE 0x030 | |
138 | ||
139 | #define UTMIP_PLL_CFG2 0x488 | |
140 | #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6) | |
141 | #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18) | |
142 | #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0) | |
143 | #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2) | |
144 | #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4) | |
145 | ||
146 | #define UTMIP_PLL_CFG1 0x484 | |
147 | #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6) | |
148 | #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0) | |
149 | #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17) | |
150 | #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16) | |
151 | #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15) | |
152 | #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14) | |
153 | #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12) | |
154 | ||
155 | #define UTMIPLL_HW_PWRDN_CFG0 0x52c | |
156 | #define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE BIT(25) | |
157 | #define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24) | |
158 | #define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET BIT(6) | |
159 | #define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5) | |
160 | #define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL BIT(4) | |
161 | #define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2) | |
162 | #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1) | |
163 | #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0) | |
164 | ||
165 | #define CLK_SOURCE_I2S0 0x1d8 | |
166 | #define CLK_SOURCE_I2S1 0x100 | |
167 | #define CLK_SOURCE_I2S2 0x104 | |
168 | #define CLK_SOURCE_NDFLASH 0x160 | |
169 | #define CLK_SOURCE_I2S3 0x3bc | |
170 | #define CLK_SOURCE_I2S4 0x3c0 | |
171 | #define CLK_SOURCE_SPDIF_OUT 0x108 | |
172 | #define CLK_SOURCE_SPDIF_IN 0x10c | |
173 | #define CLK_SOURCE_PWM 0x110 | |
174 | #define CLK_SOURCE_ADX 0x638 | |
175 | #define CLK_SOURCE_AMX 0x63c | |
176 | #define CLK_SOURCE_HDA 0x428 | |
177 | #define CLK_SOURCE_HDA2CODEC_2X 0x3e4 | |
178 | #define CLK_SOURCE_SBC1 0x134 | |
179 | #define CLK_SOURCE_SBC2 0x118 | |
180 | #define CLK_SOURCE_SBC3 0x11c | |
181 | #define CLK_SOURCE_SBC4 0x1b4 | |
182 | #define CLK_SOURCE_SBC5 0x3c8 | |
183 | #define CLK_SOURCE_SBC6 0x3cc | |
184 | #define CLK_SOURCE_SATA_OOB 0x420 | |
185 | #define CLK_SOURCE_SATA 0x424 | |
186 | #define CLK_SOURCE_NDSPEED 0x3f8 | |
187 | #define CLK_SOURCE_VFIR 0x168 | |
188 | #define CLK_SOURCE_SDMMC1 0x150 | |
189 | #define CLK_SOURCE_SDMMC2 0x154 | |
190 | #define CLK_SOURCE_SDMMC3 0x1bc | |
191 | #define CLK_SOURCE_SDMMC4 0x164 | |
192 | #define CLK_SOURCE_VDE 0x1c8 | |
193 | #define CLK_SOURCE_CSITE 0x1d4 | |
194 | #define CLK_SOURCE_LA 0x1f8 | |
195 | #define CLK_SOURCE_TRACE 0x634 | |
196 | #define CLK_SOURCE_OWR 0x1cc | |
197 | #define CLK_SOURCE_NOR 0x1d0 | |
198 | #define CLK_SOURCE_MIPI 0x174 | |
199 | #define CLK_SOURCE_I2C1 0x124 | |
200 | #define CLK_SOURCE_I2C2 0x198 | |
201 | #define CLK_SOURCE_I2C3 0x1b8 | |
202 | #define CLK_SOURCE_I2C4 0x3c4 | |
203 | #define CLK_SOURCE_I2C5 0x128 | |
204 | #define CLK_SOURCE_UARTA 0x178 | |
205 | #define CLK_SOURCE_UARTB 0x17c | |
206 | #define CLK_SOURCE_UARTC 0x1a0 | |
207 | #define CLK_SOURCE_UARTD 0x1c0 | |
208 | #define CLK_SOURCE_UARTE 0x1c4 | |
209 | #define CLK_SOURCE_UARTA_DBG 0x178 | |
210 | #define CLK_SOURCE_UARTB_DBG 0x17c | |
211 | #define CLK_SOURCE_UARTC_DBG 0x1a0 | |
212 | #define CLK_SOURCE_UARTD_DBG 0x1c0 | |
213 | #define CLK_SOURCE_UARTE_DBG 0x1c4 | |
214 | #define CLK_SOURCE_3D 0x158 | |
215 | #define CLK_SOURCE_2D 0x15c | |
216 | #define CLK_SOURCE_VI_SENSOR 0x1a8 | |
217 | #define CLK_SOURCE_VI 0x148 | |
218 | #define CLK_SOURCE_EPP 0x16c | |
219 | #define CLK_SOURCE_MSENC 0x1f0 | |
220 | #define CLK_SOURCE_TSEC 0x1f4 | |
221 | #define CLK_SOURCE_HOST1X 0x180 | |
222 | #define CLK_SOURCE_HDMI 0x18c | |
223 | #define CLK_SOURCE_DISP1 0x138 | |
224 | #define CLK_SOURCE_DISP2 0x13c | |
225 | #define CLK_SOURCE_CILAB 0x614 | |
226 | #define CLK_SOURCE_CILCD 0x618 | |
227 | #define CLK_SOURCE_CILE 0x61c | |
228 | #define CLK_SOURCE_DSIALP 0x620 | |
229 | #define CLK_SOURCE_DSIBLP 0x624 | |
230 | #define CLK_SOURCE_TSENSOR 0x3b8 | |
231 | #define CLK_SOURCE_D_AUDIO 0x3d0 | |
232 | #define CLK_SOURCE_DAM0 0x3d8 | |
233 | #define CLK_SOURCE_DAM1 0x3dc | |
234 | #define CLK_SOURCE_DAM2 0x3e0 | |
235 | #define CLK_SOURCE_ACTMON 0x3e8 | |
236 | #define CLK_SOURCE_EXTERN1 0x3ec | |
237 | #define CLK_SOURCE_EXTERN2 0x3f0 | |
238 | #define CLK_SOURCE_EXTERN3 0x3f4 | |
239 | #define CLK_SOURCE_I2CSLOW 0x3fc | |
240 | #define CLK_SOURCE_SE 0x42c | |
241 | #define CLK_SOURCE_MSELECT 0x3b4 | |
9e60121f PW |
242 | #define CLK_SOURCE_DFLL_REF 0x62c |
243 | #define CLK_SOURCE_DFLL_SOC 0x630 | |
2cb5efef PDS |
244 | #define CLK_SOURCE_SOC_THERM 0x644 |
245 | #define CLK_SOURCE_XUSB_HOST_SRC 0x600 | |
246 | #define CLK_SOURCE_XUSB_FALCON_SRC 0x604 | |
247 | #define CLK_SOURCE_XUSB_FS_SRC 0x608 | |
248 | #define CLK_SOURCE_XUSB_SS_SRC 0x610 | |
249 | #define CLK_SOURCE_XUSB_DEV_SRC 0x60c | |
250 | #define CLK_SOURCE_EMC 0x19c | |
251 | ||
d53442e9 PDS |
252 | /* PLLM override registers */ |
253 | #define PMC_PLLM_WB0_OVERRIDE 0x1dc | |
254 | #define PMC_PLLM_WB0_OVERRIDE_2 0x2b0 | |
255 | ||
31972fd9 JL |
256 | /* Tegra CPU clock and reset control regs */ |
257 | #define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470 | |
258 | ||
ad7d1140 JL |
259 | #ifdef CONFIG_PM_SLEEP |
260 | static struct cpu_clk_suspend_context { | |
261 | u32 clk_csite_src; | |
0017f447 JL |
262 | u32 cclkg_burst; |
263 | u32 cclkg_divider; | |
ad7d1140 JL |
264 | } tegra114_cpu_clk_sctx; |
265 | #endif | |
266 | ||
2cb5efef PDS |
267 | static void __iomem *clk_base; |
268 | static void __iomem *pmc_base; | |
269 | ||
270 | static DEFINE_SPINLOCK(pll_d_lock); | |
271 | static DEFINE_SPINLOCK(pll_d2_lock); | |
272 | static DEFINE_SPINLOCK(pll_u_lock); | |
273 | static DEFINE_SPINLOCK(pll_div_lock); | |
274 | static DEFINE_SPINLOCK(pll_re_lock); | |
275 | static DEFINE_SPINLOCK(clk_doubler_lock); | |
276 | static DEFINE_SPINLOCK(clk_out_lock); | |
277 | static DEFINE_SPINLOCK(sysrate_lock); | |
278 | ||
fd428ad8 PDS |
279 | static struct div_nmp pllxc_nmp = { |
280 | .divm_shift = 0, | |
281 | .divm_width = 8, | |
282 | .divn_shift = 8, | |
283 | .divn_width = 8, | |
284 | .divp_shift = 20, | |
285 | .divp_width = 4, | |
286 | }; | |
287 | ||
2cb5efef PDS |
288 | static struct pdiv_map pllxc_p[] = { |
289 | { .pdiv = 1, .hw_val = 0 }, | |
290 | { .pdiv = 2, .hw_val = 1 }, | |
291 | { .pdiv = 3, .hw_val = 2 }, | |
292 | { .pdiv = 4, .hw_val = 3 }, | |
293 | { .pdiv = 5, .hw_val = 4 }, | |
294 | { .pdiv = 6, .hw_val = 5 }, | |
295 | { .pdiv = 8, .hw_val = 6 }, | |
296 | { .pdiv = 10, .hw_val = 7 }, | |
297 | { .pdiv = 12, .hw_val = 8 }, | |
298 | { .pdiv = 16, .hw_val = 9 }, | |
299 | { .pdiv = 12, .hw_val = 10 }, | |
300 | { .pdiv = 16, .hw_val = 11 }, | |
301 | { .pdiv = 20, .hw_val = 12 }, | |
302 | { .pdiv = 24, .hw_val = 13 }, | |
303 | { .pdiv = 32, .hw_val = 14 }, | |
304 | { .pdiv = 0, .hw_val = 0 }, | |
305 | }; | |
306 | ||
307 | static struct tegra_clk_pll_freq_table pll_c_freq_table[] = { | |
308 | { 12000000, 624000000, 104, 0, 2}, | |
309 | { 12000000, 600000000, 100, 0, 2}, | |
310 | { 13000000, 600000000, 92, 0, 2}, /* actual: 598.0 MHz */ | |
311 | { 16800000, 600000000, 71, 0, 2}, /* actual: 596.4 MHz */ | |
312 | { 19200000, 600000000, 62, 0, 2}, /* actual: 595.2 MHz */ | |
313 | { 26000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */ | |
314 | { 0, 0, 0, 0, 0, 0 }, | |
315 | }; | |
316 | ||
317 | static struct tegra_clk_pll_params pll_c_params = { | |
318 | .input_min = 12000000, | |
319 | .input_max = 800000000, | |
320 | .cf_min = 12000000, | |
321 | .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */ | |
322 | .vco_min = 600000000, | |
323 | .vco_max = 1400000000, | |
324 | .base_reg = PLLC_BASE, | |
325 | .misc_reg = PLLC_MISC, | |
326 | .lock_mask = PLL_BASE_LOCK, | |
327 | .lock_enable_bit_idx = PLLC_MISC_LOCK_ENABLE, | |
328 | .lock_delay = 300, | |
329 | .iddq_reg = PLLC_MISC, | |
330 | .iddq_bit_idx = PLLC_IDDQ_BIT, | |
331 | .max_p = PLLXC_SW_MAX_P, | |
332 | .dyn_ramp_reg = PLLC_MISC2, | |
333 | .stepa_shift = 17, | |
334 | .stepb_shift = 9, | |
335 | .pdiv_tohw = pllxc_p, | |
fd428ad8 | 336 | .div_nmp = &pllxc_nmp, |
ebe142b2 PDS |
337 | .freq_table = pll_c_freq_table, |
338 | .flags = TEGRA_PLL_USE_LOCK, | |
fd428ad8 PDS |
339 | }; |
340 | ||
341 | static struct div_nmp pllcx_nmp = { | |
342 | .divm_shift = 0, | |
343 | .divm_width = 2, | |
344 | .divn_shift = 8, | |
345 | .divn_width = 8, | |
346 | .divp_shift = 20, | |
347 | .divp_width = 3, | |
2cb5efef PDS |
348 | }; |
349 | ||
350 | static struct pdiv_map pllc_p[] = { | |
351 | { .pdiv = 1, .hw_val = 0 }, | |
352 | { .pdiv = 2, .hw_val = 1 }, | |
353 | { .pdiv = 4, .hw_val = 3 }, | |
354 | { .pdiv = 8, .hw_val = 5 }, | |
355 | { .pdiv = 16, .hw_val = 7 }, | |
356 | { .pdiv = 0, .hw_val = 0 }, | |
357 | }; | |
358 | ||
359 | static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = { | |
360 | {12000000, 600000000, 100, 0, 2}, | |
361 | {13000000, 600000000, 92, 0, 2}, /* actual: 598.0 MHz */ | |
362 | {16800000, 600000000, 71, 0, 2}, /* actual: 596.4 MHz */ | |
363 | {19200000, 600000000, 62, 0, 2}, /* actual: 595.2 MHz */ | |
364 | {26000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */ | |
365 | {0, 0, 0, 0, 0, 0}, | |
366 | }; | |
367 | ||
368 | static struct tegra_clk_pll_params pll_c2_params = { | |
369 | .input_min = 12000000, | |
370 | .input_max = 48000000, | |
371 | .cf_min = 12000000, | |
372 | .cf_max = 19200000, | |
373 | .vco_min = 600000000, | |
374 | .vco_max = 1200000000, | |
375 | .base_reg = PLLC2_BASE, | |
376 | .misc_reg = PLLC2_MISC, | |
377 | .lock_mask = PLL_BASE_LOCK, | |
378 | .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, | |
379 | .lock_delay = 300, | |
380 | .pdiv_tohw = pllc_p, | |
fd428ad8 PDS |
381 | .div_nmp = &pllcx_nmp, |
382 | .max_p = 7, | |
2cb5efef PDS |
383 | .ext_misc_reg[0] = 0x4f0, |
384 | .ext_misc_reg[1] = 0x4f4, | |
385 | .ext_misc_reg[2] = 0x4f8, | |
ebe142b2 PDS |
386 | .freq_table = pll_cx_freq_table, |
387 | .flags = TEGRA_PLL_USE_LOCK, | |
2cb5efef PDS |
388 | }; |
389 | ||
390 | static struct tegra_clk_pll_params pll_c3_params = { | |
391 | .input_min = 12000000, | |
392 | .input_max = 48000000, | |
393 | .cf_min = 12000000, | |
394 | .cf_max = 19200000, | |
395 | .vco_min = 600000000, | |
396 | .vco_max = 1200000000, | |
397 | .base_reg = PLLC3_BASE, | |
398 | .misc_reg = PLLC3_MISC, | |
399 | .lock_mask = PLL_BASE_LOCK, | |
400 | .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, | |
401 | .lock_delay = 300, | |
402 | .pdiv_tohw = pllc_p, | |
fd428ad8 PDS |
403 | .div_nmp = &pllcx_nmp, |
404 | .max_p = 7, | |
2cb5efef PDS |
405 | .ext_misc_reg[0] = 0x504, |
406 | .ext_misc_reg[1] = 0x508, | |
407 | .ext_misc_reg[2] = 0x50c, | |
ebe142b2 PDS |
408 | .freq_table = pll_cx_freq_table, |
409 | .flags = TEGRA_PLL_USE_LOCK, | |
2cb5efef PDS |
410 | }; |
411 | ||
fd428ad8 PDS |
412 | static struct div_nmp pllm_nmp = { |
413 | .divm_shift = 0, | |
414 | .divm_width = 8, | |
d53442e9 | 415 | .override_divm_shift = 0, |
fd428ad8 PDS |
416 | .divn_shift = 8, |
417 | .divn_width = 8, | |
d53442e9 | 418 | .override_divn_shift = 8, |
fd428ad8 PDS |
419 | .divp_shift = 20, |
420 | .divp_width = 1, | |
d53442e9 | 421 | .override_divp_shift = 27, |
fd428ad8 PDS |
422 | }; |
423 | ||
2cb5efef PDS |
424 | static struct pdiv_map pllm_p[] = { |
425 | { .pdiv = 1, .hw_val = 0 }, | |
426 | { .pdiv = 2, .hw_val = 1 }, | |
427 | { .pdiv = 0, .hw_val = 0 }, | |
428 | }; | |
429 | ||
430 | static struct tegra_clk_pll_freq_table pll_m_freq_table[] = { | |
431 | {12000000, 800000000, 66, 0, 1}, /* actual: 792.0 MHz */ | |
432 | {13000000, 800000000, 61, 0, 1}, /* actual: 793.0 MHz */ | |
433 | {16800000, 800000000, 47, 0, 1}, /* actual: 789.6 MHz */ | |
434 | {19200000, 800000000, 41, 0, 1}, /* actual: 787.2 MHz */ | |
435 | {26000000, 800000000, 61, 1, 1}, /* actual: 793.0 MHz */ | |
436 | {0, 0, 0, 0, 0, 0}, | |
437 | }; | |
438 | ||
439 | static struct tegra_clk_pll_params pll_m_params = { | |
440 | .input_min = 12000000, | |
441 | .input_max = 500000000, | |
442 | .cf_min = 12000000, | |
443 | .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */ | |
444 | .vco_min = 400000000, | |
445 | .vco_max = 1066000000, | |
446 | .base_reg = PLLM_BASE, | |
447 | .misc_reg = PLLM_MISC, | |
448 | .lock_mask = PLL_BASE_LOCK, | |
449 | .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, | |
450 | .lock_delay = 300, | |
451 | .max_p = 2, | |
452 | .pdiv_tohw = pllm_p, | |
fd428ad8 | 453 | .div_nmp = &pllm_nmp, |
d53442e9 PDS |
454 | .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE, |
455 | .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2, | |
ebe142b2 PDS |
456 | .freq_table = pll_m_freq_table, |
457 | .flags = TEGRA_PLL_USE_LOCK, | |
fd428ad8 PDS |
458 | }; |
459 | ||
460 | static struct div_nmp pllp_nmp = { | |
461 | .divm_shift = 0, | |
462 | .divm_width = 5, | |
463 | .divn_shift = 8, | |
464 | .divn_width = 10, | |
465 | .divp_shift = 20, | |
466 | .divp_width = 3, | |
2cb5efef PDS |
467 | }; |
468 | ||
469 | static struct tegra_clk_pll_freq_table pll_p_freq_table[] = { | |
470 | {12000000, 216000000, 432, 12, 1, 8}, | |
471 | {13000000, 216000000, 432, 13, 1, 8}, | |
472 | {16800000, 216000000, 360, 14, 1, 8}, | |
473 | {19200000, 216000000, 360, 16, 1, 8}, | |
474 | {26000000, 216000000, 432, 26, 1, 8}, | |
475 | {0, 0, 0, 0, 0, 0}, | |
476 | }; | |
477 | ||
478 | static struct tegra_clk_pll_params pll_p_params = { | |
479 | .input_min = 2000000, | |
480 | .input_max = 31000000, | |
481 | .cf_min = 1000000, | |
482 | .cf_max = 6000000, | |
483 | .vco_min = 200000000, | |
484 | .vco_max = 700000000, | |
485 | .base_reg = PLLP_BASE, | |
486 | .misc_reg = PLLP_MISC, | |
487 | .lock_mask = PLL_BASE_LOCK, | |
488 | .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, | |
489 | .lock_delay = 300, | |
fd428ad8 | 490 | .div_nmp = &pllp_nmp, |
ebe142b2 PDS |
491 | .freq_table = pll_p_freq_table, |
492 | .flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK, | |
493 | .fixed_rate = 408000000, | |
2cb5efef PDS |
494 | }; |
495 | ||
496 | static struct tegra_clk_pll_freq_table pll_a_freq_table[] = { | |
497 | {9600000, 282240000, 147, 5, 0, 4}, | |
498 | {9600000, 368640000, 192, 5, 0, 4}, | |
499 | {9600000, 240000000, 200, 8, 0, 8}, | |
500 | ||
501 | {28800000, 282240000, 245, 25, 0, 8}, | |
502 | {28800000, 368640000, 320, 25, 0, 8}, | |
503 | {28800000, 240000000, 200, 24, 0, 8}, | |
504 | {0, 0, 0, 0, 0, 0}, | |
505 | }; | |
506 | ||
507 | ||
508 | static struct tegra_clk_pll_params pll_a_params = { | |
509 | .input_min = 2000000, | |
510 | .input_max = 31000000, | |
511 | .cf_min = 1000000, | |
512 | .cf_max = 6000000, | |
513 | .vco_min = 200000000, | |
514 | .vco_max = 700000000, | |
515 | .base_reg = PLLA_BASE, | |
516 | .misc_reg = PLLA_MISC, | |
517 | .lock_mask = PLL_BASE_LOCK, | |
518 | .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, | |
519 | .lock_delay = 300, | |
fd428ad8 | 520 | .div_nmp = &pllp_nmp, |
ebe142b2 PDS |
521 | .freq_table = pll_a_freq_table, |
522 | .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK, | |
2cb5efef PDS |
523 | }; |
524 | ||
525 | static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { | |
526 | {12000000, 216000000, 864, 12, 2, 12}, | |
527 | {13000000, 216000000, 864, 13, 2, 12}, | |
528 | {16800000, 216000000, 720, 14, 2, 12}, | |
529 | {19200000, 216000000, 720, 16, 2, 12}, | |
530 | {26000000, 216000000, 864, 26, 2, 12}, | |
531 | ||
532 | {12000000, 594000000, 594, 12, 0, 12}, | |
533 | {13000000, 594000000, 594, 13, 0, 12}, | |
534 | {16800000, 594000000, 495, 14, 0, 12}, | |
535 | {19200000, 594000000, 495, 16, 0, 12}, | |
536 | {26000000, 594000000, 594, 26, 0, 12}, | |
537 | ||
538 | {12000000, 1000000000, 1000, 12, 0, 12}, | |
539 | {13000000, 1000000000, 1000, 13, 0, 12}, | |
540 | {19200000, 1000000000, 625, 12, 0, 12}, | |
541 | {26000000, 1000000000, 1000, 26, 0, 12}, | |
542 | ||
543 | {0, 0, 0, 0, 0, 0}, | |
544 | }; | |
545 | ||
546 | static struct tegra_clk_pll_params pll_d_params = { | |
547 | .input_min = 2000000, | |
548 | .input_max = 40000000, | |
549 | .cf_min = 1000000, | |
550 | .cf_max = 6000000, | |
551 | .vco_min = 500000000, | |
552 | .vco_max = 1000000000, | |
553 | .base_reg = PLLD_BASE, | |
554 | .misc_reg = PLLD_MISC, | |
555 | .lock_mask = PLL_BASE_LOCK, | |
556 | .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, | |
557 | .lock_delay = 1000, | |
fd428ad8 | 558 | .div_nmp = &pllp_nmp, |
ebe142b2 PDS |
559 | .freq_table = pll_d_freq_table, |
560 | .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | | |
561 | TEGRA_PLL_USE_LOCK, | |
2cb5efef PDS |
562 | }; |
563 | ||
564 | static struct tegra_clk_pll_params pll_d2_params = { | |
565 | .input_min = 2000000, | |
566 | .input_max = 40000000, | |
567 | .cf_min = 1000000, | |
568 | .cf_max = 6000000, | |
569 | .vco_min = 500000000, | |
570 | .vco_max = 1000000000, | |
571 | .base_reg = PLLD2_BASE, | |
572 | .misc_reg = PLLD2_MISC, | |
573 | .lock_mask = PLL_BASE_LOCK, | |
574 | .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, | |
575 | .lock_delay = 1000, | |
fd428ad8 | 576 | .div_nmp = &pllp_nmp, |
ebe142b2 PDS |
577 | .freq_table = pll_d_freq_table, |
578 | .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | | |
579 | TEGRA_PLL_USE_LOCK, | |
2cb5efef PDS |
580 | }; |
581 | ||
582 | static struct pdiv_map pllu_p[] = { | |
583 | { .pdiv = 1, .hw_val = 1 }, | |
584 | { .pdiv = 2, .hw_val = 0 }, | |
585 | { .pdiv = 0, .hw_val = 0 }, | |
586 | }; | |
587 | ||
fd428ad8 PDS |
588 | static struct div_nmp pllu_nmp = { |
589 | .divm_shift = 0, | |
590 | .divm_width = 5, | |
591 | .divn_shift = 8, | |
592 | .divn_width = 10, | |
593 | .divp_shift = 20, | |
594 | .divp_width = 1, | |
595 | }; | |
596 | ||
2cb5efef PDS |
597 | static struct tegra_clk_pll_freq_table pll_u_freq_table[] = { |
598 | {12000000, 480000000, 960, 12, 0, 12}, | |
599 | {13000000, 480000000, 960, 13, 0, 12}, | |
600 | {16800000, 480000000, 400, 7, 0, 5}, | |
601 | {19200000, 480000000, 200, 4, 0, 3}, | |
602 | {26000000, 480000000, 960, 26, 0, 12}, | |
603 | {0, 0, 0, 0, 0, 0}, | |
604 | }; | |
605 | ||
606 | static struct tegra_clk_pll_params pll_u_params = { | |
607 | .input_min = 2000000, | |
608 | .input_max = 40000000, | |
609 | .cf_min = 1000000, | |
610 | .cf_max = 6000000, | |
611 | .vco_min = 480000000, | |
612 | .vco_max = 960000000, | |
613 | .base_reg = PLLU_BASE, | |
614 | .misc_reg = PLLU_MISC, | |
615 | .lock_mask = PLL_BASE_LOCK, | |
616 | .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, | |
617 | .lock_delay = 1000, | |
618 | .pdiv_tohw = pllu_p, | |
fd428ad8 | 619 | .div_nmp = &pllu_nmp, |
ebe142b2 PDS |
620 | .freq_table = pll_u_freq_table, |
621 | .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | | |
622 | TEGRA_PLL_USE_LOCK, | |
2cb5efef PDS |
623 | }; |
624 | ||
625 | static struct tegra_clk_pll_freq_table pll_x_freq_table[] = { | |
626 | /* 1 GHz */ | |
627 | {12000000, 1000000000, 83, 0, 1}, /* actual: 996.0 MHz */ | |
628 | {13000000, 1000000000, 76, 0, 1}, /* actual: 988.0 MHz */ | |
629 | {16800000, 1000000000, 59, 0, 1}, /* actual: 991.2 MHz */ | |
630 | {19200000, 1000000000, 52, 0, 1}, /* actual: 998.4 MHz */ | |
631 | {26000000, 1000000000, 76, 1, 1}, /* actual: 988.0 MHz */ | |
632 | ||
633 | {0, 0, 0, 0, 0, 0}, | |
634 | }; | |
635 | ||
636 | static struct tegra_clk_pll_params pll_x_params = { | |
637 | .input_min = 12000000, | |
638 | .input_max = 800000000, | |
639 | .cf_min = 12000000, | |
640 | .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */ | |
641 | .vco_min = 700000000, | |
642 | .vco_max = 2400000000U, | |
643 | .base_reg = PLLX_BASE, | |
644 | .misc_reg = PLLX_MISC, | |
645 | .lock_mask = PLL_BASE_LOCK, | |
646 | .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, | |
647 | .lock_delay = 300, | |
648 | .iddq_reg = PLLX_MISC3, | |
649 | .iddq_bit_idx = PLLX_IDDQ_BIT, | |
650 | .max_p = PLLXC_SW_MAX_P, | |
651 | .dyn_ramp_reg = PLLX_MISC2, | |
652 | .stepa_shift = 16, | |
653 | .stepb_shift = 24, | |
654 | .pdiv_tohw = pllxc_p, | |
fd428ad8 | 655 | .div_nmp = &pllxc_nmp, |
ebe142b2 PDS |
656 | .freq_table = pll_x_freq_table, |
657 | .flags = TEGRA_PLL_USE_LOCK, | |
2cb5efef PDS |
658 | }; |
659 | ||
660 | static struct tegra_clk_pll_freq_table pll_e_freq_table[] = { | |
661 | /* PLLE special case: use cpcon field to store cml divider value */ | |
662 | {336000000, 100000000, 100, 21, 16, 11}, | |
663 | {312000000, 100000000, 200, 26, 24, 13}, | |
8e9cc80a | 664 | {12000000, 100000000, 200, 1, 24, 13}, |
2cb5efef PDS |
665 | {0, 0, 0, 0, 0, 0}, |
666 | }; | |
667 | ||
fd428ad8 PDS |
668 | static struct div_nmp plle_nmp = { |
669 | .divm_shift = 0, | |
670 | .divm_width = 8, | |
671 | .divn_shift = 8, | |
672 | .divn_width = 8, | |
673 | .divp_shift = 24, | |
674 | .divp_width = 4, | |
675 | }; | |
676 | ||
2cb5efef PDS |
677 | static struct tegra_clk_pll_params pll_e_params = { |
678 | .input_min = 12000000, | |
679 | .input_max = 1000000000, | |
680 | .cf_min = 12000000, | |
681 | .cf_max = 75000000, | |
682 | .vco_min = 1600000000, | |
683 | .vco_max = 2400000000U, | |
684 | .base_reg = PLLE_BASE, | |
685 | .misc_reg = PLLE_MISC, | |
686 | .aux_reg = PLLE_AUX, | |
687 | .lock_mask = PLLE_MISC_LOCK, | |
688 | .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, | |
689 | .lock_delay = 300, | |
fd428ad8 | 690 | .div_nmp = &plle_nmp, |
ebe142b2 PDS |
691 | .freq_table = pll_e_freq_table, |
692 | .flags = TEGRA_PLL_FIXED, | |
693 | .fixed_rate = 100000000, | |
fd428ad8 PDS |
694 | }; |
695 | ||
696 | static struct div_nmp pllre_nmp = { | |
697 | .divm_shift = 0, | |
698 | .divm_width = 8, | |
699 | .divn_shift = 8, | |
700 | .divn_width = 8, | |
701 | .divp_shift = 16, | |
702 | .divp_width = 4, | |
2cb5efef PDS |
703 | }; |
704 | ||
705 | static struct tegra_clk_pll_params pll_re_vco_params = { | |
706 | .input_min = 12000000, | |
707 | .input_max = 1000000000, | |
708 | .cf_min = 12000000, | |
709 | .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */ | |
710 | .vco_min = 300000000, | |
711 | .vco_max = 600000000, | |
712 | .base_reg = PLLRE_BASE, | |
713 | .misc_reg = PLLRE_MISC, | |
714 | .lock_mask = PLLRE_MISC_LOCK, | |
715 | .lock_enable_bit_idx = PLLRE_MISC_LOCK_ENABLE, | |
716 | .lock_delay = 300, | |
717 | .iddq_reg = PLLRE_MISC, | |
718 | .iddq_bit_idx = PLLRE_IDDQ_BIT, | |
fd428ad8 | 719 | .div_nmp = &pllre_nmp, |
ebe142b2 | 720 | .flags = TEGRA_PLL_USE_LOCK, |
2cb5efef PDS |
721 | }; |
722 | ||
2cb5efef PDS |
723 | /* possible OSC frequencies in Hz */ |
724 | static unsigned long tegra114_input_freq[] = { | |
725 | [0] = 13000000, | |
726 | [1] = 16800000, | |
727 | [4] = 19200000, | |
728 | [5] = 38400000, | |
729 | [8] = 12000000, | |
730 | [9] = 48000000, | |
731 | [12] = 260000000, | |
732 | }; | |
733 | ||
734 | #define MASK(x) (BIT(x) - 1) | |
735 | ||
73d37e4c | 736 | #define TEGRA_INIT_DATA_MUX(_name, _parents, _offset, \ |
d5ff89a8 | 737 | _clk_num, _gate_flags, _clk_id) \ |
73d37e4c | 738 | TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\ |
252d0d2b | 739 | 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \ |
343a607c | 740 | _clk_num, _gate_flags, _clk_id, _parents##_idx, 0) |
2cb5efef | 741 | |
73d37e4c | 742 | #define TEGRA_INIT_DATA_MUX_FLAGS(_name, _parents, _offset,\ |
d5ff89a8 | 743 | _clk_num, _gate_flags, _clk_id, flags)\ |
73d37e4c | 744 | TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\ |
252d0d2b | 745 | 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\ |
343a607c | 746 | _clk_num, _gate_flags, _clk_id, _parents##_idx, flags) |
2cb5efef | 747 | |
73d37e4c | 748 | #define TEGRA_INIT_DATA_MUX8(_name, _parents, _offset, \ |
d5ff89a8 | 749 | _clk_num, _gate_flags, _clk_id) \ |
73d37e4c | 750 | TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\ |
252d0d2b | 751 | 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\ |
343a607c | 752 | _clk_num, _gate_flags, _clk_id, _parents##_idx, 0) |
2cb5efef | 753 | |
73d37e4c | 754 | #define TEGRA_INIT_DATA_INT_FLAGS(_name, _parents, _offset,\ |
d5ff89a8 | 755 | _clk_num, _gate_flags, _clk_id, flags)\ |
73d37e4c | 756 | TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\ |
252d0d2b | 757 | 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT | \ |
d5ff89a8 | 758 | TEGRA_DIVIDER_ROUND_UP, _clk_num, \ |
343a607c | 759 | _gate_flags, _clk_id, _parents##_idx, flags) |
2cb5efef | 760 | |
73d37e4c | 761 | #define TEGRA_INIT_DATA_INT8(_name, _parents, _offset,\ |
d5ff89a8 | 762 | _clk_num, _gate_flags, _clk_id) \ |
73d37e4c | 763 | TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\ |
252d0d2b | 764 | 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT | \ |
d5ff89a8 | 765 | TEGRA_DIVIDER_ROUND_UP, _clk_num, \ |
343a607c | 766 | _gate_flags, _clk_id, _parents##_idx, 0) |
2cb5efef | 767 | |
73d37e4c | 768 | #define TEGRA_INIT_DATA_UART(_name, _parents, _offset,\ |
d5ff89a8 | 769 | _clk_num, _clk_id) \ |
73d37e4c | 770 | TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\ |
252d0d2b | 771 | 30, MASK(2), 0, 0, 16, 1, TEGRA_DIVIDER_UART | \ |
d5ff89a8 | 772 | TEGRA_DIVIDER_ROUND_UP, _clk_num, \ |
343a607c | 773 | 0, _clk_id, _parents##_idx, 0) |
2cb5efef | 774 | |
73d37e4c | 775 | #define TEGRA_INIT_DATA_I2C(_name, _parents, _offset,\ |
d5ff89a8 | 776 | _clk_num, _clk_id) \ |
73d37e4c | 777 | TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\ |
252d0d2b | 778 | 30, MASK(2), 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP,\ |
343a607c | 779 | _clk_num, 0, _clk_id, _parents##_idx, 0) |
2cb5efef | 780 | |
73d37e4c | 781 | #define TEGRA_INIT_DATA_NODIV(_name, _parents, _offset, \ |
d5ff89a8 | 782 | _mux_shift, _mux_mask, _clk_num, \ |
2cb5efef | 783 | _gate_flags, _clk_id) \ |
73d37e4c | 784 | TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\ |
d5ff89a8 | 785 | _mux_shift, _mux_mask, 0, 0, 0, 0, 0,\ |
343a607c | 786 | _clk_num, _gate_flags, \ |
2cb5efef PDS |
787 | _clk_id, _parents##_idx, 0) |
788 | ||
73d37e4c | 789 | #define TEGRA_INIT_DATA_XUSB(_name, _parents, _offset, \ |
d5ff89a8 | 790 | _clk_num, _gate_flags, _clk_id) \ |
73d37e4c | 791 | TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset, \ |
252d0d2b | 792 | 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT | \ |
d5ff89a8 | 793 | TEGRA_DIVIDER_ROUND_UP, _clk_num, \ |
343a607c | 794 | _gate_flags, _clk_id, _parents##_idx, 0) |
2cb5efef | 795 | |
73d37e4c | 796 | #define TEGRA_INIT_DATA_AUDIO(_name, _offset, _clk_num,\ |
d5ff89a8 | 797 | _gate_flags, _clk_id) \ |
73d37e4c | 798 | TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, mux_d_audio_clk, \ |
252d0d2b | 799 | _offset, 16, 0xE01F, 0, 0, 8, 1, \ |
343a607c PDS |
800 | TEGRA_DIVIDER_ROUND_UP, _clk_num, \ |
801 | _gate_flags , _clk_id, mux_d_audio_clk_idx, 0) | |
2cb5efef | 802 | |
2cb5efef PDS |
803 | struct utmi_clk_param { |
804 | /* Oscillator Frequency in KHz */ | |
805 | u32 osc_frequency; | |
806 | /* UTMIP PLL Enable Delay Count */ | |
807 | u8 enable_delay_count; | |
808 | /* UTMIP PLL Stable count */ | |
809 | u8 stable_count; | |
810 | /* UTMIP PLL Active delay count */ | |
811 | u8 active_delay_count; | |
812 | /* UTMIP PLL Xtal frequency count */ | |
813 | u8 xtal_freq_count; | |
814 | }; | |
815 | ||
816 | static const struct utmi_clk_param utmi_parameters[] = { | |
817 | {.osc_frequency = 13000000, .enable_delay_count = 0x02, | |
818 | .stable_count = 0x33, .active_delay_count = 0x05, | |
819 | .xtal_freq_count = 0x7F}, | |
820 | {.osc_frequency = 19200000, .enable_delay_count = 0x03, | |
821 | .stable_count = 0x4B, .active_delay_count = 0x06, | |
822 | .xtal_freq_count = 0xBB}, | |
823 | {.osc_frequency = 12000000, .enable_delay_count = 0x02, | |
824 | .stable_count = 0x2F, .active_delay_count = 0x04, | |
825 | .xtal_freq_count = 0x76}, | |
826 | {.osc_frequency = 26000000, .enable_delay_count = 0x04, | |
827 | .stable_count = 0x66, .active_delay_count = 0x09, | |
828 | .xtal_freq_count = 0xFE}, | |
829 | {.osc_frequency = 16800000, .enable_delay_count = 0x03, | |
830 | .stable_count = 0x41, .active_delay_count = 0x0A, | |
831 | .xtal_freq_count = 0xA4}, | |
832 | }; | |
833 | ||
834 | /* peripheral mux definitions */ | |
835 | ||
836 | #define MUX_I2S_SPDIF(_id) \ | |
837 | static const char *mux_pllaout0_##_id##_2x_pllp_clkm[] = { "pll_a_out0", \ | |
838 | #_id, "pll_p",\ | |
839 | "clk_m"}; | |
840 | MUX_I2S_SPDIF(audio0) | |
841 | MUX_I2S_SPDIF(audio1) | |
842 | MUX_I2S_SPDIF(audio2) | |
843 | MUX_I2S_SPDIF(audio3) | |
844 | MUX_I2S_SPDIF(audio4) | |
845 | MUX_I2S_SPDIF(audio) | |
846 | ||
847 | #define mux_pllaout0_audio0_2x_pllp_clkm_idx NULL | |
848 | #define mux_pllaout0_audio1_2x_pllp_clkm_idx NULL | |
849 | #define mux_pllaout0_audio2_2x_pllp_clkm_idx NULL | |
850 | #define mux_pllaout0_audio3_2x_pllp_clkm_idx NULL | |
851 | #define mux_pllaout0_audio4_2x_pllp_clkm_idx NULL | |
852 | #define mux_pllaout0_audio_2x_pllp_clkm_idx NULL | |
853 | ||
854 | static const char *mux_pllp_pllc_pllm_clkm[] = { | |
855 | "pll_p", "pll_c", "pll_m", "clk_m" | |
856 | }; | |
857 | #define mux_pllp_pllc_pllm_clkm_idx NULL | |
858 | ||
859 | static const char *mux_pllp_pllc_pllm[] = { "pll_p", "pll_c", "pll_m" }; | |
860 | #define mux_pllp_pllc_pllm_idx NULL | |
861 | ||
862 | static const char *mux_pllp_pllc_clk32_clkm[] = { | |
863 | "pll_p", "pll_c", "clk_32k", "clk_m" | |
864 | }; | |
865 | #define mux_pllp_pllc_clk32_clkm_idx NULL | |
866 | ||
867 | static const char *mux_plla_pllc_pllp_clkm[] = { | |
868 | "pll_a_out0", "pll_c", "pll_p", "clk_m" | |
869 | }; | |
870 | #define mux_plla_pllc_pllp_clkm_idx mux_pllp_pllc_pllm_clkm_idx | |
871 | ||
872 | static const char *mux_pllp_pllc2_c_c3_pllm_clkm[] = { | |
873 | "pll_p", "pll_c2", "pll_c", "pll_c3", "pll_m", "clk_m" | |
874 | }; | |
875 | static u32 mux_pllp_pllc2_c_c3_pllm_clkm_idx[] = { | |
876 | [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6, | |
877 | }; | |
878 | ||
879 | static const char *mux_pllp_clkm[] = { | |
880 | "pll_p", "clk_m" | |
881 | }; | |
882 | static u32 mux_pllp_clkm_idx[] = { | |
883 | [0] = 0, [1] = 3, | |
884 | }; | |
885 | ||
886 | static const char *mux_pllm_pllc2_c_c3_pllp_plla[] = { | |
887 | "pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0" | |
888 | }; | |
889 | #define mux_pllm_pllc2_c_c3_pllp_plla_idx mux_pllp_pllc2_c_c3_pllm_clkm_idx | |
890 | ||
891 | static const char *mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = { | |
892 | "pll_p", "pll_m", "pll_d_out0", "pll_a_out0", "pll_c", | |
893 | "pll_d2_out0", "clk_m" | |
894 | }; | |
895 | #define mux_pllp_pllm_plld_plla_pllc_plld2_clkm_idx NULL | |
896 | ||
897 | static const char *mux_pllm_pllc_pllp_plla[] = { | |
898 | "pll_m", "pll_c", "pll_p", "pll_a_out0" | |
899 | }; | |
900 | #define mux_pllm_pllc_pllp_plla_idx mux_pllp_pllc_pllm_clkm_idx | |
901 | ||
902 | static const char *mux_pllp_pllc_clkm[] = { | |
903 | "pll_p", "pll_c", "pll_m" | |
904 | }; | |
905 | static u32 mux_pllp_pllc_clkm_idx[] = { | |
906 | [0] = 0, [1] = 1, [2] = 3, | |
907 | }; | |
908 | ||
909 | static const char *mux_pllp_pllc_clkm_clk32[] = { | |
910 | "pll_p", "pll_c", "clk_m", "clk_32k" | |
911 | }; | |
912 | #define mux_pllp_pllc_clkm_clk32_idx NULL | |
913 | ||
914 | static const char *mux_plla_clk32_pllp_clkm_plle[] = { | |
915 | "pll_a_out0", "clk_32k", "pll_p", "clk_m", "pll_e_out0" | |
916 | }; | |
917 | #define mux_plla_clk32_pllp_clkm_plle_idx NULL | |
918 | ||
919 | static const char *mux_clkm_pllp_pllc_pllre[] = { | |
920 | "clk_m", "pll_p", "pll_c", "pll_re_out" | |
921 | }; | |
922 | static u32 mux_clkm_pllp_pllc_pllre_idx[] = { | |
923 | [0] = 0, [1] = 1, [2] = 3, [3] = 5, | |
924 | }; | |
925 | ||
926 | static const char *mux_clkm_48M_pllp_480M[] = { | |
927 | "clk_m", "pll_u_48M", "pll_p", "pll_u_480M" | |
928 | }; | |
929 | #define mux_clkm_48M_pllp_480M_idx NULL | |
930 | ||
931 | static const char *mux_clkm_pllre_clk32_480M_pllc_ref[] = { | |
932 | "clk_m", "pll_re_out", "clk_32k", "pll_u_480M", "pll_c", "pll_ref" | |
933 | }; | |
934 | static u32 mux_clkm_pllre_clk32_480M_pllc_ref_idx[] = { | |
935 | [0] = 0, [1] = 1, [2] = 3, [3] = 3, [4] = 4, [5] = 7, | |
936 | }; | |
937 | ||
938 | static const char *mux_plld_out0_plld2_out0[] = { | |
939 | "pll_d_out0", "pll_d2_out0", | |
940 | }; | |
941 | #define mux_plld_out0_plld2_out0_idx NULL | |
942 | ||
943 | static const char *mux_d_audio_clk[] = { | |
944 | "pll_a_out0", "pll_p", "clk_m", "spdif_in_sync", "i2s0_sync", | |
945 | "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync", | |
946 | }; | |
947 | static u32 mux_d_audio_clk_idx[] = { | |
948 | [0] = 0, [1] = 0x8000, [2] = 0xc000, [3] = 0xE000, [4] = 0xE001, | |
949 | [5] = 0xE002, [6] = 0xE003, [7] = 0xE004, [8] = 0xE005, [9] = 0xE007, | |
950 | }; | |
951 | ||
952 | static const char *mux_pllmcp_clkm[] = { | |
953 | "pll_m_out0", "pll_c_out0", "pll_p_out0", "clk_m", "pll_m_ud", | |
954 | }; | |
955 | ||
956 | static const struct clk_div_table pll_re_div_table[] = { | |
957 | { .val = 0, .div = 1 }, | |
958 | { .val = 1, .div = 2 }, | |
959 | { .val = 2, .div = 3 }, | |
960 | { .val = 3, .div = 4 }, | |
961 | { .val = 4, .div = 5 }, | |
962 | { .val = 5, .div = 6 }, | |
963 | { .val = 0, .div = 0 }, | |
964 | }; | |
965 | ||
73d37e4c PDS |
966 | static struct tegra_devclk devclks[] __initdata = { |
967 | { .con_id = "clk_m", .dt_id = TEGRA114_CLK_CLK_M }, | |
968 | { .con_id = "pll_ref", .dt_id = TEGRA114_CLK_PLL_REF }, | |
969 | { .con_id = "clk_32k", .dt_id = TEGRA114_CLK_CLK_32K }, | |
970 | { .con_id = "clk_m_div2", .dt_id = TEGRA114_CLK_CLK_M_DIV2 }, | |
971 | { .con_id = "clk_m_div4", .dt_id = TEGRA114_CLK_CLK_M_DIV4 }, | |
972 | { .con_id = "pll_c", .dt_id = TEGRA114_CLK_PLL_C }, | |
973 | { .con_id = "pll_c_out1", .dt_id = TEGRA114_CLK_PLL_C_OUT1 }, | |
974 | { .con_id = "pll_c2", .dt_id = TEGRA114_CLK_PLL_C2 }, | |
975 | { .con_id = "pll_c3", .dt_id = TEGRA114_CLK_PLL_C3 }, | |
976 | { .con_id = "pll_p", .dt_id = TEGRA114_CLK_PLL_P }, | |
977 | { .con_id = "pll_p_out1", .dt_id = TEGRA114_CLK_PLL_P_OUT1 }, | |
978 | { .con_id = "pll_p_out2", .dt_id = TEGRA114_CLK_PLL_P_OUT2 }, | |
979 | { .con_id = "pll_p_out3", .dt_id = TEGRA114_CLK_PLL_P_OUT3 }, | |
980 | { .con_id = "pll_p_out4", .dt_id = TEGRA114_CLK_PLL_P_OUT4 }, | |
981 | { .con_id = "pll_m", .dt_id = TEGRA114_CLK_PLL_M }, | |
982 | { .con_id = "pll_m_out1", .dt_id = TEGRA114_CLK_PLL_M_OUT1 }, | |
983 | { .con_id = "pll_x", .dt_id = TEGRA114_CLK_PLL_X }, | |
984 | { .con_id = "pll_x_out0", .dt_id = TEGRA114_CLK_PLL_X_OUT0 }, | |
985 | { .con_id = "pll_u", .dt_id = TEGRA114_CLK_PLL_U }, | |
986 | { .con_id = "pll_u_480M", .dt_id = TEGRA114_CLK_PLL_U_480M }, | |
987 | { .con_id = "pll_u_60M", .dt_id = TEGRA114_CLK_PLL_U_60M }, | |
988 | { .con_id = "pll_u_48M", .dt_id = TEGRA114_CLK_PLL_U_48M }, | |
989 | { .con_id = "pll_u_12M", .dt_id = TEGRA114_CLK_PLL_U_12M }, | |
990 | { .con_id = "pll_d", .dt_id = TEGRA114_CLK_PLL_D }, | |
991 | { .con_id = "pll_d_out0", .dt_id = TEGRA114_CLK_PLL_D_OUT0 }, | |
992 | { .con_id = "pll_d2", .dt_id = TEGRA114_CLK_PLL_D2 }, | |
993 | { .con_id = "pll_d2_out0", .dt_id = TEGRA114_CLK_PLL_D2_OUT0 }, | |
994 | { .con_id = "pll_a", .dt_id = TEGRA114_CLK_PLL_A }, | |
995 | { .con_id = "pll_a_out0", .dt_id = TEGRA114_CLK_PLL_A_OUT0 }, | |
996 | { .con_id = "pll_re_vco", .dt_id = TEGRA114_CLK_PLL_RE_VCO }, | |
997 | { .con_id = "pll_re_out", .dt_id = TEGRA114_CLK_PLL_RE_OUT }, | |
998 | { .con_id = "pll_e_out0", .dt_id = TEGRA114_CLK_PLL_E_OUT0 }, | |
999 | { .con_id = "spdif_in_sync", .dt_id = TEGRA114_CLK_SPDIF_IN_SYNC }, | |
1000 | { .con_id = "i2s0_sync", .dt_id = TEGRA114_CLK_I2S0_SYNC }, | |
1001 | { .con_id = "i2s1_sync", .dt_id = TEGRA114_CLK_I2S1_SYNC }, | |
1002 | { .con_id = "i2s2_sync", .dt_id = TEGRA114_CLK_I2S2_SYNC }, | |
1003 | { .con_id = "i2s3_sync", .dt_id = TEGRA114_CLK_I2S3_SYNC }, | |
1004 | { .con_id = "i2s4_sync", .dt_id = TEGRA114_CLK_I2S4_SYNC }, | |
1005 | { .con_id = "vimclk_sync", .dt_id = TEGRA114_CLK_VIMCLK_SYNC }, | |
1006 | { .con_id = "audio0", .dt_id = TEGRA114_CLK_AUDIO0 }, | |
1007 | { .con_id = "audio1", .dt_id = TEGRA114_CLK_AUDIO1 }, | |
1008 | { .con_id = "audio2", .dt_id = TEGRA114_CLK_AUDIO2 }, | |
1009 | { .con_id = "audio3", .dt_id = TEGRA114_CLK_AUDIO3 }, | |
1010 | { .con_id = "audio4", .dt_id = TEGRA114_CLK_AUDIO4 }, | |
1011 | { .con_id = "spdif", .dt_id = TEGRA114_CLK_SPDIF }, | |
1012 | { .con_id = "audio0_2x", .dt_id = TEGRA114_CLK_AUDIO0_2X }, | |
1013 | { .con_id = "audio1_2x", .dt_id = TEGRA114_CLK_AUDIO1_2X }, | |
1014 | { .con_id = "audio2_2x", .dt_id = TEGRA114_CLK_AUDIO2_2X }, | |
1015 | { .con_id = "audio3_2x", .dt_id = TEGRA114_CLK_AUDIO3_2X }, | |
1016 | { .con_id = "audio4_2x", .dt_id = TEGRA114_CLK_AUDIO4_2X }, | |
1017 | { .con_id = "spdif_2x", .dt_id = TEGRA114_CLK_SPDIF_2X }, | |
1018 | { .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA114_CLK_EXTERN1 }, | |
1019 | { .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA114_CLK_EXTERN2 }, | |
1020 | { .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA114_CLK_EXTERN3 }, | |
1021 | { .con_id = "blink", .dt_id = TEGRA114_CLK_BLINK }, | |
1022 | { .con_id = "cclk_g", .dt_id = TEGRA114_CLK_CCLK_G }, | |
1023 | { .con_id = "cclk_lp", .dt_id = TEGRA114_CLK_CCLK_LP }, | |
1024 | { .con_id = "sclk", .dt_id = TEGRA114_CLK_SCLK }, | |
1025 | { .con_id = "hclk", .dt_id = TEGRA114_CLK_HCLK }, | |
1026 | { .con_id = "pclk", .dt_id = TEGRA114_CLK_PCLK }, | |
1027 | { .dev_id = "rtc-tegra", .dt_id = TEGRA114_CLK_RTC }, | |
1028 | { .dev_id = "timer", .dt_id = TEGRA114_CLK_TIMER }, | |
1029 | }; | |
1030 | ||
343a607c | 1031 | static struct clk **clks; |
2cb5efef PDS |
1032 | |
1033 | static unsigned long osc_freq; | |
1034 | static unsigned long pll_ref_freq; | |
1035 | ||
1036 | static int __init tegra114_osc_clk_init(void __iomem *clk_base) | |
1037 | { | |
1038 | struct clk *clk; | |
1039 | u32 val, pll_ref_div; | |
1040 | ||
1041 | val = readl_relaxed(clk_base + OSC_CTRL); | |
1042 | ||
1043 | osc_freq = tegra114_input_freq[val >> OSC_CTRL_OSC_FREQ_SHIFT]; | |
1044 | if (!osc_freq) { | |
1045 | WARN_ON(1); | |
1046 | return -EINVAL; | |
1047 | } | |
1048 | ||
1049 | /* clk_m */ | |
1050 | clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT, | |
1051 | osc_freq); | |
c9e2d69a | 1052 | clks[TEGRA114_CLK_CLK_M] = clk; |
2cb5efef PDS |
1053 | |
1054 | /* pll_ref */ | |
1055 | val = (val >> OSC_CTRL_PLL_REF_DIV_SHIFT) & 3; | |
1056 | pll_ref_div = 1 << val; | |
1057 | clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m", | |
1058 | CLK_SET_RATE_PARENT, 1, pll_ref_div); | |
c9e2d69a | 1059 | clks[TEGRA114_CLK_PLL_REF] = clk; |
2cb5efef PDS |
1060 | |
1061 | pll_ref_freq = osc_freq / pll_ref_div; | |
1062 | ||
1063 | return 0; | |
1064 | } | |
1065 | ||
1066 | static void __init tegra114_fixed_clk_init(void __iomem *clk_base) | |
1067 | { | |
1068 | struct clk *clk; | |
1069 | ||
1070 | /* clk_32k */ | |
1071 | clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, CLK_IS_ROOT, | |
1072 | 32768); | |
c9e2d69a | 1073 | clks[TEGRA114_CLK_CLK_32K] = clk; |
2cb5efef PDS |
1074 | |
1075 | /* clk_m_div2 */ | |
1076 | clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m", | |
1077 | CLK_SET_RATE_PARENT, 1, 2); | |
c9e2d69a | 1078 | clks[TEGRA114_CLK_CLK_M_DIV2] = clk; |
2cb5efef PDS |
1079 | |
1080 | /* clk_m_div4 */ | |
1081 | clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m", | |
1082 | CLK_SET_RATE_PARENT, 1, 4); | |
c9e2d69a | 1083 | clks[TEGRA114_CLK_CLK_M_DIV4] = clk; |
2cb5efef PDS |
1084 | |
1085 | } | |
1086 | ||
1087 | static __init void tegra114_utmi_param_configure(void __iomem *clk_base) | |
1088 | { | |
1089 | u32 reg; | |
1090 | int i; | |
1091 | ||
1092 | for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) { | |
1093 | if (osc_freq == utmi_parameters[i].osc_frequency) | |
1094 | break; | |
1095 | } | |
1096 | ||
1097 | if (i >= ARRAY_SIZE(utmi_parameters)) { | |
1098 | pr_err("%s: Unexpected oscillator freq %lu\n", __func__, | |
1099 | osc_freq); | |
1100 | return; | |
1101 | } | |
1102 | ||
1103 | reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2); | |
1104 | ||
1105 | /* Program UTMIP PLL stable and active counts */ | |
1106 | /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */ | |
1107 | reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0); | |
1108 | reg |= UTMIP_PLL_CFG2_STABLE_COUNT(utmi_parameters[i].stable_count); | |
1109 | ||
1110 | reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0); | |
1111 | ||
1112 | reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(utmi_parameters[i]. | |
1113 | active_delay_count); | |
1114 | ||
1115 | /* Remove power downs from UTMIP PLL control bits */ | |
1116 | reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN; | |
1117 | reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN; | |
1118 | reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN; | |
1119 | ||
1120 | writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2); | |
1121 | ||
1122 | /* Program UTMIP PLL delay and oscillator frequency counts */ | |
1123 | reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); | |
1124 | reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0); | |
1125 | ||
1126 | reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(utmi_parameters[i]. | |
1127 | enable_delay_count); | |
1128 | ||
1129 | reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0); | |
1130 | reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(utmi_parameters[i]. | |
1131 | xtal_freq_count); | |
1132 | ||
1133 | /* Remove power downs from UTMIP PLL control bits */ | |
1134 | reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; | |
1135 | reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN; | |
1136 | reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP; | |
1137 | reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN; | |
1138 | writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); | |
1139 | ||
1140 | /* Setup HW control of UTMIPLL */ | |
1141 | reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); | |
1142 | reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET; | |
1143 | reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL; | |
1144 | reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE; | |
1145 | writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); | |
1146 | ||
1147 | reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); | |
1148 | reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP; | |
1149 | reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; | |
1150 | writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); | |
1151 | ||
1152 | udelay(1); | |
1153 | ||
1154 | /* Setup SW override of UTMIPLL assuming USB2.0 | |
1155 | ports are assigned to USB2 */ | |
1156 | reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); | |
1157 | reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL; | |
1158 | reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE; | |
1159 | writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); | |
1160 | ||
1161 | udelay(1); | |
1162 | ||
1163 | /* Enable HW control UTMIPLL */ | |
1164 | reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); | |
1165 | reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE; | |
1166 | writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); | |
1167 | } | |
1168 | ||
2cb5efef PDS |
1169 | static void __init tegra114_pll_init(void __iomem *clk_base, |
1170 | void __iomem *pmc) | |
1171 | { | |
1172 | u32 val; | |
1173 | struct clk *clk; | |
1174 | ||
1175 | /* PLLC */ | |
04edb099 | 1176 | clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base, |
ebe142b2 | 1177 | pmc, 0, &pll_c_params, NULL); |
04edb099 PDS |
1178 | clks[TEGRA114_CLK_PLL_C] = clk; |
1179 | ||
1180 | /* PLLC_OUT1 */ | |
1181 | clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c", | |
1182 | clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, | |
1183 | 8, 8, 1, NULL); | |
1184 | clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div", | |
1185 | clk_base + PLLC_OUT, 1, 0, | |
1186 | CLK_SET_RATE_PARENT, 0, NULL); | |
04edb099 | 1187 | clks[TEGRA114_CLK_PLL_C_OUT1] = clk; |
2cb5efef PDS |
1188 | |
1189 | /* PLLC2 */ | |
ebe142b2 PDS |
1190 | clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0, |
1191 | &pll_c2_params, NULL); | |
c9e2d69a | 1192 | clks[TEGRA114_CLK_PLL_C2] = clk; |
2cb5efef PDS |
1193 | |
1194 | /* PLLC3 */ | |
ebe142b2 PDS |
1195 | clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0, |
1196 | &pll_c3_params, NULL); | |
c9e2d69a | 1197 | clks[TEGRA114_CLK_PLL_C3] = clk; |
2cb5efef PDS |
1198 | |
1199 | /* PLLP */ | |
1200 | clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base, pmc, 0, | |
ebe142b2 | 1201 | &pll_p_params, NULL); |
c9e2d69a | 1202 | clks[TEGRA114_CLK_PLL_P] = clk; |
2cb5efef PDS |
1203 | |
1204 | /* PLLP_OUT1 */ | |
1205 | clk = tegra_clk_register_divider("pll_p_out1_div", "pll_p", | |
1206 | clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED | | |
1207 | TEGRA_DIVIDER_ROUND_UP, 8, 8, 1, &pll_div_lock); | |
1208 | clk = tegra_clk_register_pll_out("pll_p_out1", "pll_p_out1_div", | |
1209 | clk_base + PLLP_OUTA, 1, 0, | |
1210 | CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, | |
1211 | &pll_div_lock); | |
c9e2d69a | 1212 | clks[TEGRA114_CLK_PLL_P_OUT1] = clk; |
2cb5efef PDS |
1213 | |
1214 | /* PLLP_OUT2 */ | |
1215 | clk = tegra_clk_register_divider("pll_p_out2_div", "pll_p", | |
1216 | clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED | | |
c388eee2 PDS |
1217 | TEGRA_DIVIDER_ROUND_UP | TEGRA_DIVIDER_INT, 24, |
1218 | 8, 1, &pll_div_lock); | |
2cb5efef PDS |
1219 | clk = tegra_clk_register_pll_out("pll_p_out2", "pll_p_out2_div", |
1220 | clk_base + PLLP_OUTA, 17, 16, | |
1221 | CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, | |
1222 | &pll_div_lock); | |
c9e2d69a | 1223 | clks[TEGRA114_CLK_PLL_P_OUT2] = clk; |
2cb5efef PDS |
1224 | |
1225 | /* PLLP_OUT3 */ | |
1226 | clk = tegra_clk_register_divider("pll_p_out3_div", "pll_p", | |
1227 | clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED | | |
1228 | TEGRA_DIVIDER_ROUND_UP, 8, 8, 1, &pll_div_lock); | |
1229 | clk = tegra_clk_register_pll_out("pll_p_out3", "pll_p_out3_div", | |
1230 | clk_base + PLLP_OUTB, 1, 0, | |
1231 | CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, | |
1232 | &pll_div_lock); | |
c9e2d69a | 1233 | clks[TEGRA114_CLK_PLL_P_OUT3] = clk; |
2cb5efef PDS |
1234 | |
1235 | /* PLLP_OUT4 */ | |
1236 | clk = tegra_clk_register_divider("pll_p_out4_div", "pll_p", | |
1237 | clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED | | |
1238 | TEGRA_DIVIDER_ROUND_UP, 24, 8, 1, | |
1239 | &pll_div_lock); | |
1240 | clk = tegra_clk_register_pll_out("pll_p_out4", "pll_p_out4_div", | |
1241 | clk_base + PLLP_OUTB, 17, 16, | |
1242 | CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, | |
1243 | &pll_div_lock); | |
c9e2d69a | 1244 | clks[TEGRA114_CLK_PLL_P_OUT4] = clk; |
2cb5efef PDS |
1245 | |
1246 | /* PLLM */ | |
2cb5efef | 1247 | clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc, |
ebe142b2 PDS |
1248 | CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE, |
1249 | &pll_m_params, NULL); | |
c9e2d69a | 1250 | clks[TEGRA114_CLK_PLL_M] = clk; |
2cb5efef PDS |
1251 | |
1252 | /* PLLM_OUT1 */ | |
1253 | clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m", | |
1254 | clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, | |
1255 | 8, 8, 1, NULL); | |
1256 | clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div", | |
1257 | clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED | | |
1258 | CLK_SET_RATE_PARENT, 0, NULL); | |
c9e2d69a | 1259 | clks[TEGRA114_CLK_PLL_M_OUT1] = clk; |
2cb5efef PDS |
1260 | |
1261 | /* PLLM_UD */ | |
1262 | clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m", | |
1263 | CLK_SET_RATE_PARENT, 1, 1); | |
1264 | ||
1265 | /* PLLX */ | |
04edb099 | 1266 | clk = tegra_clk_register_pllxc("pll_x", "pll_ref", clk_base, |
ebe142b2 | 1267 | pmc, CLK_IGNORE_UNUSED, &pll_x_params, NULL); |
04edb099 | 1268 | clks[TEGRA114_CLK_PLL_X] = clk; |
2cb5efef PDS |
1269 | |
1270 | /* PLLX_OUT0 */ | |
1271 | clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x", | |
1272 | CLK_SET_RATE_PARENT, 1, 2); | |
c9e2d69a | 1273 | clks[TEGRA114_CLK_PLL_X_OUT0] = clk; |
2cb5efef PDS |
1274 | |
1275 | /* PLLU */ | |
1276 | val = readl(clk_base + pll_u_params.base_reg); | |
1277 | val &= ~BIT(24); /* disable PLLU_OVERRIDE */ | |
1278 | writel(val, clk_base + pll_u_params.base_reg); | |
1279 | ||
1280 | clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc, 0, | |
ebe142b2 | 1281 | &pll_u_params, &pll_u_lock); |
c9e2d69a | 1282 | clks[TEGRA114_CLK_PLL_U] = clk; |
2cb5efef PDS |
1283 | |
1284 | tegra114_utmi_param_configure(clk_base); | |
1285 | ||
1286 | /* PLLU_480M */ | |
1287 | clk = clk_register_gate(NULL, "pll_u_480M", "pll_u", | |
1288 | CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, | |
1289 | 22, 0, &pll_u_lock); | |
c9e2d69a | 1290 | clks[TEGRA114_CLK_PLL_U_480M] = clk; |
2cb5efef PDS |
1291 | |
1292 | /* PLLU_60M */ | |
1293 | clk = clk_register_fixed_factor(NULL, "pll_u_60M", "pll_u", | |
1294 | CLK_SET_RATE_PARENT, 1, 8); | |
c9e2d69a | 1295 | clks[TEGRA114_CLK_PLL_U_60M] = clk; |
2cb5efef PDS |
1296 | |
1297 | /* PLLU_48M */ | |
1298 | clk = clk_register_fixed_factor(NULL, "pll_u_48M", "pll_u", | |
1299 | CLK_SET_RATE_PARENT, 1, 10); | |
c9e2d69a | 1300 | clks[TEGRA114_CLK_PLL_U_48M] = clk; |
2cb5efef PDS |
1301 | |
1302 | /* PLLU_12M */ | |
1303 | clk = clk_register_fixed_factor(NULL, "pll_u_12M", "pll_u", | |
1304 | CLK_SET_RATE_PARENT, 1, 40); | |
c9e2d69a | 1305 | clks[TEGRA114_CLK_PLL_U_12M] = clk; |
2cb5efef PDS |
1306 | |
1307 | /* PLLD */ | |
1308 | clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0, | |
ebe142b2 | 1309 | &pll_d_params, &pll_d_lock); |
c9e2d69a | 1310 | clks[TEGRA114_CLK_PLL_D] = clk; |
2cb5efef PDS |
1311 | |
1312 | /* PLLD_OUT0 */ | |
1313 | clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d", | |
1314 | CLK_SET_RATE_PARENT, 1, 2); | |
c9e2d69a | 1315 | clks[TEGRA114_CLK_PLL_D_OUT0] = clk; |
2cb5efef PDS |
1316 | |
1317 | /* PLLD2 */ | |
1318 | clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc, 0, | |
ebe142b2 | 1319 | &pll_d2_params, &pll_d2_lock); |
c9e2d69a | 1320 | clks[TEGRA114_CLK_PLL_D2] = clk; |
2cb5efef PDS |
1321 | |
1322 | /* PLLD2_OUT0 */ | |
1323 | clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2", | |
1324 | CLK_SET_RATE_PARENT, 1, 2); | |
c9e2d69a | 1325 | clks[TEGRA114_CLK_PLL_D2_OUT0] = clk; |
2cb5efef PDS |
1326 | |
1327 | /* PLLA */ | |
1328 | clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, pmc, 0, | |
ebe142b2 | 1329 | &pll_a_params, NULL); |
c9e2d69a | 1330 | clks[TEGRA114_CLK_PLL_A] = clk; |
2cb5efef PDS |
1331 | |
1332 | /* PLLA_OUT0 */ | |
1333 | clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a", | |
1334 | clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP, | |
1335 | 8, 8, 1, NULL); | |
1336 | clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div", | |
1337 | clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED | | |
1338 | CLK_SET_RATE_PARENT, 0, NULL); | |
c9e2d69a | 1339 | clks[TEGRA114_CLK_PLL_A_OUT0] = clk; |
2cb5efef PDS |
1340 | |
1341 | /* PLLRE */ | |
2cb5efef | 1342 | clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc, |
ebe142b2 | 1343 | 0, &pll_re_vco_params, &pll_re_lock, pll_ref_freq); |
c9e2d69a | 1344 | clks[TEGRA114_CLK_PLL_RE_VCO] = clk; |
2cb5efef PDS |
1345 | |
1346 | clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0, | |
1347 | clk_base + PLLRE_BASE, 16, 4, 0, | |
1348 | pll_re_div_table, &pll_re_lock); | |
c9e2d69a | 1349 | clks[TEGRA114_CLK_PLL_RE_OUT] = clk; |
2cb5efef PDS |
1350 | |
1351 | /* PLLE */ | |
8e9cc80a | 1352 | clk = tegra_clk_register_plle_tegra114("pll_e_out0", "pll_ref", |
ebe142b2 | 1353 | clk_base, 0, &pll_e_params, NULL); |
c9e2d69a | 1354 | clks[TEGRA114_CLK_PLL_E_OUT0] = clk; |
2cb5efef PDS |
1355 | } |
1356 | ||
1357 | static const char *mux_audio_sync_clk[] = { "spdif_in_sync", "i2s0_sync", | |
1358 | "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync", | |
1359 | }; | |
1360 | ||
1361 | static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2", | |
1362 | "clk_m_div4", "extern1", | |
1363 | }; | |
1364 | ||
1365 | static const char *clk_out2_parents[] = { "clk_m", "clk_m_div2", | |
1366 | "clk_m_div4", "extern2", | |
1367 | }; | |
1368 | ||
1369 | static const char *clk_out3_parents[] = { "clk_m", "clk_m_div2", | |
1370 | "clk_m_div4", "extern3", | |
1371 | }; | |
1372 | ||
1373 | static void __init tegra114_audio_clk_init(void __iomem *clk_base) | |
1374 | { | |
1375 | struct clk *clk; | |
1376 | ||
1377 | /* spdif_in_sync */ | |
1378 | clk = tegra_clk_register_sync_source("spdif_in_sync", 24000000, | |
1379 | 24000000); | |
c9e2d69a | 1380 | clks[TEGRA114_CLK_SPDIF_IN_SYNC] = clk; |
2cb5efef PDS |
1381 | |
1382 | /* i2s0_sync */ | |
1383 | clk = tegra_clk_register_sync_source("i2s0_sync", 24000000, 24000000); | |
c9e2d69a | 1384 | clks[TEGRA114_CLK_I2S0_SYNC] = clk; |
2cb5efef PDS |
1385 | |
1386 | /* i2s1_sync */ | |
1387 | clk = tegra_clk_register_sync_source("i2s1_sync", 24000000, 24000000); | |
c9e2d69a | 1388 | clks[TEGRA114_CLK_I2S1_SYNC] = clk; |
2cb5efef PDS |
1389 | |
1390 | /* i2s2_sync */ | |
1391 | clk = tegra_clk_register_sync_source("i2s2_sync", 24000000, 24000000); | |
c9e2d69a | 1392 | clks[TEGRA114_CLK_I2S2_SYNC] = clk; |
2cb5efef PDS |
1393 | |
1394 | /* i2s3_sync */ | |
1395 | clk = tegra_clk_register_sync_source("i2s3_sync", 24000000, 24000000); | |
c9e2d69a | 1396 | clks[TEGRA114_CLK_I2S3_SYNC] = clk; |
2cb5efef PDS |
1397 | |
1398 | /* i2s4_sync */ | |
1399 | clk = tegra_clk_register_sync_source("i2s4_sync", 24000000, 24000000); | |
c9e2d69a | 1400 | clks[TEGRA114_CLK_I2S4_SYNC] = clk; |
2cb5efef PDS |
1401 | |
1402 | /* vimclk_sync */ | |
1403 | clk = tegra_clk_register_sync_source("vimclk_sync", 24000000, 24000000); | |
c9e2d69a | 1404 | clks[TEGRA114_CLK_VIMCLK_SYNC] = clk; |
2cb5efef PDS |
1405 | |
1406 | /* audio0 */ | |
1407 | clk = clk_register_mux(NULL, "audio0_mux", mux_audio_sync_clk, | |
819c1de3 JH |
1408 | ARRAY_SIZE(mux_audio_sync_clk), |
1409 | CLK_SET_RATE_NO_REPARENT, | |
2cb5efef PDS |
1410 | clk_base + AUDIO_SYNC_CLK_I2S0, 0, 3, 0, |
1411 | NULL); | |
c9e2d69a | 1412 | clks[TEGRA114_CLK_AUDIO0_MUX] = clk; |
2cb5efef PDS |
1413 | clk = clk_register_gate(NULL, "audio0", "audio0_mux", 0, |
1414 | clk_base + AUDIO_SYNC_CLK_I2S0, 4, | |
1415 | CLK_GATE_SET_TO_DISABLE, NULL); | |
c9e2d69a | 1416 | clks[TEGRA114_CLK_AUDIO0] = clk; |
2cb5efef PDS |
1417 | |
1418 | /* audio1 */ | |
1419 | clk = clk_register_mux(NULL, "audio1_mux", mux_audio_sync_clk, | |
819c1de3 JH |
1420 | ARRAY_SIZE(mux_audio_sync_clk), |
1421 | CLK_SET_RATE_NO_REPARENT, | |
2cb5efef PDS |
1422 | clk_base + AUDIO_SYNC_CLK_I2S1, 0, 3, 0, |
1423 | NULL); | |
c9e2d69a | 1424 | clks[TEGRA114_CLK_AUDIO1_MUX] = clk; |
2cb5efef PDS |
1425 | clk = clk_register_gate(NULL, "audio1", "audio1_mux", 0, |
1426 | clk_base + AUDIO_SYNC_CLK_I2S1, 4, | |
1427 | CLK_GATE_SET_TO_DISABLE, NULL); | |
c9e2d69a | 1428 | clks[TEGRA114_CLK_AUDIO1] = clk; |
2cb5efef PDS |
1429 | |
1430 | /* audio2 */ | |
1431 | clk = clk_register_mux(NULL, "audio2_mux", mux_audio_sync_clk, | |
819c1de3 JH |
1432 | ARRAY_SIZE(mux_audio_sync_clk), |
1433 | CLK_SET_RATE_NO_REPARENT, | |
2cb5efef PDS |
1434 | clk_base + AUDIO_SYNC_CLK_I2S2, 0, 3, 0, |
1435 | NULL); | |
c9e2d69a | 1436 | clks[TEGRA114_CLK_AUDIO2_MUX] = clk; |
2cb5efef PDS |
1437 | clk = clk_register_gate(NULL, "audio2", "audio2_mux", 0, |
1438 | clk_base + AUDIO_SYNC_CLK_I2S2, 4, | |
1439 | CLK_GATE_SET_TO_DISABLE, NULL); | |
c9e2d69a | 1440 | clks[TEGRA114_CLK_AUDIO2] = clk; |
2cb5efef PDS |
1441 | |
1442 | /* audio3 */ | |
1443 | clk = clk_register_mux(NULL, "audio3_mux", mux_audio_sync_clk, | |
819c1de3 JH |
1444 | ARRAY_SIZE(mux_audio_sync_clk), |
1445 | CLK_SET_RATE_NO_REPARENT, | |
2cb5efef PDS |
1446 | clk_base + AUDIO_SYNC_CLK_I2S3, 0, 3, 0, |
1447 | NULL); | |
c9e2d69a | 1448 | clks[TEGRA114_CLK_AUDIO3_MUX] = clk; |
2cb5efef PDS |
1449 | clk = clk_register_gate(NULL, "audio3", "audio3_mux", 0, |
1450 | clk_base + AUDIO_SYNC_CLK_I2S3, 4, | |
1451 | CLK_GATE_SET_TO_DISABLE, NULL); | |
c9e2d69a | 1452 | clks[TEGRA114_CLK_AUDIO3] = clk; |
2cb5efef PDS |
1453 | |
1454 | /* audio4 */ | |
1455 | clk = clk_register_mux(NULL, "audio4_mux", mux_audio_sync_clk, | |
819c1de3 JH |
1456 | ARRAY_SIZE(mux_audio_sync_clk), |
1457 | CLK_SET_RATE_NO_REPARENT, | |
2cb5efef PDS |
1458 | clk_base + AUDIO_SYNC_CLK_I2S4, 0, 3, 0, |
1459 | NULL); | |
c9e2d69a | 1460 | clks[TEGRA114_CLK_AUDIO4_MUX] = clk; |
2cb5efef PDS |
1461 | clk = clk_register_gate(NULL, "audio4", "audio4_mux", 0, |
1462 | clk_base + AUDIO_SYNC_CLK_I2S4, 4, | |
1463 | CLK_GATE_SET_TO_DISABLE, NULL); | |
c9e2d69a | 1464 | clks[TEGRA114_CLK_AUDIO4] = clk; |
2cb5efef PDS |
1465 | |
1466 | /* spdif */ | |
1467 | clk = clk_register_mux(NULL, "spdif_mux", mux_audio_sync_clk, | |
819c1de3 JH |
1468 | ARRAY_SIZE(mux_audio_sync_clk), |
1469 | CLK_SET_RATE_NO_REPARENT, | |
2cb5efef PDS |
1470 | clk_base + AUDIO_SYNC_CLK_SPDIF, 0, 3, 0, |
1471 | NULL); | |
c9e2d69a | 1472 | clks[TEGRA114_CLK_SPDIF_MUX] = clk; |
2cb5efef PDS |
1473 | clk = clk_register_gate(NULL, "spdif", "spdif_mux", 0, |
1474 | clk_base + AUDIO_SYNC_CLK_SPDIF, 4, | |
1475 | CLK_GATE_SET_TO_DISABLE, NULL); | |
c9e2d69a | 1476 | clks[TEGRA114_CLK_SPDIF] = clk; |
2cb5efef PDS |
1477 | |
1478 | /* audio0_2x */ | |
1479 | clk = clk_register_fixed_factor(NULL, "audio0_doubler", "audio0", | |
1480 | CLK_SET_RATE_PARENT, 2, 1); | |
1481 | clk = tegra_clk_register_divider("audio0_div", "audio0_doubler", | |
1482 | clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 24, 1, | |
1483 | 0, &clk_doubler_lock); | |
1484 | clk = tegra_clk_register_periph_gate("audio0_2x", "audio0_div", | |
1485 | TEGRA_PERIPH_NO_RESET, clk_base, | |
d5ff89a8 | 1486 | CLK_SET_RATE_PARENT, 113, |
2cb5efef | 1487 | periph_clk_enb_refcnt); |
c9e2d69a | 1488 | clks[TEGRA114_CLK_AUDIO0_2X] = clk; |
2cb5efef PDS |
1489 | |
1490 | /* audio1_2x */ | |
1491 | clk = clk_register_fixed_factor(NULL, "audio1_doubler", "audio1", | |
1492 | CLK_SET_RATE_PARENT, 2, 1); | |
1493 | clk = tegra_clk_register_divider("audio1_div", "audio1_doubler", | |
1494 | clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 25, 1, | |
1495 | 0, &clk_doubler_lock); | |
1496 | clk = tegra_clk_register_periph_gate("audio1_2x", "audio1_div", | |
1497 | TEGRA_PERIPH_NO_RESET, clk_base, | |
d5ff89a8 | 1498 | CLK_SET_RATE_PARENT, 114, |
2cb5efef | 1499 | periph_clk_enb_refcnt); |
c9e2d69a | 1500 | clks[TEGRA114_CLK_AUDIO1_2X] = clk; |
2cb5efef PDS |
1501 | |
1502 | /* audio2_2x */ | |
1503 | clk = clk_register_fixed_factor(NULL, "audio2_doubler", "audio2", | |
1504 | CLK_SET_RATE_PARENT, 2, 1); | |
1505 | clk = tegra_clk_register_divider("audio2_div", "audio2_doubler", | |
1506 | clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 26, 1, | |
1507 | 0, &clk_doubler_lock); | |
1508 | clk = tegra_clk_register_periph_gate("audio2_2x", "audio2_div", | |
1509 | TEGRA_PERIPH_NO_RESET, clk_base, | |
d5ff89a8 | 1510 | CLK_SET_RATE_PARENT, 115, |
2cb5efef | 1511 | periph_clk_enb_refcnt); |
c9e2d69a | 1512 | clks[TEGRA114_CLK_AUDIO2_2X] = clk; |
2cb5efef PDS |
1513 | |
1514 | /* audio3_2x */ | |
1515 | clk = clk_register_fixed_factor(NULL, "audio3_doubler", "audio3", | |
1516 | CLK_SET_RATE_PARENT, 2, 1); | |
1517 | clk = tegra_clk_register_divider("audio3_div", "audio3_doubler", | |
1518 | clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 27, 1, | |
1519 | 0, &clk_doubler_lock); | |
1520 | clk = tegra_clk_register_periph_gate("audio3_2x", "audio3_div", | |
1521 | TEGRA_PERIPH_NO_RESET, clk_base, | |
d5ff89a8 | 1522 | CLK_SET_RATE_PARENT, 116, |
2cb5efef | 1523 | periph_clk_enb_refcnt); |
c9e2d69a | 1524 | clks[TEGRA114_CLK_AUDIO3_2X] = clk; |
2cb5efef PDS |
1525 | |
1526 | /* audio4_2x */ | |
1527 | clk = clk_register_fixed_factor(NULL, "audio4_doubler", "audio4", | |
1528 | CLK_SET_RATE_PARENT, 2, 1); | |
1529 | clk = tegra_clk_register_divider("audio4_div", "audio4_doubler", | |
1530 | clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 28, 1, | |
1531 | 0, &clk_doubler_lock); | |
1532 | clk = tegra_clk_register_periph_gate("audio4_2x", "audio4_div", | |
1533 | TEGRA_PERIPH_NO_RESET, clk_base, | |
d5ff89a8 | 1534 | CLK_SET_RATE_PARENT, 117, |
2cb5efef | 1535 | periph_clk_enb_refcnt); |
c9e2d69a | 1536 | clks[TEGRA114_CLK_AUDIO4_2X] = clk; |
2cb5efef PDS |
1537 | |
1538 | /* spdif_2x */ | |
1539 | clk = clk_register_fixed_factor(NULL, "spdif_doubler", "spdif", | |
1540 | CLK_SET_RATE_PARENT, 2, 1); | |
1541 | clk = tegra_clk_register_divider("spdif_div", "spdif_doubler", | |
1542 | clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 29, 1, | |
1543 | 0, &clk_doubler_lock); | |
1544 | clk = tegra_clk_register_periph_gate("spdif_2x", "spdif_div", | |
1545 | TEGRA_PERIPH_NO_RESET, clk_base, | |
1546 | CLK_SET_RATE_PARENT, 118, | |
d5ff89a8 | 1547 | periph_clk_enb_refcnt); |
c9e2d69a | 1548 | clks[TEGRA114_CLK_SPDIF_2X] = clk; |
2cb5efef PDS |
1549 | } |
1550 | ||
1551 | static void __init tegra114_pmc_clk_init(void __iomem *pmc_base) | |
1552 | { | |
1553 | struct clk *clk; | |
1554 | ||
1555 | /* clk_out_1 */ | |
1556 | clk = clk_register_mux(NULL, "clk_out_1_mux", clk_out1_parents, | |
819c1de3 JH |
1557 | ARRAY_SIZE(clk_out1_parents), |
1558 | CLK_SET_RATE_NO_REPARENT, | |
2cb5efef PDS |
1559 | pmc_base + PMC_CLK_OUT_CNTRL, 6, 3, 0, |
1560 | &clk_out_lock); | |
c9e2d69a | 1561 | clks[TEGRA114_CLK_CLK_OUT_1_MUX] = clk; |
2cb5efef PDS |
1562 | clk = clk_register_gate(NULL, "clk_out_1", "clk_out_1_mux", 0, |
1563 | pmc_base + PMC_CLK_OUT_CNTRL, 2, 0, | |
1564 | &clk_out_lock); | |
c9e2d69a | 1565 | clks[TEGRA114_CLK_CLK_OUT_1] = clk; |
2cb5efef PDS |
1566 | |
1567 | /* clk_out_2 */ | |
1568 | clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents, | |
819c1de3 JH |
1569 | ARRAY_SIZE(clk_out2_parents), |
1570 | CLK_SET_RATE_NO_REPARENT, | |
2cb5efef PDS |
1571 | pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0, |
1572 | &clk_out_lock); | |
c9e2d69a | 1573 | clks[TEGRA114_CLK_CLK_OUT_2_MUX] = clk; |
2cb5efef PDS |
1574 | clk = clk_register_gate(NULL, "clk_out_2", "clk_out_2_mux", 0, |
1575 | pmc_base + PMC_CLK_OUT_CNTRL, 10, 0, | |
1576 | &clk_out_lock); | |
c9e2d69a | 1577 | clks[TEGRA114_CLK_CLK_OUT_2] = clk; |
2cb5efef PDS |
1578 | |
1579 | /* clk_out_3 */ | |
1580 | clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents, | |
819c1de3 JH |
1581 | ARRAY_SIZE(clk_out3_parents), |
1582 | CLK_SET_RATE_NO_REPARENT, | |
2cb5efef PDS |
1583 | pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0, |
1584 | &clk_out_lock); | |
c9e2d69a | 1585 | clks[TEGRA114_CLK_CLK_OUT_3_MUX] = clk; |
2cb5efef PDS |
1586 | clk = clk_register_gate(NULL, "clk_out_3", "clk_out_3_mux", 0, |
1587 | pmc_base + PMC_CLK_OUT_CNTRL, 18, 0, | |
1588 | &clk_out_lock); | |
c9e2d69a | 1589 | clks[TEGRA114_CLK_CLK_OUT_3] = clk; |
2cb5efef PDS |
1590 | |
1591 | /* blink */ | |
9139227d AC |
1592 | /* clear the blink timer register to directly output clk_32k */ |
1593 | writel_relaxed(0, pmc_base + PMC_BLINK_TIMER); | |
2cb5efef PDS |
1594 | clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0, |
1595 | pmc_base + PMC_DPD_PADS_ORIDE, | |
1596 | PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL); | |
1597 | clk = clk_register_gate(NULL, "blink", "blink_override", 0, | |
1598 | pmc_base + PMC_CTRL, | |
1599 | PMC_CTRL_BLINK_ENB, 0, NULL); | |
c9e2d69a | 1600 | clks[TEGRA114_CLK_BLINK] = clk; |
2cb5efef PDS |
1601 | |
1602 | } | |
1603 | ||
1604 | static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4", | |
29b09447 | 1605 | "pll_p", "pll_p_out2", "unused", |
2cb5efef PDS |
1606 | "clk_32k", "pll_m_out1" }; |
1607 | ||
1608 | static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", | |
1609 | "pll_p", "pll_p_out4", "unused", | |
1610 | "unused", "pll_x" }; | |
1611 | ||
1612 | static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", | |
1613 | "pll_p", "pll_p_out4", "unused", | |
1614 | "unused", "pll_x", "pll_x_out0" }; | |
1615 | ||
1616 | static void __init tegra114_super_clk_init(void __iomem *clk_base) | |
1617 | { | |
1618 | struct clk *clk; | |
1619 | ||
1620 | /* CCLKG */ | |
1621 | clk = tegra_clk_register_super_mux("cclk_g", cclk_g_parents, | |
1622 | ARRAY_SIZE(cclk_g_parents), | |
1623 | CLK_SET_RATE_PARENT, | |
1624 | clk_base + CCLKG_BURST_POLICY, | |
1625 | 0, 4, 0, 0, NULL); | |
c9e2d69a | 1626 | clks[TEGRA114_CLK_CCLK_G] = clk; |
2cb5efef PDS |
1627 | |
1628 | /* CCLKLP */ | |
1629 | clk = tegra_clk_register_super_mux("cclk_lp", cclk_lp_parents, | |
1630 | ARRAY_SIZE(cclk_lp_parents), | |
1631 | CLK_SET_RATE_PARENT, | |
1632 | clk_base + CCLKLP_BURST_POLICY, | |
1633 | 0, 4, 8, 9, NULL); | |
c9e2d69a | 1634 | clks[TEGRA114_CLK_CCLK_LP] = clk; |
2cb5efef PDS |
1635 | |
1636 | /* SCLK */ | |
1637 | clk = tegra_clk_register_super_mux("sclk", sclk_parents, | |
1638 | ARRAY_SIZE(sclk_parents), | |
1639 | CLK_SET_RATE_PARENT, | |
1640 | clk_base + SCLK_BURST_POLICY, | |
1641 | 0, 4, 0, 0, NULL); | |
c9e2d69a | 1642 | clks[TEGRA114_CLK_SCLK] = clk; |
2cb5efef PDS |
1643 | |
1644 | /* HCLK */ | |
1645 | clk = clk_register_divider(NULL, "hclk_div", "sclk", 0, | |
1646 | clk_base + SYSTEM_CLK_RATE, 4, 2, 0, | |
1647 | &sysrate_lock); | |
1648 | clk = clk_register_gate(NULL, "hclk", "hclk_div", CLK_SET_RATE_PARENT | | |
1649 | CLK_IGNORE_UNUSED, clk_base + SYSTEM_CLK_RATE, | |
1650 | 7, CLK_GATE_SET_TO_DISABLE, &sysrate_lock); | |
c9e2d69a | 1651 | clks[TEGRA114_CLK_HCLK] = clk; |
2cb5efef PDS |
1652 | |
1653 | /* PCLK */ | |
1654 | clk = clk_register_divider(NULL, "pclk_div", "hclk", 0, | |
1655 | clk_base + SYSTEM_CLK_RATE, 0, 2, 0, | |
1656 | &sysrate_lock); | |
1657 | clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT | | |
1658 | CLK_IGNORE_UNUSED, clk_base + SYSTEM_CLK_RATE, | |
1659 | 3, CLK_GATE_SET_TO_DISABLE, &sysrate_lock); | |
c9e2d69a | 1660 | clks[TEGRA114_CLK_PCLK] = clk; |
2cb5efef PDS |
1661 | } |
1662 | ||
1663 | static struct tegra_periph_init_data tegra_periph_clk_list[] = { | |
73d37e4c PDS |
1664 | TEGRA_INIT_DATA_MUX("i2s0", mux_pllaout0_audio0_2x_pllp_clkm, CLK_SOURCE_I2S0, 30, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_I2S0), |
1665 | TEGRA_INIT_DATA_MUX("i2s1", mux_pllaout0_audio1_2x_pllp_clkm, CLK_SOURCE_I2S1, 11, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_I2S1), | |
1666 | TEGRA_INIT_DATA_MUX("i2s2", mux_pllaout0_audio2_2x_pllp_clkm, CLK_SOURCE_I2S2, 18, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_I2S2), | |
1667 | TEGRA_INIT_DATA_MUX("i2s3", mux_pllaout0_audio3_2x_pllp_clkm, CLK_SOURCE_I2S3, 101, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_I2S3), | |
1668 | TEGRA_INIT_DATA_MUX("i2s4", mux_pllaout0_audio4_2x_pllp_clkm, CLK_SOURCE_I2S4, 102, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_I2S4), | |
1669 | TEGRA_INIT_DATA_MUX("spdif_out", mux_pllaout0_audio_2x_pllp_clkm, CLK_SOURCE_SPDIF_OUT, 10, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SPDIF_OUT), | |
1670 | TEGRA_INIT_DATA_MUX("spdif_in", mux_pllp_pllc_pllm, CLK_SOURCE_SPDIF_IN, 10, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SPDIF_IN), | |
1671 | TEGRA_INIT_DATA_MUX("pwm", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_PWM, 17, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_PWM), | |
1672 | TEGRA_INIT_DATA_MUX("adx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX, 154, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_ADX), | |
1673 | TEGRA_INIT_DATA_MUX("amx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX, 153, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_AMX), | |
1674 | TEGRA_INIT_DATA_MUX("hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA, 125, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_HDA), | |
1675 | TEGRA_INIT_DATA_MUX("hda2codec_2x", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_HDA2CODEC_2X), | |
1676 | TEGRA_INIT_DATA_MUX8("sbc1", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC1, 41, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SBC1), | |
1677 | TEGRA_INIT_DATA_MUX8("sbc2", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC2, 44, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SBC2), | |
1678 | TEGRA_INIT_DATA_MUX8("sbc3", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC3, 46, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SBC3), | |
1679 | TEGRA_INIT_DATA_MUX8("sbc4", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC4, 68, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SBC4), | |
1680 | TEGRA_INIT_DATA_MUX8("sbc5", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC5, 104, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SBC5), | |
1681 | TEGRA_INIT_DATA_MUX8("sbc6", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC6, 105, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SBC6), | |
1682 | TEGRA_INIT_DATA_MUX8("ndflash", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDFLASH, 13, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_NDSPEED), | |
1683 | TEGRA_INIT_DATA_MUX8("ndspeed", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDSPEED, 80, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_NDSPEED), | |
1684 | TEGRA_INIT_DATA_MUX("vfir", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VFIR, 7, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_VFIR), | |
1685 | TEGRA_INIT_DATA_MUX("sdmmc1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC1, 14, 0, TEGRA114_CLK_SDMMC1), | |
1686 | TEGRA_INIT_DATA_MUX("sdmmc2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC2, 9, 0, TEGRA114_CLK_SDMMC2), | |
1687 | TEGRA_INIT_DATA_MUX("sdmmc3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC3, 69, 0, TEGRA114_CLK_SDMMC3), | |
1688 | TEGRA_INIT_DATA_MUX("sdmmc4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC4, 15, 0, TEGRA114_CLK_SDMMC4), | |
1689 | TEGRA_INIT_DATA_INT8("vde", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_VDE, 61, 0, TEGRA114_CLK_VDE), | |
1690 | TEGRA_INIT_DATA_MUX_FLAGS("csite", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_CSITE, 73, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_CSITE, CLK_IGNORE_UNUSED), | |
1691 | TEGRA_INIT_DATA_MUX("la", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_LA, 76, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_LA), | |
1692 | TEGRA_INIT_DATA_MUX("trace", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_TRACE, 77, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_TRACE), | |
1693 | TEGRA_INIT_DATA_MUX("owr", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_OWR, 71, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_OWR), | |
1694 | TEGRA_INIT_DATA_MUX("nor", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NOR, 42, 0, TEGRA114_CLK_NOR), | |
1695 | TEGRA_INIT_DATA_MUX("mipi", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_MIPI, 50, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_MIPI), | |
1696 | TEGRA_INIT_DATA_I2C("i2c1", mux_pllp_clkm, CLK_SOURCE_I2C1, 12, TEGRA114_CLK_I2C1), | |
1697 | TEGRA_INIT_DATA_I2C("i2c2", mux_pllp_clkm, CLK_SOURCE_I2C2, 54, TEGRA114_CLK_I2C2), | |
1698 | TEGRA_INIT_DATA_I2C("i2c3", mux_pllp_clkm, CLK_SOURCE_I2C3, 67, TEGRA114_CLK_I2C3), | |
1699 | TEGRA_INIT_DATA_I2C("i2c4", mux_pllp_clkm, CLK_SOURCE_I2C4, 103, TEGRA114_CLK_I2C4), | |
1700 | TEGRA_INIT_DATA_I2C("i2c5", mux_pllp_clkm, CLK_SOURCE_I2C5, 47, TEGRA114_CLK_I2C5), | |
1701 | TEGRA_INIT_DATA_UART("uarta", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTA, 6, TEGRA114_CLK_UARTA), | |
1702 | TEGRA_INIT_DATA_UART("uartb", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTB, 7, TEGRA114_CLK_UARTB), | |
1703 | TEGRA_INIT_DATA_UART("uartc", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTC, 55, TEGRA114_CLK_UARTC), | |
1704 | TEGRA_INIT_DATA_UART("uartd", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTD, 65, TEGRA114_CLK_UARTD), | |
1705 | TEGRA_INIT_DATA_INT8("3d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_3D, 24, 0, TEGRA114_CLK_GR3D), | |
1706 | TEGRA_INIT_DATA_INT8("2d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_2D, 21, 0, TEGRA114_CLK_GR2D), | |
1707 | TEGRA_INIT_DATA_MUX("vi_sensor", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, TEGRA114_CLK_VI_SENSOR), | |
1708 | TEGRA_INIT_DATA_INT8("vi", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI, 20, 0, TEGRA114_CLK_VI), | |
1709 | TEGRA_INIT_DATA_INT8("epp", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_EPP, 19, 0, TEGRA114_CLK_EPP), | |
1710 | TEGRA_INIT_DATA_INT8("msenc", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_MSENC, 91, TEGRA_PERIPH_WAR_1005168, TEGRA114_CLK_MSENC), | |
1711 | TEGRA_INIT_DATA_INT8("tsec", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_TSEC, 83, 0, TEGRA114_CLK_TSEC), | |
1712 | TEGRA_INIT_DATA_INT8("host1x", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_HOST1X, 28, 0, TEGRA114_CLK_HOST1X), | |
1713 | TEGRA_INIT_DATA_MUX8("hdmi", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_HDMI, 51, 0, TEGRA114_CLK_HDMI), | |
1714 | TEGRA_INIT_DATA_MUX("cilab", mux_pllp_pllc_clkm, CLK_SOURCE_CILAB, 144, 0, TEGRA114_CLK_CILAB), | |
1715 | TEGRA_INIT_DATA_MUX("cilcd", mux_pllp_pllc_clkm, CLK_SOURCE_CILCD, 145, 0, TEGRA114_CLK_CILCD), | |
1716 | TEGRA_INIT_DATA_MUX("cile", mux_pllp_pllc_clkm, CLK_SOURCE_CILE, 146, 0, TEGRA114_CLK_CILE), | |
1717 | TEGRA_INIT_DATA_MUX("dsialp", mux_pllp_pllc_clkm, CLK_SOURCE_DSIALP, 147, 0, TEGRA114_CLK_DSIALP), | |
1718 | TEGRA_INIT_DATA_MUX("dsiblp", mux_pllp_pllc_clkm, CLK_SOURCE_DSIBLP, 148, 0, TEGRA114_CLK_DSIBLP), | |
1719 | TEGRA_INIT_DATA_MUX("tsensor", mux_pllp_pllc_clkm_clk32, CLK_SOURCE_TSENSOR, 100, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_TSENSOR), | |
1720 | TEGRA_INIT_DATA_MUX("actmon", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_ACTMON, 119, 0, TEGRA114_CLK_ACTMON), | |
1721 | TEGRA_INIT_DATA_MUX8("extern1", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN1, 120, 0, TEGRA114_CLK_EXTERN1), | |
1722 | TEGRA_INIT_DATA_MUX8("extern2", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN2, 121, 0, TEGRA114_CLK_EXTERN2), | |
1723 | TEGRA_INIT_DATA_MUX8("extern3", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN3, 122, 0, TEGRA114_CLK_EXTERN3), | |
1724 | TEGRA_INIT_DATA_MUX("i2cslow", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_I2CSLOW, 81, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_I2CSLOW), | |
1725 | TEGRA_INIT_DATA_INT8("se", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SE, 127, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SE), | |
1726 | TEGRA_INIT_DATA_INT_FLAGS("mselect", mux_pllp_clkm, CLK_SOURCE_MSELECT, 99, 0, TEGRA114_CLK_MSELECT, CLK_IGNORE_UNUSED), | |
1727 | TEGRA_INIT_DATA_MUX("dfll_ref", mux_pllp_clkm, CLK_SOURCE_DFLL_REF, 155, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_DFLL_REF), | |
1728 | TEGRA_INIT_DATA_MUX("dfll_soc", mux_pllp_clkm, CLK_SOURCE_DFLL_SOC, 155, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_DFLL_SOC), | |
1729 | TEGRA_INIT_DATA_MUX8("soc_therm", mux_pllm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SOC_THERM), | |
1730 | TEGRA_INIT_DATA_XUSB("xusb_host_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, TEGRA114_CLK_XUSB_HOST_SRC), | |
1731 | TEGRA_INIT_DATA_XUSB("xusb_falcon_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, TEGRA_PERIPH_NO_RESET, TEGRA114_CLK_XUSB_FALCON_SRC), | |
1732 | TEGRA_INIT_DATA_XUSB("xusb_fs_src", mux_clkm_48M_pllp_480M, CLK_SOURCE_XUSB_FS_SRC, 143, TEGRA_PERIPH_NO_RESET, TEGRA114_CLK_XUSB_FS_SRC), | |
1733 | TEGRA_INIT_DATA_XUSB("xusb_ss_src", mux_clkm_pllre_clk32_480M_pllc_ref, CLK_SOURCE_XUSB_SS_SRC, 143, TEGRA_PERIPH_NO_RESET, TEGRA114_CLK_XUSB_SS_SRC), | |
1734 | TEGRA_INIT_DATA_XUSB("xusb_dev_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, TEGRA114_CLK_XUSB_DEV_SRC), | |
1735 | TEGRA_INIT_DATA_AUDIO("d_audio", CLK_SOURCE_D_AUDIO, 106, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_D_AUDIO), | |
1736 | TEGRA_INIT_DATA_AUDIO("dam0", CLK_SOURCE_DAM0, 108, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_DAM0), | |
1737 | TEGRA_INIT_DATA_AUDIO("dam1", CLK_SOURCE_DAM1, 109, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_DAM1), | |
1738 | TEGRA_INIT_DATA_AUDIO("dam2", CLK_SOURCE_DAM2, 110, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_DAM2), | |
2cb5efef PDS |
1739 | }; |
1740 | ||
1741 | static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = { | |
73d37e4c PDS |
1742 | TEGRA_INIT_DATA_NODIV("disp1", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP1, 29, 7, 27, 0, TEGRA114_CLK_DISP1), |
1743 | TEGRA_INIT_DATA_NODIV("disp2", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP2, 29, 7, 26, 0, TEGRA114_CLK_DISP2), | |
2cb5efef PDS |
1744 | }; |
1745 | ||
1746 | static __init void tegra114_periph_clk_init(void __iomem *clk_base) | |
1747 | { | |
1748 | struct tegra_periph_init_data *data; | |
1749 | struct clk *clk; | |
1750 | int i; | |
1751 | u32 val; | |
1752 | ||
1753 | /* apbdma */ | |
1754 | clk = tegra_clk_register_periph_gate("apbdma", "clk_m", 0, clk_base, | |
d5ff89a8 | 1755 | 0, 34, periph_clk_enb_refcnt); |
c9e2d69a | 1756 | clks[TEGRA114_CLK_APBDMA] = clk; |
2cb5efef PDS |
1757 | |
1758 | /* rtc */ | |
1759 | clk = tegra_clk_register_periph_gate("rtc", "clk_32k", | |
1760 | TEGRA_PERIPH_ON_APB | | |
1761 | TEGRA_PERIPH_NO_RESET, clk_base, | |
d5ff89a8 | 1762 | 0, 4, periph_clk_enb_refcnt); |
c9e2d69a | 1763 | clks[TEGRA114_CLK_RTC] = clk; |
2cb5efef PDS |
1764 | |
1765 | /* kbc */ | |
1766 | clk = tegra_clk_register_periph_gate("kbc", "clk_32k", | |
1767 | TEGRA_PERIPH_ON_APB | | |
1768 | TEGRA_PERIPH_NO_RESET, clk_base, | |
d5ff89a8 | 1769 | 0, 36, periph_clk_enb_refcnt); |
c9e2d69a | 1770 | clks[TEGRA114_CLK_KBC] = clk; |
2cb5efef PDS |
1771 | |
1772 | /* timer */ | |
1773 | clk = tegra_clk_register_periph_gate("timer", "clk_m", 0, clk_base, | |
d5ff89a8 | 1774 | 0, 5, periph_clk_enb_refcnt); |
c9e2d69a | 1775 | clks[TEGRA114_CLK_TIMER] = clk; |
2cb5efef PDS |
1776 | |
1777 | /* kfuse */ | |
1778 | clk = tegra_clk_register_periph_gate("kfuse", "clk_m", | |
1779 | TEGRA_PERIPH_ON_APB, clk_base, 0, 40, | |
d5ff89a8 | 1780 | periph_clk_enb_refcnt); |
c9e2d69a | 1781 | clks[TEGRA114_CLK_KFUSE] = clk; |
2cb5efef PDS |
1782 | |
1783 | /* fuse */ | |
1784 | clk = tegra_clk_register_periph_gate("fuse", "clk_m", | |
1785 | TEGRA_PERIPH_ON_APB, clk_base, 0, 39, | |
d5ff89a8 | 1786 | periph_clk_enb_refcnt); |
c9e2d69a | 1787 | clks[TEGRA114_CLK_FUSE] = clk; |
2cb5efef PDS |
1788 | |
1789 | /* fuse_burn */ | |
1790 | clk = tegra_clk_register_periph_gate("fuse_burn", "clk_m", | |
1791 | TEGRA_PERIPH_ON_APB, clk_base, 0, 39, | |
d5ff89a8 | 1792 | periph_clk_enb_refcnt); |
c9e2d69a | 1793 | clks[TEGRA114_CLK_FUSE_BURN] = clk; |
2cb5efef PDS |
1794 | |
1795 | /* apbif */ | |
1796 | clk = tegra_clk_register_periph_gate("apbif", "clk_m", | |
1797 | TEGRA_PERIPH_ON_APB, clk_base, 0, 107, | |
d5ff89a8 | 1798 | periph_clk_enb_refcnt); |
c9e2d69a | 1799 | clks[TEGRA114_CLK_APBIF] = clk; |
2cb5efef PDS |
1800 | |
1801 | /* hda2hdmi */ | |
1802 | clk = tegra_clk_register_periph_gate("hda2hdmi", "clk_m", | |
1803 | TEGRA_PERIPH_ON_APB, clk_base, 0, 128, | |
d5ff89a8 | 1804 | periph_clk_enb_refcnt); |
c9e2d69a | 1805 | clks[TEGRA114_CLK_HDA2HDMI] = clk; |
2cb5efef PDS |
1806 | |
1807 | /* vcp */ | |
1808 | clk = tegra_clk_register_periph_gate("vcp", "clk_m", 0, clk_base, 0, | |
d5ff89a8 | 1809 | 29, periph_clk_enb_refcnt); |
c9e2d69a | 1810 | clks[TEGRA114_CLK_VCP] = clk; |
2cb5efef PDS |
1811 | |
1812 | /* bsea */ | |
1813 | clk = tegra_clk_register_periph_gate("bsea", "clk_m", 0, clk_base, | |
d5ff89a8 | 1814 | 0, 62, periph_clk_enb_refcnt); |
c9e2d69a | 1815 | clks[TEGRA114_CLK_BSEA] = clk; |
2cb5efef PDS |
1816 | |
1817 | /* bsev */ | |
1818 | clk = tegra_clk_register_periph_gate("bsev", "clk_m", 0, clk_base, | |
d5ff89a8 | 1819 | 0, 63, periph_clk_enb_refcnt); |
c9e2d69a | 1820 | clks[TEGRA114_CLK_BSEV] = clk; |
2cb5efef PDS |
1821 | |
1822 | /* mipi-cal */ | |
1823 | clk = tegra_clk_register_periph_gate("mipi-cal", "clk_m", 0, clk_base, | |
d5ff89a8 | 1824 | 0, 56, periph_clk_enb_refcnt); |
c9e2d69a | 1825 | clks[TEGRA114_CLK_MIPI_CAL] = clk; |
2cb5efef PDS |
1826 | |
1827 | /* usbd */ | |
1828 | clk = tegra_clk_register_periph_gate("usbd", "clk_m", 0, clk_base, | |
d5ff89a8 | 1829 | 0, 22, periph_clk_enb_refcnt); |
c9e2d69a | 1830 | clks[TEGRA114_CLK_USBD] = clk; |
2cb5efef PDS |
1831 | |
1832 | /* usb2 */ | |
1833 | clk = tegra_clk_register_periph_gate("usb2", "clk_m", 0, clk_base, | |
d5ff89a8 | 1834 | 0, 58, periph_clk_enb_refcnt); |
c9e2d69a | 1835 | clks[TEGRA114_CLK_USB2] = clk; |
2cb5efef PDS |
1836 | |
1837 | /* usb3 */ | |
1838 | clk = tegra_clk_register_periph_gate("usb3", "clk_m", 0, clk_base, | |
d5ff89a8 | 1839 | 0, 59, periph_clk_enb_refcnt); |
c9e2d69a | 1840 | clks[TEGRA114_CLK_USB3] = clk; |
2cb5efef PDS |
1841 | |
1842 | /* csi */ | |
1843 | clk = tegra_clk_register_periph_gate("csi", "pll_p_out3", 0, clk_base, | |
d5ff89a8 | 1844 | 0, 52, periph_clk_enb_refcnt); |
c9e2d69a | 1845 | clks[TEGRA114_CLK_CSI] = clk; |
2cb5efef PDS |
1846 | |
1847 | /* isp */ | |
1848 | clk = tegra_clk_register_periph_gate("isp", "clk_m", 0, clk_base, 0, | |
d5ff89a8 | 1849 | 23, periph_clk_enb_refcnt); |
c9e2d69a | 1850 | clks[TEGRA114_CLK_ISP] = clk; |
2cb5efef PDS |
1851 | |
1852 | /* csus */ | |
1853 | clk = tegra_clk_register_periph_gate("csus", "clk_m", | |
1854 | TEGRA_PERIPH_NO_RESET, clk_base, 0, 92, | |
d5ff89a8 | 1855 | periph_clk_enb_refcnt); |
c9e2d69a | 1856 | clks[TEGRA114_CLK_CSUS] = clk; |
2cb5efef PDS |
1857 | |
1858 | /* dds */ | |
1859 | clk = tegra_clk_register_periph_gate("dds", "clk_m", | |
1860 | TEGRA_PERIPH_ON_APB, clk_base, 0, 150, | |
d5ff89a8 | 1861 | periph_clk_enb_refcnt); |
c9e2d69a | 1862 | clks[TEGRA114_CLK_DDS] = clk; |
2cb5efef PDS |
1863 | |
1864 | /* dp2 */ | |
1865 | clk = tegra_clk_register_periph_gate("dp2", "clk_m", | |
1866 | TEGRA_PERIPH_ON_APB, clk_base, 0, 152, | |
d5ff89a8 | 1867 | periph_clk_enb_refcnt); |
c9e2d69a | 1868 | clks[TEGRA114_CLK_DP2] = clk; |
2cb5efef PDS |
1869 | |
1870 | /* dtv */ | |
1871 | clk = tegra_clk_register_periph_gate("dtv", "clk_m", | |
1872 | TEGRA_PERIPH_ON_APB, clk_base, 0, 79, | |
d5ff89a8 | 1873 | periph_clk_enb_refcnt); |
c9e2d69a | 1874 | clks[TEGRA114_CLK_DTV] = clk; |
2cb5efef PDS |
1875 | |
1876 | /* dsia */ | |
1877 | clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0, | |
819c1de3 JH |
1878 | ARRAY_SIZE(mux_plld_out0_plld2_out0), |
1879 | CLK_SET_RATE_NO_REPARENT, | |
2cb5efef | 1880 | clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock); |
c9e2d69a | 1881 | clks[TEGRA114_CLK_DSIA_MUX] = clk; |
2cb5efef | 1882 | clk = tegra_clk_register_periph_gate("dsia", "dsia_mux", 0, clk_base, |
d5ff89a8 | 1883 | 0, 48, periph_clk_enb_refcnt); |
c9e2d69a | 1884 | clks[TEGRA114_CLK_DSIA] = clk; |
2cb5efef PDS |
1885 | |
1886 | /* dsib */ | |
1887 | clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0, | |
819c1de3 JH |
1888 | ARRAY_SIZE(mux_plld_out0_plld2_out0), |
1889 | CLK_SET_RATE_NO_REPARENT, | |
2cb5efef | 1890 | clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock); |
c9e2d69a | 1891 | clks[TEGRA114_CLK_DSIB_MUX] = clk; |
2cb5efef | 1892 | clk = tegra_clk_register_periph_gate("dsib", "dsib_mux", 0, clk_base, |
d5ff89a8 | 1893 | 0, 82, periph_clk_enb_refcnt); |
c9e2d69a | 1894 | clks[TEGRA114_CLK_DSIB] = clk; |
2cb5efef PDS |
1895 | |
1896 | /* xusb_hs_src */ | |
1897 | val = readl(clk_base + CLK_SOURCE_XUSB_SS_SRC); | |
1898 | val |= BIT(25); /* always select PLLU_60M */ | |
1899 | writel(val, clk_base + CLK_SOURCE_XUSB_SS_SRC); | |
1900 | ||
1901 | clk = clk_register_fixed_factor(NULL, "xusb_hs_src", "pll_u_60M", 0, | |
1902 | 1, 1); | |
c9e2d69a | 1903 | clks[TEGRA114_CLK_XUSB_HS_SRC] = clk; |
2cb5efef PDS |
1904 | |
1905 | /* xusb_host */ | |
1906 | clk = tegra_clk_register_periph_gate("xusb_host", "xusb_host_src", 0, | |
d5ff89a8 | 1907 | clk_base, 0, 89, periph_clk_enb_refcnt); |
c9e2d69a | 1908 | clks[TEGRA114_CLK_XUSB_HOST] = clk; |
2cb5efef PDS |
1909 | |
1910 | /* xusb_ss */ | |
1911 | clk = tegra_clk_register_periph_gate("xusb_ss", "xusb_ss_src", 0, | |
d5ff89a8 | 1912 | clk_base, 0, 156, periph_clk_enb_refcnt); |
c9e2d69a | 1913 | clks[TEGRA114_CLK_XUSB_HOST] = clk; |
2cb5efef PDS |
1914 | |
1915 | /* xusb_dev */ | |
1916 | clk = tegra_clk_register_periph_gate("xusb_dev", "xusb_dev_src", 0, | |
d5ff89a8 | 1917 | clk_base, 0, 95, periph_clk_enb_refcnt); |
c9e2d69a | 1918 | clks[TEGRA114_CLK_XUSB_DEV] = clk; |
2cb5efef PDS |
1919 | |
1920 | /* emc */ | |
1921 | clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, | |
819c1de3 JH |
1922 | ARRAY_SIZE(mux_pllmcp_clkm), |
1923 | CLK_SET_RATE_NO_REPARENT, | |
2cb5efef PDS |
1924 | clk_base + CLK_SOURCE_EMC, |
1925 | 29, 3, 0, NULL); | |
1926 | clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, | |
d5ff89a8 | 1927 | CLK_IGNORE_UNUSED, 57, periph_clk_enb_refcnt); |
c9e2d69a | 1928 | clks[TEGRA114_CLK_EMC] = clk; |
2cb5efef PDS |
1929 | |
1930 | for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) { | |
1931 | data = &tegra_periph_clk_list[i]; | |
d5ff89a8 PDS |
1932 | |
1933 | clk = tegra_clk_register_periph(data->name, | |
1934 | data->parent_names, data->num_parents, &data->periph, | |
1935 | clk_base, data->offset, data->flags); | |
2cb5efef PDS |
1936 | clks[data->clk_id] = clk; |
1937 | } | |
1938 | ||
1939 | for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) { | |
1940 | data = &tegra_periph_nodiv_clk_list[i]; | |
d5ff89a8 | 1941 | |
2cb5efef PDS |
1942 | clk = tegra_clk_register_periph_nodiv(data->name, |
1943 | data->parent_names, data->num_parents, | |
1944 | &data->periph, clk_base, data->offset); | |
1945 | clks[data->clk_id] = clk; | |
1946 | } | |
1947 | } | |
1948 | ||
31972fd9 JL |
1949 | /* Tegra114 CPU clock and reset control functions */ |
1950 | static void tegra114_wait_cpu_in_reset(u32 cpu) | |
1951 | { | |
1952 | unsigned int reg; | |
1953 | ||
1954 | do { | |
1955 | reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS); | |
1956 | cpu_relax(); | |
1957 | } while (!(reg & (1 << cpu))); /* check CPU been reset or not */ | |
1958 | } | |
1959 | static void tegra114_disable_cpu_clock(u32 cpu) | |
1960 | { | |
1961 | /* flow controller would take care in the power sequence. */ | |
1962 | } | |
1963 | ||
ad7d1140 JL |
1964 | #ifdef CONFIG_PM_SLEEP |
1965 | static void tegra114_cpu_clock_suspend(void) | |
1966 | { | |
1967 | /* switch coresite to clk_m, save off original source */ | |
1968 | tegra114_cpu_clk_sctx.clk_csite_src = | |
1969 | readl(clk_base + CLK_SOURCE_CSITE); | |
1970 | writel(3 << 30, clk_base + CLK_SOURCE_CSITE); | |
0017f447 JL |
1971 | |
1972 | tegra114_cpu_clk_sctx.cclkg_burst = | |
1973 | readl(clk_base + CCLKG_BURST_POLICY); | |
1974 | tegra114_cpu_clk_sctx.cclkg_divider = | |
1975 | readl(clk_base + CCLKG_BURST_POLICY + 4); | |
ad7d1140 JL |
1976 | } |
1977 | ||
1978 | static void tegra114_cpu_clock_resume(void) | |
1979 | { | |
1980 | writel(tegra114_cpu_clk_sctx.clk_csite_src, | |
1981 | clk_base + CLK_SOURCE_CSITE); | |
0017f447 JL |
1982 | |
1983 | writel(tegra114_cpu_clk_sctx.cclkg_burst, | |
1984 | clk_base + CCLKG_BURST_POLICY); | |
1985 | writel(tegra114_cpu_clk_sctx.cclkg_divider, | |
1986 | clk_base + CCLKG_BURST_POLICY + 4); | |
ad7d1140 JL |
1987 | } |
1988 | #endif | |
1989 | ||
31972fd9 JL |
1990 | static struct tegra_cpu_car_ops tegra114_cpu_car_ops = { |
1991 | .wait_for_reset = tegra114_wait_cpu_in_reset, | |
1992 | .disable_clock = tegra114_disable_cpu_clock, | |
ad7d1140 JL |
1993 | #ifdef CONFIG_PM_SLEEP |
1994 | .suspend = tegra114_cpu_clock_suspend, | |
1995 | .resume = tegra114_cpu_clock_resume, | |
1996 | #endif | |
31972fd9 | 1997 | }; |
2cb5efef PDS |
1998 | |
1999 | static const struct of_device_id pmc_match[] __initconst = { | |
2000 | { .compatible = "nvidia,tegra114-pmc" }, | |
2001 | {}, | |
2002 | }; | |
2003 | ||
9e60121f PW |
2004 | /* |
2005 | * dfll_soc/dfll_ref apparently must be kept enabled, otherwise I2C5 | |
2006 | * breaks | |
2007 | */ | |
056dfcf6 | 2008 | static struct tegra_clk_init_table init_table[] __initdata = { |
c9e2d69a PDS |
2009 | {TEGRA114_CLK_UARTA, TEGRA114_CLK_PLL_P, 408000000, 0}, |
2010 | {TEGRA114_CLK_UARTB, TEGRA114_CLK_PLL_P, 408000000, 0}, | |
2011 | {TEGRA114_CLK_UARTC, TEGRA114_CLK_PLL_P, 408000000, 0}, | |
2012 | {TEGRA114_CLK_UARTD, TEGRA114_CLK_PLL_P, 408000000, 0}, | |
2013 | {TEGRA114_CLK_PLL_A, TEGRA114_CLK_CLK_MAX, 564480000, 1}, | |
2014 | {TEGRA114_CLK_PLL_A_OUT0, TEGRA114_CLK_CLK_MAX, 11289600, 1}, | |
2015 | {TEGRA114_CLK_EXTERN1, TEGRA114_CLK_PLL_A_OUT0, 0, 1}, | |
2016 | {TEGRA114_CLK_CLK_OUT_1_MUX, TEGRA114_CLK_EXTERN1, 0, 1}, | |
2017 | {TEGRA114_CLK_CLK_OUT_1, TEGRA114_CLK_CLK_MAX, 0, 1}, | |
2018 | {TEGRA114_CLK_I2S0, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0}, | |
2019 | {TEGRA114_CLK_I2S1, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0}, | |
2020 | {TEGRA114_CLK_I2S2, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0}, | |
2021 | {TEGRA114_CLK_I2S3, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0}, | |
2022 | {TEGRA114_CLK_I2S4, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0}, | |
897e1dde | 2023 | {TEGRA114_CLK_HOST1X, TEGRA114_CLK_PLL_P, 136000000, 0}, |
c9e2d69a PDS |
2024 | {TEGRA114_CLK_DFLL_SOC, TEGRA114_CLK_PLL_P, 51000000, 1}, |
2025 | {TEGRA114_CLK_DFLL_REF, TEGRA114_CLK_PLL_P, 51000000, 1}, | |
f67a8d21 TR |
2026 | {TEGRA114_CLK_GR2D, TEGRA114_CLK_PLL_C2, 300000000, 0}, |
2027 | {TEGRA114_CLK_GR3D, TEGRA114_CLK_PLL_C2, 300000000, 0}, | |
fc20eeff | 2028 | |
c9e2d69a PDS |
2029 | /* This MUST be the last entry. */ |
2030 | {TEGRA114_CLK_CLK_MAX, TEGRA114_CLK_CLK_MAX, 0, 0}, | |
2cb5efef PDS |
2031 | }; |
2032 | ||
2033 | static void __init tegra114_clock_apply_init_table(void) | |
2034 | { | |
c9e2d69a | 2035 | tegra_init_from_table(init_table, clks, TEGRA114_CLK_CLK_MAX); |
2cb5efef PDS |
2036 | } |
2037 | ||
25c9ded6 PW |
2038 | |
2039 | /** | |
2040 | * tegra114_car_barrier - wait for pending writes to the CAR to complete | |
2041 | * | |
2042 | * Wait for any outstanding writes to the CAR MMIO space from this CPU | |
2043 | * to complete before continuing execution. No return value. | |
2044 | */ | |
2045 | static void tegra114_car_barrier(void) | |
2046 | { | |
2047 | wmb(); /* probably unnecessary */ | |
2048 | readl_relaxed(clk_base + CPU_FINETRIM_SELECT); | |
2049 | } | |
2050 | ||
2051 | /** | |
2052 | * tegra114_clock_tune_cpu_trimmers_high - use high-voltage propagation delays | |
2053 | * | |
2054 | * When the CPU rail voltage is in the high-voltage range, use the | |
2055 | * built-in hardwired clock propagation delays in the CPU clock | |
2056 | * shaper. No return value. | |
2057 | */ | |
2058 | void tegra114_clock_tune_cpu_trimmers_high(void) | |
2059 | { | |
2060 | u32 select = 0; | |
2061 | ||
2062 | /* Use hardwired rise->rise & fall->fall clock propagation delays */ | |
2063 | select |= ~(CPU_FINETRIM_1_FCPU_1 | CPU_FINETRIM_1_FCPU_2 | | |
2064 | CPU_FINETRIM_1_FCPU_3 | CPU_FINETRIM_1_FCPU_4 | | |
2065 | CPU_FINETRIM_1_FCPU_5 | CPU_FINETRIM_1_FCPU_6); | |
2066 | writel_relaxed(select, clk_base + CPU_FINETRIM_SELECT); | |
2067 | ||
2068 | tegra114_car_barrier(); | |
2069 | } | |
2070 | EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_high); | |
2071 | ||
2072 | /** | |
2073 | * tegra114_clock_tune_cpu_trimmers_low - use low-voltage propagation delays | |
2074 | * | |
2075 | * When the CPU rail voltage is in the low-voltage range, use the | |
2076 | * extended clock propagation delays set by | |
2077 | * tegra114_clock_tune_cpu_trimmers_init(). The intention is to | |
2078 | * maintain the input clock duty cycle that the FCPU subsystem | |
2079 | * expects. No return value. | |
2080 | */ | |
2081 | void tegra114_clock_tune_cpu_trimmers_low(void) | |
2082 | { | |
2083 | u32 select = 0; | |
2084 | ||
2085 | /* | |
2086 | * Use software-specified rise->rise & fall->fall clock | |
2087 | * propagation delays (from | |
2088 | * tegra114_clock_tune_cpu_trimmers_init() | |
2089 | */ | |
2090 | select |= (CPU_FINETRIM_1_FCPU_1 | CPU_FINETRIM_1_FCPU_2 | | |
2091 | CPU_FINETRIM_1_FCPU_3 | CPU_FINETRIM_1_FCPU_4 | | |
2092 | CPU_FINETRIM_1_FCPU_5 | CPU_FINETRIM_1_FCPU_6); | |
2093 | writel_relaxed(select, clk_base + CPU_FINETRIM_SELECT); | |
2094 | ||
2095 | tegra114_car_barrier(); | |
2096 | } | |
2097 | EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_low); | |
2098 | ||
2099 | /** | |
2100 | * tegra114_clock_tune_cpu_trimmers_init - set up and enable clk prop delays | |
2101 | * | |
2102 | * Program extended clock propagation delays into the FCPU clock | |
2103 | * shaper and enable them. XXX Define the purpose - peak current | |
2104 | * reduction? No return value. | |
2105 | */ | |
2106 | /* XXX Initial voltage rail state assumption issues? */ | |
2107 | void tegra114_clock_tune_cpu_trimmers_init(void) | |
2108 | { | |
2109 | u32 dr = 0, r = 0; | |
2110 | ||
2111 | /* Increment the rise->rise clock delay by four steps */ | |
2112 | r |= (CPU_FINETRIM_R_FCPU_1_MASK | CPU_FINETRIM_R_FCPU_2_MASK | | |
2113 | CPU_FINETRIM_R_FCPU_3_MASK | CPU_FINETRIM_R_FCPU_4_MASK | | |
2114 | CPU_FINETRIM_R_FCPU_5_MASK | CPU_FINETRIM_R_FCPU_6_MASK); | |
2115 | writel_relaxed(r, clk_base + CPU_FINETRIM_R); | |
2116 | ||
2117 | /* | |
2118 | * Use the rise->rise clock propagation delay specified in the | |
2119 | * r field | |
2120 | */ | |
2121 | dr |= (CPU_FINETRIM_1_FCPU_1 | CPU_FINETRIM_1_FCPU_2 | | |
2122 | CPU_FINETRIM_1_FCPU_3 | CPU_FINETRIM_1_FCPU_4 | | |
2123 | CPU_FINETRIM_1_FCPU_5 | CPU_FINETRIM_1_FCPU_6); | |
2124 | writel_relaxed(dr, clk_base + CPU_FINETRIM_DR); | |
2125 | ||
2126 | tegra114_clock_tune_cpu_trimmers_low(); | |
2127 | } | |
2128 | EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_init); | |
2129 | ||
1c472d8e PW |
2130 | /** |
2131 | * tegra114_clock_assert_dfll_dvco_reset - assert the DFLL's DVCO reset | |
2132 | * | |
2133 | * Assert the reset line of the DFLL's DVCO. No return value. | |
2134 | */ | |
2135 | void tegra114_clock_assert_dfll_dvco_reset(void) | |
2136 | { | |
2137 | u32 v; | |
2138 | ||
2139 | v = readl_relaxed(clk_base + RST_DFLL_DVCO); | |
2140 | v |= (1 << DVFS_DFLL_RESET_SHIFT); | |
2141 | writel_relaxed(v, clk_base + RST_DFLL_DVCO); | |
2142 | tegra114_car_barrier(); | |
2143 | } | |
2144 | EXPORT_SYMBOL(tegra114_clock_assert_dfll_dvco_reset); | |
2145 | ||
2146 | /** | |
2147 | * tegra114_clock_deassert_dfll_dvco_reset - deassert the DFLL's DVCO reset | |
2148 | * | |
2149 | * Deassert the reset line of the DFLL's DVCO, allowing the DVCO to | |
2150 | * operate. No return value. | |
2151 | */ | |
2152 | void tegra114_clock_deassert_dfll_dvco_reset(void) | |
2153 | { | |
2154 | u32 v; | |
2155 | ||
2156 | v = readl_relaxed(clk_base + RST_DFLL_DVCO); | |
2157 | v &= ~(1 << DVFS_DFLL_RESET_SHIFT); | |
2158 | writel_relaxed(v, clk_base + RST_DFLL_DVCO); | |
2159 | tegra114_car_barrier(); | |
2160 | } | |
2161 | EXPORT_SYMBOL(tegra114_clock_deassert_dfll_dvco_reset); | |
2162 | ||
061cec92 | 2163 | static void __init tegra114_clock_init(struct device_node *np) |
2cb5efef PDS |
2164 | { |
2165 | struct device_node *node; | |
2cb5efef PDS |
2166 | |
2167 | clk_base = of_iomap(np, 0); | |
2168 | if (!clk_base) { | |
2169 | pr_err("ioremap tegra114 CAR failed\n"); | |
2170 | return; | |
2171 | } | |
2172 | ||
2173 | node = of_find_matching_node(NULL, pmc_match); | |
2174 | if (!node) { | |
2175 | pr_err("Failed to find pmc node\n"); | |
2176 | WARN_ON(1); | |
2177 | return; | |
2178 | } | |
2179 | ||
2180 | pmc_base = of_iomap(node, 0); | |
2181 | if (!pmc_base) { | |
2182 | pr_err("Can't map pmc registers\n"); | |
2183 | WARN_ON(1); | |
2184 | return; | |
2185 | } | |
2186 | ||
343a607c PDS |
2187 | clks = tegra_clk_init(TEGRA114_CLK_CLK_MAX, TEGRA114_CLK_PERIPH_BANKS); |
2188 | if (!clks) | |
2cb5efef PDS |
2189 | return; |
2190 | ||
343a607c | 2191 | if (tegra114_osc_clk_init(clk_base) < 0) |
d5ff89a8 PDS |
2192 | return; |
2193 | ||
2cb5efef PDS |
2194 | tegra114_fixed_clk_init(clk_base); |
2195 | tegra114_pll_init(clk_base, pmc_base); | |
2196 | tegra114_periph_clk_init(clk_base); | |
2197 | tegra114_audio_clk_init(clk_base); | |
2198 | tegra114_pmc_clk_init(pmc_base); | |
2199 | tegra114_super_clk_init(clk_base); | |
2200 | ||
343a607c | 2201 | tegra_add_of_provider(np); |
73d37e4c | 2202 | tegra_register_devclks(devclks, ARRAY_SIZE(devclks)); |
2cb5efef PDS |
2203 | |
2204 | tegra_clk_apply_init_table = tegra114_clock_apply_init_table; | |
2205 | ||
2206 | tegra_cpu_car_ops = &tegra114_cpu_car_ops; | |
2207 | } | |
061cec92 | 2208 | CLK_OF_DECLARE(tegra114, "nvidia,tegra114-car", tegra114_clock_init); |